1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated
8 #define DSS_SUBSYS_NAME "HDMIPLL"
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/err.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/seq_file.h>
18 #include <video/omapfb_dss.h>
23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
26 hdmi_read_reg(pll->base, r))
28 DUMPPLL(PLLCTRL_PLL_CONTROL);
29 DUMPPLL(PLLCTRL_PLL_STATUS);
30 DUMPPLL(PLLCTRL_PLL_GO);
31 DUMPPLL(PLLCTRL_CFG1);
32 DUMPPLL(PLLCTRL_CFG2);
33 DUMPPLL(PLLCTRL_CFG3);
34 DUMPPLL(PLLCTRL_SSC_CFG1);
35 DUMPPLL(PLLCTRL_SSC_CFG2);
36 DUMPPLL(PLLCTRL_CFG4);
39 void hdmi_pll_compute(struct hdmi_pll_data *pll,
40 unsigned long target_tmds, struct dss_pll_clock_info *pi)
42 unsigned long fint, clkdco, clkout;
43 unsigned long target_bitclk, target_clkdco;
44 unsigned long min_dco;
45 unsigned n, m, mf, m2, sd;
47 const struct dss_pll_hw *hw = pll->pll.hw;
49 clkin = clk_get_rate(pll->pll.clkin);
51 DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
53 target_bitclk = target_tmds * 10;
56 n = DIV_ROUND_UP(clkin, hw->fint_max);
59 /* adjust m2 so that the clkdco will be high enough */
60 min_dco = roundup(hw->clkdco_min, fint);
61 m2 = DIV_ROUND_UP(min_dco, target_bitclk);
65 target_clkdco = target_bitclk * m2;
66 m = target_clkdco / fint;
70 /* adjust clkdco with fractional mf */
71 if (WARN_ON(target_clkdco - clkdco > fint))
74 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
77 clkdco += (u32)div_u64((u64)mf * fint, 262144);
82 sd = DIV_ROUND_UP(fint * m, 250000000);
84 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
86 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
96 pi->clkout[0] = clkout;
99 static int hdmi_pll_enable(struct dss_pll *dsspll)
101 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
102 struct hdmi_wp_data *wp = pll->wp;
105 dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
107 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
114 static void hdmi_pll_disable(struct dss_pll *dsspll)
116 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
117 struct hdmi_wp_data *wp = pll->wp;
119 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
121 dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
124 static const struct dss_pll_ops dsi_pll_ops = {
125 .enable = hdmi_pll_enable,
126 .disable = hdmi_pll_disable,
127 .set_config = dss_pll_write_config_type_b,
130 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
138 .clkdco_min = 500000000,
139 .clkdco_low = 1000000000,
140 .clkdco_max = 2000000000,
150 .has_selfreqdco = true,
153 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
161 .clkdco_min = 750000000,
162 .clkdco_low = 1500000000,
163 .clkdco_max = 2500000000UL,
173 .has_selfreqdco = true,
177 static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll)
179 struct dss_pll *pll = &hpll->pll;
183 clk = devm_clk_get(&pdev->dev, "sys_clk");
185 DSSERR("can't get sys_clk\n");
190 pll->id = DSS_PLL_HDMI;
191 pll->base = hpll->base;
194 switch (omapdss_get_version()) {
195 case OMAPDSS_VER_OMAP4430_ES1:
196 case OMAPDSS_VER_OMAP4430_ES2:
197 case OMAPDSS_VER_OMAP4:
198 pll->hw = &dss_omap4_hdmi_pll_hw;
201 case OMAPDSS_VER_OMAP5:
202 case OMAPDSS_VER_DRA7xx:
203 pll->hw = &dss_omap5_hdmi_pll_hw;
210 pll->ops = &dsi_pll_ops;
212 r = dss_pll_register(pll);
219 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
220 struct hdmi_wp_data *wp)
223 struct resource *res;
227 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
229 DSSERR("can't get PLL mem resource\n");
233 pll->base = devm_ioremap_resource(&pdev->dev, res);
234 if (IS_ERR(pll->base)) {
235 DSSERR("can't ioremap PLLCTRL\n");
236 return PTR_ERR(pll->base);
239 r = dsi_init_pll_data(pdev, pll);
241 DSSERR("failed to init HDMI PLL\n");
248 void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
250 struct dss_pll *pll = &hpll->pll;
252 dss_pll_unregister(pll);