2 * Copyright (C) 2014 Texas Instruments Incorporated
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #define DSS_SUBSYS_NAME "PLL"
19 #include <linux/clk.h>
21 #include <linux/kernel.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sched.h>
25 #include <video/omapdss.h>
29 #define PLL_CONTROL 0x0000
30 #define PLL_STATUS 0x0004
32 #define PLL_CONFIGURATION1 0x000C
33 #define PLL_CONFIGURATION2 0x0010
34 #define PLL_CONFIGURATION3 0x0014
35 #define PLL_SSC_CONFIGURATION1 0x0018
36 #define PLL_SSC_CONFIGURATION2 0x001C
37 #define PLL_CONFIGURATION4 0x0020
39 static struct dss_pll *dss_plls[4];
41 int dss_pll_register(struct dss_pll *pll)
45 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
55 void dss_pll_unregister(struct dss_pll *pll)
59 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
60 if (dss_plls[i] == pll) {
67 struct dss_pll *dss_pll_find(const char *name)
71 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
72 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0)
79 int dss_pll_enable(struct dss_pll *pll)
83 r = clk_prepare_enable(pll->clkin);
88 r = regulator_enable(pll->regulator);
93 r = pll->ops->enable(pll);
101 regulator_disable(pll->regulator);
103 clk_disable_unprepare(pll->clkin);
107 void dss_pll_disable(struct dss_pll *pll)
109 pll->ops->disable(pll);
112 regulator_disable(pll->regulator);
114 clk_disable_unprepare(pll->clkin);
116 memset(&pll->cinfo, 0, sizeof(pll->cinfo));
119 int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
123 r = pll->ops->set_config(pll, cinfo);
132 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
133 unsigned long out_min, unsigned long out_max,
134 dss_hsdiv_calc_func func, void *data)
136 const struct dss_pll_hw *hw = pll->hw;
137 int m, m_start, m_stop;
140 out_min = out_min ? out_min : 1;
141 out_max = out_max ? out_max : ULONG_MAX;
143 m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);
145 m_stop = min((unsigned)(clkdco / out_min), hw->mX_max);
147 for (m = m_start; m <= m_stop; ++m) {
150 if (func(m, out, data))
157 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
158 unsigned long pll_min, unsigned long pll_max,
159 dss_pll_calc_func func, void *data)
161 const struct dss_pll_hw *hw = pll->hw;
162 int n, n_start, n_stop;
163 int m, m_start, m_stop;
164 unsigned long fint, clkdco;
165 unsigned long pll_hw_max;
166 unsigned long fint_hw_min, fint_hw_max;
168 pll_hw_max = hw->clkdco_max;
170 fint_hw_min = hw->fint_min;
171 fint_hw_max = hw->fint_max;
173 n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
174 n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max);
176 pll_max = pll_max ? pll_max : ULONG_MAX;
178 for (n = n_start; n <= n_stop; ++n) {
181 m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
183 m_stop = min3((unsigned)(pll_max / fint / 2),
184 (unsigned)(pll_hw_max / fint / 2),
187 for (m = m_start; m <= m_stop; ++m) {
188 clkdco = 2 * m * fint;
190 if (func(n, m, fint, clkdco, data))
198 static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
200 unsigned long timeout;
204 /* first busyloop to see if the bit changes right away */
207 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
211 /* then loop for 500ms, sleeping for 1ms in between */
212 timeout = jiffies + msecs_to_jiffies(500);
213 while (time_before(jiffies, timeout)) {
214 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
217 wait = ns_to_ktime(1000 * 1000);
218 set_current_state(TASK_UNINTERRUPTIBLE);
219 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
225 static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
230 u32 v = readl_relaxed(pll->base + PLL_STATUS);
232 if (v == hsdiv_ack_mask)
239 int dss_pll_write_config_type_a(struct dss_pll *pll,
240 const struct dss_pll_clock_info *cinfo)
242 const struct dss_pll_hw *hw = pll->hw;
243 void __iomem *base = pll->base;
248 if (hw->has_stopmode)
249 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */
250 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */
251 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */
253 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,
254 hw->mX_msb[0], hw->mX_lsb[0]);
256 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,
257 hw->mX_msb[1], hw->mX_lsb[1]);
258 writel_relaxed(l, base + PLL_CONFIGURATION1);
262 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,
263 hw->mX_msb[2], hw->mX_lsb[2]);
265 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,
266 hw->mX_msb[3], hw->mX_lsb[3]);
267 writel_relaxed(l, base + PLL_CONFIGURATION3);
269 l = readl_relaxed(base + PLL_CONFIGURATION2);
270 if (hw->has_freqsel) {
271 u32 f = cinfo->fint < 1000000 ? 0x3 :
272 cinfo->fint < 1250000 ? 0x4 :
273 cinfo->fint < 1500000 ? 0x5 :
274 cinfo->fint < 1750000 ? 0x6 :
277 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */
278 } else if (hw->has_selfreqdco) {
279 u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;
281 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
283 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
284 l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */
285 l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */
286 l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */
287 l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
289 l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */
290 l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */
291 l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */
292 writel_relaxed(l, base + PLL_CONFIGURATION2);
294 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
296 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
297 DSSERR("DSS DPLL GO bit not going down.\n");
302 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
303 DSSERR("cannot lock DSS DPLL\n");
308 l = readl_relaxed(base + PLL_CONFIGURATION2);
309 l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
310 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */
311 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */
312 l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
313 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */
314 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */
315 writel_relaxed(l, base + PLL_CONFIGURATION2);
317 r = dss_wait_hsdiv_ack(pll,
318 (cinfo->mX[0] ? BIT(7) : 0) |
319 (cinfo->mX[1] ? BIT(8) : 0) |
320 (cinfo->mX[2] ? BIT(10) : 0) |
321 (cinfo->mX[3] ? BIT(11) : 0));
323 DSSERR("failed to enable HSDIV clocks\n");
331 int dss_pll_write_config_type_b(struct dss_pll *pll,
332 const struct dss_pll_clock_info *cinfo)
334 const struct dss_pll_hw *hw = pll->hw;
335 void __iomem *base = pll->base;
339 l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */
340 l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */
341 writel_relaxed(l, base + PLL_CONFIGURATION1);
343 l = readl_relaxed(base + PLL_CONFIGURATION2);
344 l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
345 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */
346 l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */
348 l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */
351 if (cinfo->clkdco > hw->clkdco_low)
352 l = FLD_MOD(l, 0x4, 3, 1);
354 l = FLD_MOD(l, 0x2, 3, 1);
355 writel_relaxed(l, base + PLL_CONFIGURATION2);
357 l = readl_relaxed(base + PLL_CONFIGURATION3);
358 l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */
359 writel_relaxed(l, base + PLL_CONFIGURATION3);
361 l = readl_relaxed(base + PLL_CONFIGURATION4);
362 l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */
363 l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */
364 writel_relaxed(l, base + PLL_CONFIGURATION4);
366 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
368 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
369 DSSERR("DSS DPLL GO bit not going down.\n");
373 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
374 DSSERR("cannot lock DSS DPLL\n");