2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <linux/interrupt.h>
32 #ifdef DSS_SUBSYS_NAME
33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
35 #define pr_fmt(fmt) fmt
38 #define DSSDBG(format, ...) \
39 pr_debug(format, ## __VA_ARGS__)
41 #ifdef DSS_SUBSYS_NAME
42 #define DSSERR(format, ...) \
43 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
46 #define DSSERR(format, ...) \
47 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
50 #ifdef DSS_SUBSYS_NAME
51 #define DSSINFO(format, ...) \
52 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
55 #define DSSINFO(format, ...) \
56 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
59 #ifdef DSS_SUBSYS_NAME
60 #define DSSWARN(format, ...) \
61 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
64 #define DSSWARN(format, ...) \
65 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
69 number. For example 7:0 */
70 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
73 #define FLD_MOD(orig, val, start, end) \
74 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
76 enum dss_io_pad_mode {
77 DSS_IO_PAD_MODE_RESET,
79 DSS_IO_PAD_MODE_BYPASS,
82 enum dss_hdmi_venc_clk_source_select {
87 enum dss_dsi_content_type {
89 DSS_DSI_CONTENT_GENERIC,
92 enum dss_writeback_channel {
105 #define DSS_PLL_MAX_HSDIVS 4
108 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
109 * Type-B PLLs: clkout[0] refers to m2.
111 struct dss_pll_clock_info {
112 /* rates that we get with dividers below */
114 unsigned long clkdco;
115 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
121 u16 mX[DSS_PLL_MAX_HSDIVS];
126 int (*enable)(struct dss_pll *pll);
127 void (*disable)(struct dss_pll *pll);
128 int (*set_config)(struct dss_pll *pll,
129 const struct dss_pll_clock_info *cinfo);
138 unsigned long fint_min, fint_max;
139 unsigned long clkdco_min, clkdco_low, clkdco_max;
143 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
155 struct regulator *regulator;
159 const struct dss_pll_hw *hw;
161 const struct dss_pll_ops *ops;
163 struct dss_pll_clock_info cinfo;
166 struct dispc_clock_info {
167 /* rates that we get with dividers below */
176 struct dss_lcd_mgr_config {
177 enum dss_io_pad_mode io_pad_mode;
182 struct dispc_clock_info clock_info;
184 int video_port_width;
186 int lcden_sig_polarity;
190 struct platform_device;
193 struct platform_device *dss_get_core_pdev(void);
194 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
195 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
196 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
197 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
200 int dss_suspend_all_devices(void);
201 int dss_resume_all_devices(void);
202 void dss_disable_all_devices(void);
204 int display_init_sysfs(struct platform_device *pdev);
205 void display_uninit_sysfs(struct platform_device *pdev);
208 int dss_init_overlay_managers(void);
209 void dss_uninit_overlay_managers(void);
210 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
211 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
212 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
213 const struct omap_overlay_manager_info *info);
214 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
215 const struct omap_video_timings *timings);
216 int dss_mgr_check(struct omap_overlay_manager *mgr,
217 struct omap_overlay_manager_info *info,
218 const struct omap_video_timings *mgr_timings,
219 const struct dss_lcd_mgr_config *config,
220 struct omap_overlay_info **overlay_infos);
222 static inline bool dss_mgr_is_lcd(enum omap_channel id)
224 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
225 id == OMAP_DSS_CHANNEL_LCD3)
231 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
232 struct platform_device *pdev);
233 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
236 void dss_init_overlays(struct platform_device *pdev);
237 void dss_uninit_overlays(struct platform_device *pdev);
238 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
239 int dss_ovl_simple_check(struct omap_overlay *ovl,
240 const struct omap_overlay_info *info);
241 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
242 const struct omap_video_timings *mgr_timings);
243 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
244 enum omap_color_mode mode);
245 int dss_overlay_kobj_init(struct omap_overlay *ovl,
246 struct platform_device *pdev);
247 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
250 int dss_init_platform_driver(void) __init;
251 void dss_uninit_platform_driver(void);
253 unsigned long dss_get_dispc_clk_rate(void);
254 int dss_dpi_select_source(int port, enum omap_channel channel);
255 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
256 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
257 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
258 void dss_dump_clocks(struct seq_file *s);
261 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
262 u32 dss_of_port_get_port_number(struct device_node *port);
264 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
265 void dss_debug_dump_clocks(struct seq_file *s);
268 void dss_sdi_init(int datapairs);
269 int dss_sdi_enable(void);
270 void dss_sdi_disable(void);
272 void dss_select_dsi_clk_source(int dsi_module,
273 enum omap_dss_clk_source clk_src);
274 void dss_select_lcd_clk_source(enum omap_channel channel,
275 enum omap_dss_clk_source clk_src);
276 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
277 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
278 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
280 void dss_set_venc_output(enum omap_dss_venc_type type);
281 void dss_set_dac_pwrdn_bgz(bool enable);
283 int dss_set_fck_rate(unsigned long rate);
285 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
286 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
287 dss_div_calc_func func, void *data);
290 int sdi_init_platform_driver(void) __init;
291 void sdi_uninit_platform_driver(void) __exit;
293 #ifdef CONFIG_OMAP2_DSS_SDI
294 int sdi_init_port(struct platform_device *pdev, struct device_node *port) __init;
295 void sdi_uninit_port(struct device_node *port) __exit;
297 static inline int __init sdi_init_port(struct platform_device *pdev,
298 struct device_node *port)
302 static inline void __exit sdi_uninit_port(struct device_node *port)
309 #ifdef CONFIG_OMAP2_DSS_DSI
312 struct file_operations;
314 int dsi_init_platform_driver(void) __init;
315 void dsi_uninit_platform_driver(void) __exit;
317 void dsi_dump_clocks(struct seq_file *s);
319 void dsi_irq_handler(void);
320 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
323 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
325 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
331 int dpi_init_platform_driver(void) __init;
332 void dpi_uninit_platform_driver(void) __exit;
334 #ifdef CONFIG_OMAP2_DSS_DPI
335 int dpi_init_port(struct platform_device *pdev, struct device_node *port) __init;
336 void dpi_uninit_port(struct device_node *port) __exit;
338 static inline int __init dpi_init_port(struct platform_device *pdev,
339 struct device_node *port)
343 static inline void __exit dpi_uninit_port(struct device_node *port)
349 int dispc_init_platform_driver(void) __init;
350 void dispc_uninit_platform_driver(void) __exit;
351 void dispc_dump_clocks(struct seq_file *s);
353 void dispc_enable_sidle(void);
354 void dispc_disable_sidle(void);
356 void dispc_lcd_enable_signal(bool enable);
357 void dispc_pck_free_enable(bool enable);
358 void dispc_enable_fifomerge(bool enable);
359 void dispc_enable_gamma_table(bool enable);
360 void dispc_set_loadmode(enum omap_dss_load_mode mode);
362 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
363 unsigned long pck, void *data);
364 bool dispc_div_calc(unsigned long dispc,
365 unsigned long pck_min, unsigned long pck_max,
366 dispc_div_calc_func func, void *data);
368 bool dispc_mgr_timings_ok(enum omap_channel channel,
369 const struct omap_video_timings *timings);
370 unsigned long dispc_fclk_rate(void);
371 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
372 struct dispc_clock_info *cinfo);
375 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
376 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
377 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
380 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
381 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
382 unsigned long dispc_core_clk_rate(void);
383 void dispc_mgr_set_clock_div(enum omap_channel channel,
384 const struct dispc_clock_info *cinfo);
385 int dispc_mgr_get_clock_div(enum omap_channel channel,
386 struct dispc_clock_info *cinfo);
387 void dispc_set_tv_pclk(unsigned long pclk);
389 u32 dispc_wb_get_framedone_irq(void);
390 bool dispc_wb_go_busy(void);
391 void dispc_wb_go(void);
392 void dispc_wb_enable(bool enable);
393 bool dispc_wb_is_enabled(void);
394 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
395 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
396 bool mem_to_mem, const struct omap_video_timings *timings);
399 int venc_init_platform_driver(void) __init;
400 void venc_uninit_platform_driver(void) __exit;
403 int hdmi4_init_platform_driver(void) __init;
404 void hdmi4_uninit_platform_driver(void) __exit;
406 int hdmi5_init_platform_driver(void) __init;
407 void hdmi5_uninit_platform_driver(void) __exit;
410 int rfbi_init_platform_driver(void) __init;
411 void rfbi_uninit_platform_driver(void) __exit;
414 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
415 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
418 for (b = 0; b < 32; ++b) {
419 if (irqstatus & (1 << b))
426 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
427 unsigned long clkdco, void *data);
428 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
431 int dss_pll_register(struct dss_pll *pll);
432 void dss_pll_unregister(struct dss_pll *pll);
433 struct dss_pll *dss_pll_find(const char *name);
434 int dss_pll_enable(struct dss_pll *pll);
435 void dss_pll_disable(struct dss_pll *pll);
436 int dss_pll_set_config(struct dss_pll *pll,
437 const struct dss_pll_clock_info *cinfo);
439 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
440 unsigned long out_min, unsigned long out_max,
441 dss_hsdiv_calc_func func, void *data);
442 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
443 unsigned long pll_min, unsigned long pll_max,
444 dss_pll_calc_func func, void *data);
445 int dss_pll_write_config_type_a(struct dss_pll *pll,
446 const struct dss_pll_clock_info *cinfo);
447 int dss_pll_write_config_type_b(struct dss_pll *pll,
448 const struct dss_pll_clock_info *cinfo);