1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OMAP1 Special OptimiSed Screen Interface support
5 * Copyright (C) 2004-2005 Nokia Corporation
6 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
8 #include <linux/module.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
13 #include <linux/interrupt.h>
15 #include <linux/omap-dma.h>
20 #define MODULE_NAME "omapfb-sossi"
22 #define OMAP_SOSSI_BASE 0xfffbac00
23 #define SOSSI_ID_REG 0x00
24 #define SOSSI_INIT1_REG 0x04
25 #define SOSSI_INIT2_REG 0x08
26 #define SOSSI_INIT3_REG 0x0c
27 #define SOSSI_FIFO_REG 0x10
28 #define SOSSI_REOTABLE_REG 0x14
29 #define SOSSI_TEARING_REG 0x18
30 #define SOSSI_INIT1B_REG 0x1c
31 #define SOSSI_FIFOB_REG 0x20
33 #define DMA_GSCR 0xfffedc04
34 #define DMA_LCD_CCR 0xfffee3c2
35 #define DMA_LCD_CTRL 0xfffee3c4
36 #define DMA_LCD_LCH_CTRL 0xfffee3ea
38 #define CONF_SOSSI_RESET_R (1 << 23)
43 #define SOSSI_MAX_XMIT_BYTES (512 * 1024)
54 void (*lcdc_callback)(void *data);
55 void *lcdc_callback_data;
56 int vsync_dma_pending;
57 /* timing for read and write access */
62 * if last_access is the same as current we don't have to change
67 struct omapfb_device *fbdev;
70 static inline u32 sossi_read_reg(int reg)
72 return readl(sossi.base + reg);
75 static inline u16 sossi_read_reg16(int reg)
77 return readw(sossi.base + reg);
80 static inline u8 sossi_read_reg8(int reg)
82 return readb(sossi.base + reg);
85 static inline void sossi_write_reg(int reg, u32 value)
87 writel(value, sossi.base + reg);
90 static inline void sossi_write_reg16(int reg, u16 value)
92 writew(value, sossi.base + reg);
95 static inline void sossi_write_reg8(int reg, u8 value)
97 writeb(value, sossi.base + reg);
100 static void sossi_set_bits(int reg, u32 bits)
102 sossi_write_reg(reg, sossi_read_reg(reg) | bits);
105 static void sossi_clear_bits(int reg, u32 bits)
107 sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
110 #define HZ_TO_PS(x) (1000000000 / (x / 1000))
112 static u32 ps_to_sossi_ticks(u32 ps, int div)
114 u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div;
115 return (clk_period + ps - 1) / clk_period;
118 static int calc_rd_timings(struct extif_timings *t)
121 int reon, reoff, recyc, actim;
122 int div = t->clk_div;
125 * Make sure that after conversion it still holds that:
126 * reoff > reon, recyc >= reoff, actim > reon
128 reon = ps_to_sossi_ticks(t->re_on_time, div);
129 /* reon will be exactly one sossi tick */
133 reoff = ps_to_sossi_ticks(t->re_off_time, div);
142 recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
147 /* values less then 3 result in the SOSSI block resetting itself */
153 actim = ps_to_sossi_ticks(t->access_time, div);
157 * access time (data hold time) will be exactly one sossi
160 if (actim - reoff > 1)
169 static int calc_wr_timings(struct extif_timings *t)
172 int weon, weoff, wecyc;
173 int div = t->clk_div;
176 * Make sure that after conversion it still holds that:
177 * weoff > weon, wecyc >= weoff
179 weon = ps_to_sossi_ticks(t->we_on_time, div);
180 /* weon will be exactly one sossi tick */
184 weoff = ps_to_sossi_ticks(t->we_off_time, div);
191 wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
196 /* values less then 3 result in the SOSSI block resetting itself */
208 static void _set_timing(int div, int tw0, int tw1)
213 dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
214 tw0 + 1, tw1 + 1, div);
217 clk_set_rate(sossi.fck, sossi.fck_hz / div);
218 clk_enable(sossi.fck);
219 l = sossi_read_reg(SOSSI_INIT1_REG);
220 l &= ~((0x0f << 20) | (0x3f << 24));
221 l |= (tw0 << 20) | (tw1 << 24);
222 sossi_write_reg(SOSSI_INIT1_REG, l);
223 clk_disable(sossi.fck);
226 static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width)
230 l = sossi_read_reg(SOSSI_INIT3_REG);
232 l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
233 sossi_write_reg(SOSSI_INIT3_REG, l);
236 static void _set_tearsync_mode(int mode, unsigned line)
240 l = sossi_read_reg(SOSSI_TEARING_REG);
241 l &= ~(((1 << 11) - 1) << 15);
245 sossi_write_reg(SOSSI_TEARING_REG, l);
247 sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */
249 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6);
252 static inline void set_timing(int access)
254 if (access != sossi.last_access) {
255 sossi.last_access = access;
256 _set_timing(sossi.clk_div,
257 sossi.clk_tw0[access], sossi.clk_tw1[access]);
261 static void sossi_start_transfer(void)
264 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
266 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
269 static void sossi_stop_transfer(void)
272 sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
274 sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
277 static void wait_end_of_write(void)
279 /* Before reading we must check if some writings are going on */
280 while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
283 static void send_data(const void *data, unsigned int len)
286 sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
291 sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
296 sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
302 static void set_cycles(unsigned int len)
304 unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
306 BUG_ON((nr_cycles - 1) & ~0x3ffff);
308 sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
309 sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
312 static int sossi_convert_timings(struct extif_timings *t)
315 int div = t->clk_div;
319 if (div <= 0 || div > 8)
322 /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
323 if ((r = calc_rd_timings(t)) < 0)
326 if ((r = calc_wr_timings(t)) < 0)
336 static void sossi_set_timings(const struct extif_timings *t)
338 BUG_ON(!t->converted);
340 sossi.clk_tw0[RD_ACCESS] = t->tim[0];
341 sossi.clk_tw1[RD_ACCESS] = t->tim[1];
343 sossi.clk_tw0[WR_ACCESS] = t->tim[2];
344 sossi.clk_tw1[WR_ACCESS] = t->tim[3];
346 sossi.clk_div = t->tim[4];
349 static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
351 *clk_period = HZ_TO_PS(sossi.fck_hz);
355 static void sossi_set_bits_per_cycle(int bpc)
357 int bus_pick_count, bus_pick_width;
360 * We set explicitly the the bus_pick_count as well, although
361 * with remapping/reordering disabled it will be calculated by HW
362 * as (32 / bus_pick_width).
377 sossi.bus_pick_width = bus_pick_width;
378 sossi.bus_pick_count = bus_pick_count;
381 static int sossi_setup_tearsync(unsigned pin_cnt,
382 unsigned hs_pulse_time, unsigned vs_pulse_time,
383 int hs_pol_inv, int vs_pol_inv, int div)
388 if (pin_cnt != 1 || div < 1 || div > 8)
391 hs = ps_to_sossi_ticks(hs_pulse_time, div);
392 vs = ps_to_sossi_ticks(vs_pulse_time, div);
393 if (vs < 8 || vs <= hs || vs >= (1 << 12))
402 dev_dbg(sossi.fbdev->dev,
403 "setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n",
404 hs, vs, hs_pol_inv, vs_pol_inv);
406 clk_enable(sossi.fck);
407 l = sossi_read_reg(SOSSI_TEARING_REG);
408 l &= ~((1 << 15) - 1);
419 sossi_write_reg(SOSSI_TEARING_REG, l);
420 clk_disable(sossi.fck);
425 static int sossi_enable_tearsync(int enable, unsigned line)
429 dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line);
434 mode = 2; /* HS or VS */
436 mode = 3; /* VS only */
439 sossi.tearsync_line = line;
440 sossi.tearsync_mode = mode;
445 static void sossi_write_command(const void *data, unsigned int len)
447 clk_enable(sossi.fck);
448 set_timing(WR_ACCESS);
449 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
451 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
453 sossi_start_transfer();
454 send_data(data, len);
455 sossi_stop_transfer();
457 clk_disable(sossi.fck);
460 static void sossi_write_data(const void *data, unsigned int len)
462 clk_enable(sossi.fck);
463 set_timing(WR_ACCESS);
464 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
466 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
468 sossi_start_transfer();
469 send_data(data, len);
470 sossi_stop_transfer();
472 clk_disable(sossi.fck);
475 static void sossi_transfer_area(int width, int height,
476 void (callback)(void *data), void *data)
478 BUG_ON(callback == NULL);
480 sossi.lcdc_callback = callback;
481 sossi.lcdc_callback_data = data;
483 clk_enable(sossi.fck);
484 set_timing(WR_ACCESS);
485 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
486 _set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line);
488 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
489 set_cycles(width * height * sossi.bus_pick_width / 8);
491 sossi_start_transfer();
492 if (sossi.tearsync_mode) {
494 * Wait for the sync signal and start the transfer only
495 * then. We can't seem to be able to use HW sync DMA for
496 * this since LCD DMA shows huge latencies, as if it
497 * would ignore some of the DMA requests from SoSSI.
501 spin_lock_irqsave(&sossi.lock, flags);
502 sossi.vsync_dma_pending++;
503 spin_unlock_irqrestore(&sossi.lock, flags);
505 /* Just start the transfer right away. */
506 omap_enable_lcd_dma();
509 static void sossi_dma_callback(void *data)
512 sossi_stop_transfer();
513 clk_disable(sossi.fck);
514 sossi.lcdc_callback(sossi.lcdc_callback_data);
517 static void sossi_read_data(void *data, unsigned int len)
519 clk_enable(sossi.fck);
520 set_timing(RD_ACCESS);
521 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
523 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
525 sossi_start_transfer();
527 *(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
532 *(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
537 *(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
541 sossi_stop_transfer();
542 clk_disable(sossi.fck);
545 static irqreturn_t sossi_match_irq(int irq, void *data)
549 spin_lock_irqsave(&sossi.lock, flags);
550 if (sossi.vsync_dma_pending) {
551 sossi.vsync_dma_pending--;
552 omap_enable_lcd_dma();
554 spin_unlock_irqrestore(&sossi.lock, flags);
558 static int sossi_init(struct omapfb_device *fbdev)
562 struct clk *dpll1out_ck;
565 sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K);
567 dev_err(fbdev->dev, "can't ioremap SoSSI\n");
572 spin_lock_init(&sossi.lock);
574 dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out");
575 if (IS_ERR(dpll1out_ck)) {
576 dev_err(fbdev->dev, "can't get DPLL1OUT clock\n");
577 return PTR_ERR(dpll1out_ck);
580 * We need the parent clock rate, which we might divide further
581 * depending on the timing requirements of the controller. See
584 sossi.fck_hz = clk_get_rate(dpll1out_ck);
585 clk_put(dpll1out_ck);
587 fck = clk_get(fbdev->dev, "ck_sossi");
589 dev_err(fbdev->dev, "can't get SoSSI functional clock\n");
594 /* Reset and enable the SoSSI module */
595 l = omap_readl(MOD_CONF_CTRL_1);
596 l |= CONF_SOSSI_RESET_R;
597 omap_writel(l, MOD_CONF_CTRL_1);
598 l &= ~CONF_SOSSI_RESET_R;
599 omap_writel(l, MOD_CONF_CTRL_1);
601 clk_enable(sossi.fck);
602 l = omap_readl(ARM_IDLECT2);
603 l &= ~(1 << 8); /* DMACK_REQ */
604 omap_writel(l, ARM_IDLECT2);
606 l = sossi_read_reg(SOSSI_INIT2_REG);
607 /* Enable and reset the SoSSI block */
608 l |= (1 << 0) | (1 << 1);
609 sossi_write_reg(SOSSI_INIT2_REG, l);
610 /* Take SoSSI out of reset */
612 sossi_write_reg(SOSSI_INIT2_REG, l);
614 sossi_write_reg(SOSSI_ID_REG, 0);
615 l = sossi_read_reg(SOSSI_ID_REG);
616 k = sossi_read_reg(SOSSI_ID_REG);
618 if (l != 0x55555555 || k != 0xaaaaaaaa) {
620 "invalid SoSSI sync pattern: %08x, %08x\n", l, k);
625 if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
626 dev_err(fbdev->dev, "can't get LCDC IRQ\n");
631 l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
632 l = sossi_read_reg(SOSSI_ID_REG);
633 dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n",
634 l >> 16, l & 0xffff);
636 l = sossi_read_reg(SOSSI_INIT1_REG);
637 l |= (1 << 19); /* DMA_MODE */
638 l &= ~(1 << 31); /* REORDERING */
639 sossi_write_reg(SOSSI_INIT1_REG, l);
641 if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
642 IRQ_TYPE_EDGE_FALLING,
643 "sossi_match", sossi.fbdev->dev)) < 0) {
644 dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
648 clk_disable(sossi.fck);
652 clk_disable(sossi.fck);
657 static void sossi_cleanup(void)
659 omap_lcdc_free_dma_callback();
664 struct lcd_ctrl_extif omap1_ext_if = {
666 .cleanup = sossi_cleanup,
667 .get_clk_info = sossi_get_clk_info,
668 .convert_timings = sossi_convert_timings,
669 .set_timings = sossi_set_timings,
670 .set_bits_per_cycle = sossi_set_bits_per_cycle,
671 .setup_tearsync = sossi_setup_tearsync,
672 .enable_tearsync = sossi_enable_tearsync,
673 .write_command = sossi_write_command,
674 .read_data = sossi_read_data,
675 .write_data = sossi_write_data,
676 .transfer_area = sossi_transfer_area,
678 .max_transmit_size = SOSSI_MAX_XMIT_BYTES,