2 * drivers/video/aty/radeon_base.c
4 * framebuffer driver for ATI Radeon chipset video boards
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
11 * Special thanks to ATI DevRel team for their hardware donations.
13 * ...Insert GPL boilerplate here...
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
21 * All Rights Reserved.
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
44 * XFree86 driver authors:
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
53 #define RADEON_VERSION "0.2.0"
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/ctype.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/time.h>
68 #include <linux/ioport.h>
69 #include <linux/init.h>
70 #include <linux/pci.h>
71 #include <linux/vmalloc.h>
72 #include <linux/device.h>
75 #include <linux/uaccess.h>
79 #include <asm/pci-bridge.h>
80 #include "../macmodes.h"
82 #ifdef CONFIG_BOOTX_TEXT
83 #include <asm/btext.h>
86 #endif /* CONFIG_PPC */
88 #include <video/radeon.h>
89 #include <linux/radeonfb.h>
91 #include "../edid.h" // MOVE THAT TO include/video
94 #define MAX_MAPPED_VRAM (2048*2048*4)
95 #define MIN_MAPPED_VRAM (1024*768*1)
97 #define CHIP_DEF(id, family, flags) \
98 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
100 static struct pci_device_id radeonfb_pci_table[] = {
101 /* Radeon Xpress 200m */
102 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
103 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
108 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
109 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
110 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
111 /* Radeon IGP320M (U1) */
112 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
113 /* Radeon IGP320 (A3) */
114 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
115 /* IGP330M/340M/350M (U2) */
116 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* IGP330/340/350 (A4) */
118 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* Mobility 7000 IGP */
120 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
125 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
127 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
131 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
133 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
136 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
137 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
139 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
145 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
147 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
148 /* Mobility 9100 IGP (U3) */
149 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
153 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
154 /* Mobility 9200 (M9+) */
155 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
158 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
159 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
165 /* 9600TX / FireGL Z1 */
166 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
168 /* 9700/9500/Pro/FireGL X1 */
169 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
172 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
173 /* Mobility M10/M11 */
174 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
187 /* 9800/Pro/FileGL X2 */
188 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
200 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
201 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
207 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
208 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
215 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
224 /* Original Radeon/7200 */
225 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
226 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
227 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
231 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
240 /* these common regs are cleared before mode setting so they do not
241 * interfere with anything
243 static reg_val common_regs[] = {
245 { OVR_WID_LEFT_RIGHT, 0 },
246 { OVR_WID_TOP_BOTTOM, 0 },
247 { OV0_SCALE_CNTL, 0 },
252 { CAP0_TRIG_CNTL, 0 },
253 { CAP1_TRIG_CNTL, 0 },
260 static char *mode_option;
261 static char *monitor_layout;
262 static bool noaccel = 0;
263 static int default_dynclk = -2;
264 static bool nomodeset = 0;
265 static bool ignore_edid = 0;
266 static bool mirror = 0;
267 static int panel_yres = 0;
268 static bool force_dfp = 0;
269 static bool force_measure_pll = 0;
270 static bool nomtrr = 0;
271 static bool force_sleep;
272 static bool ignore_devlist;
273 #ifdef CONFIG_PMAC_BACKLIGHT
274 static int backlight = 1;
276 static int backlight = 0;
283 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
285 if (!rinfo->bios_seg)
287 pci_unmap_rom(dev, rinfo->bios_seg);
290 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
297 /* If this is a primary card, there is a shadow copy of the
298 * ROM somewhere in the first meg. We will just ignore the copy
299 * and use the ROM directly.
302 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
304 temp = INREG(MPP_TB_CONFIG);
307 OUTREG(MPP_TB_CONFIG, temp);
308 temp = INREG(MPP_TB_CONFIG);
310 rom = pci_map_rom(dev, &rom_size);
312 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
313 pci_name(rinfo->pdev));
317 rinfo->bios_seg = rom;
319 /* Very simple test to make sure it appeared */
320 if (BIOS_IN16(0) != 0xaa55) {
321 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
322 "should be 0xaa55\n",
323 pci_name(rinfo->pdev), BIOS_IN16(0));
326 /* Look for the PCI data to check the ROM type */
327 dptr = BIOS_IN16(0x18);
329 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
330 * for now, until I've verified this works everywhere. The goal here is more
331 * to phase out Open Firmware images.
333 * Currently, we only look at the first PCI data, we could iteratre and deal with
334 * them all, and we should use fb_bios_start relative to start of image and not
335 * relative start of ROM, but so far, I never found a dual-image ATI card
338 * u32 signature; + 0x00
341 * u16 reserved_1; + 0x08
343 * u8 drevision; + 0x0c
344 * u8 class_hi; + 0x0d
345 * u16 class_lo; + 0x0e
347 * u16 irevision; + 0x12
349 * u8 indicator; + 0x15
350 * u16 reserved_2; + 0x16
353 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
354 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
355 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
358 rom_type = BIOS_IN8(dptr + 0x14);
361 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
364 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
367 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
370 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
374 /* Locate the flat panel infos, do some sanity checking !!! */
375 rinfo->fp_bios_start = BIOS_IN16(0x48);
379 rinfo->bios_seg = NULL;
380 radeon_unmap_ROM(rinfo, dev);
385 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
387 /* I simplified this code as we used to miss the signatures in
388 * a lot of case. It's now closer to XFree, we just don't check
389 * for signatures at all... Something better will have to be done
390 * if we end up having conflicts
393 void __iomem *rom_base = NULL;
395 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
396 rom_base = ioremap(segstart, 0x10000);
397 if (rom_base == NULL)
399 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
404 if (rom_base == NULL)
407 /* Locate the flat panel infos, do some sanity checking !!! */
408 rinfo->bios_seg = rom_base;
409 rinfo->fp_bios_start = BIOS_IN16(0x48);
415 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
417 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
418 * tree. Hopefully, ATI OF driver is kind enough to fill these
420 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
422 struct device_node *dp = rinfo->of_node;
427 val = of_get_property(dp, "ATY,RefCLK", NULL);
429 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
433 rinfo->pll.ref_clk = (*val) / 10;
435 val = of_get_property(dp, "ATY,SCLK", NULL);
437 rinfo->pll.sclk = (*val) / 10;
439 val = of_get_property(dp, "ATY,MCLK", NULL);
441 rinfo->pll.mclk = (*val) / 10;
445 #endif /* CONFIG_PPC || CONFIG_SPARC */
448 * Read PLL infos from chip registers
450 static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
452 unsigned char ppll_div_sel;
454 unsigned sclk, mclk, tmp, ref_div;
455 int hTotal, vTotal, num, denom, m, n;
456 unsigned long long hz, vclk;
458 struct timeval start_tv, stop_tv;
459 long total_secs, total_usecs;
462 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
466 /* Flush PCI buffers ? */
467 tmp = INREG16(DEVICE_ID);
471 for(i=0; i<1000000; i++)
472 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
475 do_gettimeofday(&start_tv);
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
481 for(i=0; i<1000000; i++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
485 do_gettimeofday(&stop_tv);
489 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
492 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
493 total_usecs += total_secs * 1000000;
495 total_usecs = -total_usecs;
496 hz = 1000000/total_usecs;
498 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
499 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
500 vclk = (long long)hTotal * (long long)vTotal * hz;
502 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
509 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
510 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
522 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
523 radeon_pll_errata_after_index(rinfo);
525 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
526 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
531 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
553 do_div(vclk, 1000 * num);
556 if ((xtal > 26900) && (xtal < 27100))
558 else if ((xtal > 14200) && (xtal < 14400))
560 else if ((xtal > 29400) && (xtal < 29600))
563 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
567 tmp = INPLL(M_SPLL_REF_FB_DIV);
568 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
570 Ns = (tmp & 0xff0000) >> 16;
571 Nm = (tmp & 0xff00) >> 8;
573 sclk = round_div((2 * Ns * xtal), (2 * M));
574 mclk = round_div((2 * Nm * xtal), (2 * M));
576 /* we're done, hopefully these are sane values */
577 rinfo->pll.ref_clk = xtal;
578 rinfo->pll.ref_div = ref_div;
579 rinfo->pll.sclk = sclk;
580 rinfo->pll.mclk = mclk;
586 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
588 static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
591 * In the case nothing works, these are defaults; they are mostly
592 * incomplete, however. It does provide ppll_max and _min values
593 * even for most other methods, however.
595 switch (rinfo->chipset) {
596 case PCI_DEVICE_ID_ATI_RADEON_QW:
597 case PCI_DEVICE_ID_ATI_RADEON_QX:
598 rinfo->pll.ppll_max = 35000;
599 rinfo->pll.ppll_min = 12000;
600 rinfo->pll.mclk = 23000;
601 rinfo->pll.sclk = 23000;
602 rinfo->pll.ref_clk = 2700;
604 case PCI_DEVICE_ID_ATI_RADEON_QL:
605 case PCI_DEVICE_ID_ATI_RADEON_QN:
606 case PCI_DEVICE_ID_ATI_RADEON_QO:
607 case PCI_DEVICE_ID_ATI_RADEON_Ql:
608 case PCI_DEVICE_ID_ATI_RADEON_BB:
609 rinfo->pll.ppll_max = 35000;
610 rinfo->pll.ppll_min = 12000;
611 rinfo->pll.mclk = 27500;
612 rinfo->pll.sclk = 27500;
613 rinfo->pll.ref_clk = 2700;
615 case PCI_DEVICE_ID_ATI_RADEON_Id:
616 case PCI_DEVICE_ID_ATI_RADEON_Ie:
617 case PCI_DEVICE_ID_ATI_RADEON_If:
618 case PCI_DEVICE_ID_ATI_RADEON_Ig:
619 rinfo->pll.ppll_max = 35000;
620 rinfo->pll.ppll_min = 12000;
621 rinfo->pll.mclk = 25000;
622 rinfo->pll.sclk = 25000;
623 rinfo->pll.ref_clk = 2700;
625 case PCI_DEVICE_ID_ATI_RADEON_ND:
626 case PCI_DEVICE_ID_ATI_RADEON_NE:
627 case PCI_DEVICE_ID_ATI_RADEON_NF:
628 case PCI_DEVICE_ID_ATI_RADEON_NG:
629 rinfo->pll.ppll_max = 40000;
630 rinfo->pll.ppll_min = 20000;
631 rinfo->pll.mclk = 27000;
632 rinfo->pll.sclk = 27000;
633 rinfo->pll.ref_clk = 2700;
635 case PCI_DEVICE_ID_ATI_RADEON_QD:
636 case PCI_DEVICE_ID_ATI_RADEON_QE:
637 case PCI_DEVICE_ID_ATI_RADEON_QF:
638 case PCI_DEVICE_ID_ATI_RADEON_QG:
640 rinfo->pll.ppll_max = 35000;
641 rinfo->pll.ppll_min = 12000;
642 rinfo->pll.mclk = 16600;
643 rinfo->pll.sclk = 16600;
644 rinfo->pll.ref_clk = 2700;
647 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
650 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
652 * Retrieve PLL infos from Open Firmware first
654 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
655 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
658 #endif /* CONFIG_PPC || CONFIG_SPARC */
661 * Check out if we have an X86 which gave us some PLL informations
662 * and if yes, retrieve them
664 if (!force_measure_pll && rinfo->bios_seg) {
665 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
667 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
668 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
669 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
670 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
671 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
672 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
674 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
679 * We didn't get PLL parameters from either OF or BIOS, we try to
682 if (radeon_probe_pll_params(rinfo) == 0) {
683 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
688 * Fall back to already-set defaults...
690 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
694 * Some methods fail to retrieve SCLK and MCLK values, we apply default
695 * settings in this case (200Mhz). If that really happens often, we
696 * could fetch from registers instead...
698 if (rinfo->pll.mclk == 0)
699 rinfo->pll.mclk = 20000;
700 if (rinfo->pll.sclk == 0)
701 rinfo->pll.sclk = 20000;
703 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
704 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
706 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
707 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
708 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
711 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
713 struct radeonfb_info *rinfo = info->par;
714 struct fb_var_screeninfo v;
718 if (radeon_match_mode(rinfo, &v, var))
721 switch (v.bits_per_pixel) {
723 v.bits_per_pixel = 8;
726 v.bits_per_pixel = 16;
729 #if 0 /* Doesn't seem to work */
730 v.bits_per_pixel = 24;
735 v.bits_per_pixel = 32;
741 switch (var_to_depth(&v)) {
744 v.red.offset = v.green.offset = v.blue.offset = 0;
745 v.red.length = v.green.length = v.blue.length = 8;
746 v.transp.offset = v.transp.length = 0;
754 v.red.length = v.green.length = v.blue.length = 5;
755 v.transp.offset = v.transp.length = 0;
766 v.transp.offset = v.transp.length = 0;
774 v.red.length = v.blue.length = v.green.length = 8;
775 v.transp.offset = v.transp.length = 0;
783 v.red.length = v.blue.length = v.green.length = 8;
784 v.transp.offset = 24;
788 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
789 var->xres, var->yres, var->bits_per_pixel);
793 if (v.yres_virtual < v.yres)
794 v.yres_virtual = v.yres;
795 if (v.xres_virtual < v.xres)
796 v.xres_virtual = v.xres;
799 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
800 * with some panels, though I don't quite like this solution
802 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
803 v.xres_virtual = v.xres_virtual & ~7ul;
805 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
807 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
810 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
813 if (v.xres_virtual < v.xres)
814 v.xres = v.xres_virtual;
816 if (v.xoffset > v.xres_virtual - v.xres)
817 v.xoffset = v.xres_virtual - v.xres - 1;
819 if (v.yoffset > v.yres_virtual - v.yres)
820 v.yoffset = v.yres_virtual - v.yres - 1;
822 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
823 v.transp.offset = v.transp.length =
824 v.transp.msb_right = 0;
826 memcpy(var, &v, sizeof(v));
832 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
833 struct fb_info *info)
835 struct radeonfb_info *rinfo = info->par;
837 if ((var->xoffset + info->var.xres > info->var.xres_virtual)
838 || (var->yoffset + info->var.yres > info->var.yres_virtual))
845 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
846 var->xoffset * info->var.bits_per_pixel / 8) & ~7);
851 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
854 struct radeonfb_info *rinfo = info->par;
861 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
862 * and do something better using 2nd CRTC instead of just hackish
863 * routing to second output
865 case FBIO_RADEON_SET_MIRROR:
866 if (!rinfo->is_mobility)
869 rc = get_user(value, (__u32 __user *)arg);
876 tmp = INREG(LVDS_GEN_CNTL);
878 tmp |= (LVDS_ON | LVDS_BLON);
880 tmp = INREG(LVDS_GEN_CNTL);
882 tmp &= ~(LVDS_ON | LVDS_BLON);
885 OUTREG(LVDS_GEN_CNTL, tmp);
888 tmp = INREG(CRTC_EXT_CNTL);
893 tmp = INREG(CRTC_EXT_CNTL);
899 OUTREG(CRTC_EXT_CNTL, tmp);
902 case FBIO_RADEON_GET_MIRROR:
903 if (!rinfo->is_mobility)
906 tmp = INREG(LVDS_GEN_CNTL);
907 if ((LVDS_ON | LVDS_BLON) & tmp)
910 tmp = INREG(CRTC_EXT_CNTL);
911 if (CRTC_CRT_ON & tmp)
914 return put_user(value, (__u32 __user *)arg);
923 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
929 if (rinfo->lock_blank)
932 radeon_engine_idle();
934 val = INREG(CRTC_EXT_CNTL);
935 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
938 case FB_BLANK_VSYNC_SUSPEND:
939 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
941 case FB_BLANK_HSYNC_SUSPEND:
942 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
944 case FB_BLANK_POWERDOWN:
945 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
948 case FB_BLANK_NORMAL:
949 val |= CRTC_DISPLAY_DIS;
951 case FB_BLANK_UNBLANK:
955 OUTREG(CRTC_EXT_CNTL, val);
958 switch (rinfo->mon1_type) {
961 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
962 ~(FP_FPON | FP_TMDS_EN));
964 if (mode_switch || blank == FB_BLANK_NORMAL)
966 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
970 del_timer_sync(&rinfo->lvds_timer);
971 val = INREG(LVDS_GEN_CNTL);
973 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
974 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
975 & (LVDS_DIGON | LVDS_BL_MOD_EN));
976 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
977 OUTREG(LVDS_GEN_CNTL, target_val);
978 else if ((val ^ target_val) != 0) {
979 OUTREG(LVDS_GEN_CNTL, target_val
980 & ~(LVDS_ON | LVDS_BL_MOD_EN));
981 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
982 rinfo->init_state.lvds_gen_cntl |=
983 target_val & LVDS_STATE_MASK;
985 radeon_msleep(rinfo->panel_info.pwr_delay);
986 OUTREG(LVDS_GEN_CNTL, target_val);
989 rinfo->pending_lvds_gen_cntl = target_val;
990 mod_timer(&rinfo->lvds_timer,
992 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
996 val |= LVDS_DISPLAY_DIS;
997 OUTREG(LVDS_GEN_CNTL, val);
999 /* We don't do a full switch-off on a simple mode switch */
1000 if (mode_switch || blank == FB_BLANK_NORMAL)
1003 /* Asic bug, when turning off LVDS_ON, we have to make sure
1004 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1006 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1007 if (rinfo->is_mobility || rinfo->is_IGP)
1008 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1009 val &= ~(LVDS_BL_MOD_EN);
1010 OUTREG(LVDS_GEN_CNTL, val);
1012 val &= ~(LVDS_ON | LVDS_EN);
1013 OUTREG(LVDS_GEN_CNTL, val);
1015 rinfo->pending_lvds_gen_cntl = val;
1016 mod_timer(&rinfo->lvds_timer,
1018 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1019 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1020 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1021 if (rinfo->is_mobility || rinfo->is_IGP)
1022 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1026 // todo: powerdown DAC
1034 static int radeonfb_blank (int blank, struct fb_info *info)
1036 struct radeonfb_info *rinfo = info->par;
1041 return radeon_screen_blank(rinfo, blank, 0);
1044 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1045 unsigned blue, unsigned transp,
1046 struct radeonfb_info *rinfo)
1058 rinfo->palette[regno].red = red;
1059 rinfo->palette[regno].green = green;
1060 rinfo->palette[regno].blue = blue;
1065 if (!rinfo->asleep) {
1066 radeon_fifo_wait(9);
1068 if (rinfo->bpp == 16) {
1071 if (rinfo->depth == 16 && regno > 63)
1073 if (rinfo->depth == 15 && regno > 31)
1076 /* For 565, the green component is mixed one order
1079 if (rinfo->depth == 16) {
1080 OUTREG(PALETTE_INDEX, pindex>>1);
1081 OUTREG(PALETTE_DATA,
1082 (rinfo->palette[regno>>1].red << 16) |
1084 (rinfo->palette[regno>>1].blue));
1085 green = rinfo->palette[regno<<1].green;
1089 if (rinfo->depth != 16 || regno < 32) {
1090 OUTREG(PALETTE_INDEX, pindex);
1091 OUTREG(PALETTE_DATA, (red << 16) |
1092 (green << 8) | blue);
1096 u32 *pal = rinfo->info->pseudo_palette;
1097 switch (rinfo->depth) {
1099 pal[regno] = (regno << 10) | (regno << 5) | regno;
1102 pal[regno] = (regno << 11) | (regno << 5) | regno;
1105 pal[regno] = (regno << 16) | (regno << 8) | regno;
1108 i = (regno << 8) | regno;
1109 pal[regno] = (i << 16) | i;
1116 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1117 unsigned blue, unsigned transp,
1118 struct fb_info *info)
1120 struct radeonfb_info *rinfo = info->par;
1121 u32 dac_cntl2, vclk_cntl = 0;
1124 if (!rinfo->asleep) {
1125 if (rinfo->is_mobility) {
1126 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1127 OUTPLL(VCLK_ECP_CNTL,
1128 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1131 /* Make sure we are on first palette */
1132 if (rinfo->has_CRTC2) {
1133 dac_cntl2 = INREG(DAC_CNTL2);
1134 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1135 OUTREG(DAC_CNTL2, dac_cntl2);
1139 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1141 if (!rinfo->asleep && rinfo->is_mobility)
1142 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1147 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1149 struct radeonfb_info *rinfo = info->par;
1150 u16 *red, *green, *blue, *transp;
1151 u32 dac_cntl2, vclk_cntl = 0;
1152 int i, start, rc = 0;
1154 if (!rinfo->asleep) {
1155 if (rinfo->is_mobility) {
1156 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1157 OUTPLL(VCLK_ECP_CNTL,
1158 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1161 /* Make sure we are on first palette */
1162 if (rinfo->has_CRTC2) {
1163 dac_cntl2 = INREG(DAC_CNTL2);
1164 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1165 OUTREG(DAC_CNTL2, dac_cntl2);
1170 green = cmap->green;
1172 transp = cmap->transp;
1173 start = cmap->start;
1175 for (i = 0; i < cmap->len; i++) {
1176 u_int hred, hgreen, hblue, htransp = 0xffff;
1182 htransp = *transp++;
1183 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1189 if (!rinfo->asleep && rinfo->is_mobility)
1190 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1195 static void radeon_save_state (struct radeonfb_info *rinfo,
1196 struct radeon_regs *save)
1199 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1200 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1201 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1202 save->dac_cntl = INREG(DAC_CNTL);
1203 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1204 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1205 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1206 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1207 save->crtc_pitch = INREG(CRTC_PITCH);
1208 save->surface_cntl = INREG(SURFACE_CNTL);
1211 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1212 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1213 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1214 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1215 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1216 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1217 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1218 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1219 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1220 save->tmds_crc = INREG(TMDS_CRC);
1221 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1222 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1225 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1226 radeon_pll_errata_after_index(rinfo);
1227 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1228 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1232 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1236 radeon_fifo_wait(20);
1238 /* Workaround from XFree */
1239 if (rinfo->is_mobility) {
1240 /* A temporal workaround for the occasional blanking on certain laptop
1241 * panels. This appears to related to the PLL divider registers
1242 * (fail to lock?). It occurs even when all dividers are the same
1243 * with their old settings. In this case we really don't need to
1244 * fiddle with PLL registers. By doing this we can avoid the blanking
1245 * problem with some panels.
1247 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1248 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1249 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1250 /* We still have to force a switch to selected PPLL div thanks to
1251 * an XFree86 driver bug which will switch it away in some cases
1252 * even when using UseFDev */
1253 OUTREGP(CLOCK_CNTL_INDEX,
1254 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1255 ~PPLL_DIV_SEL_MASK);
1256 radeon_pll_errata_after_index(rinfo);
1257 radeon_pll_errata_after_data(rinfo);
1262 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1263 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1265 /* Reset PPLL & enable atomic update */
1267 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1268 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1270 /* Switch to selected PPLL divider */
1271 OUTREGP(CLOCK_CNTL_INDEX,
1272 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1273 ~PPLL_DIV_SEL_MASK);
1274 radeon_pll_errata_after_index(rinfo);
1275 radeon_pll_errata_after_data(rinfo);
1277 /* Set PPLL ref. div */
1278 if (IS_R300_VARIANT(rinfo) ||
1279 rinfo->family == CHIP_FAMILY_RS300 ||
1280 rinfo->family == CHIP_FAMILY_RS400 ||
1281 rinfo->family == CHIP_FAMILY_RS480) {
1282 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1283 /* When restoring console mode, use saved PPLL_REF_DIV
1286 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1288 /* R300 uses ref_div_acc field as real ref divider */
1289 OUTPLLP(PPLL_REF_DIV,
1290 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1291 ~R300_PPLL_REF_DIV_ACC_MASK);
1294 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1296 /* Set PPLL divider 3 & post divider*/
1297 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1298 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1301 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1303 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1305 /* Wait read update complete */
1306 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1307 the cause yet, but this workaround will mask the problem for now.
1308 Other chips usually will pass at the very first test, so the
1309 workaround shouldn't have any effect on them. */
1310 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1313 OUTPLL(HTOTAL_CNTL, 0);
1315 /* Clear reset & atomic update */
1316 OUTPLLP(PPLL_CNTL, 0,
1317 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1319 /* We may want some locking ... oh well */
1322 /* Switch back VCLK source to PPLL */
1323 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1327 * Timer function for delayed LVDS panel power up/down
1329 static void radeon_lvds_timer_func(unsigned long data)
1331 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1333 radeon_engine_idle();
1335 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1339 * Apply a video mode. This will apply the whole register set, including
1340 * the PLL registers, to the card
1342 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1346 int primary_mon = PRIMARY_MONITOR(rinfo);
1352 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1354 radeon_fifo_wait(31);
1355 for (i=0; i<10; i++)
1356 OUTREG(common_regs[i].reg, common_regs[i].val);
1358 /* Apply surface registers */
1359 for (i=0; i<8; i++) {
1360 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1361 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1362 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1365 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1366 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1367 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1368 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1369 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1370 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1371 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1372 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1373 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1374 OUTREG(CRTC_OFFSET, 0);
1375 OUTREG(CRTC_OFFSET_CNTL, 0);
1376 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1377 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1379 radeon_write_pll_regs(rinfo, mode);
1381 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1382 radeon_fifo_wait(10);
1383 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1384 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1385 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1386 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1387 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1388 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1389 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1390 OUTREG(TMDS_CRC, mode->tmds_crc);
1391 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1395 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1397 radeon_fifo_wait(2);
1398 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1404 * Calculate the PLL values for a given mode
1406 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1424 int fb_div, pll_output_freq = 0;
1427 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1428 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1429 * recent than an r(v)100...
1432 /* XXX I had reports of flicker happening with the cinema display
1433 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1434 * this case. This could just be a bandwidth calculation issue, I
1435 * haven't implemented the bandwidth code yet, but in the meantime,
1436 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1437 * I haven't seen a case were were absolutely needed an odd PLL
1438 * divider. I'll find a better fix once I have more infos on the
1439 * real cause of the problem.
1441 while (rinfo->has_CRTC2) {
1442 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1443 u32 disp_output_cntl;
1446 /* FP2 path not enabled */
1447 if ((fp2_gen_cntl & FP2_ON) == 0)
1449 /* Not all chip revs have the same format for this register,
1450 * extract the source selection
1452 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1453 source = (fp2_gen_cntl >> 10) & 0x3;
1454 /* sourced from transform unit, check for transform unit
1458 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1459 source = (disp_output_cntl >> 12) & 0x3;
1462 source = (fp2_gen_cntl >> 13) & 0x1;
1463 /* sourced from CRTC2 -> exit */
1467 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1474 if (freq > rinfo->pll.ppll_max)
1475 freq = rinfo->pll.ppll_max;
1476 if (freq*12 < rinfo->pll.ppll_min)
1477 freq = rinfo->pll.ppll_min / 12;
1478 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1479 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1481 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1482 pll_output_freq = post_div->divider * freq;
1483 /* If we output to the DVO port (external TMDS), we don't allow an
1484 * odd PLL divider as those aren't supported on this path
1486 if (uses_dvo && (post_div->divider & 1))
1488 if (pll_output_freq >= rinfo->pll.ppll_min &&
1489 pll_output_freq <= rinfo->pll.ppll_max)
1493 /* If we fall through the bottom, try the "default value"
1494 given by the terminal post_div->bitvalue */
1495 if ( !post_div->divider ) {
1496 post_div = &post_divs[post_div->bitvalue];
1497 pll_output_freq = post_div->divider * freq;
1499 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1500 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1503 /* If we fall through the bottom, try the "default value"
1504 given by the terminal post_div->bitvalue */
1505 if ( !post_div->divider ) {
1506 post_div = &post_divs[post_div->bitvalue];
1507 pll_output_freq = post_div->divider * freq;
1509 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1510 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1513 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1514 rinfo->pll.ref_clk);
1515 regs->ppll_ref_div = rinfo->pll.ref_div;
1516 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1518 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1519 pr_debug("fb_div = 0x%x\n", fb_div);
1520 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1523 static int radeonfb_set_par(struct fb_info *info)
1525 struct radeonfb_info *rinfo = info->par;
1526 struct fb_var_screeninfo *mode = &info->var;
1527 struct radeon_regs *newmode;
1528 int hTotal, vTotal, hSyncStart, hSyncEnd,
1529 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1530 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1531 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1532 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1536 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1537 int primary_mon = PRIMARY_MONITOR(rinfo);
1538 int depth = var_to_depth(mode);
1541 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1545 /* We always want engine to be idle on a mode switch, even
1546 * if we won't actually change the mode
1548 radeon_engine_idle();
1550 hSyncStart = mode->xres + mode->right_margin;
1551 hSyncEnd = hSyncStart + mode->hsync_len;
1552 hTotal = hSyncEnd + mode->left_margin;
1554 vSyncStart = mode->yres + mode->lower_margin;
1555 vSyncEnd = vSyncStart + mode->vsync_len;
1556 vTotal = vSyncEnd + mode->upper_margin;
1557 pixClock = mode->pixclock;
1560 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1561 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1563 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1564 if (rinfo->panel_info.xres < mode->xres)
1565 mode->xres = rinfo->panel_info.xres;
1566 if (rinfo->panel_info.yres < mode->yres)
1567 mode->yres = rinfo->panel_info.yres;
1569 hTotal = mode->xres + rinfo->panel_info.hblank;
1570 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1571 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1573 vTotal = mode->yres + rinfo->panel_info.vblank;
1574 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1575 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1577 h_sync_pol = !rinfo->panel_info.hAct_high;
1578 v_sync_pol = !rinfo->panel_info.vAct_high;
1580 pixClock = 100000000 / rinfo->panel_info.clock;
1582 if (rinfo->panel_info.use_bios_dividers) {
1584 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1585 (rinfo->panel_info.post_divider << 16);
1586 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1589 dotClock = 1000000000 / pixClock;
1590 freq = dotClock / 10; /* x100 */
1592 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1593 hSyncStart, hSyncEnd, hTotal);
1594 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1595 vSyncStart, vSyncEnd, vTotal);
1597 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1598 vsync_wid = vSyncEnd - vSyncStart;
1601 else if (hsync_wid > 0x3f) /* max */
1606 else if (vsync_wid > 0x1f) /* max */
1609 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1610 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1612 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1614 format = radeon_get_dstbpp(depth);
1615 bytpp = mode->bits_per_pixel >> 3;
1617 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1618 hsync_fudge = hsync_fudge_fp[format-1];
1620 hsync_fudge = hsync_adj_tab[format-1];
1622 hsync_start = hSyncStart - 8 + hsync_fudge;
1624 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1627 /* Clear auto-center etc... */
1628 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1629 newmode->crtc_more_cntl &= 0xfffffff0;
1631 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1632 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1634 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1636 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1639 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1643 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1646 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1647 (((mode->xres / 8) - 1) << 16));
1649 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1650 (hsync_wid << 16) | (h_sync_pol << 23));
1652 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1653 ((mode->yres - 1) << 16);
1655 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1656 (vsync_wid << 16) | (v_sync_pol << 23));
1658 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1659 /* We first calculate the engine pitch */
1660 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1663 /* Then, re-multiply it to get the CRTC pitch */
1664 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1666 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1668 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1671 * It looks like recent chips have a problem with SURFACE_CNTL,
1672 * setting SURF_TRANSLATION_DIS completely disables the
1673 * swapper as well, so we leave it unset now.
1675 newmode->surface_cntl = 0;
1677 #if defined(__BIG_ENDIAN)
1679 /* Setup swapping on both apertures, though we currently
1680 * only use aperture 0, enabling swapper on aperture 1
1683 switch (mode->bits_per_pixel) {
1685 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1686 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1690 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1691 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1696 /* Clear surface registers */
1697 for (i=0; i<8; i++) {
1698 newmode->surf_lower_bound[i] = 0;
1699 newmode->surf_upper_bound[i] = 0x1f;
1700 newmode->surf_info[i] = 0;
1703 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1704 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1705 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1706 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1708 rinfo->bpp = mode->bits_per_pixel;
1709 rinfo->depth = depth;
1711 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1712 pr_debug("freq = %lu\n", (unsigned long)freq);
1714 /* We use PPLL_DIV_3 */
1715 newmode->clk_cntl_index = 0x300;
1717 /* Calculate PPLL value if necessary */
1719 radeon_calc_pll_regs(rinfo, newmode, freq);
1721 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1723 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1724 unsigned int hRatio, vRatio;
1726 if (mode->xres > rinfo->panel_info.xres)
1727 mode->xres = rinfo->panel_info.xres;
1728 if (mode->yres > rinfo->panel_info.yres)
1729 mode->yres = rinfo->panel_info.yres;
1731 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1732 << HORZ_PANEL_SHIFT);
1733 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1734 << VERT_PANEL_SHIFT);
1736 if (mode->xres != rinfo->panel_info.xres) {
1737 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1738 rinfo->panel_info.xres);
1739 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1740 (newmode->fp_horz_stretch &
1741 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1742 HORZ_AUTO_RATIO_INC)));
1743 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1744 HORZ_STRETCH_ENABLE);
1747 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1749 if (mode->yres != rinfo->panel_info.yres) {
1750 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1751 rinfo->panel_info.yres);
1752 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1753 (newmode->fp_vert_stretch &
1754 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1755 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1756 VERT_STRETCH_ENABLE);
1759 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1761 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1763 FP_RMX_HVSYNC_CONTROL_EN |
1768 FP_CRTC_USE_SHADOW_VEND |
1771 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1772 FP_CRTC_DONT_SHADOW_HEND |
1775 if (IS_R300_VARIANT(rinfo) ||
1776 (rinfo->family == CHIP_FAMILY_R200)) {
1777 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1779 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1781 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1783 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1785 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1786 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1787 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1788 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1790 if (primary_mon == MT_LCD) {
1791 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1792 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1795 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1796 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1797 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1798 if (IS_R300_VARIANT(rinfo) ||
1799 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1800 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1802 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1803 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1806 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1807 (((mode->xres / 8) - 1) << 16));
1808 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1809 ((mode->yres - 1) << 16);
1810 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1811 (hsync_wid << 16) | (h_sync_pol << 23));
1812 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1813 (vsync_wid << 16) | (v_sync_pol << 23));
1817 if (!rinfo->asleep) {
1818 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1819 radeon_write_mode (rinfo, newmode, 0);
1820 /* (re)initialize the engine */
1821 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1822 radeonfb_engine_init (rinfo);
1825 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1826 info->fix.line_length = rinfo->pitch*64;
1828 info->fix.line_length = mode->xres_virtual
1829 * ((mode->bits_per_pixel + 1) / 8);
1830 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1831 : FB_VISUAL_DIRECTCOLOR;
1833 #ifdef CONFIG_BOOTX_TEXT
1834 /* Update debug text engine */
1835 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1836 rinfo->depth, info->fix.line_length);
1844 static struct fb_ops radeonfb_ops = {
1845 .owner = THIS_MODULE,
1846 .fb_check_var = radeonfb_check_var,
1847 .fb_set_par = radeonfb_set_par,
1848 .fb_setcolreg = radeonfb_setcolreg,
1849 .fb_setcmap = radeonfb_setcmap,
1850 .fb_pan_display = radeonfb_pan_display,
1851 .fb_blank = radeonfb_blank,
1852 .fb_ioctl = radeonfb_ioctl,
1853 .fb_sync = radeonfb_sync,
1854 .fb_fillrect = radeonfb_fillrect,
1855 .fb_copyarea = radeonfb_copyarea,
1856 .fb_imageblit = radeonfb_imageblit,
1860 static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1862 struct fb_info *info = rinfo->info;
1865 info->pseudo_palette = rinfo->pseudo_palette;
1866 info->flags = FBINFO_DEFAULT
1867 | FBINFO_HWACCEL_COPYAREA
1868 | FBINFO_HWACCEL_FILLRECT
1869 | FBINFO_HWACCEL_XPAN
1870 | FBINFO_HWACCEL_YPAN;
1871 info->fbops = &radeonfb_ops;
1872 info->screen_base = rinfo->fb_base;
1873 info->screen_size = rinfo->mapped_vram;
1874 /* Fill fix common fields */
1875 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1876 info->fix.smem_start = rinfo->fb_base_phys;
1877 info->fix.smem_len = rinfo->video_ram;
1878 info->fix.type = FB_TYPE_PACKED_PIXELS;
1879 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1880 info->fix.xpanstep = 8;
1881 info->fix.ypanstep = 1;
1882 info->fix.ywrapstep = 0;
1883 info->fix.type_aux = 0;
1884 info->fix.mmio_start = rinfo->mmio_base_phys;
1885 info->fix.mmio_len = RADEON_REGSIZE;
1886 info->fix.accel = FB_ACCEL_ATI_RADEON;
1888 fb_alloc_cmap(&info->cmap, 256, 0);
1891 info->flags |= FBINFO_HWACCEL_DISABLED;
1897 * This reconfigure the card's internal memory map. In theory, we'd like
1898 * to setup the card's memory at the same address as it's PCI bus address,
1899 * and the AGP aperture right after that so that system RAM on 32 bits
1900 * machines at least, is directly accessible. However, doing so would
1901 * conflict with the current XFree drivers...
1902 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1903 * on the proper way to set this up and duplicate this here. In the meantime,
1904 * I put the card's memory at 0 in card space and AGP at some random high
1905 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1908 #undef SET_MC_FB_FROM_APERTURE
1909 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1911 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1912 u32 save_crtc_ext_cntl;
1913 u32 aper_base, aper_size;
1916 /* First, we disable display to avoid interfering */
1917 if (rinfo->has_CRTC2) {
1918 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1919 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1921 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1922 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1924 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1925 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1928 aper_base = INREG(CNFG_APER_0_BASE);
1929 aper_size = INREG(CNFG_APER_SIZE);
1931 #ifdef SET_MC_FB_FROM_APERTURE
1932 /* Set framebuffer to be at the same address as set in PCI BAR */
1933 OUTREG(MC_FB_LOCATION,
1934 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1935 rinfo->fb_local_base = aper_base;
1937 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1938 rinfo->fb_local_base = 0;
1940 agp_base = aper_base + aper_size;
1941 if (agp_base & 0xf0000000)
1942 agp_base = (aper_base | 0x0fffffff) + 1;
1944 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1945 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1946 * always the case on PPCs afaik.
1948 #ifdef SET_MC_FB_FROM_APERTURE
1949 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1951 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1954 /* Fixup the display base addresses & engine offsets while we
1957 #ifdef SET_MC_FB_FROM_APERTURE
1958 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1959 if (rinfo->has_CRTC2)
1960 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1961 OUTREG(OV0_BASE_ADDR, aper_base);
1963 OUTREG(DISPLAY_BASE_ADDR, 0);
1964 if (rinfo->has_CRTC2)
1965 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1966 OUTREG(OV0_BASE_ADDR, 0);
1970 /* Restore display settings */
1971 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1972 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1973 if (rinfo->has_CRTC2)
1974 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1976 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1978 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1979 0xffff0000 | (agp_base >> 16));
1981 #endif /* CONFIG_PPC */
1984 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1988 /* framebuffer size */
1989 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1990 (rinfo->family == CHIP_FAMILY_RS200) ||
1991 (rinfo->family == CHIP_FAMILY_RS300) ||
1992 (rinfo->family == CHIP_FAMILY_RC410) ||
1993 (rinfo->family == CHIP_FAMILY_RS400) ||
1994 (rinfo->family == CHIP_FAMILY_RS480) ) {
1995 u32 tom = INREG(NB_TOM);
1996 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
1998 radeon_fifo_wait(6);
1999 OUTREG(MC_FB_LOCATION, tom);
2000 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2001 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2002 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2004 /* This is supposed to fix the crtc2 noise problem. */
2005 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2007 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2008 (rinfo->family == CHIP_FAMILY_RS200)) {
2009 /* This is to workaround the asic bug for RMX, some versions
2010 of BIOS doesn't have this register initialized correctly.
2012 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2013 ~CRTC_H_CUTOFF_ACTIVE_EN);
2016 tmp = INREG(CNFG_MEMSIZE);
2019 /* mem size is bits [28:0], mask off the rest */
2020 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2023 * Hack to get around some busted production M6's
2026 if (rinfo->video_ram == 0) {
2027 switch (rinfo->pdev->device) {
2028 case PCI_CHIP_RADEON_LY:
2029 case PCI_CHIP_RADEON_LZ:
2030 rinfo->video_ram = 8192 * 1024;
2039 * Now try to identify VRAM type
2041 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2042 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2043 rinfo->vram_ddr = 1;
2045 rinfo->vram_ddr = 0;
2047 tmp = INREG(MEM_CNTL);
2048 if (IS_R300_VARIANT(rinfo)) {
2049 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2051 case 0: rinfo->vram_width = 64; break;
2052 case 1: rinfo->vram_width = 128; break;
2053 case 2: rinfo->vram_width = 256; break;
2054 default: rinfo->vram_width = 128; break;
2056 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2057 (rinfo->family == CHIP_FAMILY_RS100) ||
2058 (rinfo->family == CHIP_FAMILY_RS200)){
2059 if (tmp & RV100_MEM_HALF_MODE)
2060 rinfo->vram_width = 32;
2062 rinfo->vram_width = 64;
2064 if (tmp & MEM_NUM_CHANNELS_MASK)
2065 rinfo->vram_width = 128;
2067 rinfo->vram_width = 64;
2070 /* This may not be correct, as some cards can have half of channel disabled
2071 * ToDo: identify these cases
2074 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2075 pci_name(rinfo->pdev),
2076 rinfo->video_ram / 1024,
2077 rinfo->vram_ddr ? "DDR" : "SDRAM",
2085 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2087 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2091 static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2092 struct bin_attribute *bin_attr,
2093 char *buf, loff_t off, size_t count)
2095 struct device *dev = container_of(kobj, struct device, kobj);
2096 struct pci_dev *pdev = to_pci_dev(dev);
2097 struct fb_info *info = pci_get_drvdata(pdev);
2098 struct radeonfb_info *rinfo = info->par;
2100 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2104 static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2105 struct bin_attribute *bin_attr,
2106 char *buf, loff_t off, size_t count)
2108 struct device *dev = container_of(kobj, struct device, kobj);
2109 struct pci_dev *pdev = to_pci_dev(dev);
2110 struct fb_info *info = pci_get_drvdata(pdev);
2111 struct radeonfb_info *rinfo = info->par;
2113 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2116 static struct bin_attribute edid1_attr = {
2121 .size = EDID_LENGTH,
2122 .read = radeon_show_edid1,
2125 static struct bin_attribute edid2_attr = {
2130 .size = EDID_LENGTH,
2131 .read = radeon_show_edid2,
2135 static int radeonfb_pci_register(struct pci_dev *pdev,
2136 const struct pci_device_id *ent)
2138 struct fb_info *info;
2139 struct radeonfb_info *rinfo;
2141 unsigned char c1, c2;
2144 pr_debug("radeonfb_pci_register BEGIN\n");
2146 /* Enable device in PCI config */
2147 ret = pci_enable_device(pdev);
2149 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2154 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2156 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2165 spin_lock_init(&rinfo->reg_lock);
2166 init_timer(&rinfo->lvds_timer);
2167 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2168 rinfo->lvds_timer.data = (unsigned long)rinfo;
2170 c1 = ent->device >> 8;
2171 c2 = ent->device & 0xff;
2172 if (isprint(c1) && isprint(c2))
2173 snprintf(rinfo->name, sizeof(rinfo->name),
2174 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2176 snprintf(rinfo->name, sizeof(rinfo->name),
2177 "ATI Radeon %x", ent->device & 0xffff);
2179 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2180 rinfo->chipset = pdev->device;
2181 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2182 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2183 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2185 /* Set base addrs */
2186 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2187 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2189 /* request the mem regions */
2190 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2192 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2193 pci_name(rinfo->pdev));
2194 goto err_release_fb;
2197 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2199 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2200 pci_name(rinfo->pdev));
2201 goto err_release_pci0;
2204 /* map the regions */
2205 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2206 if (!rinfo->mmio_base) {
2207 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2208 pci_name(rinfo->pdev));
2210 goto err_release_pci2;
2213 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2219 if (rinfo->family == CHIP_FAMILY_R300 &&
2220 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2222 rinfo->errata |= CHIP_ERRATA_R300_CG;
2224 if (rinfo->family == CHIP_FAMILY_RV200 ||
2225 rinfo->family == CHIP_FAMILY_RS200)
2226 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2228 if (rinfo->family == CHIP_FAMILY_RV100 ||
2229 rinfo->family == CHIP_FAMILY_RS100 ||
2230 rinfo->family == CHIP_FAMILY_RS200)
2231 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2233 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
2234 /* On PPC, we obtain the OF device-node pointer to the firmware
2235 * data for this chip
2237 rinfo->of_node = pci_device_to_OF_node(pdev);
2238 if (rinfo->of_node == NULL)
2239 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2240 pci_name(rinfo->pdev));
2242 #endif /* CONFIG_PPC || CONFIG_SPARC */
2244 /* On PPC, the firmware sets up a memory mapping that tends
2245 * to cause lockups when enabling the engine. We reconfigure
2246 * the card internal memory mappings properly
2248 fixup_memory_mappings(rinfo);
2249 #endif /* CONFIG_PPC */
2251 /* Get VRAM size and type */
2252 radeon_identify_vram(rinfo);
2254 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2257 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
2258 rinfo->mapped_vram);
2259 } while (rinfo->fb_base == NULL &&
2260 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2262 if (rinfo->fb_base == NULL) {
2263 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2264 pci_name(rinfo->pdev));
2269 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2270 rinfo->mapped_vram/1024);
2273 * Map the BIOS ROM if any and retrieve PLL parameters from
2274 * the BIOS. We skip that on mobility chips as the real panel
2275 * values we need aren't in the ROM but in the BIOS image in
2276 * memory. This is definitely not the best meacnism though,
2277 * we really need the arch code to tell us which is the "primary"
2278 * video adapter to use the memory image (or better, the arch
2279 * should provide us a copy of the BIOS image to shield us from
2280 * archs who would store that elsewhere and/or could initialize
2281 * more than one adapter during boot).
2283 if (!rinfo->is_mobility)
2284 radeon_map_ROM(rinfo, pdev);
2287 * On x86, the primary display on laptop may have it's BIOS
2288 * ROM elsewhere, try to locate it at the legacy memory hole.
2289 * We probably need to make sure this is the primary display,
2290 * but that is difficult without some arch support.
2293 if (rinfo->bios_seg == NULL)
2294 radeon_find_mem_vbios(rinfo);
2297 /* If both above failed, try the BIOS ROM again for mobility
2300 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2301 radeon_map_ROM(rinfo, pdev);
2303 /* Get informations about the board's PLL */
2304 radeon_get_pllinfo(rinfo);
2306 #ifdef CONFIG_FB_RADEON_I2C
2307 /* Register I2C bus */
2308 radeon_create_i2c_busses(rinfo);
2311 /* set all the vital stuff */
2312 radeon_set_fbinfo (rinfo);
2314 /* Probe screen types */
2315 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2317 /* Build mode list, check out panel native model */
2318 radeon_check_modes(rinfo, mode_option);
2320 /* Register some sysfs stuff (should be done better) */
2321 if (rinfo->mon1_EDID)
2322 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2324 if (rinfo->mon2_EDID)
2325 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2328 pr_warning("%s() Creating sysfs files failed, continuing\n",
2331 /* save current mode regs before we switch into the new one
2332 * so we can restore this upon __exit
2334 radeon_save_state (rinfo, &rinfo->init_state);
2335 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2337 /* Setup Power Management capabilities */
2338 if (default_dynclk < -1) {
2339 /* -2 is special: means ON on mobility chips and do not
2342 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2344 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2346 pci_set_drvdata(pdev, info);
2348 /* Register with fbdev layer */
2349 ret = register_framebuffer(info);
2351 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2352 pci_name(rinfo->pdev));
2357 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
2361 radeonfb_bl_init(rinfo);
2363 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2365 if (rinfo->bios_seg)
2366 radeon_unmap_ROM(rinfo, pdev);
2367 pr_debug("radeonfb_pci_register END\n");
2371 iounmap(rinfo->fb_base);
2373 kfree(rinfo->mon1_EDID);
2374 kfree(rinfo->mon2_EDID);
2375 if (rinfo->mon1_modedb)
2376 fb_destroy_modedb(rinfo->mon1_modedb);
2377 fb_dealloc_cmap(&info->cmap);
2378 #ifdef CONFIG_FB_RADEON_I2C
2379 radeon_delete_i2c_busses(rinfo);
2381 if (rinfo->bios_seg)
2382 radeon_unmap_ROM(rinfo, pdev);
2383 iounmap(rinfo->mmio_base);
2385 pci_release_region(pdev, 2);
2387 pci_release_region(pdev, 0);
2389 framebuffer_release(info);
2397 static void radeonfb_pci_unregister(struct pci_dev *pdev)
2399 struct fb_info *info = pci_get_drvdata(pdev);
2400 struct radeonfb_info *rinfo = info->par;
2405 radeonfb_pm_exit(rinfo);
2407 if (rinfo->mon1_EDID)
2408 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2409 if (rinfo->mon2_EDID)
2410 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2413 /* restore original state
2415 * Doesn't quite work yet, I suspect if we come from a legacy
2416 * VGA mode (or worse, text mode), we need to do some VGA black
2417 * magic here that I know nothing about. --BenH
2419 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2422 del_timer_sync(&rinfo->lvds_timer);
2423 arch_phys_wc_del(rinfo->wc_cookie);
2424 unregister_framebuffer(info);
2426 radeonfb_bl_exit(rinfo);
2428 iounmap(rinfo->mmio_base);
2429 iounmap(rinfo->fb_base);
2431 pci_release_region(pdev, 2);
2432 pci_release_region(pdev, 0);
2434 kfree(rinfo->mon1_EDID);
2435 kfree(rinfo->mon2_EDID);
2436 if (rinfo->mon1_modedb)
2437 fb_destroy_modedb(rinfo->mon1_modedb);
2438 #ifdef CONFIG_FB_RADEON_I2C
2439 radeon_delete_i2c_busses(rinfo);
2441 fb_dealloc_cmap(&info->cmap);
2442 framebuffer_release(info);
2446 static struct pci_driver radeonfb_driver = {
2448 .id_table = radeonfb_pci_table,
2449 .probe = radeonfb_pci_register,
2450 .remove = radeonfb_pci_unregister,
2452 .suspend = radeonfb_pci_suspend,
2453 .resume = radeonfb_pci_resume,
2454 #endif /* CONFIG_PM */
2458 static int __init radeonfb_setup (char *options)
2462 if (!options || !*options)
2465 while ((this_opt = strsep (&options, ",")) != NULL) {
2469 if (!strncmp(this_opt, "noaccel", 7)) {
2471 } else if (!strncmp(this_opt, "mirror", 6)) {
2473 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2475 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2476 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2477 } else if (!strncmp(this_opt, "backlight:", 10)) {
2478 backlight = simple_strtoul(this_opt+10, NULL, 0);
2479 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2481 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2483 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2484 force_measure_pll = 1;
2485 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2487 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2488 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2490 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2494 mode_option = this_opt;
2500 static int __init radeonfb_init (void)
2503 char *option = NULL;
2505 if (fb_get_options("radeonfb", &option))
2507 radeonfb_setup(option);
2509 return pci_register_driver (&radeonfb_driver);
2513 static void __exit radeonfb_exit (void)
2515 pci_unregister_driver (&radeonfb_driver);
2518 module_init(radeonfb_init);
2519 module_exit(radeonfb_exit);
2521 MODULE_AUTHOR("Ani Joshi");
2522 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2523 MODULE_LICENSE("GPL");
2524 module_param(noaccel, bool, 0);
2525 module_param(default_dynclk, int, 0);
2526 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2527 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2528 module_param(nomodeset, bool, 0);
2529 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2530 module_param(mirror, bool, 0);
2531 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2532 module_param(force_dfp, bool, 0);
2533 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2534 module_param(ignore_edid, bool, 0);
2535 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2536 module_param(monitor_layout, charp, 0);
2537 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2538 module_param(force_measure_pll, bool, 0);
2539 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2540 module_param(nomtrr, bool, 0);
2541 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2542 module_param(panel_yres, int, 0);
2543 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2544 module_param(mode_option, charp, 0);
2545 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2546 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2547 module_param(force_sleep, bool, 0);
2548 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2549 module_param(ignore_devlist, bool, 0);
2550 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");