2 * Samsung DP (Display port) register interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <video/exynos_dp.h>
19 #include "exynos_dp_core.h"
20 #include "exynos_dp_reg.h"
22 #define COMMON_INT_MASK_1 (0)
23 #define COMMON_INT_MASK_2 (0)
24 #define COMMON_INT_MASK_3 (0)
25 #define COMMON_INT_MASK_4 (0)
26 #define INT_STA_MASK (0)
28 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
33 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
34 reg |= HDCP_VIDEO_MUTE;
35 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
37 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
38 reg &= ~HDCP_VIDEO_MUTE;
39 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
43 void exynos_dp_stop_video(struct exynos_dp_device *dp)
47 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
49 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
52 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
57 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
58 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
60 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
61 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
63 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
66 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
70 reg = TX_TERMINAL_CTRL_50_OHM;
71 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
73 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
74 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
76 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
80 TX_CUR1_2X | TX_CUR_8_MA;
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
84 CH1_AMP_400_MV | CH0_AMP_400_MV;
85 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
88 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
90 /* Set interrupt pin assertion polarity as high */
91 writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
93 /* Clear pending regisers */
94 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
95 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
96 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
97 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
98 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
100 /* 0:mask,1: unmask */
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
104 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
105 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
108 void exynos_dp_reset(struct exynos_dp_device *dp)
112 exynos_dp_stop_video(dp);
113 exynos_dp_enable_video_mute(dp, 0);
115 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
116 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
117 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
118 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
120 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
121 SERDES_FIFO_FUNC_EN_N |
122 LS_CLK_DOMAIN_FUNC_EN_N;
123 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
127 exynos_dp_lane_swap(dp, 0);
129 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
130 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
132 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
134 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
135 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
137 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
138 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
140 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
142 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
144 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
145 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
147 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
152 exynos_dp_init_analog_param(dp);
153 exynos_dp_init_interrupt(dp);
156 void exynos_dp_swreset(struct exynos_dp_device *dp)
158 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
161 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
165 /* 0: mask, 1: unmask */
166 reg = COMMON_INT_MASK_1;
167 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
169 reg = COMMON_INT_MASK_2;
170 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
172 reg = COMMON_INT_MASK_3;
173 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
175 reg = COMMON_INT_MASK_4;
176 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
179 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
182 u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
186 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
193 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
200 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
202 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
204 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
208 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
209 enum analog_power_block block,
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
219 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
221 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
223 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
230 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
232 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
234 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
239 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
241 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
243 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
245 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
250 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
252 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
254 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
256 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
261 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
263 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
265 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
267 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
272 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
274 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
276 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
278 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
283 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
285 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
287 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
295 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
298 int timeout_loop = 0;
300 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
303 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
305 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
306 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
307 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
310 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
311 exynos_dp_set_pll_power_down(dp, 0);
313 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
315 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
316 dev_err(dp->dev, "failed to get pll lock status\n");
319 usleep_range(10, 20);
323 /* Enable Serdes FIFO function and Link symbol clock domain module */
324 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
325 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
327 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
330 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
334 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
335 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
338 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
340 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
341 reg &= ~(F_HPD | HPD_CTRL);
342 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
345 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
349 /* Disable AUX channel module */
350 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
351 reg |= AUX_FUNC_EN_N;
352 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
355 void exynos_dp_init_aux(struct exynos_dp_device *dp)
359 /* Clear inerrupts related to AUX channel */
360 reg = RPLY_RECEIV | AUX_ERR;
361 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
363 exynos_dp_reset_aux(dp);
365 /* Disable AUX transaction H/W retry */
366 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
367 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
368 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
370 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
371 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
372 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
374 /* Enable AUX channel module */
375 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
376 reg &= ~AUX_FUNC_EN_N;
377 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
380 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
384 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
385 if (reg & HPD_STATUS)
391 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
395 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
396 reg &= ~SW_FUNC_EN_N;
397 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
400 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
405 /* Enable AUX CH operation */
406 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
408 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
410 /* Is AUX CH command reply received? */
411 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
412 while (!(reg & RPLY_RECEIV))
413 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
415 /* Clear interrupt source for AUX CH command reply */
416 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
418 /* Clear interrupt source for AUX CH access error */
419 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
421 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
425 /* Check AUX CH error access status */
426 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
427 if ((reg & AUX_STATUS_MASK) != 0) {
428 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
429 reg & AUX_STATUS_MASK);
436 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
437 unsigned int reg_addr,
444 for (i = 0; i < 3; i++) {
445 /* Clear AUX CH data buffer */
447 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
449 /* Select DPCD device address */
450 reg = AUX_ADDR_7_0(reg_addr);
451 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
452 reg = AUX_ADDR_15_8(reg_addr);
453 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
454 reg = AUX_ADDR_19_16(reg_addr);
455 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
457 /* Write data buffer */
458 reg = (unsigned int)data;
459 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
462 * Set DisplayPort transaction and write 1 byte
463 * If bit 3 is 1, DisplayPort transaction.
464 * If Bit 3 is 0, I2C transaction.
466 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
467 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
469 /* Start AUX transaction */
470 retval = exynos_dp_start_aux_transaction(dp);
474 dev_err(dp->dev, "Aux Transaction fail!\n");
480 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
481 unsigned int reg_addr,
488 for (i = 0; i < 10; i++) {
489 /* Clear AUX CH data buffer */
491 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
493 /* Select DPCD device address */
494 reg = AUX_ADDR_7_0(reg_addr);
495 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
496 reg = AUX_ADDR_15_8(reg_addr);
497 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
498 reg = AUX_ADDR_19_16(reg_addr);
499 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
502 * Set DisplayPort transaction and read 1 byte
503 * If bit 3 is 1, DisplayPort transaction.
504 * If Bit 3 is 0, I2C transaction.
506 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
507 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
509 /* Start AUX transaction */
510 retval = exynos_dp_start_aux_transaction(dp);
514 dev_err(dp->dev, "Aux Transaction fail!\n");
517 /* Read data buffer */
518 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
519 *data = (unsigned char)(reg & 0xff);
524 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
525 unsigned int reg_addr,
527 unsigned char data[])
530 unsigned int start_offset;
531 unsigned int cur_data_count;
532 unsigned int cur_data_idx;
536 /* Clear AUX CH data buffer */
538 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
541 while (start_offset < count) {
542 /* Buffer size of AUX CH is 16 * 4bytes */
543 if ((count - start_offset) > 16)
546 cur_data_count = count - start_offset;
548 for (i = 0; i < 10; i++) {
549 /* Select DPCD device address */
550 reg = AUX_ADDR_7_0(reg_addr + start_offset);
551 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
552 reg = AUX_ADDR_15_8(reg_addr + start_offset);
553 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
554 reg = AUX_ADDR_19_16(reg_addr + start_offset);
555 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
557 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
559 reg = data[start_offset + cur_data_idx];
560 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
565 * Set DisplayPort transaction and write
566 * If bit 3 is 1, DisplayPort transaction.
567 * If Bit 3 is 0, I2C transaction.
569 reg = AUX_LENGTH(cur_data_count) |
570 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
571 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
573 /* Start AUX transaction */
574 retval = exynos_dp_start_aux_transaction(dp);
578 dev_err(dp->dev, "Aux Transaction fail!\n");
581 start_offset += cur_data_count;
587 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
588 unsigned int reg_addr,
590 unsigned char data[])
593 unsigned int start_offset;
594 unsigned int cur_data_count;
595 unsigned int cur_data_idx;
599 /* Clear AUX CH data buffer */
601 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
604 while (start_offset < count) {
605 /* Buffer size of AUX CH is 16 * 4bytes */
606 if ((count - start_offset) > 16)
609 cur_data_count = count - start_offset;
611 /* AUX CH Request Transaction process */
612 for (i = 0; i < 10; i++) {
613 /* Select DPCD device address */
614 reg = AUX_ADDR_7_0(reg_addr + start_offset);
615 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
616 reg = AUX_ADDR_15_8(reg_addr + start_offset);
617 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
618 reg = AUX_ADDR_19_16(reg_addr + start_offset);
619 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
622 * Set DisplayPort transaction and read
623 * If bit 3 is 1, DisplayPort transaction.
624 * If Bit 3 is 0, I2C transaction.
626 reg = AUX_LENGTH(cur_data_count) |
627 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
628 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
630 /* Start AUX transaction */
631 retval = exynos_dp_start_aux_transaction(dp);
635 dev_err(dp->dev, "Aux Transaction fail!\n");
638 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
640 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
642 data[start_offset + cur_data_idx] =
646 start_offset += cur_data_count;
652 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
653 unsigned int device_addr,
654 unsigned int reg_addr)
659 /* Set EDID device address */
661 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
662 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
663 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
665 /* Set offset from base address of EDID device */
666 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
669 * Set I2C transaction and write address
670 * If bit 3 is 1, DisplayPort transaction.
671 * If Bit 3 is 0, I2C transaction.
673 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
675 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
677 /* Start AUX transaction */
678 retval = exynos_dp_start_aux_transaction(dp);
680 dev_err(dp->dev, "Aux Transaction fail!\n");
685 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
686 unsigned int device_addr,
687 unsigned int reg_addr,
694 for (i = 0; i < 10; i++) {
695 /* Clear AUX CH data buffer */
697 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
699 /* Select EDID device */
700 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
702 dev_err(dp->dev, "Select EDID device fail!\n");
707 * Set I2C transaction and read data
708 * If bit 3 is 1, DisplayPort transaction.
709 * If Bit 3 is 0, I2C transaction.
711 reg = AUX_TX_COMM_I2C_TRANSACTION |
713 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
715 /* Start AUX transaction */
716 retval = exynos_dp_start_aux_transaction(dp);
720 dev_err(dp->dev, "Aux Transaction fail!\n");
725 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
730 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
731 unsigned int device_addr,
732 unsigned int reg_addr,
734 unsigned char edid[])
738 unsigned int cur_data_idx;
739 unsigned int defer = 0;
742 for (i = 0; i < count; i += 16) {
743 for (j = 0; j < 100; j++) {
744 /* Clear AUX CH data buffer */
746 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
748 /* Set normal AUX CH command */
749 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
751 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
754 * If Rx sends defer, Tx sends only reads
755 * request without sending address
758 retval = exynos_dp_select_i2c_device(dp,
759 device_addr, reg_addr + i);
765 * Set I2C transaction and write data
766 * If bit 3 is 1, DisplayPort transaction.
767 * If Bit 3 is 0, I2C transaction.
769 reg = AUX_LENGTH(16) |
770 AUX_TX_COMM_I2C_TRANSACTION |
772 writel(reg, dp->reg_base +
773 EXYNOS_DP_AUX_CH_CTL_1);
775 /* Start AUX transaction */
776 retval = exynos_dp_start_aux_transaction(dp);
780 dev_err(dp->dev, "Aux Transaction fail!\n");
782 /* Check if Rx sends defer */
783 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
784 if (reg == AUX_RX_COMM_AUX_DEFER ||
785 reg == AUX_RX_COMM_I2C_DEFER) {
786 dev_err(dp->dev, "Defer: %d\n\n", reg);
791 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
792 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
794 edid[i + cur_data_idx] = (unsigned char)reg;
801 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
806 if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
807 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
810 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
814 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
818 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
823 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
826 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
830 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
834 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
839 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
841 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
843 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
845 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
849 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
850 enum pattern_set pattern)
856 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
857 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
860 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
861 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
864 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
865 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
868 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
869 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
872 reg = SCRAMBLING_ENABLE |
873 LINK_QUAL_PATTERN_SET_DISABLE |
874 SW_TRAINING_PATTERN_SET_NORMAL;
875 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
882 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
886 reg = level << PRE_EMPHASIS_SET_SHIFT;
887 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
890 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
894 reg = level << PRE_EMPHASIS_SET_SHIFT;
895 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
898 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
902 reg = level << PRE_EMPHASIS_SET_SHIFT;
903 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
906 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
910 reg = level << PRE_EMPHASIS_SET_SHIFT;
911 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
914 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
920 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
923 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
929 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
932 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
938 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
941 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
947 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
950 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
954 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
958 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
962 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
966 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
970 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
974 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
978 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
982 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
986 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
988 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
990 /* 10 us is the minimum reset time. */
994 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
997 int exynos_dp_init_video(struct exynos_dp_device *dp)
1001 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1002 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1005 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1007 reg = CHA_CRI(4) | CHA_CTRL;
1008 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1011 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1013 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1014 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1019 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
1027 /* Configure the input color depth, color space, dynamic range */
1028 reg = (dynamic_range << IN_D_RANGE_SHIFT) |
1029 (color_depth << IN_BPC_SHIFT) |
1030 (color_space << IN_COLOR_F_SHIFT);
1031 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1033 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1034 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1035 reg &= ~IN_YC_COEFFI_MASK;
1037 reg |= IN_YC_COEFFI_ITU709;
1039 reg |= IN_YC_COEFFI_ITU601;
1040 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1043 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1047 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1048 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1050 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1052 if (!(reg & DET_STA)) {
1053 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1057 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1058 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1060 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1061 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1063 if (reg & CHA_STA) {
1064 dev_dbg(dp->dev, "Input stream clk is changing\n");
1071 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1072 enum clock_recovery_m_value_type type,
1078 if (type == REGISTER_M) {
1079 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1081 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1082 reg = m_value & 0xff;
1083 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1084 reg = (m_value >> 8) & 0xff;
1085 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1086 reg = (m_value >> 16) & 0xff;
1087 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1089 reg = n_value & 0xff;
1090 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1091 reg = (n_value >> 8) & 0xff;
1092 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1093 reg = (n_value >> 16) & 0xff;
1094 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1096 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1098 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1100 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1101 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1102 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1106 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1110 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1111 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1113 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1115 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1117 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1121 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1126 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1127 reg &= ~VIDEO_MODE_MASK;
1128 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1129 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1131 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1132 reg &= ~VIDEO_MODE_MASK;
1133 reg |= VIDEO_MODE_SLAVE_MODE;
1134 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1138 void exynos_dp_start_video(struct exynos_dp_device *dp)
1142 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1144 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1147 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1151 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1152 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1154 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1155 if (!(reg & STRM_VALID)) {
1156 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1163 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1164 struct video_info *video_info)
1168 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1169 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1170 reg |= MASTER_VID_FUNC_EN_N;
1171 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1173 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1174 reg &= ~INTERACE_SCAN_CFG;
1175 reg |= (video_info->interlaced << 2);
1176 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1178 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1179 reg &= ~VSYNC_POLARITY_CFG;
1180 reg |= (video_info->v_sync_polarity << 1);
1181 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1183 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1184 reg &= ~HSYNC_POLARITY_CFG;
1185 reg |= (video_info->h_sync_polarity << 0);
1186 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1188 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1189 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1192 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1196 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1197 reg &= ~SCRAMBLING_DISABLE;
1198 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1201 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1205 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1206 reg |= SCRAMBLING_DISABLE;
1207 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);