drivers/video/da8xx-fb.c

   1 /*
   2  * Copyright (C) 2008-2009 MontaVista Software Inc.
   3  * Copyright (C) 2008-2009 Texas Instruments Inc
   4  *
   5  * Based on the LCD driver for TI Avalanche processors written by
   6  * Ajay Singh and Shalom Hai.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option)any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/fb.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/wait.h>
  32 #include <linux/clk.h>
  33 #include <linux/cpufreq.h>
  34 #include <linux/console.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38 #include <linux/lcm.h>
  39 #include <video/da8xx-fb.h>
  40 #include <asm/div64.h>
  41
  42 #define DRIVER_NAME "da8xx_lcdc"
  43
  44 #define LCD_VERSION_1   1
  45 #define LCD_VERSION_2   2
  46
  47 /* LCD Status Register */
  48 #define LCD_END_OF_FRAME1               BIT(9)
  49 #define LCD_END_OF_FRAME0               BIT(8)
  50 #define LCD_PL_LOAD_DONE                BIT(6)
  51 #define LCD_FIFO_UNDERFLOW              BIT(5)
  52 #define LCD_SYNC_LOST                   BIT(2)
  53 #define LCD_FRAME_DONE                  BIT(0)
  54
  55 /* LCD DMA Control Register */
  56 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  57 #define LCD_DMA_BURST_1                 0x0
  58 #define LCD_DMA_BURST_2                 0x1
  59 #define LCD_DMA_BURST_4                 0x2
  60 #define LCD_DMA_BURST_8                 0x3
  61 #define LCD_DMA_BURST_16                0x4
  62 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
  63 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
  64 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
  65 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  66
  67 /* LCD Control Register */
  68 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  69 #define LCD_RASTER_MODE                 0x01
  70
  71 /* LCD Raster Control Register */
  72 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  73 #define PALETTE_AND_DATA                0x00
  74 #define PALETTE_ONLY                    0x01
  75 #define DATA_ONLY                       0x02
  76
  77 #define LCD_MONO_8BIT_MODE              BIT(9)
  78 #define LCD_RASTER_ORDER                BIT(8)
  79 #define LCD_TFT_MODE                    BIT(7)
  80 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
  81 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
  82 #define LCD_V1_PL_INT_ENA               BIT(4)
  83 #define LCD_V2_PL_INT_ENA               BIT(6)
  84 #define LCD_MONOCHROME_MODE             BIT(1)
  85 #define LCD_RASTER_ENABLE               BIT(0)
  86 #define LCD_TFT_ALT_ENABLE              BIT(23)
  87 #define LCD_STN_565_ENABLE              BIT(24)
  88 #define LCD_V2_DMA_CLK_EN               BIT(2)
  89 #define LCD_V2_LIDD_CLK_EN              BIT(1)
  90 #define LCD_V2_CORE_CLK_EN              BIT(0)
  91 #define LCD_V2_LPP_B10                  26
  92 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
  93 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
  94
  95 /* LCD Raster Timing 2 Register */
  96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  97 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  98 #define LCD_SYNC_CTRL                           BIT(25)
  99 #define LCD_SYNC_EDGE                           BIT(24)
 100 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
 101 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
 102 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
 103
 104 /* LCD Block */
 105 #define  LCD_PID_REG                            0x0
 106 #define  LCD_CTRL_REG                           0x4
 107 #define  LCD_STAT_REG                           0x8
 108 #define  LCD_RASTER_CTRL_REG                    0x28
 109 #define  LCD_RASTER_TIMING_0_REG                0x2C
 110 #define  LCD_RASTER_TIMING_1_REG                0x30
 111 #define  LCD_RASTER_TIMING_2_REG                0x34
 112 #define  LCD_DMA_CTRL_REG                       0x40
 113 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
 114 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
 115 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
 116 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
 117
 118 /* Interrupt Registers available only in Version 2 */
 119 #define  LCD_RAW_STAT_REG                       0x58
 120 #define  LCD_MASKED_STAT_REG                    0x5c
 121 #define  LCD_INT_ENABLE_SET_REG                 0x60
 122 #define  LCD_INT_ENABLE_CLR_REG                 0x64
 123 #define  LCD_END_OF_INT_IND_REG                 0x68
 124
 125 /* Clock registers available only on Version 2 */
 126 #define  LCD_CLK_ENABLE_REG                     0x6c
 127 #define  LCD_CLK_RESET_REG                      0x70
 128 #define  LCD_CLK_MAIN_RESET                     BIT(3)
 129
 130 #define LCD_NUM_BUFFERS 2
 131
 132 #define WSI_TIMEOUT     50
 133 #define PALETTE_SIZE    256
 134
 135 static void __iomem *da8xx_fb_reg_base;
 136 static struct resource *lcdc_regs;
 137 static unsigned int lcd_revision;
 138 static irq_handler_t lcdc_irq_handler;
 139 static wait_queue_head_t frame_done_wq;
 140 static int frame_done_flag;
 141
 142 static inline unsigned int lcdc_read(unsigned int addr)
 143 {
 144         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 145 }
 146
 147 static inline void lcdc_write(unsigned int val, unsigned int addr)
 148 {
 149         __raw_writel(val, da8xx_fb_reg_base + (addr));
 150 }
 151
 152 struct da8xx_fb_par {
 153         struct device           *dev;
 154         resource_size_t p_palette_base;
 155         unsigned char *v_palette_base;
 156         dma_addr_t              vram_phys;
 157         unsigned long           vram_size;
 158         void                    *vram_virt;
 159         unsigned int            dma_start;
 160         unsigned int            dma_end;
 161         struct clk *lcdc_clk;
 162         int irq;
 163         unsigned int palette_sz;
 164         int blank;
 165         wait_queue_head_t       vsync_wait;
 166         int                     vsync_flag;
 167         int                     vsync_timeout;
 168         spinlock_t              lock_for_chan_update;
 169
 170         /*
 171          * LCDC has 2 ping pong DMA channels, channel 0
 172          * and channel 1.
 173          */
 174         unsigned int            which_dma_channel_done;
 175 #ifdef CONFIG_CPU_FREQ
 176         struct notifier_block   freq_transition;
 177 #endif
 178         unsigned int            lcd_fck_rate;
 179         void (*panel_power_ctrl)(int);
 180         u32 pseudo_palette[16];
 181         struct fb_videomode     mode;
 182         struct lcd_ctrl_config  cfg;
 183 };
 184
 185 static struct fb_var_screeninfo da8xx_fb_var;
 186
 187 static struct fb_fix_screeninfo da8xx_fb_fix = {
 188         .id = "DA8xx FB Drv",
 189         .type = FB_TYPE_PACKED_PIXELS,
 190         .type_aux = 0,
 191         .visual = FB_VISUAL_PSEUDOCOLOR,
 192         .xpanstep = 0,
 193         .ypanstep = 1,
 194         .ywrapstep = 0,
 195         .accel = FB_ACCEL_NONE
 196 };
 197
 198 static struct fb_videomode known_lcd_panels[] = {
 199         /* Sharp LCD035Q3DG01 */
 200         [0] = {
 201                 .name           = "Sharp_LCD035Q3DG01",
 202                 .xres           = 320,
 203                 .yres           = 240,
 204                 .pixclock       = KHZ2PICOS(4607),
 205                 .left_margin    = 6,
 206                 .right_margin   = 8,
 207                 .upper_margin   = 2,
 208                 .lower_margin   = 2,
 209                 .hsync_len      = 0,
 210                 .vsync_len      = 0,
 211                 .sync           = FB_SYNC_CLK_INVERT |
 212                         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 213         },
 214         /* Sharp LK043T1DG01 */
 215         [1] = {
 216                 .name           = "Sharp_LK043T1DG01",
 217                 .xres           = 480,
 218                 .yres           = 272,
 219                 .pixclock       = KHZ2PICOS(7833),
 220                 .left_margin    = 2,
 221                 .right_margin   = 2,
 222                 .upper_margin   = 2,
 223                 .lower_margin   = 2,
 224                 .hsync_len      = 41,
 225                 .vsync_len      = 10,
 226                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 227                 .flag           = 0,
 228         },
 229         [2] = {
 230                 /* Hitachi SP10Q010 */
 231                 .name           = "SP10Q010",
 232                 .xres           = 320,
 233                 .yres           = 240,
 234                 .pixclock       = KHZ2PICOS(7833),
 235                 .left_margin    = 10,
 236                 .right_margin   = 10,
 237                 .upper_margin   = 10,
 238                 .lower_margin   = 10,
 239                 .hsync_len      = 10,
 240                 .vsync_len      = 10,
 241                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 242                 .flag           = 0,
 243         },
 244 };
 245
 246 static inline bool da8xx_fb_is_raster_enabled(void)
 247 {
 248         return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
 249 }
 250
 251 /* Enable the Raster Engine of the LCD Controller */
 252 static inline void lcd_enable_raster(void)
 253 {
 254         u32 reg;
 255
 256         /* Put LCDC in reset for several cycles */
 257         if (lcd_revision == LCD_VERSION_2)
 258                 /* Write 1 to reset LCDC */
 259                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 260         mdelay(1);
 261
 262         /* Bring LCDC out of reset */
 263         if (lcd_revision == LCD_VERSION_2)
 264                 lcdc_write(0, LCD_CLK_RESET_REG);
 265         mdelay(1);
 266
 267         /* Above reset sequence doesnot reset register context */
 268         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 269         if (!(reg & LCD_RASTER_ENABLE))
 270                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 271 }
 272
 273 /* Disable the Raster Engine of the LCD Controller */
 274 static inline void lcd_disable_raster(enum da8xx_frame_complete
 275                                         wait_for_frame_done)
 276 {
 277         u32 reg;
 278         int ret;
 279
 280         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 281         if (reg & LCD_RASTER_ENABLE)
 282                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 283         else
 284                 /* return if already disabled */
 285                 return;
 286
 287         if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
 288                         (lcd_revision == LCD_VERSION_2)) {
 289                 frame_done_flag = 0;
 290                 ret = wait_event_interruptible_timeout(frame_done_wq,
 291                                 frame_done_flag != 0,
 292                                 msecs_to_jiffies(50));
 293                 if (ret == 0)
 294                         pr_err("LCD Controller timed out\n");
 295         }
 296 }
 297
 298 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 299 {
 300         u32 start;
 301         u32 end;
 302         u32 reg_ras;
 303         u32 reg_dma;
 304         u32 reg_int;
 305
 306         /* init reg to clear PLM (loading mode) fields */
 307         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
 308         reg_ras &= ~(3 << 20);
 309
 310         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
 311
 312         if (load_mode == LOAD_DATA) {
 313                 start    = par->dma_start;
 314                 end      = par->dma_end;
 315
 316                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 317                 if (lcd_revision == LCD_VERSION_1) {
 318                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 319                 } else {
 320                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 321                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 322                                 LCD_V2_END_OF_FRAME1_INT_ENA |
 323                                 LCD_FRAME_DONE;
 324                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 325                 }
 326                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 327
 328                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 329                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 330                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 331                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 332         } else if (load_mode == LOAD_PALETTE) {
 333                 start    = par->p_palette_base;
 334                 end      = start + par->palette_sz - 1;
 335
 336                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 337
 338                 if (lcd_revision == LCD_VERSION_1) {
 339                         reg_ras |= LCD_V1_PL_INT_ENA;
 340                 } else {
 341                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 342                                 LCD_V2_PL_INT_ENA;
 343                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 344                 }
 345
 346                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 347                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 348         }
 349
 350         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
 351         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 352
 353         /*
 354          * The Raster enable bit must be set after all other control fields are
 355          * set.
 356          */
 357         lcd_enable_raster();
 358 }
 359
 360 /* Configure the Burst Size and fifo threhold of DMA */
 361 static int lcd_cfg_dma(int burst_size, int fifo_th)
 362 {
 363         u32 reg;
 364
 365         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 366         switch (burst_size) {
 367         case 1:
 368                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 369                 break;
 370         case 2:
 371                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 372                 break;
 373         case 4:
 374                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 375                 break;
 376         case 8:
 377                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 378                 break;
 379         case 16:
 380         default:
 381                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 382                 break;
 383         }
 384
 385         reg |= (fifo_th << 8);
 386
 387         lcdc_write(reg, LCD_DMA_CTRL_REG);
 388
 389         return 0;
 390 }
 391
 392 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 393 {
 394         u32 reg;
 395
 396         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 397         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 398         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 399                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 400         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 401 }
 402
 403 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 404                 int front_porch)
 405 {
 406         u32 reg;
 407
 408         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
 409         reg |= ((back_porch & 0xff) << 24)
 410             | ((front_porch & 0xff) << 16)
 411             | ((pulse_width & 0x3f) << 10);
 412         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 413 }
 414
 415 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 416                 int front_porch)
 417 {
 418         u32 reg;
 419
 420         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 421         reg |= ((back_porch & 0xff) << 24)
 422             | ((front_porch & 0xff) << 16)
 423             | ((pulse_width & 0x3f) << 10);
 424         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 425 }
 426
 427 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
 428                 struct fb_videomode *panel)
 429 {
 430         u32 reg;
 431         u32 reg_int;
 432
 433         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 434                                                 LCD_MONO_8BIT_MODE |
 435                                                 LCD_MONOCHROME_MODE);
 436
 437         switch (cfg->panel_shade) {
 438         case MONOCHROME:
 439                 reg |= LCD_MONOCHROME_MODE;
 440                 if (cfg->mono_8bit_mode)
 441                         reg |= LCD_MONO_8BIT_MODE;
 442                 break;
 443         case COLOR_ACTIVE:
 444                 reg |= LCD_TFT_MODE;
 445                 if (cfg->tft_alt_mode)
 446                         reg |= LCD_TFT_ALT_ENABLE;
 447                 break;
 448
 449         case COLOR_PASSIVE:
 450                 /* AC bias applicable only for Pasive panels */
 451                 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 452                 if (cfg->bpp == 12 && cfg->stn_565_mode)
 453                         reg |= LCD_STN_565_ENABLE;
 454                 break;
 455
 456         default:
 457                 return -EINVAL;
 458         }
 459
 460         /* enable additional interrupts here */
 461         if (lcd_revision == LCD_VERSION_1) {
 462                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 463         } else {
 464                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 465                         LCD_V2_UNDERFLOW_INT_ENA;
 466                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 467         }
 468
 469         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 470
 471         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 472
 473         reg |= LCD_SYNC_CTRL;
 474
 475         if (cfg->sync_edge)
 476                 reg |= LCD_SYNC_EDGE;
 477         else
 478                 reg &= ~LCD_SYNC_EDGE;
 479
 480         if (panel->sync & FB_SYNC_HOR_HIGH_ACT)
 481                 reg |= LCD_INVERT_LINE_CLOCK;
 482         else
 483                 reg &= ~LCD_INVERT_LINE_CLOCK;
 484
 485         if (panel->sync & FB_SYNC_VERT_HIGH_ACT)
 486                 reg |= LCD_INVERT_FRAME_CLOCK;
 487         else
 488                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 489
 490         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 491
 492         return 0;
 493 }
 494
 495 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 496                 u32 bpp, u32 raster_order)
 497 {
 498         u32 reg;
 499
 500         if (bpp > 16 && lcd_revision == LCD_VERSION_1)
 501                 return -EINVAL;
 502
 503         /* Set the Panel Width */
 504         /* Pixels per line = (PPL + 1)*16 */
 505         if (lcd_revision == LCD_VERSION_1) {
 506                 /*
 507                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 508                  * pixels.
 509                  */
 510                 width &= 0x3f0;
 511         } else {
 512                 /*
 513                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 514                  * pixels.
 515                  */
 516                 width &= 0x7f0;
 517         }
 518
 519         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 520         reg &= 0xfffffc00;
 521         if (lcd_revision == LCD_VERSION_1) {
 522                 reg |= ((width >> 4) - 1) << 4;
 523         } else {
 524                 width = (width >> 4) - 1;
 525                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 526         }
 527         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 528
 529         /* Set the Panel Height */
 530         /* Set bits 9:0 of Lines Per Pixel */
 531         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 532         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 533         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 534
 535         /* Set bit 10 of Lines Per Pixel */
 536         if (lcd_revision == LCD_VERSION_2) {
 537                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 538                 reg |= ((height - 1) & 0x400) << 16;
 539                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 540         }
 541
 542         /* Set the Raster Order of the Frame Buffer */
 543         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 544         if (raster_order)
 545                 reg |= LCD_RASTER_ORDER;
 546
 547         par->palette_sz = 16 * 2;
 548
 549         switch (bpp) {
 550         case 1:
 551         case 2:
 552         case 4:
 553         case 16:
 554                 break;
 555         case 24:
 556                 reg |= LCD_V2_TFT_24BPP_MODE;
 557         case 32:
 558                 reg |= LCD_V2_TFT_24BPP_UNPACK;
 559                 break;
 560
 561         case 8:
 562                 par->palette_sz = 256 * 2;
 563                 break;
 564
 565         default:
 566                 return -EINVAL;
 567         }
 568
 569         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 570
 571         return 0;
 572 }
 573
 574 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
 575 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 576                               unsigned blue, unsigned transp,
 577                               struct fb_info *info)
 578 {
 579         struct da8xx_fb_par *par = info->par;
 580         unsigned short *palette = (unsigned short *) par->v_palette_base;
 581         u_short pal;
 582         int update_hw = 0;
 583
 584         if (regno > 255)
 585                 return 1;
 586
 587         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 588                 return 1;
 589
 590         if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
 591                 return -EINVAL;
 592
 593         switch (info->fix.visual) {
 594         case FB_VISUAL_TRUECOLOR:
 595                 red = CNVT_TOHW(red, info->var.red.length);
 596                 green = CNVT_TOHW(green, info->var.green.length);
 597                 blue = CNVT_TOHW(blue, info->var.blue.length);
 598                 break;
 599         case FB_VISUAL_PSEUDOCOLOR:
 600                 switch (info->var.bits_per_pixel) {
 601                 case 4:
 602                         if (regno > 15)
 603                                 return -EINVAL;
 604
 605                         if (info->var.grayscale) {
 606                                 pal = regno;
 607                         } else {
 608                                 red >>= 4;
 609                                 green >>= 8;
 610                                 blue >>= 12;
 611
 612                                 pal = red & 0x0f00;
 613                                 pal |= green & 0x00f0;
 614                                 pal |= blue & 0x000f;
 615                         }
 616                         if (regno == 0)
 617                                 pal |= 0x2000;
 618                         palette[regno] = pal;
 619                         break;
 620
 621                 case 8:
 622                         red >>= 4;
 623                         green >>= 8;
 624                         blue >>= 12;
 625
 626                         pal = (red & 0x0f00);
 627                         pal |= (green & 0x00f0);
 628                         pal |= (blue & 0x000f);
 629
 630                         if (palette[regno] != pal) {
 631                                 update_hw = 1;
 632                                 palette[regno] = pal;
 633                         }
 634                         break;
 635                 }
 636                 break;
 637         }
 638
 639         /* Truecolor has hardware independent palette */
 640         if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
 641                 u32 v;
 642
 643                 if (regno > 15)
 644                         return -EINVAL;
 645
 646                 v = (red << info->var.red.offset) |
 647                         (green << info->var.green.offset) |
 648                         (blue << info->var.blue.offset);
 649
 650                 switch (info->var.bits_per_pixel) {
 651                 case 16:
 652                         ((u16 *) (info->pseudo_palette))[regno] = v;
 653                         break;
 654                 case 24:
 655                 case 32:
 656                         ((u32 *) (info->pseudo_palette))[regno] = v;
 657                         break;
 658                 }
 659                 if (palette[0] != 0x4000) {
 660                         update_hw = 1;
 661                         palette[0] = 0x4000;
 662                 }
 663         }
 664
 665         /* Update the palette in the h/w as needed. */
 666         if (update_hw)
 667                 lcd_blit(LOAD_PALETTE, par);
 668
 669         return 0;
 670 }
 671 #undef CNVT_TOHW
 672
 673 static void da8xx_fb_lcd_reset(void)
 674 {
 675         /* DMA has to be disabled */
 676         lcdc_write(0, LCD_DMA_CTRL_REG);
 677         lcdc_write(0, LCD_RASTER_CTRL_REG);
 678
 679         if (lcd_revision == LCD_VERSION_2) {
 680                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
 681                 /* Write 1 to reset */
 682                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 683                 lcdc_write(0, LCD_CLK_RESET_REG);
 684         }
 685 }
 686
 687 static inline unsigned da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
 688                                                  unsigned pixclock)
 689 {
 690         return par->lcd_fck_rate / (PICOS2KHZ(pixclock) * 1000);
 691 }
 692
 693 static inline unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
 694                                           unsigned pixclock)
 695 {
 696         unsigned div;
 697
 698         div = da8xx_fb_calc_clk_divider(par, pixclock);
 699         return KHZ2PICOS(par->lcd_fck_rate / (1000 * div));
 700 }
 701
 702 static inline void da8xx_fb_config_clk_divider(unsigned div)
 703 {
 704         /* Configure the LCD clock divisor. */
 705         lcdc_write(LCD_CLK_DIVISOR(div) |
 706                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 707
 708         if (lcd_revision == LCD_VERSION_2)
 709                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 710                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
 711 }
 712
 713 static inline void da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
 714                                                     struct fb_videomode *mode)
 715 {
 716         unsigned div = da8xx_fb_calc_clk_divider(par, mode->pixclock);
 717
 718         da8xx_fb_config_clk_divider(div);
 719 }
 720
 721 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 722                 struct fb_videomode *panel)
 723 {
 724         u32 bpp;
 725         int ret = 0;
 726
 727         da8xx_fb_calc_config_clk_divider(par, panel);
 728
 729         if (panel->sync & FB_SYNC_CLK_INVERT)
 730                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 731                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 732         else
 733                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 734                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 735
 736         /* Configure the DMA burst size and fifo threshold. */
 737         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
 738         if (ret < 0)
 739                 return ret;
 740
 741         /* Configure the vertical and horizontal sync properties. */
 742         lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len,
 743                         panel->upper_margin);
 744         lcd_cfg_horizontal_sync(panel->right_margin, panel->hsync_len,
 745                         panel->left_margin);
 746
 747         /* Configure for disply */
 748         ret = lcd_cfg_display(cfg, panel);
 749         if (ret < 0)
 750                 return ret;
 751
 752         bpp = cfg->bpp;
 753
 754         if (bpp == 12)
 755                 bpp = 16;
 756         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
 757                                 (unsigned int)panel->yres, bpp,
 758                                 cfg->raster_order);
 759         if (ret < 0)
 760                 return ret;
 761
 762         /* Configure FDD */
 763         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 764                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 765
 766         return 0;
 767 }
 768
 769 /* IRQ handler for version 2 of LCDC */
 770 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
 771 {
 772         struct da8xx_fb_par *par = arg;
 773         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
 774
 775         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 776                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 777                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 778                 lcd_enable_raster();
 779         } else if (stat & LCD_PL_LOAD_DONE) {
 780                 /*
 781                  * Must disable raster before changing state of any control bit.
 782                  * And also must be disabled before clearing the PL loading
 783                  * interrupt via the following write to the status register. If
 784                  * this is done after then one gets multiple PL done interrupts.
 785                  */
 786                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 787
 788                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 789
 790                 /* Disable PL completion interrupt */
 791                 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
 792
 793                 /* Setup and start data loading mode */
 794                 lcd_blit(LOAD_DATA, par);
 795         } else {
 796                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 797
 798                 if (stat & LCD_END_OF_FRAME0) {
 799                         par->which_dma_channel_done = 0;
 800                         lcdc_write(par->dma_start,
 801                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 802                         lcdc_write(par->dma_end,
 803                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 804                         par->vsync_flag = 1;
 805                         wake_up_interruptible(&par->vsync_wait);
 806                 }
 807
 808                 if (stat & LCD_END_OF_FRAME1) {
 809                         par->which_dma_channel_done = 1;
 810                         lcdc_write(par->dma_start,
 811                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 812                         lcdc_write(par->dma_end,
 813                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 814                         par->vsync_flag = 1;
 815                         wake_up_interruptible(&par->vsync_wait);
 816                 }
 817
 818                 /* Set only when controller is disabled and at the end of
 819                  * active frame
 820                  */
 821                 if (stat & BIT(0)) {
 822                         frame_done_flag = 1;
 823                         wake_up_interruptible(&frame_done_wq);
 824                 }
 825         }
 826
 827         lcdc_write(0, LCD_END_OF_INT_IND_REG);
 828         return IRQ_HANDLED;
 829 }
 830
 831 /* IRQ handler for version 1 LCDC */
 832 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
 833 {
 834         struct da8xx_fb_par *par = arg;
 835         u32 stat = lcdc_read(LCD_STAT_REG);
 836         u32 reg_ras;
 837
 838         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 839                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 840                 lcdc_write(stat, LCD_STAT_REG);
 841                 lcd_enable_raster();
 842         } else if (stat & LCD_PL_LOAD_DONE) {
 843                 /*
 844                  * Must disable raster before changing state of any control bit.
 845                  * And also must be disabled before clearing the PL loading
 846                  * interrupt via the following write to the status register. If
 847                  * this is done after then one gets multiple PL done interrupts.
 848                  */
 849                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 850
 851                 lcdc_write(stat, LCD_STAT_REG);
 852
 853                 /* Disable PL completion inerrupt */
 854                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
 855                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 856                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 857
 858                 /* Setup and start data loading mode */
 859                 lcd_blit(LOAD_DATA, par);
 860         } else {
 861                 lcdc_write(stat, LCD_STAT_REG);
 862
 863                 if (stat & LCD_END_OF_FRAME0) {
 864                         par->which_dma_channel_done = 0;
 865                         lcdc_write(par->dma_start,
 866                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 867                         lcdc_write(par->dma_end,
 868                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 869                         par->vsync_flag = 1;
 870                         wake_up_interruptible(&par->vsync_wait);
 871                 }
 872
 873                 if (stat & LCD_END_OF_FRAME1) {
 874                         par->which_dma_channel_done = 1;
 875                         lcdc_write(par->dma_start,
 876                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 877                         lcdc_write(par->dma_end,
 878                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 879                         par->vsync_flag = 1;
 880                         wake_up_interruptible(&par->vsync_wait);
 881                 }
 882         }
 883
 884         return IRQ_HANDLED;
 885 }
 886
 887 static int fb_check_var(struct fb_var_screeninfo *var,
 888                         struct fb_info *info)
 889 {
 890         int err = 0;
 891         struct da8xx_fb_par *par = info->par;
 892         int bpp = var->bits_per_pixel >> 3;
 893         unsigned long line_size = var->xres_virtual * bpp;
 894
 895         if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
 896                 return -EINVAL;
 897
 898         switch (var->bits_per_pixel) {
 899         case 1:
 900         case 8:
 901                 var->red.offset = 0;
 902                 var->red.length = 8;
 903                 var->green.offset = 0;
 904                 var->green.length = 8;
 905                 var->blue.offset = 0;
 906                 var->blue.length = 8;
 907                 var->transp.offset = 0;
 908                 var->transp.length = 0;
 909                 var->nonstd = 0;
 910                 break;
 911         case 4:
 912                 var->red.offset = 0;
 913                 var->red.length = 4;
 914                 var->green.offset = 0;
 915                 var->green.length = 4;
 916                 var->blue.offset = 0;
 917                 var->blue.length = 4;
 918                 var->transp.offset = 0;
 919                 var->transp.length = 0;
 920                 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
 921                 break;
 922         case 16:                /* RGB 565 */
 923                 var->red.offset = 11;
 924                 var->red.length = 5;
 925                 var->green.offset = 5;
 926                 var->green.length = 6;
 927                 var->blue.offset = 0;
 928                 var->blue.length = 5;
 929                 var->transp.offset = 0;
 930                 var->transp.length = 0;
 931                 var->nonstd = 0;
 932                 break;
 933         case 24:
 934                 var->red.offset = 16;
 935                 var->red.length = 8;
 936                 var->green.offset = 8;
 937                 var->green.length = 8;
 938                 var->blue.offset = 0;
 939                 var->blue.length = 8;
 940                 var->nonstd = 0;
 941                 break;
 942         case 32:
 943                 var->transp.offset = 24;
 944                 var->transp.length = 8;
 945                 var->red.offset = 16;
 946                 var->red.length = 8;
 947                 var->green.offset = 8;
 948                 var->green.length = 8;
 949                 var->blue.offset = 0;
 950                 var->blue.length = 8;
 951                 var->nonstd = 0;
 952                 break;
 953         default:
 954                 err = -EINVAL;
 955         }
 956
 957         var->red.msb_right = 0;
 958         var->green.msb_right = 0;
 959         var->blue.msb_right = 0;
 960         var->transp.msb_right = 0;
 961
 962         if (line_size * var->yres_virtual > par->vram_size)
 963                 var->yres_virtual = par->vram_size / line_size;
 964
 965         if (var->yres > var->yres_virtual)
 966                 var->yres = var->yres_virtual;
 967
 968         if (var->xres > var->xres_virtual)
 969                 var->xres = var->xres_virtual;
 970
 971         if (var->xres + var->xoffset > var->xres_virtual)
 972                 var->xoffset = var->xres_virtual - var->xres;
 973         if (var->yres + var->yoffset > var->yres_virtual)
 974                 var->yoffset = var->yres_virtual - var->yres;
 975
 976         var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
 977
 978         return err;
 979 }
 980
 981 #ifdef CONFIG_CPU_FREQ
 982 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
 983                                      unsigned long val, void *data)
 984 {
 985         struct da8xx_fb_par *par;
 986
 987         par = container_of(nb, struct da8xx_fb_par, freq_transition);
 988         if (val == CPUFREQ_POSTCHANGE) {
 989                 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
 990                         par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
 991                         lcd_disable_raster(DA8XX_FRAME_WAIT);
 992                         da8xx_fb_calc_config_clk_divider(par, &par->mode);
 993                         if (par->blank == FB_BLANK_UNBLANK)
 994                                 lcd_enable_raster();
 995                 }
 996         }
 997
 998         return 0;
 999 }
1000
1001 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1002 {
1003         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1004
1005         return cpufreq_register_notifier(&par->freq_transition,
1006                                          CPUFREQ_TRANSITION_NOTIFIER);
1007 }
1008
1009 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1010 {
1011         cpufreq_unregister_notifier(&par->freq_transition,
1012                                     CPUFREQ_TRANSITION_NOTIFIER);
1013 }
1014 #endif
1015
1016 static int fb_remove(struct platform_device *dev)
1017 {
1018         struct fb_info *info = dev_get_drvdata(&dev->dev);
1019
1020         if (info) {
1021                 struct da8xx_fb_par *par = info->par;
1022
1023 #ifdef CONFIG_CPU_FREQ
1024                 lcd_da8xx_cpufreq_deregister(par);
1025 #endif
1026                 if (par->panel_power_ctrl)
1027                         par->panel_power_ctrl(0);
1028
1029                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1030                 lcdc_write(0, LCD_RASTER_CTRL_REG);
1031
1032                 /* disable DMA  */
1033                 lcdc_write(0, LCD_DMA_CTRL_REG);
1034
1035                 unregister_framebuffer(info);
1036                 fb_dealloc_cmap(&info->cmap);
1037                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1038                                   par->p_palette_base);
1039                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1040                                   par->vram_phys);
1041                 free_irq(par->irq, par);
1042                 pm_runtime_put_sync(&dev->dev);
1043                 pm_runtime_disable(&dev->dev);
1044                 framebuffer_release(info);
1045                 iounmap(da8xx_fb_reg_base);
1046                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
1047
1048         }
1049         return 0;
1050 }
1051
1052 /*
1053  * Function to wait for vertical sync which for this LCD peripheral
1054  * translates into waiting for the current raster frame to complete.
1055  */
1056 static int fb_wait_for_vsync(struct fb_info *info)
1057 {
1058         struct da8xx_fb_par *par = info->par;
1059         int ret;
1060
1061         /*
1062          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1063          * race condition here where the ISR could have occurred just before or
1064          * just after this set. But since we are just coarsely waiting for
1065          * a frame to complete then that's OK. i.e. if the frame completed
1066          * just before this code executed then we have to wait another full
1067          * frame time but there is no way to avoid such a situation. On the
1068          * other hand if the frame completed just after then we don't need
1069          * to wait long at all. Either way we are guaranteed to return to the
1070          * user immediately after a frame completion which is all that is
1071          * required.
1072          */
1073         par->vsync_flag = 0;
1074         ret = wait_event_interruptible_timeout(par->vsync_wait,
1075                                                par->vsync_flag != 0,
1076                                                par->vsync_timeout);
1077         if (ret < 0)
1078                 return ret;
1079         if (ret == 0)
1080                 return -ETIMEDOUT;
1081
1082         return 0;
1083 }
1084
1085 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1086                           unsigned long arg)
1087 {
1088         struct lcd_sync_arg sync_arg;
1089
1090         switch (cmd) {
1091         case FBIOGET_CONTRAST:
1092         case FBIOPUT_CONTRAST:
1093         case FBIGET_BRIGHTNESS:
1094         case FBIPUT_BRIGHTNESS:
1095         case FBIGET_COLOR:
1096         case FBIPUT_COLOR:
1097                 return -ENOTTY;
1098         case FBIPUT_HSYNC:
1099                 if (copy_from_user(&sync_arg, (char *)arg,
1100                                 sizeof(struct lcd_sync_arg)))
1101                         return -EFAULT;
1102                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1103                                         sync_arg.pulse_width,
1104                                         sync_arg.front_porch);
1105                 break;
1106         case FBIPUT_VSYNC:
1107                 if (copy_from_user(&sync_arg, (char *)arg,
1108                                 sizeof(struct lcd_sync_arg)))
1109                         return -EFAULT;
1110                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1111                                         sync_arg.pulse_width,
1112                                         sync_arg.front_porch);
1113                 break;
1114         case FBIO_WAITFORVSYNC:
1115                 return fb_wait_for_vsync(info);
1116         default:
1117                 return -EINVAL;
1118         }
1119         return 0;
1120 }
1121
1122 static int cfb_blank(int blank, struct fb_info *info)
1123 {
1124         struct da8xx_fb_par *par = info->par;
1125         int ret = 0;
1126
1127         if (par->blank == blank)
1128                 return 0;
1129
1130         par->blank = blank;
1131         switch (blank) {
1132         case FB_BLANK_UNBLANK:
1133                 lcd_enable_raster();
1134
1135                 if (par->panel_power_ctrl)
1136                         par->panel_power_ctrl(1);
1137                 break;
1138         case FB_BLANK_NORMAL:
1139         case FB_BLANK_VSYNC_SUSPEND:
1140         case FB_BLANK_HSYNC_SUSPEND:
1141         case FB_BLANK_POWERDOWN:
1142                 if (par->panel_power_ctrl)
1143                         par->panel_power_ctrl(0);
1144
1145                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1146                 break;
1147         default:
1148                 ret = -EINVAL;
1149         }
1150
1151         return ret;
1152 }
1153
1154 /*
1155  * Set new x,y offsets in the virtual display for the visible area and switch
1156  * to the new mode.
1157  */
1158 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1159                              struct fb_info *fbi)
1160 {
1161         int ret = 0;
1162         struct fb_var_screeninfo new_var;
1163         struct da8xx_fb_par         *par = fbi->par;
1164         struct fb_fix_screeninfo    *fix = &fbi->fix;
1165         unsigned int end;
1166         unsigned int start;
1167         unsigned long irq_flags;
1168
1169         if (var->xoffset != fbi->var.xoffset ||
1170                         var->yoffset != fbi->var.yoffset) {
1171                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1172                 new_var.xoffset = var->xoffset;
1173                 new_var.yoffset = var->yoffset;
1174                 if (fb_check_var(&new_var, fbi))
1175                         ret = -EINVAL;
1176                 else {
1177                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1178
1179                         start   = fix->smem_start +
1180                                 new_var.yoffset * fix->line_length +
1181                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1182                         end     = start + fbi->var.yres * fix->line_length - 1;
1183                         par->dma_start  = start;
1184                         par->dma_end    = end;
1185                         spin_lock_irqsave(&par->lock_for_chan_update,
1186                                         irq_flags);
1187                         if (par->which_dma_channel_done == 0) {
1188                                 lcdc_write(par->dma_start,
1189                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1190                                 lcdc_write(par->dma_end,
1191                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1192                         } else if (par->which_dma_channel_done == 1) {
1193                                 lcdc_write(par->dma_start,
1194                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1195                                 lcdc_write(par->dma_end,
1196                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1197                         }
1198                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1199                                         irq_flags);
1200                 }
1201         }
1202
1203         return ret;
1204 }
1205
1206 static int da8xxfb_set_par(struct fb_info *info)
1207 {
1208         struct da8xx_fb_par *par = info->par;
1209         int ret;
1210         bool raster = da8xx_fb_is_raster_enabled();
1211
1212         if (raster)
1213                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1214
1215         fb_var_to_videomode(&par->mode, &info->var);
1216
1217         par->cfg.bpp = info->var.bits_per_pixel;
1218
1219         info->fix.visual = (par->cfg.bpp <= 8) ?
1220                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1221         info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1222
1223         ret = lcd_init(par, &par->cfg, &par->mode);
1224         if (ret < 0) {
1225                 dev_err(par->dev, "lcd init failed\n");
1226                 return ret;
1227         }
1228
1229         par->dma_start = info->fix.smem_start +
1230                          info->var.yoffset * info->fix.line_length +
1231                          info->var.xoffset * info->var.bits_per_pixel / 8;
1232         par->dma_end   = par->dma_start +
1233                          info->var.yres * info->fix.line_length - 1;
1234
1235         lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1236         lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1237         lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1238         lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1239
1240         if (raster)
1241                 lcd_enable_raster();
1242
1243         return 0;
1244 }
1245
1246 static struct fb_ops da8xx_fb_ops = {
1247         .owner = THIS_MODULE,
1248         .fb_check_var = fb_check_var,
1249         .fb_set_par = da8xxfb_set_par,
1250         .fb_setcolreg = fb_setcolreg,
1251         .fb_pan_display = da8xx_pan_display,
1252         .fb_ioctl = fb_ioctl,
1253         .fb_fillrect = cfb_fillrect,
1254         .fb_copyarea = cfb_copyarea,
1255         .fb_imageblit = cfb_imageblit,
1256         .fb_blank = cfb_blank,
1257 };
1258
1259 static int fb_probe(struct platform_device *device)
1260 {
1261         struct da8xx_lcdc_platform_data *fb_pdata =
1262                                                 device->dev.platform_data;
1263         struct lcd_ctrl_config *lcd_cfg;
1264         struct fb_videomode *lcdc_info;
1265         struct fb_info *da8xx_fb_info;
1266         struct clk *fb_clk = NULL;
1267         struct da8xx_fb_par *par;
1268         resource_size_t len;
1269         int ret, i;
1270         unsigned long ulcm;
1271
1272         if (fb_pdata == NULL) {
1273                 dev_err(&device->dev, "Can not get platform data\n");
1274                 return -ENOENT;
1275         }
1276
1277         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1278         if (!lcdc_regs) {
1279                 dev_err(&device->dev,
1280                         "Can not get memory resource for LCD controller\n");
1281                 return -ENOENT;
1282         }
1283
1284         len = resource_size(lcdc_regs);
1285
1286         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1287         if (!lcdc_regs)
1288                 return -EBUSY;
1289
1290         da8xx_fb_reg_base = ioremap(lcdc_regs->start, len);
1291         if (!da8xx_fb_reg_base) {
1292                 ret = -EBUSY;
1293                 goto err_request_mem;
1294         }
1295
1296         fb_clk = clk_get(&device->dev, "fck");
1297         if (IS_ERR(fb_clk)) {
1298                 dev_err(&device->dev, "Can not get device clock\n");
1299                 ret = -ENODEV;
1300                 goto err_ioremap;
1301         }
1302
1303         pm_runtime_enable(&device->dev);
1304         pm_runtime_get_sync(&device->dev);
1305
1306         /* Determine LCD IP Version */
1307         switch (lcdc_read(LCD_PID_REG)) {
1308         case 0x4C100102:
1309                 lcd_revision = LCD_VERSION_1;
1310                 break;
1311         case 0x4F200800:
1312         case 0x4F201000:
1313                 lcd_revision = LCD_VERSION_2;
1314                 break;
1315         default:
1316                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1317                                 "defaulting to LCD revision 1\n",
1318                                 lcdc_read(LCD_PID_REG));
1319                 lcd_revision = LCD_VERSION_1;
1320                 break;
1321         }
1322
1323         for (i = 0, lcdc_info = known_lcd_panels;
1324                 i < ARRAY_SIZE(known_lcd_panels);
1325                 i++, lcdc_info++) {
1326                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1327                         break;
1328         }
1329
1330         if (i == ARRAY_SIZE(known_lcd_panels)) {
1331                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1332                 ret = -ENODEV;
1333                 goto err_pm_runtime_disable;
1334         } else
1335                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1336                                         fb_pdata->type);
1337
1338         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1339
1340         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1341                                         &device->dev);
1342         if (!da8xx_fb_info) {
1343                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1344                 ret = -ENOMEM;
1345                 goto err_pm_runtime_disable;
1346         }
1347
1348         par = da8xx_fb_info->par;
1349         par->dev = &device->dev;
1350         par->lcdc_clk = fb_clk;
1351         par->lcd_fck_rate = clk_get_rate(fb_clk);
1352         if (fb_pdata->panel_power_ctrl) {
1353                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1354                 par->panel_power_ctrl(1);
1355         }
1356
1357         fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1358         par->cfg = *lcd_cfg;
1359
1360         da8xx_fb_lcd_reset();
1361
1362         /* allocate frame buffer */
1363         par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1364         ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1365         par->vram_size = roundup(par->vram_size/8, ulcm);
1366         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1367
1368         par->vram_virt = dma_alloc_coherent(NULL,
1369                                             par->vram_size,
1370                                             (resource_size_t *) &par->vram_phys,
1371                                             GFP_KERNEL | GFP_DMA);
1372         if (!par->vram_virt) {
1373                 dev_err(&device->dev,
1374                         "GLCD: kmalloc for frame buffer failed\n");
1375                 ret = -EINVAL;
1376                 goto err_release_fb;
1377         }
1378
1379         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1380         da8xx_fb_fix.smem_start    = par->vram_phys;
1381         da8xx_fb_fix.smem_len      = par->vram_size;
1382         da8xx_fb_fix.line_length   = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1383
1384         par->dma_start = par->vram_phys;
1385         par->dma_end   = par->dma_start + lcdc_info->yres *
1386                 da8xx_fb_fix.line_length - 1;
1387
1388         /* allocate palette buffer */
1389         par->v_palette_base = dma_alloc_coherent(NULL,
1390                                                PALETTE_SIZE,
1391                                                (resource_size_t *)
1392                                                &par->p_palette_base,
1393                                                GFP_KERNEL | GFP_DMA);
1394         if (!par->v_palette_base) {
1395                 dev_err(&device->dev,
1396                         "GLCD: kmalloc for palette buffer failed\n");
1397                 ret = -EINVAL;
1398                 goto err_release_fb_mem;
1399         }
1400         memset(par->v_palette_base, 0, PALETTE_SIZE);
1401
1402         par->irq = platform_get_irq(device, 0);
1403         if (par->irq < 0) {
1404                 ret = -ENOENT;
1405                 goto err_release_pl_mem;
1406         }
1407
1408         da8xx_fb_var.grayscale =
1409             lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1410         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1411
1412         /* Initialize fbinfo */
1413         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1414         da8xx_fb_info->fix = da8xx_fb_fix;
1415         da8xx_fb_info->var = da8xx_fb_var;
1416         da8xx_fb_info->fbops = &da8xx_fb_ops;
1417         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1418         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1419                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1420
1421         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1422         if (ret)
1423                 goto err_release_pl_mem;
1424         da8xx_fb_info->cmap.len = par->palette_sz;
1425
1426         /* initialize var_screeninfo */
1427         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1428         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1429
1430         dev_set_drvdata(&device->dev, da8xx_fb_info);
1431
1432         /* initialize the vsync wait queue */
1433         init_waitqueue_head(&par->vsync_wait);
1434         par->vsync_timeout = HZ / 5;
1435         par->which_dma_channel_done = -1;
1436         spin_lock_init(&par->lock_for_chan_update);
1437
1438         /* Register the Frame Buffer  */
1439         if (register_framebuffer(da8xx_fb_info) < 0) {
1440                 dev_err(&device->dev,
1441                         "GLCD: Frame Buffer Registration Failed!\n");
1442                 ret = -EINVAL;
1443                 goto err_dealloc_cmap;
1444         }
1445
1446 #ifdef CONFIG_CPU_FREQ
1447         ret = lcd_da8xx_cpufreq_register(par);
1448         if (ret) {
1449                 dev_err(&device->dev, "failed to register cpufreq\n");
1450                 goto err_cpu_freq;
1451         }
1452 #endif
1453
1454         if (lcd_revision == LCD_VERSION_1)
1455                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1456         else {
1457                 init_waitqueue_head(&frame_done_wq);
1458                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1459         }
1460
1461         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1462                         DRIVER_NAME, par);
1463         if (ret)
1464                 goto irq_freq;
1465         return 0;
1466
1467 irq_freq:
1468 #ifdef CONFIG_CPU_FREQ
1469         lcd_da8xx_cpufreq_deregister(par);
1470 err_cpu_freq:
1471 #endif
1472         unregister_framebuffer(da8xx_fb_info);
1473
1474 err_dealloc_cmap:
1475         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1476
1477 err_release_pl_mem:
1478         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1479                           par->p_palette_base);
1480
1481 err_release_fb_mem:
1482         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1483
1484 err_release_fb:
1485         framebuffer_release(da8xx_fb_info);
1486
1487 err_pm_runtime_disable:
1488         pm_runtime_put_sync(&device->dev);
1489         pm_runtime_disable(&device->dev);
1490
1491 err_ioremap:
1492         iounmap(da8xx_fb_reg_base);
1493
1494 err_request_mem:
1495         release_mem_region(lcdc_regs->start, len);
1496
1497         return ret;
1498 }
1499
1500 #ifdef CONFIG_PM
1501 struct lcdc_context {
1502         u32 clk_enable;
1503         u32 ctrl;
1504         u32 dma_ctrl;
1505         u32 raster_timing_0;
1506         u32 raster_timing_1;
1507         u32 raster_timing_2;
1508         u32 int_enable_set;
1509         u32 dma_frm_buf_base_addr_0;
1510         u32 dma_frm_buf_ceiling_addr_0;
1511         u32 dma_frm_buf_base_addr_1;
1512         u32 dma_frm_buf_ceiling_addr_1;
1513         u32 raster_ctrl;
1514 } reg_context;
1515
1516 static void lcd_context_save(void)
1517 {
1518         if (lcd_revision == LCD_VERSION_2) {
1519                 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1520                 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1521         }
1522
1523         reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1524         reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1525         reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1526         reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1527         reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1528         reg_context.dma_frm_buf_base_addr_0 =
1529                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1530         reg_context.dma_frm_buf_ceiling_addr_0 =
1531                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1532         reg_context.dma_frm_buf_base_addr_1 =
1533                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1534         reg_context.dma_frm_buf_ceiling_addr_1 =
1535                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1536         reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1537         return;
1538 }
1539
1540 static void lcd_context_restore(void)
1541 {
1542         if (lcd_revision == LCD_VERSION_2) {
1543                 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1544                 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1545         }
1546
1547         lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1548         lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1549         lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1550         lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1551         lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1552         lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1553                         LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1554         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1555                         LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1556         lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1557                         LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1558         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1559                         LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1560         lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1561         return;
1562 }
1563
1564 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1565 {
1566         struct fb_info *info = platform_get_drvdata(dev);
1567         struct da8xx_fb_par *par = info->par;
1568
1569         console_lock();
1570         if (par->panel_power_ctrl)
1571                 par->panel_power_ctrl(0);
1572
1573         fb_set_suspend(info, 1);
1574         lcd_disable_raster(DA8XX_FRAME_WAIT);
1575         lcd_context_save();
1576         pm_runtime_put_sync(&dev->dev);
1577         console_unlock();
1578
1579         return 0;
1580 }
1581 static int fb_resume(struct platform_device *dev)
1582 {
1583         struct fb_info *info = platform_get_drvdata(dev);
1584         struct da8xx_fb_par *par = info->par;
1585
1586         console_lock();
1587         pm_runtime_get_sync(&dev->dev);
1588         lcd_context_restore();
1589         if (par->blank == FB_BLANK_UNBLANK) {
1590                 lcd_enable_raster();
1591
1592                 if (par->panel_power_ctrl)
1593                         par->panel_power_ctrl(1);
1594         }
1595
1596         fb_set_suspend(info, 0);
1597         console_unlock();
1598
1599         return 0;
1600 }
1601 #else
1602 #define fb_suspend NULL
1603 #define fb_resume NULL
1604 #endif
1605
1606 static struct platform_driver da8xx_fb_driver = {
1607         .probe = fb_probe,
1608         .remove = fb_remove,
1609         .suspend = fb_suspend,
1610         .resume = fb_resume,
1611         .driver = {
1612                    .name = DRIVER_NAME,
1613                    .owner = THIS_MODULE,
1614                    },
1615 };
1616
1617 static int __init da8xx_fb_init(void)
1618 {
1619         return platform_driver_register(&da8xx_fb_driver);
1620 }
1621
1622 static void __exit da8xx_fb_cleanup(void)
1623 {
1624         platform_driver_unregister(&da8xx_fb_driver);
1625 }
1626
1627 module_init(da8xx_fb_init);
1628 module_exit(da8xx_fb_cleanup);
1629
1630 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1631 MODULE_AUTHOR("Texas Instruments");
1632 MODULE_LICENSE("GPL");