2 * VFIO PCI config space virtualization
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
32 #include "vfio_pci_private.h"
34 #define PCI_CFG_SPACE_SIZE 256
36 /* Fake capability ID for standard config space */
37 #define PCI_CAP_ID_BASIC 0
39 #define is_bar(offset) \
40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
44 * Lengths of PCI Config Capabilities
45 * 0: Removed from the user visible capability list
48 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
49 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
50 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
51 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
52 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
53 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
54 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
55 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
57 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
58 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
59 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
60 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
61 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
62 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
63 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
64 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
65 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
66 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
67 [PCI_CAP_ID_SATA] = 0xFF,
68 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
72 * Lengths of PCIe/PCI-X Extended Config Capabilities
73 * 0: Removed or masked from the user visible capabilty list
76 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
77 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
78 [PCI_EXT_CAP_ID_VC] = 0xFF,
79 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
80 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
81 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
85 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
86 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
87 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
88 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
89 [PCI_EXT_CAP_ID_ACS] = 0xFF,
90 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
91 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
92 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
93 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
94 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
95 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
96 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
98 [PCI_EXT_CAP_ID_DPA] = 0xFF,
99 [PCI_EXT_CAP_ID_TPH] = 0xFF,
100 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
101 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
102 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
107 * Read/Write Permission Bits - one bit for each bit in capability
108 * Any field can be read if it exists, but what is read depends on
109 * whether the field is 'virtualized', or just pass thru to the
110 * hardware. Any virtualized field is also virtualized for writes.
111 * Writes are only permitted if they have a 1 bit here.
114 u8 *virt; /* read/write virtual data, not hw */
115 u8 *write; /* writeable bits */
116 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
117 struct perm_bits *perm, int offset, __le32 *val);
118 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
119 struct perm_bits *perm, int offset, __le32 val);
123 #define ALL_VIRT 0xFFFFFFFFU
125 #define ALL_WRITE 0xFFFFFFFFU
127 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
128 __le32 *val, int count)
137 ret = pci_user_read_config_byte(pdev, offset, &tmp);
144 ret = pci_user_read_config_word(pdev, offset, &tmp);
149 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
153 *val = cpu_to_le32(tmp_val);
155 return pcibios_err_to_errno(ret);
158 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
159 __le32 val, int count)
162 u32 tmp_val = le32_to_cpu(val);
166 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
169 ret = pci_user_write_config_word(pdev, offset, tmp_val);
172 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
176 return pcibios_err_to_errno(ret);
179 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
180 int count, struct perm_bits *perm,
181 int offset, __le32 *val)
185 memcpy(val, vdev->vconfig + pos, count);
187 memcpy(&virt, perm->virt + offset, count);
189 /* Any non-virtualized bits? */
190 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
191 struct pci_dev *pdev = vdev->pdev;
195 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
199 *val = (phys_val & ~virt) | (*val & virt);
205 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
206 int count, struct perm_bits *perm,
207 int offset, __le32 val)
209 __le32 virt = 0, write = 0;
211 memcpy(&write, perm->write + offset, count);
214 return count; /* drop, no writable bits */
216 memcpy(&virt, perm->virt + offset, count);
218 /* Virtualized and writable bits go to vconfig */
222 memcpy(&virt_val, vdev->vconfig + pos, count);
224 virt_val &= ~(write & virt);
225 virt_val |= (val & (write & virt));
227 memcpy(vdev->vconfig + pos, &virt_val, count);
230 /* Non-virtualzed and writable bits go to hardware */
232 struct pci_dev *pdev = vdev->pdev;
236 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
240 phys_val &= ~(write & ~virt);
241 phys_val |= (val & (write & ~virt));
243 ret = vfio_user_config_write(pdev, pos, phys_val, count);
251 /* Allow direct read from hardware, except for capability next pointer */
252 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
253 int count, struct perm_bits *perm,
254 int offset, __le32 *val)
258 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
260 return pcibios_err_to_errno(ret);
262 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
264 memcpy(val, vdev->vconfig + pos, count);
265 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
266 if (offset == PCI_CAP_LIST_ID && count > 1)
267 memcpy(val, vdev->vconfig + pos,
268 min(PCI_CAP_FLAGS, count));
269 else if (offset == PCI_CAP_LIST_NEXT)
270 memcpy(val, vdev->vconfig + pos, 1);
276 /* Raw access skips any kind of virtualization */
277 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
278 int count, struct perm_bits *perm,
279 int offset, __le32 val)
283 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
290 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
291 int count, struct perm_bits *perm,
292 int offset, __le32 *val)
296 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
298 return pcibios_err_to_errno(ret);
303 /* Virt access uses only virtualization */
304 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
305 int count, struct perm_bits *perm,
306 int offset, __le32 val)
308 memcpy(vdev->vconfig + pos, &val, count);
312 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
313 int count, struct perm_bits *perm,
314 int offset, __le32 *val)
316 memcpy(val, vdev->vconfig + pos, count);
320 /* Default capability regions to read-only, no-virtualization */
321 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
322 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
324 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
325 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
328 * Default unassigned regions to raw read-write access. Some devices
329 * require this to function as they hide registers between the gaps in
330 * config space (be2net). Like MMIO and I/O port registers, we have
331 * to trust the hardware isolation.
333 static struct perm_bits unassigned_perms = {
334 .readfn = vfio_raw_config_read,
335 .writefn = vfio_raw_config_write
338 static struct perm_bits virt_perms = {
339 .readfn = vfio_virt_config_read,
340 .writefn = vfio_virt_config_write
343 static void free_perm_bits(struct perm_bits *perm)
351 static int alloc_perm_bits(struct perm_bits *perm, int size)
354 * Round up all permission bits to the next dword, this lets us
355 * ignore whether a read/write exceeds the defined capability
356 * structure. We can do this because:
357 * - Standard config space is already dword aligned
358 * - Capabilities are all dword alinged (bits 0:1 of next reserved)
359 * - Express capabilities defined as dword aligned
361 size = round_up(size, 4);
365 * - All Readable, None Writeable, None Virtualized
367 perm->virt = kzalloc(size, GFP_KERNEL);
368 perm->write = kzalloc(size, GFP_KERNEL);
369 if (!perm->virt || !perm->write) {
370 free_perm_bits(perm);
374 perm->readfn = vfio_default_config_read;
375 perm->writefn = vfio_default_config_write;
381 * Helper functions for filling in permission tables
383 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
386 p->write[off] = write;
389 /* Handle endian-ness - pci and tables are little-endian */
390 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
392 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
393 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
396 /* Handle endian-ness - pci and tables are little-endian */
397 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
399 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
400 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
404 * Restore the *real* BARs after we detect a FLR or backdoor reset.
405 * (backdoor = some device specific technique that we didn't catch)
407 static void vfio_bar_restore(struct vfio_pci_device *vdev)
409 struct pci_dev *pdev = vdev->pdev;
410 u32 *rbar = vdev->rbar;
416 pr_info("%s: %s reset recovery - restoring bars\n",
417 __func__, dev_name(&pdev->dev));
419 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
420 pci_user_write_config_dword(pdev, i, *rbar);
422 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
425 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
427 unsigned long flags = pci_resource_flags(pdev, bar);
430 if (flags & IORESOURCE_IO)
431 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
433 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
435 if (flags & IORESOURCE_PREFETCH)
436 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
438 if (flags & IORESOURCE_MEM_64)
439 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
441 return cpu_to_le32(val);
445 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
446 * to reflect the hardware capabilities. This implements BAR sizing.
448 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
450 struct pci_dev *pdev = vdev->pdev;
455 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
457 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
458 if (!pci_resource_start(pdev, i)) {
459 *bar = 0; /* Unmapped by host = unimplemented to user */
463 mask = ~(pci_resource_len(pdev, i) - 1);
465 *bar &= cpu_to_le32((u32)mask);
466 *bar |= vfio_generate_bar_flags(pdev, i);
468 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
470 *bar &= cpu_to_le32((u32)(mask >> 32));
475 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
478 * NB. we expose the actual BAR size here, regardless of whether
479 * we can read it. When we report the REGION_INFO for the ROM
480 * we report what PCI tells us is the actual ROM size.
482 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
483 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
484 mask |= PCI_ROM_ADDRESS_ENABLE;
485 *bar &= cpu_to_le32((u32)mask);
489 vdev->bardirty = false;
492 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
493 int count, struct perm_bits *perm,
494 int offset, __le32 *val)
496 if (is_bar(offset)) /* pos == offset for basic config */
497 vfio_bar_fixup(vdev);
499 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
501 /* Mask in virtual memory enable for SR-IOV devices */
502 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
503 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
504 u32 tmp_val = le32_to_cpu(*val);
506 tmp_val |= cmd & PCI_COMMAND_MEMORY;
507 *val = cpu_to_le32(tmp_val);
513 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
514 int count, struct perm_bits *perm,
515 int offset, __le32 val)
517 struct pci_dev *pdev = vdev->pdev;
522 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
524 if (offset == PCI_COMMAND) {
525 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
528 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
532 new_cmd = le32_to_cpu(val);
534 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
535 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
536 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
538 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
539 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
540 new_io = !!(new_cmd & PCI_COMMAND_IO);
543 * If the user is writing mem/io enable (new_mem/io) and we
544 * think it's already enabled (virt_mem/io), but the hardware
545 * shows it disabled (phys_mem/io, then the device has
546 * undergone some kind of backdoor reset and needs to be
547 * restored before we allow it to enable the bars.
548 * SR-IOV devices will trigger this, but we catch them later
550 if ((new_mem && virt_mem && !phys_mem) ||
551 (new_io && virt_io && !phys_io))
552 vfio_bar_restore(vdev);
555 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
560 * Save current memory/io enable bits in vconfig to allow for
561 * the test above next time.
563 if (offset == PCI_COMMAND) {
564 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
566 *virt_cmd &= cpu_to_le16(~mask);
567 *virt_cmd |= cpu_to_le16(new_cmd & mask);
570 /* Emulate INTx disable */
571 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
572 bool virt_intx_disable;
574 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
575 PCI_COMMAND_INTX_DISABLE);
577 if (virt_intx_disable && !vdev->virq_disabled) {
578 vdev->virq_disabled = true;
579 vfio_pci_intx_mask(vdev);
580 } else if (!virt_intx_disable && vdev->virq_disabled) {
581 vdev->virq_disabled = false;
582 vfio_pci_intx_unmask(vdev);
587 vdev->bardirty = true;
592 /* Permissions for the Basic PCI Header */
593 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
595 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
598 perm->readfn = vfio_basic_config_read;
599 perm->writefn = vfio_basic_config_write;
601 /* Virtualized for SR-IOV functions, which just have FFFF */
602 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
603 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
606 * Virtualize INTx disable, we use it internally for interrupt
607 * control and can emulate it for non-PCI 2.3 devices.
609 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
611 /* Virtualize capability list, we might want to skip/disable */
612 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
614 /* No harm to write */
615 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
616 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
617 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
619 /* Virtualize all bars, can't touch the real ones */
620 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
621 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
622 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
623 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
624 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
625 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
626 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
628 /* Allow us to adjust capability chain */
629 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
631 /* Sometimes used by sw, just virtualize */
632 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
634 /* Virtualize interrupt pin to allow hiding INTx */
635 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
640 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
641 int count, struct perm_bits *perm,
642 int offset, __le32 val)
644 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
648 if (offset == PCI_PM_CTRL) {
651 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
666 pci_set_power_state(vdev->pdev, state);
672 /* Permissions for the Power Management capability */
673 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
675 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
678 perm->writefn = vfio_pm_config_write;
681 * We always virtualize the next field so we can remove
682 * capabilities from the chain if we want to.
684 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
687 * Power management is defined *per function*, so we can let
688 * the user change power state, but we trap and initiate the
689 * change ourselves, so the state bits are read-only.
691 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
695 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
696 int count, struct perm_bits *perm,
697 int offset, __le32 val)
699 struct pci_dev *pdev = vdev->pdev;
700 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
701 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
706 * Write through to emulation. If the write includes the upper byte
707 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
710 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
711 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
712 offset + count <= PCI_VPD_ADDR + 1)
715 addr = le16_to_cpu(*paddr);
717 if (addr & PCI_VPD_ADDR_F) {
718 data = le32_to_cpu(*pdata);
719 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
722 if (pci_read_vpd(pdev, addr, 4, &data) != 4)
724 *pdata = cpu_to_le32(data);
728 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
729 * signal completion. If an error occurs above, we assume that not
730 * toggling this bit will induce a driver timeout.
732 addr ^= PCI_VPD_ADDR_F;
733 *paddr = cpu_to_le16(addr);
738 /* Permissions for Vital Product Data capability */
739 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
741 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
744 perm->writefn = vfio_vpd_config_write;
747 * We always virtualize the next field so we can remove
748 * capabilities from the chain if we want to.
750 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
753 * Both the address and data registers are virtualized to
754 * enable access through the pci_vpd_read/write functions
756 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
757 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
762 /* Permissions for PCI-X capability */
763 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
765 /* Alloc 24, but only 8 are used in v0 */
766 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
769 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
771 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
772 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
776 /* Permissions for PCI Express capability */
777 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
779 /* Alloc larger of two possible sizes */
780 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
783 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
786 * Allow writes to device control fields (includes FLR!)
787 * but not to devctl_phantom which could confuse IOMMU
788 * or to the ARI bit in devctl2 which is set at probe time
790 p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM);
791 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
795 /* Permissions for Advanced Function capability */
796 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
798 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
801 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
802 p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR);
806 /* Permissions for Advanced Error Reporting extended capability */
807 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
811 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
815 * Virtualize the first dword of all express capabilities
816 * because it includes the next pointer. This lets us later
817 * remove capabilities from the chain if we need to.
819 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
821 /* Writable bits mask */
822 mask = PCI_ERR_UNC_UND | /* Undefined */
823 PCI_ERR_UNC_DLP | /* Data Link Protocol */
824 PCI_ERR_UNC_SURPDN | /* Surprise Down */
825 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
826 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
827 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
828 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
829 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
830 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
831 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
832 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
833 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
834 PCI_ERR_UNC_ACSV | /* ACS Violation */
835 PCI_ERR_UNC_INTN | /* internal error */
836 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
837 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
838 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
839 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
840 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
841 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
843 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
844 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
845 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
846 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
847 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
848 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
849 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
850 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
851 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
852 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
854 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
855 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
856 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
860 /* Permissions for Power Budgeting extended capability */
861 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
863 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
866 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
868 /* Writing the data selector is OK, the info is still read-only */
869 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
874 * Initialize the shared permission tables
876 void vfio_pci_uninit_perm_bits(void)
878 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
880 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
881 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
882 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
883 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
884 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
886 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
887 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
890 int __init vfio_pci_init_perm_bits(void)
894 /* Basic config space */
895 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
898 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
899 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
900 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
901 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
902 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
903 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
905 /* Extended capabilities */
906 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
907 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
908 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
911 vfio_pci_uninit_perm_bits();
916 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
919 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
920 PCI_STD_HEADER_SIZEOF;
921 cap = vdev->pci_config_map[pos];
923 if (cap == PCI_CAP_ID_BASIC)
926 /* XXX Can we have to abutting capabilities of the same type? */
927 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
933 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
934 int count, struct perm_bits *perm,
935 int offset, __le32 *val)
937 /* Update max available queue size from msi_qmax */
938 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
942 start = vfio_find_cap_start(vdev, pos);
944 flags = (__le16 *)&vdev->vconfig[start];
946 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
947 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
950 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
953 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
954 int count, struct perm_bits *perm,
955 int offset, __le32 val)
957 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
961 /* Fixup and write configured queue size and enable to hardware */
962 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
967 start = vfio_find_cap_start(vdev, pos);
969 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
971 flags = le16_to_cpu(*pflags);
973 /* MSI is enabled via ioctl */
975 flags &= ~PCI_MSI_FLAGS_ENABLE;
977 /* Check queue size */
978 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
979 flags &= ~PCI_MSI_FLAGS_QSIZE;
980 flags |= vdev->msi_qmax << 4;
983 /* Write back to virt and to hardware */
984 *pflags = cpu_to_le16(flags);
985 ret = pci_user_write_config_word(vdev->pdev,
986 start + PCI_MSI_FLAGS,
989 return pcibios_err_to_errno(ret);
996 * MSI determination is per-device, so this routine gets used beyond
997 * initialization time. Don't add __init
999 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1001 if (alloc_perm_bits(perm, len))
1004 perm->readfn = vfio_msi_config_read;
1005 perm->writefn = vfio_msi_config_write;
1007 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1010 * The upper byte of the control register is reserved,
1011 * just setup the lower byte.
1013 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1014 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1015 if (flags & PCI_MSI_FLAGS_64BIT) {
1016 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1017 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1018 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1019 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1020 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1023 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1024 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1025 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1026 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1032 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1033 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1035 struct pci_dev *pdev = vdev->pdev;
1039 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1041 return pcibios_err_to_errno(ret);
1043 len = 10; /* Minimum size */
1044 if (flags & PCI_MSI_FLAGS_64BIT)
1046 if (flags & PCI_MSI_FLAGS_MASKBIT)
1052 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1053 if (!vdev->msi_perm)
1056 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1063 /* Determine extended capability length for VC (2 & 9) and MFVC */
1064 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1066 struct pci_dev *pdev = vdev->pdev;
1068 int ret, evcc, phases, vc_arb;
1069 int len = PCI_CAP_VC_BASE_SIZEOF;
1071 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1073 return pcibios_err_to_errno(ret);
1075 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1076 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1078 return pcibios_err_to_errno(ret);
1080 if (tmp & PCI_VC_CAP2_128_PHASE)
1082 else if (tmp & PCI_VC_CAP2_64_PHASE)
1084 else if (tmp & PCI_VC_CAP2_32_PHASE)
1089 vc_arb = phases * 4;
1092 * Port arbitration tables are root & switch only;
1093 * function arbitration tables are function 0 only.
1094 * In either case, we'll never let user write them so
1095 * we don't care how big they are
1097 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1099 len = round_up(len, 16);
1105 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1107 struct pci_dev *pdev = vdev->pdev;
1114 case PCI_CAP_ID_MSI:
1115 return vfio_msi_cap_len(vdev, pos);
1116 case PCI_CAP_ID_PCIX:
1117 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1119 return pcibios_err_to_errno(ret);
1121 if (PCI_X_CMD_VERSION(word)) {
1122 /* Test for extended capabilities */
1123 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1124 vdev->extended_caps = (dword != 0);
1125 return PCI_CAP_PCIX_SIZEOF_V2;
1127 return PCI_CAP_PCIX_SIZEOF_V0;
1128 case PCI_CAP_ID_VNDR:
1129 /* length follows next field */
1130 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1132 return pcibios_err_to_errno(ret);
1135 case PCI_CAP_ID_EXP:
1136 /* Test for extended capabilities */
1137 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1138 vdev->extended_caps = (dword != 0);
1140 /* length based on version */
1141 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1)
1142 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1144 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1146 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1148 return pcibios_err_to_errno(ret);
1150 return (byte & HT_3BIT_CAP_MASK) ?
1151 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1152 case PCI_CAP_ID_SATA:
1153 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1155 return pcibios_err_to_errno(ret);
1157 byte &= PCI_SATA_REGS_MASK;
1158 if (byte == PCI_SATA_REGS_INLINE)
1159 return PCI_SATA_SIZEOF_LONG;
1161 return PCI_SATA_SIZEOF_SHORT;
1163 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1164 dev_name(&pdev->dev), __func__, cap, pos);
1170 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1172 struct pci_dev *pdev = vdev->pdev;
1178 case PCI_EXT_CAP_ID_VNDR:
1179 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1181 return pcibios_err_to_errno(ret);
1183 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1184 case PCI_EXT_CAP_ID_VC:
1185 case PCI_EXT_CAP_ID_VC9:
1186 case PCI_EXT_CAP_ID_MFVC:
1187 return vfio_vc_cap_len(vdev, epos);
1188 case PCI_EXT_CAP_ID_ACS:
1189 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1191 return pcibios_err_to_errno(ret);
1193 if (byte & PCI_ACS_EC) {
1196 ret = pci_read_config_byte(pdev,
1197 epos + PCI_ACS_EGRESS_BITS,
1200 return pcibios_err_to_errno(ret);
1202 bits = byte ? round_up(byte, 32) : 256;
1203 return 8 + (bits / 8);
1207 case PCI_EXT_CAP_ID_REBAR:
1208 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1210 return pcibios_err_to_errno(ret);
1212 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1213 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1215 return 4 + (byte * 8);
1216 case PCI_EXT_CAP_ID_DPA:
1217 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1219 return pcibios_err_to_errno(ret);
1221 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1222 return PCI_DPA_BASE_SIZEOF + byte + 1;
1223 case PCI_EXT_CAP_ID_TPH:
1224 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1226 return pcibios_err_to_errno(ret);
1228 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1231 sts = dword & PCI_TPH_CAP_ST_MASK;
1232 sts >>= PCI_TPH_CAP_ST_SHIFT;
1233 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1235 return PCI_TPH_BASE_SIZEOF;
1237 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1238 dev_name(&pdev->dev), __func__, ecap, epos);
1244 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1245 int offset, int size)
1247 struct pci_dev *pdev = vdev->pdev;
1251 * We try to read physical config space in the largest chunks
1252 * we can, assuming that all of the fields support dword access.
1253 * pci_save_state() makes this same assumption and seems to do ok.
1258 if (size >= 4 && !(offset % 4)) {
1259 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1262 ret = pci_read_config_dword(pdev, offset, &dword);
1265 *dwordp = cpu_to_le32(dword);
1267 } else if (size >= 2 && !(offset % 2)) {
1268 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1271 ret = pci_read_config_word(pdev, offset, &word);
1274 *wordp = cpu_to_le16(word);
1277 u8 *byte = &vdev->vconfig[offset];
1278 ret = pci_read_config_byte(pdev, offset, byte);
1291 static int vfio_cap_init(struct vfio_pci_device *vdev)
1293 struct pci_dev *pdev = vdev->pdev;
1294 u8 *map = vdev->pci_config_map;
1297 int loops, ret, caps = 0;
1299 /* Any capabilities? */
1300 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1304 if (!(status & PCI_STATUS_CAP_LIST))
1305 return 0; /* Done */
1307 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1311 /* Mark the previous position in case we want to skip a capability */
1312 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1314 /* We can bound our loop, capabilities are dword aligned */
1315 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1316 while (pos && loops--) {
1320 ret = pci_read_config_byte(pdev, pos, &cap);
1324 ret = pci_read_config_byte(pdev,
1325 pos + PCI_CAP_LIST_NEXT, &next);
1329 if (cap <= PCI_CAP_ID_MAX) {
1330 len = pci_cap_length[cap];
1331 if (len == 0xFF) { /* Variable length */
1332 len = vfio_cap_len(vdev, cap, pos);
1339 pr_info("%s: %s hiding cap 0x%x\n",
1340 __func__, dev_name(&pdev->dev), cap);
1346 /* Sanity check, do we overlap other capabilities? */
1347 for (i = 0; i < len; i++) {
1348 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1351 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1352 __func__, dev_name(&pdev->dev),
1353 pos + i, map[pos + i], cap);
1356 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1358 memset(map + pos, cap, len);
1359 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1363 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1368 /* If we didn't fill any capabilities, clear the status flag */
1370 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1371 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1377 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1379 struct pci_dev *pdev = vdev->pdev;
1380 u8 *map = vdev->pci_config_map;
1382 __le32 *prev = NULL;
1383 int loops, ret, ecaps = 0;
1385 if (!vdev->extended_caps)
1388 epos = PCI_CFG_SPACE_SIZE;
1390 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1392 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1396 bool hidden = false;
1398 ret = pci_read_config_dword(pdev, epos, &header);
1402 ecap = PCI_EXT_CAP_ID(header);
1404 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1405 len = pci_ext_cap_length[ecap];
1407 len = vfio_ext_cap_len(vdev, ecap, epos);
1414 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1415 __func__, dev_name(&pdev->dev), ecap, epos);
1417 /* If not the first in the chain, we can skip over it */
1419 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1420 *prev &= cpu_to_le32(~(0xffcU << 20));
1421 *prev |= cpu_to_le32(val << 20);
1426 * Otherwise, fill in a placeholder, the direct
1427 * readfn will virtualize this automatically
1429 len = PCI_CAP_SIZEOF;
1433 for (i = 0; i < len; i++) {
1434 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1437 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1438 __func__, dev_name(&pdev->dev),
1439 epos + i, map[epos + i], ecap);
1443 * Even though ecap is 2 bytes, we're currently a long way
1444 * from exceeding 1 byte capabilities. If we ever make it
1445 * up to 0xFE we'll need to up this to a two-byte, byte map.
1447 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1449 memset(map + epos, ecap, len);
1450 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1455 * If we're just using this capability to anchor the list,
1456 * hide the real ID. Only count real ecaps. XXX PCI spec
1457 * indicates to use cap id = 0, version = 0, next = 0 if
1458 * ecaps are absent, hope users check all the way to next.
1461 *(__le32 *)&vdev->vconfig[epos] &=
1462 cpu_to_le32((0xffcU << 20));
1466 prev = (__le32 *)&vdev->vconfig[epos];
1467 epos = PCI_EXT_CAP_NEXT(header);
1471 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1477 * For each device we allocate a pci_config_map that indicates the
1478 * capability occupying each dword and thus the struct perm_bits we
1479 * use for read and write. We also allocate a virtualized config
1480 * space which tracks reads and writes to bits that we emulate for
1481 * the user. Initial values filled from device.
1483 * Using shared stuct perm_bits between all vfio-pci devices saves
1484 * us from allocating cfg_size buffers for virt and write for every
1485 * device. We could remove vconfig and allocate individual buffers
1486 * for each area requring emulated bits, but the array of pointers
1487 * would be comparable in size (at least for standard config space).
1489 int vfio_config_init(struct vfio_pci_device *vdev)
1491 struct pci_dev *pdev = vdev->pdev;
1496 * Config space, caps and ecaps are all dword aligned, so we could
1497 * use one byte per dword to record the type. However, there are
1498 * no requiremenst on the length of a capability, so the gap between
1499 * capabilities needs byte granularity.
1501 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1505 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1511 vdev->pci_config_map = map;
1512 vdev->vconfig = vconfig;
1514 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1515 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1516 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1518 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1522 vdev->bardirty = true;
1525 * XXX can we just pci_load_saved_state/pci_restore_state?
1526 * may need to rebuild vconfig after that
1529 /* For restore after reset */
1530 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1531 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1532 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1533 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1534 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1535 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1536 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1538 if (pdev->is_virtfn) {
1539 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1540 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1543 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX))
1544 vconfig[PCI_INTERRUPT_PIN] = 0;
1546 ret = vfio_cap_init(vdev);
1550 ret = vfio_ecap_init(vdev);
1558 vdev->pci_config_map = NULL;
1560 vdev->vconfig = NULL;
1561 return pcibios_err_to_errno(ret);
1564 void vfio_config_free(struct vfio_pci_device *vdev)
1566 kfree(vdev->vconfig);
1567 vdev->vconfig = NULL;
1568 kfree(vdev->pci_config_map);
1569 vdev->pci_config_map = NULL;
1570 kfree(vdev->msi_perm);
1571 vdev->msi_perm = NULL;
1575 * Find the remaining number of bytes in a dword that match the given
1576 * position. Stop at either the end of the capability or the dword boundary.
1578 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1581 u8 cap = vdev->pci_config_map[pos];
1584 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1590 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1591 size_t count, loff_t *ppos, bool iswrite)
1593 struct pci_dev *pdev = vdev->pdev;
1594 struct perm_bits *perm;
1596 int cap_start = 0, offset;
1600 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1601 *ppos + count > pdev->cfg_size)
1605 * Chop accesses into aligned chunks containing no more than a
1606 * single capability. Caller increments to the next chunk.
1608 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1609 if (count >= 4 && !(*ppos % 4))
1611 else if (count >= 2 && !(*ppos % 2))
1618 cap_id = vdev->pci_config_map[*ppos];
1620 if (cap_id == PCI_CAP_ID_INVALID) {
1621 perm = &unassigned_perms;
1623 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1627 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1628 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1630 perm = &ecap_perms[cap_id];
1631 cap_start = vfio_find_cap_start(vdev, *ppos);
1633 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1635 perm = &cap_perms[cap_id];
1637 if (cap_id == PCI_CAP_ID_MSI)
1638 perm = vdev->msi_perm;
1640 if (cap_id > PCI_CAP_ID_BASIC)
1641 cap_start = vfio_find_cap_start(vdev, *ppos);
1645 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1646 WARN_ON(cap_start > *ppos);
1648 offset = *ppos - cap_start;
1654 if (copy_from_user(&val, buf, count))
1657 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1660 ret = perm->readfn(vdev, *ppos, count,
1661 perm, offset, &val);
1666 if (copy_to_user(buf, &val, count))
1673 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1674 size_t count, loff_t *ppos, bool iswrite)
1680 pos &= VFIO_PCI_OFFSET_MASK;
1683 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);