1 // SPDX-License-Identifier: GPL-2.0+
3 * Allwinner sun4i MUSB Glue Layer
5 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/extcon.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/phy/phy-sun4i-usb.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/soc/sunxi/sunxi_sram.h>
32 #include <linux/usb/musb.h>
33 #include <linux/usb/of.h>
34 #include <linux/usb/usb_phy_generic.h>
35 #include <linux/workqueue.h>
36 #include "musb_core.h"
39 * Register offsets, note sunxi musb has a different layout then most
40 * musb implementations, we translate the layout in musb_readb & friends.
42 #define SUNXI_MUSB_POWER 0x0040
43 #define SUNXI_MUSB_DEVCTL 0x0041
44 #define SUNXI_MUSB_INDEX 0x0042
45 #define SUNXI_MUSB_VEND0 0x0043
46 #define SUNXI_MUSB_INTRTX 0x0044
47 #define SUNXI_MUSB_INTRRX 0x0046
48 #define SUNXI_MUSB_INTRTXE 0x0048
49 #define SUNXI_MUSB_INTRRXE 0x004a
50 #define SUNXI_MUSB_INTRUSB 0x004c
51 #define SUNXI_MUSB_INTRUSBE 0x0050
52 #define SUNXI_MUSB_FRAME 0x0054
53 #define SUNXI_MUSB_TXFIFOSZ 0x0090
54 #define SUNXI_MUSB_TXFIFOADD 0x0092
55 #define SUNXI_MUSB_RXFIFOSZ 0x0094
56 #define SUNXI_MUSB_RXFIFOADD 0x0096
57 #define SUNXI_MUSB_FADDR 0x0098
58 #define SUNXI_MUSB_TXFUNCADDR 0x0098
59 #define SUNXI_MUSB_TXHUBADDR 0x009a
60 #define SUNXI_MUSB_TXHUBPORT 0x009b
61 #define SUNXI_MUSB_RXFUNCADDR 0x009c
62 #define SUNXI_MUSB_RXHUBADDR 0x009e
63 #define SUNXI_MUSB_RXHUBPORT 0x009f
64 #define SUNXI_MUSB_CONFIGDATA 0x00c0
67 #define SUNXI_MUSB_VEND0_PIO_MODE 0
70 #define SUNXI_MUSB_FL_ENABLED 0
71 #define SUNXI_MUSB_FL_HOSTMODE 1
72 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2
73 #define SUNXI_MUSB_FL_VBUS_ON 3
74 #define SUNXI_MUSB_FL_PHY_ON 4
75 #define SUNXI_MUSB_FL_HAS_SRAM 5
76 #define SUNXI_MUSB_FL_HAS_RESET 6
77 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7
78 #define SUNXI_MUSB_FL_PHY_MODE_PEND 8
80 /* Our read/write methods need access and do not get passed in a musb ref :| */
81 static struct musb *sunxi_musb;
86 struct platform_device *musb_pdev;
88 struct reset_control *rst;
90 struct platform_device *usb_phy;
91 struct usb_phy *xceiv;
92 enum phy_mode phy_mode;
94 struct work_struct work;
95 struct extcon_dev *extcon;
96 struct notifier_block host_nb;
99 /* phy_power_on / off may sleep, so we use a workqueue */
100 static void sunxi_musb_work(struct work_struct *work)
102 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
103 bool vbus_on, phy_on;
105 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
108 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
109 struct musb *musb = glue->musb;
113 spin_lock_irqsave(&musb->lock, flags);
115 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
116 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
117 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
118 musb->xceiv->otg->default_a = 1;
119 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
121 devctl |= MUSB_DEVCTL_SESSION;
123 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
124 musb->xceiv->otg->default_a = 0;
125 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
127 devctl &= ~MUSB_DEVCTL_SESSION;
129 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
131 spin_unlock_irqrestore(&musb->lock, flags);
134 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
135 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
137 if (phy_on != vbus_on) {
139 phy_power_on(glue->phy);
140 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
142 phy_power_off(glue->phy);
143 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
147 if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags))
148 phy_set_mode(glue->phy, glue->phy_mode);
151 static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
153 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
156 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
157 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
159 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
162 schedule_work(&glue->work);
165 static void sunxi_musb_pre_root_reset_end(struct musb *musb)
167 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
169 sun4i_usb_phy_set_squelch_detect(glue->phy, false);
172 static void sunxi_musb_post_root_reset_end(struct musb *musb)
174 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
176 sun4i_usb_phy_set_squelch_detect(glue->phy, true);
179 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
181 struct musb *musb = __hci;
184 spin_lock_irqsave(&musb->lock, flags);
186 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
188 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
190 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
191 /* ep0 FADDR must be 0 when (re)entering peripheral mode */
192 musb_ep_select(musb->mregs, 0);
193 musb_writeb(musb->mregs, MUSB_FADDR, 0);
196 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
198 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
200 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
202 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
204 musb_interrupt(musb);
206 spin_unlock_irqrestore(&musb->lock, flags);
211 static int sunxi_musb_host_notifier(struct notifier_block *nb,
212 unsigned long event, void *ptr)
214 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
217 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
219 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
221 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
222 schedule_work(&glue->work);
227 static int sunxi_musb_init(struct musb *musb)
229 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
233 musb->phy = glue->phy;
234 musb->xceiv = glue->xceiv;
236 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
237 ret = sunxi_sram_claim(musb->controller->parent);
242 ret = clk_prepare_enable(glue->clk);
244 goto error_sram_release;
246 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
247 ret = reset_control_deassert(glue->rst);
249 goto error_clk_disable;
252 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
254 /* Register notifier before calling phy_init() */
255 ret = devm_extcon_register_notifier(glue->dev, glue->extcon,
256 EXTCON_USB_HOST, &glue->host_nb);
258 goto error_reset_assert;
260 ret = phy_init(glue->phy);
262 goto error_reset_assert;
264 musb->isr = sunxi_musb_interrupt;
266 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
267 pm_runtime_get(musb->controller);
272 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
273 reset_control_assert(glue->rst);
275 clk_disable_unprepare(glue->clk);
277 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
278 sunxi_sram_release(musb->controller->parent);
282 static int sunxi_musb_exit(struct musb *musb)
284 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
286 pm_runtime_put(musb->controller);
288 cancel_work_sync(&glue->work);
289 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
290 phy_power_off(glue->phy);
294 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
295 reset_control_assert(glue->rst);
297 clk_disable_unprepare(glue->clk);
298 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
299 sunxi_sram_release(musb->controller->parent);
301 devm_usb_put_phy(glue->dev, glue->xceiv);
306 static void sunxi_musb_enable(struct musb *musb)
308 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
312 /* musb_core does not call us in a balanced manner */
313 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
316 schedule_work(&glue->work);
319 static void sunxi_musb_disable(struct musb *musb)
321 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
323 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
326 static struct dma_controller *
327 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base)
332 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
336 static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
338 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
339 enum phy_mode new_mode;
343 new_mode = PHY_MODE_USB_HOST;
345 case MUSB_PERIPHERAL:
346 new_mode = PHY_MODE_USB_DEVICE;
349 new_mode = PHY_MODE_USB_OTG;
352 dev_err(musb->controller->parent,
353 "Error requested mode not supported by this kernel\n");
357 if (glue->phy_mode == new_mode)
360 if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE) {
361 dev_err(musb->controller->parent,
362 "Error changing modes is only supported in dual role mode\n");
366 if (musb->port1_status & USB_PORT_STAT_ENABLE)
367 musb_root_disconnect(musb);
370 * phy_set_mode may sleep, and we're called with a spinlock held,
371 * so let sunxi_musb_work deal with it.
373 glue->phy_mode = new_mode;
374 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
375 schedule_work(&glue->work);
380 static int sunxi_musb_recover(struct musb *musb)
382 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
385 * Schedule a phy_set_mode with the current glue->phy_mode value,
386 * this will force end the current session.
388 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
389 schedule_work(&glue->work);
395 * sunxi musb register layout
396 * 0x00 - 0x17 fifo regs, 1 long per fifo
397 * 0x40 - 0x57 generic control regs (power - frame)
398 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
399 * 0x90 - 0x97 fifo control regs (indexed)
400 * 0x98 - 0x9f multipoint / busctl regs (indexed)
401 * 0xc0 configdata reg
404 static u32 sunxi_musb_fifo_offset(u8 epnum)
409 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
411 WARN_ONCE(offset != 0,
412 "sunxi_musb_ep_offset called with non 0 offset\n");
414 return 0x80; /* indexed, so ignore epnum */
417 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
419 return SUNXI_MUSB_TXFUNCADDR + offset;
422 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
424 struct sunxi_glue *glue;
426 if (addr == sunxi_musb->mregs) {
427 /* generic control or fifo control reg access */
430 return readb(addr + SUNXI_MUSB_FADDR);
432 return readb(addr + SUNXI_MUSB_POWER);
434 return readb(addr + SUNXI_MUSB_INTRUSB);
436 return readb(addr + SUNXI_MUSB_INTRUSBE);
438 return readb(addr + SUNXI_MUSB_INDEX);
440 return 0; /* No testmode on sunxi */
442 return readb(addr + SUNXI_MUSB_DEVCTL);
444 return readb(addr + SUNXI_MUSB_TXFIFOSZ);
446 return readb(addr + SUNXI_MUSB_RXFIFOSZ);
447 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
448 glue = dev_get_drvdata(sunxi_musb->controller->parent);
449 /* A33 saves a reg, and we get to hardcode this */
450 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
454 return readb(addr + SUNXI_MUSB_CONFIGDATA);
455 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
456 case SUNXI_MUSB_TXFUNCADDR:
457 case SUNXI_MUSB_TXHUBADDR:
458 case SUNXI_MUSB_TXHUBPORT:
459 case SUNXI_MUSB_RXFUNCADDR:
460 case SUNXI_MUSB_RXHUBADDR:
461 case SUNXI_MUSB_RXHUBPORT:
462 /* multipoint / busctl reg access */
463 return readb(addr + offset);
465 dev_err(sunxi_musb->controller->parent,
466 "Error unknown readb offset %u\n", offset);
469 } else if (addr == (sunxi_musb->mregs + 0x80)) {
470 /* ep control reg access */
471 /* sunxi has a 2 byte hole before the txtype register */
472 if (offset >= MUSB_TXTYPE)
474 return readb(addr + offset);
477 dev_err(sunxi_musb->controller->parent,
478 "Error unknown readb at 0x%x bytes offset\n",
479 (int)(addr - sunxi_musb->mregs));
483 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
485 if (addr == sunxi_musb->mregs) {
486 /* generic control or fifo control reg access */
489 return writeb(data, addr + SUNXI_MUSB_FADDR);
491 return writeb(data, addr + SUNXI_MUSB_POWER);
493 return writeb(data, addr + SUNXI_MUSB_INTRUSB);
495 return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
497 return writeb(data, addr + SUNXI_MUSB_INDEX);
500 dev_warn(sunxi_musb->controller->parent,
501 "sunxi-musb does not have testmode\n");
504 return writeb(data, addr + SUNXI_MUSB_DEVCTL);
506 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
508 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
509 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
510 case SUNXI_MUSB_TXFUNCADDR:
511 case SUNXI_MUSB_TXHUBADDR:
512 case SUNXI_MUSB_TXHUBPORT:
513 case SUNXI_MUSB_RXFUNCADDR:
514 case SUNXI_MUSB_RXHUBADDR:
515 case SUNXI_MUSB_RXHUBPORT:
516 /* multipoint / busctl reg access */
517 return writeb(data, addr + offset);
519 dev_err(sunxi_musb->controller->parent,
520 "Error unknown writeb offset %u\n", offset);
523 } else if (addr == (sunxi_musb->mregs + 0x80)) {
524 /* ep control reg access */
525 if (offset >= MUSB_TXTYPE)
527 return writeb(data, addr + offset);
530 dev_err(sunxi_musb->controller->parent,
531 "Error unknown writeb at 0x%x bytes offset\n",
532 (int)(addr - sunxi_musb->mregs));
535 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
537 if (addr == sunxi_musb->mregs) {
538 /* generic control or fifo control reg access */
541 return readw(addr + SUNXI_MUSB_INTRTX);
543 return readw(addr + SUNXI_MUSB_INTRRX);
545 return readw(addr + SUNXI_MUSB_INTRTXE);
547 return readw(addr + SUNXI_MUSB_INTRRXE);
549 return readw(addr + SUNXI_MUSB_FRAME);
551 return readw(addr + SUNXI_MUSB_TXFIFOADD);
553 return readw(addr + SUNXI_MUSB_RXFIFOADD);
555 return 0; /* sunxi musb version is not known */
557 dev_err(sunxi_musb->controller->parent,
558 "Error unknown readw offset %u\n", offset);
561 } else if (addr == (sunxi_musb->mregs + 0x80)) {
562 /* ep control reg access */
563 return readw(addr + offset);
566 dev_err(sunxi_musb->controller->parent,
567 "Error unknown readw at 0x%x bytes offset\n",
568 (int)(addr - sunxi_musb->mregs));
572 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
574 if (addr == sunxi_musb->mregs) {
575 /* generic control or fifo control reg access */
578 return writew(data, addr + SUNXI_MUSB_INTRTX);
580 return writew(data, addr + SUNXI_MUSB_INTRRX);
582 return writew(data, addr + SUNXI_MUSB_INTRTXE);
584 return writew(data, addr + SUNXI_MUSB_INTRRXE);
586 return writew(data, addr + SUNXI_MUSB_FRAME);
588 return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
590 return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
592 dev_err(sunxi_musb->controller->parent,
593 "Error unknown writew offset %u\n", offset);
596 } else if (addr == (sunxi_musb->mregs + 0x80)) {
597 /* ep control reg access */
598 return writew(data, addr + offset);
601 dev_err(sunxi_musb->controller->parent,
602 "Error unknown writew at 0x%x bytes offset\n",
603 (int)(addr - sunxi_musb->mregs));
606 static const struct musb_platform_ops sunxi_musb_ops = {
607 .quirks = MUSB_INDEXED_EP,
608 .init = sunxi_musb_init,
609 .exit = sunxi_musb_exit,
610 .enable = sunxi_musb_enable,
611 .disable = sunxi_musb_disable,
612 .fifo_offset = sunxi_musb_fifo_offset,
613 .ep_offset = sunxi_musb_ep_offset,
614 .busctl_offset = sunxi_musb_busctl_offset,
615 .readb = sunxi_musb_readb,
616 .writeb = sunxi_musb_writeb,
617 .readw = sunxi_musb_readw,
618 .writew = sunxi_musb_writew,
619 .dma_init = sunxi_musb_dma_controller_create,
620 .dma_exit = sunxi_musb_dma_controller_destroy,
621 .set_mode = sunxi_musb_set_mode,
622 .recover = sunxi_musb_recover,
623 .set_vbus = sunxi_musb_set_vbus,
624 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
625 .post_root_reset_end = sunxi_musb_post_root_reset_end,
628 /* Allwinner OTG supports up to 5 endpoints */
629 #define SUNXI_MUSB_MAX_EP_NUM 6
630 #define SUNXI_MUSB_RAM_BITS 11
632 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
633 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
634 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
635 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
636 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
637 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
638 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
639 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
640 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
641 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
642 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
645 /* H3/V3s OTG supports only 4 endpoints */
646 #define SUNXI_MUSB_MAX_EP_NUM_H3 5
648 static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
649 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
650 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
651 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
652 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
653 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
654 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
655 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
656 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
659 static const struct musb_hdrc_config sunxi_musb_hdrc_config = {
660 .fifo_cfg = sunxi_musb_mode_cfg,
661 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
665 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
666 .ram_bits = SUNXI_MUSB_RAM_BITS,
670 static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = {
671 .fifo_cfg = sunxi_musb_mode_cfg_h3,
672 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
676 .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
677 .ram_bits = SUNXI_MUSB_RAM_BITS,
682 static int sunxi_musb_probe(struct platform_device *pdev)
684 struct musb_hdrc_platform_data pdata;
685 struct platform_device_info pinfo;
686 struct sunxi_glue *glue;
687 struct device_node *np = pdev->dev.of_node;
691 dev_err(&pdev->dev, "Error no device tree node found\n");
695 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
699 memset(&pdata, 0, sizeof(pdata));
700 switch (usb_get_dr_mode(&pdev->dev)) {
701 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
702 case USB_DR_MODE_HOST:
703 pdata.mode = MUSB_PORT_MODE_HOST;
704 glue->phy_mode = PHY_MODE_USB_HOST;
707 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET
708 case USB_DR_MODE_PERIPHERAL:
709 pdata.mode = MUSB_PORT_MODE_GADGET;
710 glue->phy_mode = PHY_MODE_USB_DEVICE;
713 #ifdef CONFIG_USB_MUSB_DUAL_ROLE
714 case USB_DR_MODE_OTG:
715 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
716 glue->phy_mode = PHY_MODE_USB_OTG;
720 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
723 pdata.platform_ops = &sunxi_musb_ops;
724 if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb"))
725 pdata.config = &sunxi_musb_hdrc_config;
727 pdata.config = &sunxi_musb_hdrc_config_h3;
729 glue->dev = &pdev->dev;
730 INIT_WORK(&glue->work, sunxi_musb_work);
731 glue->host_nb.notifier_call = sunxi_musb_host_notifier;
733 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
734 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
736 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
737 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
739 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
740 of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
741 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
742 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
745 glue->clk = devm_clk_get(&pdev->dev, NULL);
746 if (IS_ERR(glue->clk)) {
747 dev_err(&pdev->dev, "Error getting clock: %ld\n",
749 return PTR_ERR(glue->clk);
752 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
753 glue->rst = devm_reset_control_get(&pdev->dev, NULL);
754 if (IS_ERR(glue->rst)) {
755 if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
756 return -EPROBE_DEFER;
757 dev_err(&pdev->dev, "Error getting reset %ld\n",
759 return PTR_ERR(glue->rst);
763 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
764 if (IS_ERR(glue->extcon)) {
765 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
766 return -EPROBE_DEFER;
767 dev_err(&pdev->dev, "Invalid or missing extcon\n");
768 return PTR_ERR(glue->extcon);
771 glue->phy = devm_phy_get(&pdev->dev, "usb");
772 if (IS_ERR(glue->phy)) {
773 if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
774 return -EPROBE_DEFER;
775 dev_err(&pdev->dev, "Error getting phy %ld\n",
777 return PTR_ERR(glue->phy);
780 glue->usb_phy = usb_phy_generic_register();
781 if (IS_ERR(glue->usb_phy)) {
782 dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
783 PTR_ERR(glue->usb_phy));
784 return PTR_ERR(glue->usb_phy);
787 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
788 if (IS_ERR(glue->xceiv)) {
789 ret = PTR_ERR(glue->xceiv);
790 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
791 goto err_unregister_usb_phy;
794 platform_set_drvdata(pdev, glue);
796 memset(&pinfo, 0, sizeof(pinfo));
797 pinfo.name = "musb-hdrc";
798 pinfo.id = PLATFORM_DEVID_AUTO;
799 pinfo.parent = &pdev->dev;
800 pinfo.res = pdev->resource;
801 pinfo.num_res = pdev->num_resources;
803 pinfo.size_data = sizeof(pdata);
805 glue->musb_pdev = platform_device_register_full(&pinfo);
806 if (IS_ERR(glue->musb_pdev)) {
807 ret = PTR_ERR(glue->musb_pdev);
808 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
809 goto err_unregister_usb_phy;
814 err_unregister_usb_phy:
815 usb_phy_generic_unregister(glue->usb_phy);
819 static int sunxi_musb_remove(struct platform_device *pdev)
821 struct sunxi_glue *glue = platform_get_drvdata(pdev);
822 struct platform_device *usb_phy = glue->usb_phy;
824 platform_device_unregister(glue->musb_pdev);
825 usb_phy_generic_unregister(usb_phy);
830 static const struct of_device_id sunxi_musb_match[] = {
831 { .compatible = "allwinner,sun4i-a10-musb", },
832 { .compatible = "allwinner,sun6i-a31-musb", },
833 { .compatible = "allwinner,sun8i-a33-musb", },
834 { .compatible = "allwinner,sun8i-h3-musb", },
837 MODULE_DEVICE_TABLE(of, sunxi_musb_match);
839 static struct platform_driver sunxi_musb_driver = {
840 .probe = sunxi_musb_probe,
841 .remove = sunxi_musb_remove,
843 .name = "musb-sunxi",
844 .of_match_table = sunxi_musb_match,
847 module_platform_driver(sunxi_musb_driver);
849 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
850 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
851 MODULE_LICENSE("GPL v2");