2 * Allwinner sun4i MUSB Glue Layer
4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/extcon.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
27 #include <linux/phy/phy-sun4i-usb.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/soc/sunxi/sunxi_sram.h>
31 #include <linux/usb/musb.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/usb_phy_generic.h>
34 #include <linux/workqueue.h>
35 #include "musb_core.h"
38 * Register offsets, note sunxi musb has a different layout then most
39 * musb implementations, we translate the layout in musb_readb & friends.
41 #define SUNXI_MUSB_POWER 0x0040
42 #define SUNXI_MUSB_DEVCTL 0x0041
43 #define SUNXI_MUSB_INDEX 0x0042
44 #define SUNXI_MUSB_VEND0 0x0043
45 #define SUNXI_MUSB_INTRTX 0x0044
46 #define SUNXI_MUSB_INTRRX 0x0046
47 #define SUNXI_MUSB_INTRTXE 0x0048
48 #define SUNXI_MUSB_INTRRXE 0x004a
49 #define SUNXI_MUSB_INTRUSB 0x004c
50 #define SUNXI_MUSB_INTRUSBE 0x0050
51 #define SUNXI_MUSB_FRAME 0x0054
52 #define SUNXI_MUSB_TXFIFOSZ 0x0090
53 #define SUNXI_MUSB_TXFIFOADD 0x0092
54 #define SUNXI_MUSB_RXFIFOSZ 0x0094
55 #define SUNXI_MUSB_RXFIFOADD 0x0096
56 #define SUNXI_MUSB_FADDR 0x0098
57 #define SUNXI_MUSB_TXFUNCADDR 0x0098
58 #define SUNXI_MUSB_TXHUBADDR 0x009a
59 #define SUNXI_MUSB_TXHUBPORT 0x009b
60 #define SUNXI_MUSB_RXFUNCADDR 0x009c
61 #define SUNXI_MUSB_RXHUBADDR 0x009e
62 #define SUNXI_MUSB_RXHUBPORT 0x009f
63 #define SUNXI_MUSB_CONFIGDATA 0x00c0
66 #define SUNXI_MUSB_VEND0_PIO_MODE 0
69 #define SUNXI_MUSB_FL_ENABLED 0
70 #define SUNXI_MUSB_FL_HOSTMODE 1
71 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2
72 #define SUNXI_MUSB_FL_VBUS_ON 3
73 #define SUNXI_MUSB_FL_PHY_ON 4
74 #define SUNXI_MUSB_FL_HAS_SRAM 5
75 #define SUNXI_MUSB_FL_HAS_RESET 6
76 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7
78 /* Our read/write methods need access and do not get passed in a musb ref :| */
79 static struct musb *sunxi_musb;
84 struct platform_device *musb_pdev;
86 struct reset_control *rst;
88 struct platform_device *usb_phy;
89 struct usb_phy *xceiv;
91 struct work_struct work;
92 struct extcon_dev *extcon;
93 struct notifier_block host_nb;
96 /* phy_power_on / off may sleep, so we use a workqueue */
97 static void sunxi_musb_work(struct work_struct *work)
99 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
100 bool vbus_on, phy_on;
102 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
105 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
106 struct musb *musb = glue->musb;
110 spin_lock_irqsave(&musb->lock, flags);
112 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
113 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
114 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
115 musb->xceiv->otg->default_a = 1;
116 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
118 devctl |= MUSB_DEVCTL_SESSION;
120 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
121 musb->xceiv->otg->default_a = 0;
122 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
124 devctl &= ~MUSB_DEVCTL_SESSION;
126 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
128 spin_unlock_irqrestore(&musb->lock, flags);
131 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
132 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
134 if (phy_on != vbus_on) {
136 phy_power_on(glue->phy);
137 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
139 phy_power_off(glue->phy);
140 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
145 static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
147 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
150 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
151 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
153 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
156 schedule_work(&glue->work);
159 static void sunxi_musb_pre_root_reset_end(struct musb *musb)
161 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
163 sun4i_usb_phy_set_squelch_detect(glue->phy, false);
166 static void sunxi_musb_post_root_reset_end(struct musb *musb)
168 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
170 sun4i_usb_phy_set_squelch_detect(glue->phy, true);
173 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
175 struct musb *musb = __hci;
178 spin_lock_irqsave(&musb->lock, flags);
180 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
182 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
185 * sunxi musb often signals babble on low / full speed device
186 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
187 * normally babble never happens treat it as disconnect.
189 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
190 musb->int_usb &= ~MUSB_INTR_BABBLE;
191 musb->int_usb |= MUSB_INTR_DISCONNECT;
194 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
195 /* ep0 FADDR must be 0 when (re)entering peripheral mode */
196 musb_ep_select(musb->mregs, 0);
197 musb_writeb(musb->mregs, MUSB_FADDR, 0);
200 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
202 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
204 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
206 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
208 musb_interrupt(musb);
210 spin_unlock_irqrestore(&musb->lock, flags);
215 static int sunxi_musb_host_notifier(struct notifier_block *nb,
216 unsigned long event, void *ptr)
218 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
221 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
223 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
225 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
226 schedule_work(&glue->work);
231 static int sunxi_musb_init(struct musb *musb)
233 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
237 musb->phy = glue->phy;
238 musb->xceiv = glue->xceiv;
240 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
241 ret = sunxi_sram_claim(musb->controller->parent);
246 ret = clk_prepare_enable(glue->clk);
248 goto error_sram_release;
250 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
251 ret = reset_control_deassert(glue->rst);
253 goto error_clk_disable;
256 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
258 /* Register notifier before calling phy_init() */
259 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST,
262 goto error_reset_assert;
264 ret = phy_init(glue->phy);
266 goto error_unregister_notifier;
268 musb->isr = sunxi_musb_interrupt;
270 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
271 pm_runtime_get(musb->controller);
275 error_unregister_notifier:
276 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
279 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
280 reset_control_assert(glue->rst);
282 clk_disable_unprepare(glue->clk);
284 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
285 sunxi_sram_release(musb->controller->parent);
289 static int sunxi_musb_exit(struct musb *musb)
291 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
293 pm_runtime_put(musb->controller);
295 cancel_work_sync(&glue->work);
296 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
297 phy_power_off(glue->phy);
301 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
304 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
305 reset_control_assert(glue->rst);
307 clk_disable_unprepare(glue->clk);
308 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
309 sunxi_sram_release(musb->controller->parent);
314 static void sunxi_musb_enable(struct musb *musb)
316 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
320 /* musb_core does not call us in a balanced manner */
321 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
324 schedule_work(&glue->work);
327 static void sunxi_musb_disable(struct musb *musb)
329 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
331 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
334 static struct dma_controller *
335 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base)
340 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
345 * sunxi musb register layout
346 * 0x00 - 0x17 fifo regs, 1 long per fifo
347 * 0x40 - 0x57 generic control regs (power - frame)
348 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
349 * 0x90 - 0x97 fifo control regs (indexed)
350 * 0x98 - 0x9f multipoint / busctl regs (indexed)
351 * 0xc0 configdata reg
354 static u32 sunxi_musb_fifo_offset(u8 epnum)
359 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
361 WARN_ONCE(offset != 0,
362 "sunxi_musb_ep_offset called with non 0 offset\n");
364 return 0x80; /* indexed, so ignore epnum */
367 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
369 return SUNXI_MUSB_TXFUNCADDR + offset;
372 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
374 struct sunxi_glue *glue;
376 if (addr == sunxi_musb->mregs) {
377 /* generic control or fifo control reg access */
380 return readb(addr + SUNXI_MUSB_FADDR);
382 return readb(addr + SUNXI_MUSB_POWER);
384 return readb(addr + SUNXI_MUSB_INTRUSB);
386 return readb(addr + SUNXI_MUSB_INTRUSBE);
388 return readb(addr + SUNXI_MUSB_INDEX);
390 return 0; /* No testmode on sunxi */
392 return readb(addr + SUNXI_MUSB_DEVCTL);
394 return readb(addr + SUNXI_MUSB_TXFIFOSZ);
396 return readb(addr + SUNXI_MUSB_RXFIFOSZ);
397 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
398 glue = dev_get_drvdata(sunxi_musb->controller->parent);
399 /* A33 saves a reg, and we get to hardcode this */
400 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
404 return readb(addr + SUNXI_MUSB_CONFIGDATA);
405 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
406 case SUNXI_MUSB_TXFUNCADDR:
407 case SUNXI_MUSB_TXHUBADDR:
408 case SUNXI_MUSB_TXHUBPORT:
409 case SUNXI_MUSB_RXFUNCADDR:
410 case SUNXI_MUSB_RXHUBADDR:
411 case SUNXI_MUSB_RXHUBPORT:
412 /* multipoint / busctl reg access */
413 return readb(addr + offset);
415 dev_err(sunxi_musb->controller->parent,
416 "Error unknown readb offset %u\n", offset);
419 } else if (addr == (sunxi_musb->mregs + 0x80)) {
420 /* ep control reg access */
421 /* sunxi has a 2 byte hole before the txtype register */
422 if (offset >= MUSB_TXTYPE)
424 return readb(addr + offset);
427 dev_err(sunxi_musb->controller->parent,
428 "Error unknown readb at 0x%x bytes offset\n",
429 (int)(addr - sunxi_musb->mregs));
433 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
435 if (addr == sunxi_musb->mregs) {
436 /* generic control or fifo control reg access */
439 return writeb(data, addr + SUNXI_MUSB_FADDR);
441 return writeb(data, addr + SUNXI_MUSB_POWER);
443 return writeb(data, addr + SUNXI_MUSB_INTRUSB);
445 return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
447 return writeb(data, addr + SUNXI_MUSB_INDEX);
450 dev_warn(sunxi_musb->controller->parent,
451 "sunxi-musb does not have testmode\n");
454 return writeb(data, addr + SUNXI_MUSB_DEVCTL);
456 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
458 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
459 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
460 case SUNXI_MUSB_TXFUNCADDR:
461 case SUNXI_MUSB_TXHUBADDR:
462 case SUNXI_MUSB_TXHUBPORT:
463 case SUNXI_MUSB_RXFUNCADDR:
464 case SUNXI_MUSB_RXHUBADDR:
465 case SUNXI_MUSB_RXHUBPORT:
466 /* multipoint / busctl reg access */
467 return writeb(data, addr + offset);
469 dev_err(sunxi_musb->controller->parent,
470 "Error unknown writeb offset %u\n", offset);
473 } else if (addr == (sunxi_musb->mregs + 0x80)) {
474 /* ep control reg access */
475 if (offset >= MUSB_TXTYPE)
477 return writeb(data, addr + offset);
480 dev_err(sunxi_musb->controller->parent,
481 "Error unknown writeb at 0x%x bytes offset\n",
482 (int)(addr - sunxi_musb->mregs));
485 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
487 if (addr == sunxi_musb->mregs) {
488 /* generic control or fifo control reg access */
491 return readw(addr + SUNXI_MUSB_INTRTX);
493 return readw(addr + SUNXI_MUSB_INTRRX);
495 return readw(addr + SUNXI_MUSB_INTRTXE);
497 return readw(addr + SUNXI_MUSB_INTRRXE);
499 return readw(addr + SUNXI_MUSB_FRAME);
501 return readw(addr + SUNXI_MUSB_TXFIFOADD);
503 return readw(addr + SUNXI_MUSB_RXFIFOADD);
505 return 0; /* sunxi musb version is not known */
507 dev_err(sunxi_musb->controller->parent,
508 "Error unknown readw offset %u\n", offset);
511 } else if (addr == (sunxi_musb->mregs + 0x80)) {
512 /* ep control reg access */
513 return readw(addr + offset);
516 dev_err(sunxi_musb->controller->parent,
517 "Error unknown readw at 0x%x bytes offset\n",
518 (int)(addr - sunxi_musb->mregs));
522 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
524 if (addr == sunxi_musb->mregs) {
525 /* generic control or fifo control reg access */
528 return writew(data, addr + SUNXI_MUSB_INTRTX);
530 return writew(data, addr + SUNXI_MUSB_INTRRX);
532 return writew(data, addr + SUNXI_MUSB_INTRTXE);
534 return writew(data, addr + SUNXI_MUSB_INTRRXE);
536 return writew(data, addr + SUNXI_MUSB_FRAME);
538 return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
540 return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
542 dev_err(sunxi_musb->controller->parent,
543 "Error unknown writew offset %u\n", offset);
546 } else if (addr == (sunxi_musb->mregs + 0x80)) {
547 /* ep control reg access */
548 return writew(data, addr + offset);
551 dev_err(sunxi_musb->controller->parent,
552 "Error unknown writew at 0x%x bytes offset\n",
553 (int)(addr - sunxi_musb->mregs));
556 static const struct musb_platform_ops sunxi_musb_ops = {
557 .quirks = MUSB_INDEXED_EP,
558 .init = sunxi_musb_init,
559 .exit = sunxi_musb_exit,
560 .enable = sunxi_musb_enable,
561 .disable = sunxi_musb_disable,
562 .fifo_offset = sunxi_musb_fifo_offset,
563 .ep_offset = sunxi_musb_ep_offset,
564 .busctl_offset = sunxi_musb_busctl_offset,
565 .readb = sunxi_musb_readb,
566 .writeb = sunxi_musb_writeb,
567 .readw = sunxi_musb_readw,
568 .writew = sunxi_musb_writew,
569 .dma_init = sunxi_musb_dma_controller_create,
570 .dma_exit = sunxi_musb_dma_controller_destroy,
571 .set_vbus = sunxi_musb_set_vbus,
572 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
573 .post_root_reset_end = sunxi_musb_post_root_reset_end,
576 /* Allwinner OTG supports up to 5 endpoints */
577 #define SUNXI_MUSB_MAX_EP_NUM 6
578 #define SUNXI_MUSB_RAM_BITS 11
580 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
581 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
582 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
583 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
584 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
585 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
586 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
587 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
588 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
589 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
590 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
593 static struct musb_hdrc_config sunxi_musb_hdrc_config = {
594 .fifo_cfg = sunxi_musb_mode_cfg,
595 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
599 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
600 .ram_bits = SUNXI_MUSB_RAM_BITS,
604 static int sunxi_musb_probe(struct platform_device *pdev)
606 struct musb_hdrc_platform_data pdata;
607 struct platform_device_info pinfo;
608 struct sunxi_glue *glue;
609 struct device_node *np = pdev->dev.of_node;
613 dev_err(&pdev->dev, "Error no device tree node found\n");
617 memset(&pdata, 0, sizeof(pdata));
618 switch (usb_get_dr_mode(&pdev->dev)) {
619 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
620 case USB_DR_MODE_HOST:
621 pdata.mode = MUSB_PORT_MODE_HOST;
624 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET
625 case USB_DR_MODE_PERIPHERAL:
626 pdata.mode = MUSB_PORT_MODE_GADGET;
629 #ifdef CONFIG_USB_MUSB_DUAL_ROLE
630 case USB_DR_MODE_OTG:
631 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
635 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
638 pdata.platform_ops = &sunxi_musb_ops;
639 pdata.config = &sunxi_musb_hdrc_config;
641 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
645 glue->dev = &pdev->dev;
646 INIT_WORK(&glue->work, sunxi_musb_work);
647 glue->host_nb.notifier_call = sunxi_musb_host_notifier;
649 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
650 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
652 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
653 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
655 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) {
656 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
657 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
660 glue->clk = devm_clk_get(&pdev->dev, NULL);
661 if (IS_ERR(glue->clk)) {
662 dev_err(&pdev->dev, "Error getting clock: %ld\n",
664 return PTR_ERR(glue->clk);
667 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
668 glue->rst = devm_reset_control_get(&pdev->dev, NULL);
669 if (IS_ERR(glue->rst)) {
670 if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
671 return -EPROBE_DEFER;
672 dev_err(&pdev->dev, "Error getting reset %ld\n",
674 return PTR_ERR(glue->rst);
678 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
679 if (IS_ERR(glue->extcon)) {
680 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
681 return -EPROBE_DEFER;
682 dev_err(&pdev->dev, "Invalid or missing extcon\n");
683 return PTR_ERR(glue->extcon);
686 glue->phy = devm_phy_get(&pdev->dev, "usb");
687 if (IS_ERR(glue->phy)) {
688 if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
689 return -EPROBE_DEFER;
690 dev_err(&pdev->dev, "Error getting phy %ld\n",
692 return PTR_ERR(glue->phy);
695 glue->usb_phy = usb_phy_generic_register();
696 if (IS_ERR(glue->usb_phy)) {
697 dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
698 PTR_ERR(glue->usb_phy));
699 return PTR_ERR(glue->usb_phy);
702 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
703 if (IS_ERR(glue->xceiv)) {
704 ret = PTR_ERR(glue->xceiv);
705 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
706 goto err_unregister_usb_phy;
709 platform_set_drvdata(pdev, glue);
711 memset(&pinfo, 0, sizeof(pinfo));
712 pinfo.name = "musb-hdrc";
713 pinfo.id = PLATFORM_DEVID_AUTO;
714 pinfo.parent = &pdev->dev;
715 pinfo.res = pdev->resource;
716 pinfo.num_res = pdev->num_resources;
718 pinfo.size_data = sizeof(pdata);
720 glue->musb_pdev = platform_device_register_full(&pinfo);
721 if (IS_ERR(glue->musb_pdev)) {
722 ret = PTR_ERR(glue->musb_pdev);
723 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
724 goto err_unregister_usb_phy;
729 err_unregister_usb_phy:
730 usb_phy_generic_unregister(glue->usb_phy);
734 static int sunxi_musb_remove(struct platform_device *pdev)
736 struct sunxi_glue *glue = platform_get_drvdata(pdev);
737 struct platform_device *usb_phy = glue->usb_phy;
739 platform_device_unregister(glue->musb_pdev);
740 usb_phy_generic_unregister(usb_phy);
745 static const struct of_device_id sunxi_musb_match[] = {
746 { .compatible = "allwinner,sun4i-a10-musb", },
747 { .compatible = "allwinner,sun6i-a31-musb", },
748 { .compatible = "allwinner,sun8i-a33-musb", },
751 MODULE_DEVICE_TABLE(of, sunxi_musb_match);
753 static struct platform_driver sunxi_musb_driver = {
754 .probe = sunxi_musb_probe,
755 .remove = sunxi_musb_remove,
757 .name = "musb-sunxi",
758 .of_match_table = sunxi_musb_match,
761 module_platform_driver(sunxi_musb_driver);
763 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
764 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
765 MODULE_LICENSE("GPL v2");