drivers/usb/musb/musbhsdma.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MUSB OTG driver - support for Mentor's DMA controller
   4  *
   5  * Copyright 2005 Mentor Graphics Corporation
   6  * Copyright (C) 2005-2007 by Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34 #include <linux/device.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/slab.h>
  38 #include "musb_core.h"
  39 #include "musbhsdma.h"
  40
  41 static void dma_channel_release(struct dma_channel *channel);
  42
  43 static void dma_controller_stop(struct musb_dma_controller *controller)
  44 {
  45         struct musb *musb = controller->private_data;
  46         struct dma_channel *channel;
  47         u8 bit;
  48
  49         if (controller->used_channels != 0) {
  50                 dev_err(musb->controller,
  51                         "Stopping DMA controller while channel active\n");
  52
  53                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  54                         if (controller->used_channels & (1 << bit)) {
  55                                 channel = &controller->channel[bit].channel;
  56                                 dma_channel_release(channel);
  57
  58                                 if (!controller->used_channels)
  59                                         break;
  60                         }
  61                 }
  62         }
  63 }
  64
  65 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
  66                                 struct musb_hw_ep *hw_ep, u8 transmit)
  67 {
  68         struct musb_dma_controller *controller = container_of(c,
  69                         struct musb_dma_controller, controller);
  70         struct musb_dma_channel *musb_channel = NULL;
  71         struct dma_channel *channel = NULL;
  72         u8 bit;
  73
  74         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  75                 if (!(controller->used_channels & (1 << bit))) {
  76                         controller->used_channels |= (1 << bit);
  77                         musb_channel = &(controller->channel[bit]);
  78                         musb_channel->controller = controller;
  79                         musb_channel->idx = bit;
  80                         musb_channel->epnum = hw_ep->epnum;
  81                         musb_channel->transmit = transmit;
  82                         channel = &(musb_channel->channel);
  83                         channel->private_data = musb_channel;
  84                         channel->status = MUSB_DMA_STATUS_FREE;
  85                         channel->max_len = 0x100000;
  86                         /* Tx => mode 1; Rx => mode 0 */
  87                         channel->desired_mode = transmit;
  88                         channel->actual_len = 0;
  89                         break;
  90                 }
  91         }
  92
  93         return channel;
  94 }
  95
  96 static void dma_channel_release(struct dma_channel *channel)
  97 {
  98         struct musb_dma_channel *musb_channel = channel->private_data;
  99
 100         channel->actual_len = 0;
 101         musb_channel->start_addr = 0;
 102         musb_channel->len = 0;
 103
 104         musb_channel->controller->used_channels &=
 105                 ~(1 << musb_channel->idx);
 106
 107         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 108 }
 109
 110 static void configure_channel(struct dma_channel *channel,
 111                                 u16 packet_sz, u8 mode,
 112                                 dma_addr_t dma_addr, u32 len)
 113 {
 114         struct musb_dma_channel *musb_channel = channel->private_data;
 115         struct musb_dma_controller *controller = musb_channel->controller;
 116         struct musb *musb = controller->private_data;
 117         void __iomem *mbase = controller->base;
 118         u8 bchannel = musb_channel->idx;
 119         u16 csr = 0;
 120
 121         musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
 122                         channel, packet_sz, &dma_addr, len, mode);
 123
 124         if (mode) {
 125                 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 126                 BUG_ON(len < packet_sz);
 127         }
 128         csr |= MUSB_HSDMA_BURSTMODE_INCR16
 129                                 << MUSB_HSDMA_BURSTMODE_SHIFT;
 130
 131         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 132                 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 133                 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 134                 | (musb_channel->transmit
 135                                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 136                                 : 0);
 137
 138         /* address/count */
 139         musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 140         musb_write_hsdma_count(mbase, bchannel, len);
 141
 142         /* control (this should start things) */
 143         musb_writew(mbase,
 144                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 145                 csr);
 146 }
 147
 148 static int dma_channel_program(struct dma_channel *channel,
 149                                 u16 packet_sz, u8 mode,
 150                                 dma_addr_t dma_addr, u32 len)
 151 {
 152         struct musb_dma_channel *musb_channel = channel->private_data;
 153         struct musb_dma_controller *controller = musb_channel->controller;
 154         struct musb *musb = controller->private_data;
 155
 156         musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
 157                 musb_channel->epnum,
 158                 musb_channel->transmit ? "Tx" : "Rx",
 159                 packet_sz, &dma_addr, len, mode);
 160
 161         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 162                 channel->status == MUSB_DMA_STATUS_BUSY);
 163
 164         /* Let targets check/tweak the arguments */
 165         if (musb->ops->adjust_channel_params) {
 166                 int ret = musb->ops->adjust_channel_params(channel,
 167                         packet_sz, &mode, &dma_addr, &len);
 168                 if (ret)
 169                         return ret;
 170         }
 171
 172         /*
 173          * The DMA engine in RTL1.8 and above cannot handle
 174          * DMA addresses that are not aligned to a 4 byte boundary.
 175          * It ends up masking the last two bits of the address
 176          * programmed in DMA_ADDR.
 177          *
 178          * Fail such DMA transfers, so that the backup PIO mode
 179          * can carry out the transfer
 180          */
 181         if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
 182                 return false;
 183
 184         channel->actual_len = 0;
 185         musb_channel->start_addr = dma_addr;
 186         musb_channel->len = len;
 187         musb_channel->max_packet_sz = packet_sz;
 188         channel->status = MUSB_DMA_STATUS_BUSY;
 189
 190         configure_channel(channel, packet_sz, mode, dma_addr, len);
 191
 192         return true;
 193 }
 194
 195 static int dma_channel_abort(struct dma_channel *channel)
 196 {
 197         struct musb_dma_channel *musb_channel = channel->private_data;
 198         void __iomem *mbase = musb_channel->controller->base;
 199         struct musb *musb = musb_channel->controller->private_data;
 200
 201         u8 bchannel = musb_channel->idx;
 202         int offset;
 203         u16 csr;
 204
 205         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 206                 if (musb_channel->transmit) {
 207                         offset = musb->io.ep_offset(musb_channel->epnum,
 208                                                 MUSB_TXCSR);
 209
 210                         /*
 211                          * The programming guide says that we must clear
 212                          * the DMAENAB bit before the DMAMODE bit...
 213                          */
 214                         csr = musb_readw(mbase, offset);
 215                         csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
 216                         musb_writew(mbase, offset, csr);
 217                         csr &= ~MUSB_TXCSR_DMAMODE;
 218                         musb_writew(mbase, offset, csr);
 219                 } else {
 220                         offset = musb->io.ep_offset(musb_channel->epnum,
 221                                                 MUSB_RXCSR);
 222
 223                         csr = musb_readw(mbase, offset);
 224                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 225                                  MUSB_RXCSR_DMAENAB |
 226                                  MUSB_RXCSR_DMAMODE);
 227                         musb_writew(mbase, offset, csr);
 228                 }
 229
 230                 musb_writew(mbase,
 231                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 232                         0);
 233                 musb_write_hsdma_addr(mbase, bchannel, 0);
 234                 musb_write_hsdma_count(mbase, bchannel, 0);
 235                 channel->status = MUSB_DMA_STATUS_FREE;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 242 {
 243         struct musb_dma_controller *controller = private_data;
 244         struct musb *musb = controller->private_data;
 245         struct musb_dma_channel *musb_channel;
 246         struct dma_channel *channel;
 247
 248         void __iomem *mbase = controller->base;
 249
 250         irqreturn_t retval = IRQ_NONE;
 251
 252         unsigned long flags;
 253
 254         u8 bchannel;
 255         u8 int_hsdma;
 256
 257         u32 addr, count;
 258         u16 csr;
 259
 260         spin_lock_irqsave(&musb->lock, flags);
 261
 262         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 263
 264 #ifdef CONFIG_BLACKFIN
 265         /* Clear DMA interrupt flags */
 266         musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
 267 #endif
 268
 269         if (!int_hsdma) {
 270                 musb_dbg(musb, "spurious DMA irq");
 271
 272                 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 273                         musb_channel = (struct musb_dma_channel *)
 274                                         &(controller->channel[bchannel]);
 275                         channel = &musb_channel->channel;
 276                         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 277                                 count = musb_read_hsdma_count(mbase, bchannel);
 278
 279                                 if (count == 0)
 280                                         int_hsdma |= (1 << bchannel);
 281                         }
 282                 }
 283
 284                 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
 285
 286                 if (!int_hsdma)
 287                         goto done;
 288         }
 289
 290         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 291                 if (int_hsdma & (1 << bchannel)) {
 292                         musb_channel = (struct musb_dma_channel *)
 293                                         &(controller->channel[bchannel]);
 294                         channel = &musb_channel->channel;
 295
 296                         csr = musb_readw(mbase,
 297                                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 298                                                         MUSB_HSDMA_CONTROL));
 299
 300                         if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 301                                 musb_channel->channel.status =
 302                                         MUSB_DMA_STATUS_BUS_ABORT;
 303                         } else {
 304                                 u8 devctl;
 305
 306                                 addr = musb_read_hsdma_addr(mbase,
 307                                                 bchannel);
 308                                 channel->actual_len = addr
 309                                         - musb_channel->start_addr;
 310
 311                                 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
 312                                         channel, musb_channel->start_addr,
 313                                         addr, channel->actual_len,
 314                                         musb_channel->len,
 315                                         (channel->actual_len
 316                                                 < musb_channel->len) ?
 317                                         "=> reconfig 0" : "=> complete");
 318
 319                                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 320
 321                                 channel->status = MUSB_DMA_STATUS_FREE;
 322
 323                                 /* completed */
 324                                 if ((devctl & MUSB_DEVCTL_HM)
 325                                         && (musb_channel->transmit)
 326                                         && ((channel->desired_mode == 0)
 327                                             || (channel->actual_len &
 328                                             (musb_channel->max_packet_sz - 1)))
 329                                     ) {
 330                                         u8  epnum  = musb_channel->epnum;
 331                                         int offset = musb->io.ep_offset(epnum,
 332                                                                     MUSB_TXCSR);
 333                                         u16 txcsr;
 334
 335                                         /*
 336                                          * The programming guide says that we
 337                                          * must clear DMAENAB before DMAMODE.
 338                                          */
 339                                         musb_ep_select(mbase, epnum);
 340                                         txcsr = musb_readw(mbase, offset);
 341                                         txcsr &= ~(MUSB_TXCSR_DMAENAB
 342                                                         | MUSB_TXCSR_AUTOSET);
 343                                         musb_writew(mbase, offset, txcsr);
 344                                         /* Send out the packet */
 345                                         txcsr &= ~MUSB_TXCSR_DMAMODE;
 346                                         txcsr |=  MUSB_TXCSR_TXPKTRDY;
 347                                         musb_writew(mbase, offset, txcsr);
 348                                 }
 349                                 musb_dma_completion(musb, musb_channel->epnum,
 350                                                     musb_channel->transmit);
 351                         }
 352                 }
 353         }
 354
 355         retval = IRQ_HANDLED;
 356 done:
 357         spin_unlock_irqrestore(&musb->lock, flags);
 358         return retval;
 359 }
 360
 361 void musbhs_dma_controller_destroy(struct dma_controller *c)
 362 {
 363         struct musb_dma_controller *controller = container_of(c,
 364                         struct musb_dma_controller, controller);
 365
 366         dma_controller_stop(controller);
 367
 368         if (controller->irq)
 369                 free_irq(controller->irq, c);
 370
 371         kfree(controller);
 372 }
 373 EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
 374
 375 struct dma_controller *musbhs_dma_controller_create(struct musb *musb,
 376                                                     void __iomem *base)
 377 {
 378         struct musb_dma_controller *controller;
 379         struct device *dev = musb->controller;
 380         struct platform_device *pdev = to_platform_device(dev);
 381         int irq = platform_get_irq_byname(pdev, "dma");
 382
 383         if (irq <= 0) {
 384                 dev_err(dev, "No DMA interrupt line!\n");
 385                 return NULL;
 386         }
 387
 388         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 389         if (!controller)
 390                 return NULL;
 391
 392         controller->channel_count = MUSB_HSDMA_CHANNELS;
 393         controller->private_data = musb;
 394         controller->base = base;
 395
 396         controller->controller.channel_alloc = dma_channel_allocate;
 397         controller->controller.channel_release = dma_channel_release;
 398         controller->controller.channel_program = dma_channel_program;
 399         controller->controller.channel_abort = dma_channel_abort;
 400
 401         if (request_irq(irq, dma_controller_irq, 0,
 402                         dev_name(musb->controller), &controller->controller)) {
 403                 dev_err(dev, "request_irq %d failed!\n", irq);
 404                 musb_dma_controller_destroy(&controller->controller);
 405
 406                 return NULL;
 407         }
 408
 409         controller->irq = irq;
 410
 411         return &controller->controller;
 412 }
 413 EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);