1 #include <linux/device.h>
2 #include <linux/dma-mapping.h>
3 #include <linux/dmaengine.h>
4 #include <linux/sizes.h>
5 #include <linux/platform_device.h>
10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
12 #define EP_MODE_AUTOREG_NONE 0
13 #define EP_MODE_AUTOREG_ALL_NEOP 1
14 #define EP_MODE_AUTOREG_ALWAYS 3
16 #define EP_MODE_DMA_TRANSPARENT 0
17 #define EP_MODE_DMA_RNDIS 1
18 #define EP_MODE_DMA_GEN_RNDIS 3
20 #define USB_CTRL_TX_MODE 0x70
21 #define USB_CTRL_RX_MODE 0x74
22 #define USB_CTRL_AUTOREQ 0xd0
23 #define USB_TDOWN 0xd8
25 struct cppi41_dma_channel {
26 struct dma_channel channel;
27 struct cppi41_dma_controller *controller;
28 struct musb_hw_ep *hw_ep;
41 struct list_head tx_check;
44 #define MUSB_DMA_NUM_CHANNELS 15
46 struct cppi41_dma_controller {
47 struct dma_controller controller;
48 struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
49 struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
51 struct hrtimer early_tx;
52 struct list_head early_tx_list;
58 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
63 if (cppi41_channel->is_tx)
65 if (!is_host_active(cppi41_channel->controller->musb))
68 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
69 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
71 cppi41_channel->usb_toggle = toggle;
74 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
79 if (cppi41_channel->is_tx)
81 if (!is_host_active(cppi41_channel->controller->musb))
84 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
85 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
88 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
89 * data toggle may reset from DATA1 to DATA0 during receiving data from
90 * more than one endpoint.
92 if (!toggle && toggle == cppi41_channel->usb_toggle) {
93 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
94 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
95 dev_dbg(cppi41_channel->controller->musb->controller,
96 "Restoring DATA1 toggle.\n");
99 cppi41_channel->usb_toggle = toggle;
102 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
104 u8 epnum = hw_ep->epnum;
105 struct musb *musb = hw_ep->musb;
106 void __iomem *epio = musb->endpoints[epnum].regs;
109 csr = musb_readw(epio, MUSB_TXCSR);
110 if (csr & MUSB_TXCSR_TXPKTRDY)
115 static void cppi41_dma_callback(void *private_data);
117 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
119 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
120 struct musb *musb = hw_ep->musb;
122 if (!cppi41_channel->prog_len) {
125 cppi41_channel->channel.actual_len =
126 cppi41_channel->transferred;
127 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
128 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
130 /* next iteration, reload */
131 struct dma_chan *dc = cppi41_channel->dc;
132 struct dma_async_tx_descriptor *dma_desc;
133 enum dma_transfer_direction direction;
136 void __iomem *epio = cppi41_channel->hw_ep->regs;
138 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
140 remain_bytes = cppi41_channel->total_len;
141 remain_bytes -= cppi41_channel->transferred;
142 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
143 cppi41_channel->prog_len = remain_bytes;
145 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
147 dma_desc = dmaengine_prep_slave_single(dc,
148 cppi41_channel->buf_addr,
151 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
152 if (WARN_ON(!dma_desc))
155 dma_desc->callback = cppi41_dma_callback;
156 dma_desc->callback_param = &cppi41_channel->channel;
157 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
158 dma_async_issue_pending(dc);
160 if (!cppi41_channel->is_tx) {
161 csr = musb_readw(epio, MUSB_RXCSR);
162 csr |= MUSB_RXCSR_H_REQPKT;
163 musb_writew(epio, MUSB_RXCSR, csr);
168 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
170 struct cppi41_dma_controller *controller;
171 struct cppi41_dma_channel *cppi41_channel, *n;
174 enum hrtimer_restart ret = HRTIMER_NORESTART;
176 controller = container_of(timer, struct cppi41_dma_controller,
178 musb = controller->musb;
180 spin_lock_irqsave(&musb->lock, flags);
181 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
184 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
186 empty = musb_is_tx_fifo_empty(hw_ep);
188 list_del_init(&cppi41_channel->tx_check);
189 cppi41_trans_done(cppi41_channel);
193 if (!list_empty(&controller->early_tx_list)) {
194 ret = HRTIMER_RESTART;
195 hrtimer_forward_now(&controller->early_tx,
196 ktime_set(0, 150 * NSEC_PER_USEC));
199 spin_unlock_irqrestore(&musb->lock, flags);
203 static void cppi41_dma_callback(void *private_data)
205 struct dma_channel *channel = private_data;
206 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
207 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
208 struct musb *musb = hw_ep->musb;
210 struct dma_tx_state txstate;
214 spin_lock_irqsave(&musb->lock, flags);
216 dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
218 transferred = cppi41_channel->prog_len - txstate.residue;
219 cppi41_channel->transferred += transferred;
221 dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
222 hw_ep->epnum, cppi41_channel->transferred,
223 cppi41_channel->total_len);
225 update_rx_toggle(cppi41_channel);
227 if (cppi41_channel->transferred == cppi41_channel->total_len ||
228 transferred < cppi41_channel->packet_sz)
229 cppi41_channel->prog_len = 0;
231 empty = musb_is_tx_fifo_empty(hw_ep);
233 cppi41_trans_done(cppi41_channel);
235 struct cppi41_dma_controller *controller;
237 * On AM335x it has been observed that the TX interrupt fires
238 * too early that means the TXFIFO is not yet empty but the DMA
239 * engine says that it is done with the transfer. We don't
240 * receive a FIFO empty interrupt so the only thing we can do is
241 * to poll for the bit. On HS it usually takes 2us, on FS around
242 * 110us - 150us depending on the transfer size.
243 * We spin on HS (no longer than than 25us and setup a timer on
244 * FS to check for the bit and complete the transfer.
246 controller = cppi41_channel->controller;
248 if (musb->g.speed == USB_SPEED_HIGH) {
252 empty = musb_is_tx_fifo_empty(hw_ep);
261 empty = musb_is_tx_fifo_empty(hw_ep);
263 cppi41_trans_done(cppi41_channel);
267 list_add_tail(&cppi41_channel->tx_check,
268 &controller->early_tx_list);
269 if (!hrtimer_active(&controller->early_tx)) {
270 hrtimer_start_range_ns(&controller->early_tx,
271 ktime_set(0, 140 * NSEC_PER_USEC),
277 spin_unlock_irqrestore(&musb->lock, flags);
280 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
284 shift = (ep - 1) * 2;
285 old &= ~(3 << shift);
286 old |= mode << shift;
290 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
293 struct cppi41_dma_controller *controller = cppi41_channel->controller;
298 if (cppi41_channel->is_tx)
299 old_mode = controller->tx_mode;
301 old_mode = controller->rx_mode;
302 port = cppi41_channel->port_num;
303 new_mode = update_ep_mode(port, mode, old_mode);
305 if (new_mode == old_mode)
307 if (cppi41_channel->is_tx) {
308 controller->tx_mode = new_mode;
309 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
312 controller->rx_mode = new_mode;
313 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
318 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
321 struct cppi41_dma_controller *controller = cppi41_channel->controller;
326 old_mode = controller->auto_req;
327 port = cppi41_channel->port_num;
328 new_mode = update_ep_mode(port, mode, old_mode);
330 if (new_mode == old_mode)
332 controller->auto_req = new_mode;
333 musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
336 static bool cppi41_configure_channel(struct dma_channel *channel,
337 u16 packet_sz, u8 mode,
338 dma_addr_t dma_addr, u32 len)
340 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
341 struct dma_chan *dc = cppi41_channel->dc;
342 struct dma_async_tx_descriptor *dma_desc;
343 enum dma_transfer_direction direction;
344 struct musb *musb = cppi41_channel->controller->musb;
345 unsigned use_gen_rndis = 0;
347 dev_dbg(musb->controller,
348 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
349 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
350 packet_sz, mode, (unsigned long long) dma_addr,
351 len, cppi41_channel->is_tx);
353 cppi41_channel->buf_addr = dma_addr;
354 cppi41_channel->total_len = len;
355 cppi41_channel->transferred = 0;
356 cppi41_channel->packet_sz = packet_sz;
359 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
360 * than max packet size at a time.
362 if (cppi41_channel->is_tx)
367 if (len > packet_sz) {
368 musb_writel(musb->ctrl_base,
369 RNDIS_REG(cppi41_channel->port_num), len);
371 cppi41_set_dma_mode(cppi41_channel,
372 EP_MODE_DMA_GEN_RNDIS);
375 cppi41_set_autoreq_mode(cppi41_channel,
376 EP_MODE_AUTOREG_ALL_NEOP);
378 musb_writel(musb->ctrl_base,
379 RNDIS_REG(cppi41_channel->port_num), 0);
380 cppi41_set_dma_mode(cppi41_channel,
381 EP_MODE_DMA_TRANSPARENT);
382 cppi41_set_autoreq_mode(cppi41_channel,
383 EP_MODE_AUTOREG_NONE);
387 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
388 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
389 len = min_t(u32, packet_sz, len);
391 cppi41_channel->prog_len = len;
392 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
393 dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
394 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
398 dma_desc->callback = cppi41_dma_callback;
399 dma_desc->callback_param = channel;
400 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
402 save_rx_toggle(cppi41_channel);
403 dma_async_issue_pending(dc);
407 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
408 struct musb_hw_ep *hw_ep, u8 is_tx)
410 struct cppi41_dma_controller *controller = container_of(c,
411 struct cppi41_dma_controller, controller);
412 struct cppi41_dma_channel *cppi41_channel = NULL;
413 u8 ch_num = hw_ep->epnum - 1;
415 if (ch_num >= MUSB_DMA_NUM_CHANNELS)
419 cppi41_channel = &controller->tx_channel[ch_num];
421 cppi41_channel = &controller->rx_channel[ch_num];
423 if (!cppi41_channel->dc)
426 if (cppi41_channel->is_allocated)
429 cppi41_channel->hw_ep = hw_ep;
430 cppi41_channel->is_allocated = 1;
432 return &cppi41_channel->channel;
435 static void cppi41_dma_channel_release(struct dma_channel *channel)
437 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
439 if (cppi41_channel->is_allocated) {
440 cppi41_channel->is_allocated = 0;
441 channel->status = MUSB_DMA_STATUS_FREE;
442 channel->actual_len = 0;
446 static int cppi41_dma_channel_program(struct dma_channel *channel,
447 u16 packet_sz, u8 mode,
448 dma_addr_t dma_addr, u32 len)
452 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
453 channel->status == MUSB_DMA_STATUS_BUSY);
455 channel->status = MUSB_DMA_STATUS_BUSY;
456 channel->actual_len = 0;
457 ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
459 channel->status = MUSB_DMA_STATUS_FREE;
464 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
465 void *buf, u32 length)
467 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
468 struct cppi41_dma_controller *controller = cppi41_channel->controller;
469 struct musb *musb = controller->musb;
471 if (is_host_active(musb)) {
475 if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
477 if (cppi41_channel->is_tx)
479 /* AM335x Advisory 1.0.13. No workaround for device RX mode */
483 static int cppi41_dma_channel_abort(struct dma_channel *channel)
485 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
486 struct cppi41_dma_controller *controller = cppi41_channel->controller;
487 struct musb *musb = controller->musb;
488 void __iomem *epio = cppi41_channel->hw_ep->regs;
494 is_tx = cppi41_channel->is_tx;
495 dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
496 cppi41_channel->port_num, is_tx);
498 if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
501 list_del_init(&cppi41_channel->tx_check);
503 csr = musb_readw(epio, MUSB_TXCSR);
504 csr &= ~MUSB_TXCSR_DMAENAB;
505 musb_writew(epio, MUSB_TXCSR, csr);
507 csr = musb_readw(epio, MUSB_RXCSR);
508 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
509 musb_writew(epio, MUSB_RXCSR, csr);
511 csr = musb_readw(epio, MUSB_RXCSR);
512 if (csr & MUSB_RXCSR_RXPKTRDY) {
513 csr |= MUSB_RXCSR_FLUSHFIFO;
514 musb_writew(epio, MUSB_RXCSR, csr);
515 musb_writew(epio, MUSB_RXCSR, csr);
519 tdbit = 1 << cppi41_channel->port_num;
524 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
525 ret = dmaengine_terminate_all(cppi41_channel->dc);
526 } while (ret == -EAGAIN);
528 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
531 csr = musb_readw(epio, MUSB_TXCSR);
532 if (csr & MUSB_TXCSR_TXPKTRDY) {
533 csr |= MUSB_TXCSR_FLUSHFIFO;
534 musb_writew(epio, MUSB_TXCSR, csr);
538 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
542 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
547 for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
548 dc = ctrl->tx_channel[i].dc;
550 dma_release_channel(dc);
551 dc = ctrl->rx_channel[i].dc;
553 dma_release_channel(dc);
557 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
559 cppi41_release_all_dma_chans(controller);
562 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
564 struct musb *musb = controller->musb;
565 struct device *dev = musb->controller;
566 struct device_node *np = dev->of_node;
567 struct cppi41_dma_channel *cppi41_channel;
572 count = of_property_count_strings(np, "dma-names");
576 for (i = 0; i < count; i++) {
578 struct dma_channel *musb_dma;
583 ret = of_property_read_string_index(np, "dma-names", i, &str);
586 if (!strncmp(str, "tx", 2))
588 else if (!strncmp(str, "rx", 2))
591 dev_err(dev, "Wrong dmatype %s\n", str);
594 ret = kstrtouint(str + 2, 0, &port);
599 if (port > MUSB_DMA_NUM_CHANNELS || !port)
602 cppi41_channel = &controller->tx_channel[port - 1];
604 cppi41_channel = &controller->rx_channel[port - 1];
606 cppi41_channel->controller = controller;
607 cppi41_channel->port_num = port;
608 cppi41_channel->is_tx = is_tx;
609 INIT_LIST_HEAD(&cppi41_channel->tx_check);
611 musb_dma = &cppi41_channel->channel;
612 musb_dma->private_data = cppi41_channel;
613 musb_dma->status = MUSB_DMA_STATUS_FREE;
614 musb_dma->max_len = SZ_4M;
616 dc = dma_request_slave_channel(dev, str);
618 dev_err(dev, "Falied to request %s.\n", str);
622 cppi41_channel->dc = dc;
626 cppi41_release_all_dma_chans(controller);
630 void dma_controller_destroy(struct dma_controller *c)
632 struct cppi41_dma_controller *controller = container_of(c,
633 struct cppi41_dma_controller, controller);
635 hrtimer_cancel(&controller->early_tx);
636 cppi41_dma_controller_stop(controller);
640 struct dma_controller *dma_controller_create(struct musb *musb,
643 struct cppi41_dma_controller *controller;
646 if (!musb->controller->of_node) {
647 dev_err(musb->controller, "Need DT for the DMA engine.\n");
651 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
655 hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
656 controller->early_tx.function = cppi41_recheck_tx_req;
657 INIT_LIST_HEAD(&controller->early_tx_list);
658 controller->musb = musb;
660 controller->controller.channel_alloc = cppi41_dma_channel_allocate;
661 controller->controller.channel_release = cppi41_dma_channel_release;
662 controller->controller.channel_program = cppi41_dma_channel_program;
663 controller->controller.channel_abort = cppi41_dma_channel_abort;
664 controller->controller.is_compatible = cppi41_is_compatible;
666 ret = cppi41_dma_controller_start(controller);
669 return &controller->controller;
674 if (ret == -EPROBE_DEFER)