2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
125 #define MUSB_VERSION "6.0"
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
138 /*-------------------------------------------------------------------------*/
140 static inline struct musb *dev_to_musb(struct device *dev)
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
146 return dev_get_drvdata(dev);
150 /*-------------------------------------------------------------------------*/
152 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
155 * Load an endpoint's FIFO
157 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
159 void __iomem *fifo = hw_ep->fifo;
163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 'T', hw_ep->epnum, fifo, len, src);
166 /* we can't assume unaligned reads work */
167 if (likely((0x01 & (unsigned long) src) == 0)) {
170 /* best case is 32bit-aligned source address */
171 if ((0x02 & (unsigned long) src) == 0) {
173 writesl(fifo, src + index, len >> 2);
174 index += len & ~0x03;
177 musb_writew(fifo, 0, *(u16 *)&src[index]);
182 writesw(fifo, src + index, len >> 1);
183 index += len & ~0x01;
187 musb_writeb(fifo, 0, src[index]);
190 writesb(fifo, src, len);
195 * Unload an endpoint's FIFO
197 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
199 void __iomem *fifo = hw_ep->fifo;
201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 'R', hw_ep->epnum, fifo, len, dst);
204 /* we can't assume unaligned writes work */
205 if (likely((0x01 & (unsigned long) dst) == 0)) {
208 /* best case is 32bit-aligned destination address */
209 if ((0x02 & (unsigned long) dst) == 0) {
211 readsl(fifo, dst, len >> 2);
215 *(u16 *)&dst[index] = musb_readw(fifo, 0);
220 readsw(fifo, dst, len >> 1);
225 dst[index] = musb_readb(fifo, 0);
228 readsb(fifo, dst, len);
232 #endif /* normal PIO */
235 /*-------------------------------------------------------------------------*/
237 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
238 static const u8 musb_test_packet[53] = {
239 /* implicit SYNC then DATA0 to start */
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 /* JJJJJJJKKKKKKK x8 */
248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 /* JKKKKKKK x10, JK */
252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
254 /* implicit CRC16 then EOP to end */
257 void musb_load_testpacket(struct musb *musb)
259 void __iomem *regs = musb->endpoints[0].regs;
261 musb_ep_select(musb->mregs, 0);
262 musb_write_fifo(musb->control_ep,
263 sizeof(musb_test_packet), musb_test_packet);
264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
267 /*-------------------------------------------------------------------------*/
269 const char *otg_state_string(struct musb *musb)
271 switch (musb->xceiv->state) {
272 case OTG_STATE_A_IDLE: return "a_idle";
273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
275 case OTG_STATE_A_HOST: return "a_host";
276 case OTG_STATE_A_SUSPEND: return "a_suspend";
277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
280 case OTG_STATE_B_IDLE: return "b_idle";
281 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
284 case OTG_STATE_B_HOST: return "b_host";
285 default: return "UNDEFINED";
289 #ifdef CONFIG_USB_MUSB_OTG
292 * Handles OTG hnp timeouts, such as b_ase0_brst
294 void musb_otg_timer_func(unsigned long data)
296 struct musb *musb = (struct musb *)data;
299 spin_lock_irqsave(&musb->lock, flags);
300 switch (musb->xceiv->state) {
301 case OTG_STATE_B_WAIT_ACON:
302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 musb_g_disconnect(musb);
304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
307 case OTG_STATE_A_SUSPEND:
308 case OTG_STATE_A_WAIT_BCON:
309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
310 musb_set_vbus(musb, 0);
311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
316 musb->ignore_disconnect = 0;
317 spin_unlock_irqrestore(&musb->lock, flags);
321 * Stops the HNP transition. Caller must take care of locking.
323 void musb_hnp_stop(struct musb *musb)
325 struct usb_hcd *hcd = musb_to_hcd(musb);
326 void __iomem *mbase = musb->mregs;
329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
331 switch (musb->xceiv->state) {
332 case OTG_STATE_A_PERIPHERAL:
333 musb_g_disconnect(musb);
334 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
336 case OTG_STATE_B_HOST:
337 DBG(1, "HNP: Disabling HR\n");
338 hcd->self.is_b_host = 0;
339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
341 reg = musb_readb(mbase, MUSB_POWER);
342 reg |= MUSB_POWER_SUSPENDM;
343 musb_writeb(mbase, MUSB_POWER, reg);
344 /* REVISIT: Start SESSION_REQUEST here? */
347 DBG(1, "HNP: Stopping in unknown state %s\n",
348 otg_state_string(musb));
352 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 * which cause occasional OPT A "Did not receive reset after connect"
356 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
362 * Interrupt Service Routine to record USB "global" interrupts.
363 * Since these do not happen often and signify things of
364 * paramount importance, it seems OK to check them individually;
365 * the order of the tests is specified in the manual
367 * @param musb instance pointer
368 * @param int_usb register contents
373 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
374 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
377 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
380 irqreturn_t handled = IRQ_NONE;
382 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
385 /* in host mode, the peripheral may issue remote wakeup.
386 * in peripheral mode, the host may resume the link.
387 * spurious RESUME irqs happen too, paired with SUSPEND.
389 if (int_usb & MUSB_INTR_RESUME) {
390 handled = IRQ_HANDLED;
391 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
393 if (devctl & MUSB_DEVCTL_HM) {
394 #ifdef CONFIG_USB_MUSB_HDRC_HCD
395 void __iomem *mbase = musb->mregs;
397 switch (musb->xceiv->state) {
398 case OTG_STATE_A_SUSPEND:
399 /* remote wakeup? later, GetPortStatus
400 * will stop RESUME signaling
403 if (power & MUSB_POWER_SUSPENDM) {
405 musb->int_usb &= ~MUSB_INTR_SUSPEND;
406 DBG(2, "Spurious SUSPENDM\n");
410 power &= ~MUSB_POWER_SUSPENDM;
411 musb_writeb(mbase, MUSB_POWER,
412 power | MUSB_POWER_RESUME);
414 musb->port1_status |=
415 (USB_PORT_STAT_C_SUSPEND << 16)
416 | MUSB_PORT_STAT_RESUME;
417 musb->rh_timer = jiffies
418 + msecs_to_jiffies(20);
420 musb->xceiv->state = OTG_STATE_A_HOST;
422 usb_hcd_resume_root_hub(musb_to_hcd(musb));
424 case OTG_STATE_B_WAIT_ACON:
425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
430 WARNING("bogus %s RESUME (%s)\n",
432 otg_state_string(musb));
436 switch (musb->xceiv->state) {
437 #ifdef CONFIG_USB_MUSB_HDRC_HCD
438 case OTG_STATE_A_SUSPEND:
439 /* possibly DISCONNECT is upcoming */
440 musb->xceiv->state = OTG_STATE_A_HOST;
441 usb_hcd_resume_root_hub(musb_to_hcd(musb));
444 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
445 case OTG_STATE_B_WAIT_ACON:
446 case OTG_STATE_B_PERIPHERAL:
447 /* disconnect while suspended? we may
448 * not get a disconnect irq...
450 if ((devctl & MUSB_DEVCTL_VBUS)
451 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
453 musb->int_usb |= MUSB_INTR_DISCONNECT;
454 musb->int_usb &= ~MUSB_INTR_SUSPEND;
459 case OTG_STATE_B_IDLE:
460 musb->int_usb &= ~MUSB_INTR_SUSPEND;
464 WARNING("bogus %s RESUME (%s)\n",
466 otg_state_string(musb));
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 /* see manual for the order of the tests */
473 if (int_usb & MUSB_INTR_SESSREQ) {
474 void __iomem *mbase = musb->mregs;
476 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
478 /* IRQ arrives from ID pin sense or (later, if VBUS power
479 * is removed) SRP. responses are time critical:
480 * - turn on VBUS (with silicon-specific mechanism)
481 * - go through A_WAIT_VRISE
482 * - ... to A_WAIT_BCON.
483 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
485 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
486 musb->ep0_stage = MUSB_EP0_START;
487 musb->xceiv->state = OTG_STATE_A_IDLE;
489 musb_set_vbus(musb, 1);
491 handled = IRQ_HANDLED;
494 if (int_usb & MUSB_INTR_VBUSERROR) {
497 /* During connection as an A-Device, we may see a short
498 * current spikes causing voltage drop, because of cable
499 * and peripheral capacitance combined with vbus draw.
500 * (So: less common with truly self-powered devices, where
501 * vbus doesn't act like a power supply.)
503 * Such spikes are short; usually less than ~500 usec, max
504 * of ~2 msec. That is, they're not sustained overcurrent
505 * errors, though they're reported using VBUSERROR irqs.
507 * Workarounds: (a) hardware: use self powered devices.
508 * (b) software: ignore non-repeated VBUS errors.
510 * REVISIT: do delays from lots of DEBUG_KERNEL checks
511 * make trouble here, keeping VBUS < 4.4V ?
513 switch (musb->xceiv->state) {
514 case OTG_STATE_A_HOST:
515 /* recovery is dicey once we've gotten past the
516 * initial stages of enumeration, but if VBUS
517 * stayed ok at the other end of the link, and
518 * another reset is due (at least for high speed,
519 * to redo the chirp etc), it might work OK...
521 case OTG_STATE_A_WAIT_BCON:
522 case OTG_STATE_A_WAIT_VRISE:
523 if (musb->vbuserr_retry) {
524 void __iomem *mbase = musb->mregs;
526 musb->vbuserr_retry--;
528 devctl |= MUSB_DEVCTL_SESSION;
529 musb_writeb(mbase, MUSB_DEVCTL, devctl);
531 musb->port1_status |=
532 USB_PORT_STAT_OVERCURRENT
533 | (USB_PORT_STAT_C_OVERCURRENT << 16);
540 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
541 otg_state_string(musb),
544 switch (devctl & MUSB_DEVCTL_VBUS) {
545 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
546 s = "<SessEnd"; break;
547 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
548 s = "<AValid"; break;
549 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
550 s = "<VBusValid"; break;
551 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
555 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
558 /* go through A_WAIT_VFALL then start a new session */
560 musb_set_vbus(musb, 0);
561 handled = IRQ_HANDLED;
565 if (int_usb & MUSB_INTR_SUSPEND) {
566 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
567 otg_state_string(musb), devctl, power);
568 handled = IRQ_HANDLED;
570 switch (musb->xceiv->state) {
571 #ifdef CONFIG_USB_MUSB_OTG
572 case OTG_STATE_A_PERIPHERAL:
573 /* We also come here if the cable is removed, since
574 * this silicon doesn't report ID-no-longer-grounded.
576 * We depend on T(a_wait_bcon) to shut us down, and
577 * hope users don't do anything dicey during this
578 * undesired detour through A_WAIT_BCON.
581 usb_hcd_resume_root_hub(musb_to_hcd(musb));
582 musb_root_disconnect(musb);
583 musb_platform_try_idle(musb, jiffies
584 + msecs_to_jiffies(musb->a_wait_bcon
585 ? : OTG_TIME_A_WAIT_BCON));
589 case OTG_STATE_B_IDLE:
590 if (!musb->is_active)
592 case OTG_STATE_B_PERIPHERAL:
593 musb_g_suspend(musb);
594 musb->is_active = is_otg_enabled(musb)
595 && musb->xceiv->gadget->b_hnp_enable;
596 if (musb->is_active) {
597 #ifdef CONFIG_USB_MUSB_OTG
598 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
599 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
600 mod_timer(&musb->otg_timer, jiffies
602 OTG_TIME_B_ASE0_BRST));
606 case OTG_STATE_A_WAIT_BCON:
607 if (musb->a_wait_bcon != 0)
608 musb_platform_try_idle(musb, jiffies
609 + msecs_to_jiffies(musb->a_wait_bcon));
611 case OTG_STATE_A_HOST:
612 musb->xceiv->state = OTG_STATE_A_SUSPEND;
613 musb->is_active = is_otg_enabled(musb)
614 && musb->xceiv->host->b_hnp_enable;
616 case OTG_STATE_B_HOST:
617 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
618 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
621 /* "should not happen" */
627 if (int_usb & MUSB_INTR_CONNECT) {
628 struct usb_hcd *hcd = musb_to_hcd(musb);
629 void __iomem *mbase = musb->mregs;
631 handled = IRQ_HANDLED;
633 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
635 musb->ep0_stage = MUSB_EP0_START;
637 #ifdef CONFIG_USB_MUSB_OTG
638 /* flush endpoints when transitioning from Device Mode */
639 if (is_peripheral_active(musb)) {
640 /* REVISIT HNP; just force disconnect */
642 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
643 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
644 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
646 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
647 |USB_PORT_STAT_HIGH_SPEED
648 |USB_PORT_STAT_ENABLE
650 musb->port1_status |= USB_PORT_STAT_CONNECTION
651 |(USB_PORT_STAT_C_CONNECTION << 16);
653 /* high vs full speed is just a guess until after reset */
654 if (devctl & MUSB_DEVCTL_LSDEV)
655 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
657 /* indicate new connection to OTG machine */
658 switch (musb->xceiv->state) {
659 case OTG_STATE_B_PERIPHERAL:
660 if (int_usb & MUSB_INTR_SUSPEND) {
661 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
662 int_usb &= ~MUSB_INTR_SUSPEND;
665 DBG(1, "CONNECT as b_peripheral???\n");
667 case OTG_STATE_B_WAIT_ACON:
668 DBG(1, "HNP: CONNECT, now b_host\n");
670 musb->xceiv->state = OTG_STATE_B_HOST;
671 hcd->self.is_b_host = 1;
672 musb->ignore_disconnect = 0;
673 del_timer(&musb->otg_timer);
676 if ((devctl & MUSB_DEVCTL_VBUS)
677 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
678 musb->xceiv->state = OTG_STATE_A_HOST;
679 hcd->self.is_b_host = 0;
684 /* poke the root hub */
687 usb_hcd_poll_rh_status(hcd);
689 usb_hcd_resume_root_hub(hcd);
691 DBG(1, "CONNECT (%s) devctl %02x\n",
692 otg_state_string(musb), devctl);
694 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
696 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
697 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
698 otg_state_string(musb),
699 MUSB_MODE(musb), devctl);
700 handled = IRQ_HANDLED;
702 switch (musb->xceiv->state) {
703 #ifdef CONFIG_USB_MUSB_HDRC_HCD
704 case OTG_STATE_A_HOST:
705 case OTG_STATE_A_SUSPEND:
706 usb_hcd_resume_root_hub(musb_to_hcd(musb));
707 musb_root_disconnect(musb);
708 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
709 musb_platform_try_idle(musb, jiffies
710 + msecs_to_jiffies(musb->a_wait_bcon));
713 #ifdef CONFIG_USB_MUSB_OTG
714 case OTG_STATE_B_HOST:
715 /* REVISIT this behaves for "real disconnect"
716 * cases; make sure the other transitions from
717 * from B_HOST act right too. The B_HOST code
718 * in hnp_stop() is currently not used...
720 musb_root_disconnect(musb);
721 musb_to_hcd(musb)->self.is_b_host = 0;
722 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
724 musb_g_disconnect(musb);
726 case OTG_STATE_A_PERIPHERAL:
728 musb_root_disconnect(musb);
730 case OTG_STATE_B_WAIT_ACON:
733 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
734 case OTG_STATE_B_PERIPHERAL:
735 case OTG_STATE_B_IDLE:
736 musb_g_disconnect(musb);
740 WARNING("unhandled DISCONNECT transition (%s)\n",
741 otg_state_string(musb));
746 /* mentor saves a bit: bus reset and babble share the same irq.
747 * only host sees babble; only peripheral sees bus reset.
749 if (int_usb & MUSB_INTR_RESET) {
750 handled = IRQ_HANDLED;
751 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
753 * Looks like non-HS BABBLE can be ignored, but
754 * HS BABBLE is an error condition. For HS the solution
755 * is to avoid babble in the first place and fix what
756 * caused BABBLE. When HS BABBLE happens we can only
759 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
760 DBG(1, "BABBLE devctl: %02x\n", devctl);
762 ERR("Stopping host session -- babble\n");
763 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
765 } else if (is_peripheral_capable()) {
766 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
767 switch (musb->xceiv->state) {
768 #ifdef CONFIG_USB_OTG
769 case OTG_STATE_A_SUSPEND:
770 /* We need to ignore disconnect on suspend
771 * otherwise tusb 2.0 won't reconnect after a
772 * power cycle, which breaks otg compliance.
774 musb->ignore_disconnect = 1;
777 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
778 /* never use invalid T(a_wait_bcon) */
779 DBG(1, "HNP: in %s, %d msec timeout\n",
780 otg_state_string(musb),
782 mod_timer(&musb->otg_timer, jiffies
783 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
785 case OTG_STATE_A_PERIPHERAL:
786 musb->ignore_disconnect = 0;
787 del_timer(&musb->otg_timer);
790 case OTG_STATE_B_WAIT_ACON:
791 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
792 otg_state_string(musb));
793 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
797 case OTG_STATE_B_IDLE:
798 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
800 case OTG_STATE_B_PERIPHERAL:
804 DBG(1, "Unhandled BUS RESET as %s\n",
805 otg_state_string(musb));
811 /* REVISIT ... this would be for multiplexing periodic endpoints, or
812 * supporting transfer phasing to prevent exceeding ISO bandwidth
813 * limits of a given frame or microframe.
815 * It's not needed for peripheral side, which dedicates endpoints;
816 * though it _might_ use SOF irqs for other purposes.
818 * And it's not currently needed for host side, which also dedicates
819 * endpoints, relies on TX/RX interval registers, and isn't claimed
820 * to support ISO transfers yet.
822 if (int_usb & MUSB_INTR_SOF) {
823 void __iomem *mbase = musb->mregs;
824 struct musb_hw_ep *ep;
828 DBG(6, "START_OF_FRAME\n");
829 handled = IRQ_HANDLED;
831 /* start any periodic Tx transfers waiting for current frame */
832 frame = musb_readw(mbase, MUSB_FRAME);
833 ep = musb->endpoints;
834 for (epnum = 1; (epnum < musb->nr_endpoints)
835 && (musb->epmask >= (1 << epnum));
838 * FIXME handle framecounter wraps (12 bits)
839 * eliminate duplicated StartUrb logic
841 if (ep->dwWaitFrame >= frame) {
843 pr_debug("SOF --> periodic TX%s on %d\n",
844 ep->tx_channel ? " DMA" : "",
847 musb_h_tx_start(musb, epnum);
849 cppi_hostdma_start(musb, epnum);
851 } /* end of for loop */
855 schedule_work(&musb->irq_work);
860 /*-------------------------------------------------------------------------*/
863 * Program the HDRC to start (enable interrupts, dma, etc.).
865 void musb_start(struct musb *musb)
867 void __iomem *regs = musb->mregs;
868 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
870 DBG(2, "<== devctl %02x\n", devctl);
872 /* Set INT enable registers, enable interrupts */
873 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
874 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
875 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
877 musb_writeb(regs, MUSB_TESTMODE, 0);
879 /* put into basic highspeed mode and start session */
880 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
881 | MUSB_POWER_SOFTCONN
883 /* ENSUSPEND wedges tusb */
884 /* | MUSB_POWER_ENSUSPEND */
888 devctl = musb_readb(regs, MUSB_DEVCTL);
889 devctl &= ~MUSB_DEVCTL_SESSION;
891 if (is_otg_enabled(musb)) {
892 /* session started after:
893 * (a) ID-grounded irq, host mode;
894 * (b) vbus present/connect IRQ, peripheral mode;
895 * (c) peripheral initiates, using SRP
897 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
900 devctl |= MUSB_DEVCTL_SESSION;
902 } else if (is_host_enabled(musb)) {
903 /* assume ID pin is hard-wired to ground */
904 devctl |= MUSB_DEVCTL_SESSION;
906 } else /* peripheral is enabled */ {
907 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
910 musb_platform_enable(musb);
911 musb_writeb(regs, MUSB_DEVCTL, devctl);
915 static void musb_generic_disable(struct musb *musb)
917 void __iomem *mbase = musb->mregs;
920 /* disable interrupts */
921 musb_writeb(mbase, MUSB_INTRUSBE, 0);
922 musb_writew(mbase, MUSB_INTRTXE, 0);
923 musb_writew(mbase, MUSB_INTRRXE, 0);
926 musb_writeb(mbase, MUSB_DEVCTL, 0);
928 /* flush pending interrupts */
929 temp = musb_readb(mbase, MUSB_INTRUSB);
930 temp = musb_readw(mbase, MUSB_INTRTX);
931 temp = musb_readw(mbase, MUSB_INTRRX);
936 * Make the HDRC stop (disable interrupts, etc.);
937 * reversible by musb_start
938 * called on gadget driver unregister
939 * with controller locked, irqs blocked
940 * acts as a NOP unless some role activated the hardware
942 void musb_stop(struct musb *musb)
944 /* stop IRQs, timers, ... */
945 musb_platform_disable(musb);
946 musb_generic_disable(musb);
947 DBG(3, "HDRC disabled\n");
950 * - mark host and/or peripheral drivers unusable/inactive
951 * - disable DMA (and enable it in HdrcStart)
952 * - make sure we can musb_start() after musb_stop(); with
953 * OTG mode, gadget driver module rmmod/modprobe cycles that
956 musb_platform_try_idle(musb, 0);
959 static void musb_shutdown(struct platform_device *pdev)
961 struct musb *musb = dev_to_musb(&pdev->dev);
964 spin_lock_irqsave(&musb->lock, flags);
965 musb_platform_disable(musb);
966 musb_generic_disable(musb);
968 clk_put(musb->clock);
969 spin_unlock_irqrestore(&musb->lock, flags);
971 /* FIXME power down */
975 /*-------------------------------------------------------------------------*/
978 * The silicon either has hard-wired endpoint configurations, or else
979 * "dynamic fifo" sizing. The driver has support for both, though at this
980 * writing only the dynamic sizing is very well tested. Since we switched
981 * away from compile-time hardware parameters, we can no longer rely on
982 * dead code elimination to leave only the relevant one in the object file.
984 * We don't currently use dynamic fifo setup capability to do anything
985 * more than selecting one of a bunch of predefined configurations.
987 #if defined(CONFIG_USB_TUSB6010) || \
988 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
989 || defined(CONFIG_ARCH_OMAP4)
990 static ushort __initdata fifo_mode = 4;
992 static ushort __initdata fifo_mode = 2;
995 /* "modprobe ... fifo_mode=1" etc */
996 module_param(fifo_mode, ushort, 0);
997 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1000 * tables defining fifo_mode values. define more if you like.
1001 * for host side, make sure both halves of ep1 are set up.
1004 /* mode 0 - fits in 2KB */
1005 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1006 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1007 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1008 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1009 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1010 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1013 /* mode 1 - fits in 4KB */
1014 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1015 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1016 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1017 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1018 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1019 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1022 /* mode 2 - fits in 4KB */
1023 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1024 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1025 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1026 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1027 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1028 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1029 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1032 /* mode 3 - fits in 4KB */
1033 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1034 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1035 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1036 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1037 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1038 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1039 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1042 /* mode 4 - fits in 16KB */
1043 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1044 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1045 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1046 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1047 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1048 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1049 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1050 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1051 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1052 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1053 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1054 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1055 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1056 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1057 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1058 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1059 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1060 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1061 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1062 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1063 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1064 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1065 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1066 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1067 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1068 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1069 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1070 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1073 /* mode 5 - fits in 8KB */
1074 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1075 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1076 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1077 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1082 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1083 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1084 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1085 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1086 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1087 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1088 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1089 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1090 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1091 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1092 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1093 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1094 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1095 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1096 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1097 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1098 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1099 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1100 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1101 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1105 * configure a fifo; for non-shared endpoints, this may be called
1106 * once for a tx fifo and once for an rx fifo.
1108 * returns negative errno or offset for next fifo.
1111 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1112 const struct musb_fifo_cfg *cfg, u16 offset)
1114 void __iomem *mbase = musb->mregs;
1116 u16 maxpacket = cfg->maxpacket;
1117 u16 c_off = offset >> 3;
1120 /* expect hw_ep has already been zero-initialized */
1122 size = ffs(max(maxpacket, (u16) 8)) - 1;
1123 maxpacket = 1 << size;
1126 if (cfg->mode == BUF_DOUBLE) {
1127 if ((offset + (maxpacket << 1)) >
1128 (1 << (musb->config->ram_bits + 2)))
1130 c_size |= MUSB_FIFOSZ_DPB;
1132 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1136 /* configure the FIFO */
1137 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1139 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1140 /* EP0 reserved endpoint for control, bidirectional;
1141 * EP1 reserved for bulk, two unidirection halves.
1143 if (hw_ep->epnum == 1)
1144 musb->bulk_ep = hw_ep;
1145 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1147 switch (cfg->style) {
1149 musb_write_txfifosz(mbase, c_size);
1150 musb_write_txfifoadd(mbase, c_off);
1151 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1152 hw_ep->max_packet_sz_tx = maxpacket;
1155 musb_write_rxfifosz(mbase, c_size);
1156 musb_write_rxfifoadd(mbase, c_off);
1157 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1158 hw_ep->max_packet_sz_rx = maxpacket;
1161 musb_write_txfifosz(mbase, c_size);
1162 musb_write_txfifoadd(mbase, c_off);
1163 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1164 hw_ep->max_packet_sz_rx = maxpacket;
1166 musb_write_rxfifosz(mbase, c_size);
1167 musb_write_rxfifoadd(mbase, c_off);
1168 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1169 hw_ep->max_packet_sz_tx = maxpacket;
1171 hw_ep->is_shared_fifo = true;
1175 /* NOTE rx and tx endpoint irqs aren't managed separately,
1176 * which happens to be ok
1178 musb->epmask |= (1 << hw_ep->epnum);
1180 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1183 static struct musb_fifo_cfg __initdata ep0_cfg = {
1184 .style = FIFO_RXTX, .maxpacket = 64,
1187 static int __init ep_config_from_table(struct musb *musb)
1189 const struct musb_fifo_cfg *cfg;
1192 struct musb_hw_ep *hw_ep = musb->endpoints;
1194 if (musb->config->fifo_cfg) {
1195 cfg = musb->config->fifo_cfg;
1196 n = musb->config->fifo_cfg_size;
1200 switch (fifo_mode) {
1206 n = ARRAY_SIZE(mode_0_cfg);
1210 n = ARRAY_SIZE(mode_1_cfg);
1214 n = ARRAY_SIZE(mode_2_cfg);
1218 n = ARRAY_SIZE(mode_3_cfg);
1222 n = ARRAY_SIZE(mode_4_cfg);
1226 n = ARRAY_SIZE(mode_5_cfg);
1230 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1231 musb_driver_name, fifo_mode);
1235 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1236 /* assert(offset > 0) */
1238 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1239 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1242 for (i = 0; i < n; i++) {
1243 u8 epn = cfg->hw_ep_num;
1245 if (epn >= musb->config->num_eps) {
1246 pr_debug("%s: invalid ep %d\n",
1247 musb_driver_name, epn);
1250 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1252 pr_debug("%s: mem overrun, ep %d\n",
1253 musb_driver_name, epn);
1257 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1260 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1262 n + 1, musb->config->num_eps * 2 - 1,
1263 offset, (1 << (musb->config->ram_bits + 2)));
1265 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1266 if (!musb->bulk_ep) {
1267 pr_debug("%s: missing bulk\n", musb_driver_name);
1277 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1278 * @param musb the controller
1280 static int __init ep_config_from_hw(struct musb *musb)
1283 struct musb_hw_ep *hw_ep;
1284 void *mbase = musb->mregs;
1287 DBG(2, "<== static silicon ep config\n");
1289 /* FIXME pick up ep0 maxpacket size */
1291 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1292 musb_ep_select(mbase, epnum);
1293 hw_ep = musb->endpoints + epnum;
1295 ret = musb_read_fifosize(musb, hw_ep, epnum);
1299 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1301 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1302 /* pick an RX/TX endpoint for bulk */
1303 if (hw_ep->max_packet_sz_tx < 512
1304 || hw_ep->max_packet_sz_rx < 512)
1307 /* REVISIT: this algorithm is lazy, we should at least
1308 * try to pick a double buffered endpoint.
1312 musb->bulk_ep = hw_ep;
1316 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1317 if (!musb->bulk_ep) {
1318 pr_debug("%s: missing bulk\n", musb_driver_name);
1326 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1328 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1329 * configure endpoints, or take their config from silicon
1331 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1335 char aInfo[90], aRevision[32], aDate[12];
1336 void __iomem *mbase = musb->mregs;
1340 /* log core options (read using indexed model) */
1341 reg = musb_read_configdata(mbase);
1343 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1344 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1345 strcat(aInfo, ", dyn FIFOs");
1346 musb->dyn_fifo = true;
1348 if (reg & MUSB_CONFIGDATA_MPRXE) {
1349 strcat(aInfo, ", bulk combine");
1350 musb->bulk_combine = true;
1352 if (reg & MUSB_CONFIGDATA_MPTXE) {
1353 strcat(aInfo, ", bulk split");
1354 musb->bulk_split = true;
1356 if (reg & MUSB_CONFIGDATA_HBRXE) {
1357 strcat(aInfo, ", HB-ISO Rx");
1358 musb->hb_iso_rx = true;
1360 if (reg & MUSB_CONFIGDATA_HBTXE) {
1361 strcat(aInfo, ", HB-ISO Tx");
1362 musb->hb_iso_tx = true;
1364 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1365 strcat(aInfo, ", SoftConn");
1367 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1368 musb_driver_name, reg, aInfo);
1371 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1372 musb->is_multipoint = 1;
1375 musb->is_multipoint = 0;
1377 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1378 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1380 "%s: kernel must blacklist external hubs\n",
1386 /* log release info */
1387 musb->hwvers = musb_read_hwvers(mbase);
1388 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1389 MUSB_HWVERS_MINOR(musb->hwvers),
1390 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1391 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1392 musb_driver_name, type, aRevision, aDate);
1395 musb_configure_ep0(musb);
1397 /* discover endpoint configuration */
1398 musb->nr_endpoints = 1;
1402 status = ep_config_from_table(musb);
1404 status = ep_config_from_hw(musb);
1409 /* finish init, and print endpoint config */
1410 for (i = 0; i < musb->nr_endpoints; i++) {
1411 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1413 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1414 #ifdef CONFIG_USB_TUSB6010
1415 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1416 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1417 hw_ep->fifo_sync_va =
1418 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1421 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1423 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1426 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1427 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1428 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1429 hw_ep->rx_reinit = 1;
1430 hw_ep->tx_reinit = 1;
1433 if (hw_ep->max_packet_sz_tx) {
1435 "%s: hw_ep %d%s, %smax %d\n",
1436 musb_driver_name, i,
1437 hw_ep->is_shared_fifo ? "shared" : "tx",
1438 hw_ep->tx_double_buffered
1439 ? "doublebuffer, " : "",
1440 hw_ep->max_packet_sz_tx);
1442 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1444 "%s: hw_ep %d%s, %smax %d\n",
1445 musb_driver_name, i,
1447 hw_ep->rx_double_buffered
1448 ? "doublebuffer, " : "",
1449 hw_ep->max_packet_sz_rx);
1451 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1452 DBG(1, "hw_ep %d not configured\n", i);
1458 /*-------------------------------------------------------------------------*/
1460 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1461 defined(CONFIG_ARCH_OMAP4)
1463 static irqreturn_t generic_interrupt(int irq, void *__hci)
1465 unsigned long flags;
1466 irqreturn_t retval = IRQ_NONE;
1467 struct musb *musb = __hci;
1469 spin_lock_irqsave(&musb->lock, flags);
1471 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1472 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1473 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1475 if (musb->int_usb || musb->int_tx || musb->int_rx)
1476 retval = musb_interrupt(musb);
1478 spin_unlock_irqrestore(&musb->lock, flags);
1484 #define generic_interrupt NULL
1488 * handle all the irqs defined by the HDRC core. for now we expect: other
1489 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1490 * will be assigned, and the irq will already have been acked.
1492 * called in irq context with spinlock held, irqs blocked
1494 irqreturn_t musb_interrupt(struct musb *musb)
1496 irqreturn_t retval = IRQ_NONE;
1501 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1502 power = musb_readb(musb->mregs, MUSB_POWER);
1504 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1505 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1506 musb->int_usb, musb->int_tx, musb->int_rx);
1508 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1509 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1510 if (!musb->gadget_driver) {
1511 DBG(5, "No gadget driver loaded\n");
1516 /* the core can interrupt us for multiple reasons; docs have
1517 * a generic interrupt flowchart to follow
1519 if (musb->int_usb & STAGE0_MASK)
1520 retval |= musb_stage0_irq(musb, musb->int_usb,
1523 /* "stage 1" is handling endpoint irqs */
1525 /* handle endpoint 0 first */
1526 if (musb->int_tx & 1) {
1527 if (devctl & MUSB_DEVCTL_HM)
1528 retval |= musb_h_ep0_irq(musb);
1530 retval |= musb_g_ep0_irq(musb);
1533 /* RX on endpoints 1-15 */
1534 reg = musb->int_rx >> 1;
1538 /* musb_ep_select(musb->mregs, ep_num); */
1539 /* REVISIT just retval = ep->rx_irq(...) */
1540 retval = IRQ_HANDLED;
1541 if (devctl & MUSB_DEVCTL_HM) {
1542 if (is_host_capable())
1543 musb_host_rx(musb, ep_num);
1545 if (is_peripheral_capable())
1546 musb_g_rx(musb, ep_num);
1554 /* TX on endpoints 1-15 */
1555 reg = musb->int_tx >> 1;
1559 /* musb_ep_select(musb->mregs, ep_num); */
1560 /* REVISIT just retval |= ep->tx_irq(...) */
1561 retval = IRQ_HANDLED;
1562 if (devctl & MUSB_DEVCTL_HM) {
1563 if (is_host_capable())
1564 musb_host_tx(musb, ep_num);
1566 if (is_peripheral_capable())
1567 musb_g_tx(musb, ep_num);
1578 #ifndef CONFIG_MUSB_PIO_ONLY
1579 static int __initdata use_dma = 1;
1581 /* "modprobe ... use_dma=0" etc */
1582 module_param(use_dma, bool, 0);
1583 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1585 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1587 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1589 /* called with controller lock already held */
1592 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1593 if (!is_cppi_enabled()) {
1595 if (devctl & MUSB_DEVCTL_HM)
1596 musb_h_ep0_irq(musb);
1598 musb_g_ep0_irq(musb);
1602 /* endpoints 1..15 */
1604 if (devctl & MUSB_DEVCTL_HM) {
1605 if (is_host_capable())
1606 musb_host_tx(musb, epnum);
1608 if (is_peripheral_capable())
1609 musb_g_tx(musb, epnum);
1613 if (devctl & MUSB_DEVCTL_HM) {
1614 if (is_host_capable())
1615 musb_host_rx(musb, epnum);
1617 if (is_peripheral_capable())
1618 musb_g_rx(musb, epnum);
1628 /*-------------------------------------------------------------------------*/
1633 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1635 struct musb *musb = dev_to_musb(dev);
1636 unsigned long flags;
1639 spin_lock_irqsave(&musb->lock, flags);
1640 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1641 spin_unlock_irqrestore(&musb->lock, flags);
1647 musb_mode_store(struct device *dev, struct device_attribute *attr,
1648 const char *buf, size_t n)
1650 struct musb *musb = dev_to_musb(dev);
1651 unsigned long flags;
1654 spin_lock_irqsave(&musb->lock, flags);
1655 if (sysfs_streq(buf, "host"))
1656 status = musb_platform_set_mode(musb, MUSB_HOST);
1657 else if (sysfs_streq(buf, "peripheral"))
1658 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1659 else if (sysfs_streq(buf, "otg"))
1660 status = musb_platform_set_mode(musb, MUSB_OTG);
1663 spin_unlock_irqrestore(&musb->lock, flags);
1665 return (status == 0) ? n : status;
1667 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1670 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1671 const char *buf, size_t n)
1673 struct musb *musb = dev_to_musb(dev);
1674 unsigned long flags;
1677 if (sscanf(buf, "%lu", &val) < 1) {
1678 dev_err(dev, "Invalid VBUS timeout ms value\n");
1682 spin_lock_irqsave(&musb->lock, flags);
1683 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1684 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1685 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1686 musb->is_active = 0;
1687 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1688 spin_unlock_irqrestore(&musb->lock, flags);
1694 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1696 struct musb *musb = dev_to_musb(dev);
1697 unsigned long flags;
1701 spin_lock_irqsave(&musb->lock, flags);
1702 val = musb->a_wait_bcon;
1703 /* FIXME get_vbus_status() is normally #defined as false...
1704 * and is effectively TUSB-specific.
1706 vbus = musb_platform_get_vbus_status(musb);
1707 spin_unlock_irqrestore(&musb->lock, flags);
1709 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1710 vbus ? "on" : "off", val);
1712 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1714 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1716 /* Gadget drivers can't know that a host is connected so they might want
1717 * to start SRP, but users can. This allows userspace to trigger SRP.
1720 musb_srp_store(struct device *dev, struct device_attribute *attr,
1721 const char *buf, size_t n)
1723 struct musb *musb = dev_to_musb(dev);
1726 if (sscanf(buf, "%hu", &srp) != 1
1728 dev_err(dev, "SRP: Value must be 1\n");
1733 musb_g_wakeup(musb);
1737 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1739 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1741 static struct attribute *musb_attributes[] = {
1742 &dev_attr_mode.attr,
1743 &dev_attr_vbus.attr,
1744 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1750 static const struct attribute_group musb_attr_group = {
1751 .attrs = musb_attributes,
1756 /* Only used to provide driver mode change events */
1757 static void musb_irq_work(struct work_struct *data)
1759 struct musb *musb = container_of(data, struct musb, irq_work);
1760 static int old_state;
1762 if (musb->xceiv->state != old_state) {
1763 old_state = musb->xceiv->state;
1764 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1768 /* --------------------------------------------------------------------------
1772 static struct musb *__init
1773 allocate_instance(struct device *dev,
1774 struct musb_hdrc_config *config, void __iomem *mbase)
1777 struct musb_hw_ep *ep;
1779 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1780 struct usb_hcd *hcd;
1782 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1785 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1787 musb = hcd_to_musb(hcd);
1788 INIT_LIST_HEAD(&musb->control);
1789 INIT_LIST_HEAD(&musb->in_bulk);
1790 INIT_LIST_HEAD(&musb->out_bulk);
1792 hcd->uses_new_polling = 1;
1794 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1795 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1797 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1800 dev_set_drvdata(dev, musb);
1804 musb->mregs = mbase;
1805 musb->ctrl_base = mbase;
1806 musb->nIrq = -ENODEV;
1807 musb->config = config;
1808 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1809 for (epnum = 0, ep = musb->endpoints;
1810 epnum < musb->config->num_eps;
1816 musb->controller = dev;
1820 static void musb_free(struct musb *musb)
1822 /* this has multiple entry modes. it handles fault cleanup after
1823 * probe(), where things may be partially set up, as well as rmmod
1824 * cleanup after everything's been de-activated.
1828 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1831 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1832 musb_gadget_cleanup(musb);
1835 if (musb->nIrq >= 0) {
1837 disable_irq_wake(musb->nIrq);
1838 free_irq(musb->nIrq, musb);
1840 if (is_dma_capable() && musb->dma_controller) {
1841 struct dma_controller *c = musb->dma_controller;
1844 dma_controller_destroy(c);
1847 #ifdef CONFIG_USB_MUSB_OTG
1848 put_device(musb->xceiv->dev);
1851 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1852 usb_put_hcd(musb_to_hcd(musb));
1859 * Perform generic per-controller initialization.
1861 * @pDevice: the controller (already clocked, etc)
1863 * @mregs: virtual address of controller registers,
1864 * not yet corrected for platform-specific offsets
1867 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1871 struct musb_hdrc_platform_data *plat = dev->platform_data;
1873 /* The driver might handle more features than the board; OK.
1874 * Fail when the board needs a feature that's not enabled.
1877 dev_dbg(dev, "no platform_data?\n");
1882 switch (plat->mode) {
1884 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1889 case MUSB_PERIPHERAL:
1890 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1896 #ifdef CONFIG_USB_MUSB_OTG
1902 dev_err(dev, "incompatible Kconfig role setting\n");
1908 musb = allocate_instance(dev, plat->config, ctrl);
1914 spin_lock_init(&musb->lock);
1915 musb->board_mode = plat->mode;
1916 musb->board_set_power = plat->set_power;
1917 musb->set_clock = plat->set_clock;
1918 musb->min_power = plat->min_power;
1920 /* Clock usage is chip-specific ... functional clock (DaVinci,
1921 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1922 * code does is make sure a clock handle is available; platform
1923 * code manages it during start/stop and suspend/resume.
1926 musb->clock = clk_get(dev, plat->clock);
1927 if (IS_ERR(musb->clock)) {
1928 status = PTR_ERR(musb->clock);
1934 /* The musb_platform_init() call:
1935 * - adjusts musb->mregs and musb->isr if needed,
1936 * - may initialize an integrated tranceiver
1937 * - initializes musb->xceiv, usually by otg_get_transceiver()
1938 * - activates clocks.
1939 * - stops powering VBUS
1940 * - assigns musb->board_set_vbus if host mode is enabled
1942 * There are various transciever configurations. Blackfin,
1943 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1944 * external/discrete ones in various flavors (twl4030 family,
1945 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1947 musb->isr = generic_interrupt;
1948 status = musb_platform_init(musb, plat->board_data);
1957 #ifndef CONFIG_MUSB_PIO_ONLY
1958 if (use_dma && dev->dma_mask) {
1959 struct dma_controller *c;
1961 c = dma_controller_create(musb, musb->mregs);
1962 musb->dma_controller = c;
1967 /* ideally this would be abstracted in platform setup */
1968 if (!is_dma_capable() || !musb->dma_controller)
1969 dev->dma_mask = NULL;
1971 /* be sure interrupts are disabled before connecting ISR */
1972 musb_platform_disable(musb);
1973 musb_generic_disable(musb);
1975 /* setup musb parts of the core (especially endpoints) */
1976 status = musb_core_init(plat->config->multipoint
1977 ? MUSB_CONTROLLER_MHDRC
1978 : MUSB_CONTROLLER_HDRC, musb);
1982 #ifdef CONFIG_USB_MUSB_OTG
1983 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1986 /* Init IRQ workqueue before request_irq */
1987 INIT_WORK(&musb->irq_work, musb_irq_work);
1989 /* attach to the IRQ */
1990 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1991 dev_err(dev, "request_irq %d failed!\n", nIrq);
1996 /* FIXME this handles wakeup irqs wrong */
1997 if (enable_irq_wake(nIrq) == 0) {
1999 device_init_wakeup(dev, 1);
2004 /* host side needs more setup */
2005 if (is_host_enabled(musb)) {
2006 struct usb_hcd *hcd = musb_to_hcd(musb);
2008 otg_set_host(musb->xceiv, &hcd->self);
2010 if (is_otg_enabled(musb))
2011 hcd->self.otg_port = 1;
2012 musb->xceiv->host = &hcd->self;
2013 hcd->power_budget = 2 * (plat->power ? : 250);
2015 /* program PHY to use external vBus if required */
2016 if (plat->extvbus) {
2017 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2018 busctl |= MUSB_ULPI_USE_EXTVBUS;
2019 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2023 /* For the host-only role, we can activate right away.
2024 * (We expect the ID pin to be forcibly grounded!!)
2025 * Otherwise, wait till the gadget driver hooks up.
2027 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2028 MUSB_HST_MODE(musb);
2029 musb->xceiv->default_a = 1;
2030 musb->xceiv->state = OTG_STATE_A_IDLE;
2032 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2034 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2036 musb_readb(musb->mregs, MUSB_DEVCTL),
2037 (musb_readb(musb->mregs, MUSB_DEVCTL)
2038 & MUSB_DEVCTL_BDEVICE
2041 } else /* peripheral is enabled */ {
2042 MUSB_DEV_MODE(musb);
2043 musb->xceiv->default_a = 0;
2044 musb->xceiv->state = OTG_STATE_B_IDLE;
2046 status = musb_gadget_setup(musb);
2048 DBG(1, "%s mode, status %d, dev%02x\n",
2049 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2051 musb_readb(musb->mregs, MUSB_DEVCTL));
2057 status = musb_init_debugfs(musb);
2062 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2067 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2069 switch (musb->board_mode) {
2070 case MUSB_HOST: s = "Host"; break;
2071 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2072 default: s = "OTG"; break;
2075 (is_dma_capable() && musb->dma_controller)
2082 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2083 usb_remove_hcd(musb_to_hcd(musb));
2085 musb_gadget_cleanup(musb);
2089 device_init_wakeup(dev, 0);
2090 musb_platform_exit(musb);
2094 clk_put(musb->clock);
2097 dev_err(musb->controller,
2098 "musb_init_controller failed with status %d\n", status);
2108 /*-------------------------------------------------------------------------*/
2110 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2111 * bridge to a platform device; this driver then suffices.
2114 #ifndef CONFIG_MUSB_PIO_ONLY
2115 static u64 *orig_dma_mask;
2118 static int __init musb_probe(struct platform_device *pdev)
2120 struct device *dev = &pdev->dev;
2121 int irq = platform_get_irq(pdev, 0);
2123 struct resource *iomem;
2126 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2127 if (!iomem || irq == 0)
2130 base = ioremap(iomem->start, resource_size(iomem));
2132 dev_err(dev, "ioremap failed\n");
2136 #ifndef CONFIG_MUSB_PIO_ONLY
2137 /* clobbered by use_dma=n */
2138 orig_dma_mask = dev->dma_mask;
2140 status = musb_init_controller(dev, irq, base);
2147 static int __exit musb_remove(struct platform_device *pdev)
2149 struct musb *musb = dev_to_musb(&pdev->dev);
2150 void __iomem *ctrl_base = musb->ctrl_base;
2152 /* this gets called on rmmod.
2153 * - Host mode: host may still be active
2154 * - Peripheral mode: peripheral is deactivated (or never-activated)
2155 * - OTG mode: both roles are deactivated (or never-activated)
2157 musb_exit_debugfs(musb);
2158 musb_shutdown(pdev);
2159 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2160 if (musb->board_mode == MUSB_HOST)
2161 usb_remove_hcd(musb_to_hcd(musb));
2163 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2164 musb_platform_exit(musb);
2165 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2169 device_init_wakeup(&pdev->dev, 0);
2170 #ifndef CONFIG_MUSB_PIO_ONLY
2171 pdev->dev.dma_mask = orig_dma_mask;
2178 static struct musb_context_registers musb_context;
2180 void musb_save_context(struct musb *musb)
2183 void __iomem *musb_base = musb->mregs;
2185 if (is_host_enabled(musb)) {
2186 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2187 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2188 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2190 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2191 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2192 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2193 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2194 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2195 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2197 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2198 musb_writeb(musb_base, MUSB_INDEX, i);
2199 musb_context.index_regs[i].txmaxp =
2200 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2201 musb_context.index_regs[i].txcsr =
2202 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2203 musb_context.index_regs[i].rxmaxp =
2204 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2205 musb_context.index_regs[i].rxcsr =
2206 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2208 if (musb->dyn_fifo) {
2209 musb_context.index_regs[i].txfifoadd =
2210 musb_read_txfifoadd(musb_base);
2211 musb_context.index_regs[i].rxfifoadd =
2212 musb_read_rxfifoadd(musb_base);
2213 musb_context.index_regs[i].txfifosz =
2214 musb_read_txfifosz(musb_base);
2215 musb_context.index_regs[i].rxfifosz =
2216 musb_read_rxfifosz(musb_base);
2218 if (is_host_enabled(musb)) {
2219 musb_context.index_regs[i].txtype =
2220 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2221 musb_context.index_regs[i].txinterval =
2222 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2223 musb_context.index_regs[i].rxtype =
2224 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2225 musb_context.index_regs[i].rxinterval =
2226 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2228 musb_context.index_regs[i].txfunaddr =
2229 musb_read_txfunaddr(musb_base, i);
2230 musb_context.index_regs[i].txhubaddr =
2231 musb_read_txhubaddr(musb_base, i);
2232 musb_context.index_regs[i].txhubport =
2233 musb_read_txhubport(musb_base, i);
2235 musb_context.index_regs[i].rxfunaddr =
2236 musb_read_rxfunaddr(musb_base, i);
2237 musb_context.index_regs[i].rxhubaddr =
2238 musb_read_rxhubaddr(musb_base, i);
2239 musb_context.index_regs[i].rxhubport =
2240 musb_read_rxhubport(musb_base, i);
2244 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2246 musb_platform_save_context(musb, &musb_context);
2249 void musb_restore_context(struct musb *musb)
2252 void __iomem *musb_base = musb->mregs;
2253 void __iomem *ep_target_regs;
2255 musb_platform_restore_context(musb, &musb_context);
2257 if (is_host_enabled(musb)) {
2258 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2259 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2260 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2262 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2263 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2264 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2265 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2266 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2268 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2269 musb_writeb(musb_base, MUSB_INDEX, i);
2270 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2271 musb_context.index_regs[i].txmaxp);
2272 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2273 musb_context.index_regs[i].txcsr);
2274 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2275 musb_context.index_regs[i].rxmaxp);
2276 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2277 musb_context.index_regs[i].rxcsr);
2279 if (musb->dyn_fifo) {
2280 musb_write_txfifosz(musb_base,
2281 musb_context.index_regs[i].txfifosz);
2282 musb_write_rxfifosz(musb_base,
2283 musb_context.index_regs[i].rxfifosz);
2284 musb_write_txfifoadd(musb_base,
2285 musb_context.index_regs[i].txfifoadd);
2286 musb_write_rxfifoadd(musb_base,
2287 musb_context.index_regs[i].rxfifoadd);
2290 if (is_host_enabled(musb)) {
2291 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2292 musb_context.index_regs[i].txtype);
2293 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2294 musb_context.index_regs[i].txinterval);
2295 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2296 musb_context.index_regs[i].rxtype);
2297 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2299 musb_context.index_regs[i].rxinterval);
2300 musb_write_txfunaddr(musb_base, i,
2301 musb_context.index_regs[i].txfunaddr);
2302 musb_write_txhubaddr(musb_base, i,
2303 musb_context.index_regs[i].txhubaddr);
2304 musb_write_txhubport(musb_base, i,
2305 musb_context.index_regs[i].txhubport);
2308 musb_read_target_reg_base(i, musb_base);
2310 musb_write_rxfunaddr(ep_target_regs,
2311 musb_context.index_regs[i].rxfunaddr);
2312 musb_write_rxhubaddr(ep_target_regs,
2313 musb_context.index_regs[i].rxhubaddr);
2314 musb_write_rxhubport(ep_target_regs,
2315 musb_context.index_regs[i].rxhubport);
2319 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2322 static int musb_suspend(struct device *dev)
2324 struct platform_device *pdev = to_platform_device(dev);
2325 unsigned long flags;
2326 struct musb *musb = dev_to_musb(&pdev->dev);
2331 spin_lock_irqsave(&musb->lock, flags);
2333 if (is_peripheral_active(musb)) {
2334 /* FIXME force disconnect unless we know USB will wake
2335 * the system up quickly enough to respond ...
2337 } else if (is_host_active(musb)) {
2338 /* we know all the children are suspended; sometimes
2339 * they will even be wakeup-enabled.
2343 musb_save_context(musb);
2345 if (musb->set_clock)
2346 musb->set_clock(musb->clock, 0);
2348 clk_disable(musb->clock);
2349 spin_unlock_irqrestore(&musb->lock, flags);
2353 static int musb_resume_noirq(struct device *dev)
2355 struct platform_device *pdev = to_platform_device(dev);
2356 struct musb *musb = dev_to_musb(&pdev->dev);
2361 if (musb->set_clock)
2362 musb->set_clock(musb->clock, 1);
2364 clk_enable(musb->clock);
2366 musb_restore_context(musb);
2368 /* for static cmos like DaVinci, register values were preserved
2369 * unless for some reason the whole soc powered down or the USB
2370 * module got reset through the PSC (vs just being disabled).
2375 static const struct dev_pm_ops musb_dev_pm_ops = {
2376 .suspend = musb_suspend,
2377 .resume_noirq = musb_resume_noirq,
2380 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2382 #define MUSB_DEV_PM_OPS NULL
2385 static struct platform_driver musb_driver = {
2387 .name = (char *)musb_driver_name,
2388 .bus = &platform_bus_type,
2389 .owner = THIS_MODULE,
2390 .pm = MUSB_DEV_PM_OPS,
2392 .remove = __exit_p(musb_remove),
2393 .shutdown = musb_shutdown,
2396 /*-------------------------------------------------------------------------*/
2398 static int __init musb_init(void)
2400 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2405 pr_info("%s: version " MUSB_VERSION ", "
2406 #ifdef CONFIG_MUSB_PIO_ONLY
2408 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2410 #elif defined(CONFIG_USB_INVENTRA_DMA)
2412 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2418 #ifdef CONFIG_USB_MUSB_OTG
2419 "otg (peripheral+host)"
2420 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2422 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2426 musb_driver_name, musb_debug);
2427 return platform_driver_probe(&musb_driver, musb_probe);
2430 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2431 * and before usb gadget and host-side drivers start to register
2433 fs_initcall(musb_init);
2435 static void __exit musb_cleanup(void)
2437 platform_driver_unregister(&musb_driver);
2439 module_exit(musb_cleanup);