2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102 #include <linux/idr.h>
103 #include <linux/dma-mapping.h>
105 #include "musb_core.h"
107 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
110 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113 #define MUSB_VERSION "6.0"
115 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117 #define MUSB_DRIVER_NAME "musb-hdrc"
118 const char musb_driver_name[] = MUSB_DRIVER_NAME;
120 MODULE_DESCRIPTION(DRIVER_INFO);
121 MODULE_AUTHOR(DRIVER_AUTHOR);
122 MODULE_LICENSE("GPL");
123 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
126 /*-------------------------------------------------------------------------*/
128 static inline struct musb *dev_to_musb(struct device *dev)
130 return dev_get_drvdata(dev);
133 /*-------------------------------------------------------------------------*/
135 #ifndef CONFIG_BLACKFIN
136 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
138 void __iomem *addr = phy->io_priv;
144 pm_runtime_get_sync(phy->io_dev);
146 /* Make sure the transceiver is not in low power mode */
147 power = musb_readb(addr, MUSB_POWER);
148 power &= ~MUSB_POWER_SUSPENDM;
149 musb_writeb(addr, MUSB_POWER, power);
151 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
152 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
155 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
156 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
157 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
159 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
160 & MUSB_ULPI_REG_CMPLT)) {
168 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
169 r &= ~MUSB_ULPI_REG_CMPLT;
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
172 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
175 pm_runtime_put(phy->io_dev);
180 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
182 void __iomem *addr = phy->io_priv;
188 pm_runtime_get_sync(phy->io_dev);
190 /* Make sure the transceiver is not in low power mode */
191 power = musb_readb(addr, MUSB_POWER);
192 power &= ~MUSB_POWER_SUSPENDM;
193 musb_writeb(addr, MUSB_POWER, power);
195 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
196 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
197 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
199 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
200 & MUSB_ULPI_REG_CMPLT)) {
208 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
209 r &= ~MUSB_ULPI_REG_CMPLT;
210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
213 pm_runtime_put(phy->io_dev);
218 #define musb_ulpi_read NULL
219 #define musb_ulpi_write NULL
222 static struct usb_phy_io_ops musb_ulpi_access = {
223 .read = musb_ulpi_read,
224 .write = musb_ulpi_write,
227 /*-------------------------------------------------------------------------*/
229 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
232 * Load an endpoint's FIFO
234 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
236 struct musb *musb = hw_ep->musb;
237 void __iomem *fifo = hw_ep->fifo;
239 if (unlikely(len == 0))
244 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
268 musb_writeb(fifo, 0, src[index]);
271 writesb(fifo, src, len);
275 #if !defined(CONFIG_USB_MUSB_AM35X)
277 * Unload an endpoint's FIFO
279 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
281 struct musb *musb = hw_ep->musb;
282 void __iomem *fifo = hw_ep->fifo;
284 if (unlikely(len == 0))
287 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
288 'R', hw_ep->epnum, fifo, len, dst);
290 /* we can't assume unaligned writes work */
291 if (likely((0x01 & (unsigned long) dst) == 0)) {
294 /* best case is 32bit-aligned destination address */
295 if ((0x02 & (unsigned long) dst) == 0) {
297 readsl(fifo, dst, len >> 2);
301 *(u16 *)&dst[index] = musb_readw(fifo, 0);
306 readsw(fifo, dst, len >> 1);
311 dst[index] = musb_readb(fifo, 0);
314 readsb(fifo, dst, len);
319 #endif /* normal PIO */
322 /*-------------------------------------------------------------------------*/
324 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
325 static const u8 musb_test_packet[53] = {
326 /* implicit SYNC then DATA0 to start */
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
331 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
333 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
334 /* JJJJJJJKKKKKKK x8 */
335 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
337 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
338 /* JKKKKKKK x10, JK */
339 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
341 /* implicit CRC16 then EOP to end */
344 void musb_load_testpacket(struct musb *musb)
346 void __iomem *regs = musb->endpoints[0].regs;
348 musb_ep_select(musb->mregs, 0);
349 musb_write_fifo(musb->control_ep,
350 sizeof(musb_test_packet), musb_test_packet);
351 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
354 /*-------------------------------------------------------------------------*/
357 * Handles OTG hnp timeouts, such as b_ase0_brst
359 static void musb_otg_timer_func(unsigned long data)
361 struct musb *musb = (struct musb *)data;
364 spin_lock_irqsave(&musb->lock, flags);
365 switch (musb->xceiv->state) {
366 case OTG_STATE_B_WAIT_ACON:
367 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
368 musb_g_disconnect(musb);
369 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
372 case OTG_STATE_A_SUSPEND:
373 case OTG_STATE_A_WAIT_BCON:
374 dev_dbg(musb->controller, "HNP: %s timeout\n",
375 otg_state_string(musb->xceiv->state));
376 musb_platform_set_vbus(musb, 0);
377 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
380 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
381 otg_state_string(musb->xceiv->state));
383 musb->ignore_disconnect = 0;
384 spin_unlock_irqrestore(&musb->lock, flags);
388 * Stops the HNP transition. Caller must take care of locking.
390 void musb_hnp_stop(struct musb *musb)
392 struct usb_hcd *hcd = musb_to_hcd(musb);
393 void __iomem *mbase = musb->mregs;
396 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
398 switch (musb->xceiv->state) {
399 case OTG_STATE_A_PERIPHERAL:
400 musb_g_disconnect(musb);
401 dev_dbg(musb->controller, "HNP: back to %s\n",
402 otg_state_string(musb->xceiv->state));
404 case OTG_STATE_B_HOST:
405 dev_dbg(musb->controller, "HNP: Disabling HR\n");
406 hcd->self.is_b_host = 0;
407 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
409 reg = musb_readb(mbase, MUSB_POWER);
410 reg |= MUSB_POWER_SUSPENDM;
411 musb_writeb(mbase, MUSB_POWER, reg);
412 /* REVISIT: Start SESSION_REQUEST here? */
415 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
416 otg_state_string(musb->xceiv->state));
420 * When returning to A state after HNP, avoid hub_port_rebounce(),
421 * which cause occasional OPT A "Did not receive reset after connect"
424 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
428 * Interrupt Service Routine to record USB "global" interrupts.
429 * Since these do not happen often and signify things of
430 * paramount importance, it seems OK to check them individually;
431 * the order of the tests is specified in the manual
433 * @param musb instance pointer
434 * @param int_usb register contents
439 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
442 struct usb_otg *otg = musb->xceiv->otg;
443 irqreturn_t handled = IRQ_NONE;
445 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
448 /* in host mode, the peripheral may issue remote wakeup.
449 * in peripheral mode, the host may resume the link.
450 * spurious RESUME irqs happen too, paired with SUSPEND.
452 if (int_usb & MUSB_INTR_RESUME) {
453 handled = IRQ_HANDLED;
454 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
456 if (devctl & MUSB_DEVCTL_HM) {
457 void __iomem *mbase = musb->mregs;
460 switch (musb->xceiv->state) {
461 case OTG_STATE_A_SUSPEND:
462 /* remote wakeup? later, GetPortStatus
463 * will stop RESUME signaling
466 power = musb_readb(musb->mregs, MUSB_POWER);
467 if (power & MUSB_POWER_SUSPENDM) {
469 musb->int_usb &= ~MUSB_INTR_SUSPEND;
470 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
474 power &= ~MUSB_POWER_SUSPENDM;
475 musb_writeb(mbase, MUSB_POWER,
476 power | MUSB_POWER_RESUME);
478 musb->port1_status |=
479 (USB_PORT_STAT_C_SUSPEND << 16)
480 | MUSB_PORT_STAT_RESUME;
481 musb->rh_timer = jiffies
482 + msecs_to_jiffies(20);
484 musb->xceiv->state = OTG_STATE_A_HOST;
486 usb_hcd_resume_root_hub(musb_to_hcd(musb));
488 case OTG_STATE_B_WAIT_ACON:
489 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
494 WARNING("bogus %s RESUME (%s)\n",
496 otg_state_string(musb->xceiv->state));
499 switch (musb->xceiv->state) {
500 case OTG_STATE_A_SUSPEND:
501 /* possibly DISCONNECT is upcoming */
502 musb->xceiv->state = OTG_STATE_A_HOST;
503 usb_hcd_resume_root_hub(musb_to_hcd(musb));
505 case OTG_STATE_B_WAIT_ACON:
506 case OTG_STATE_B_PERIPHERAL:
507 /* disconnect while suspended? we may
508 * not get a disconnect irq...
510 if ((devctl & MUSB_DEVCTL_VBUS)
511 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513 musb->int_usb |= MUSB_INTR_DISCONNECT;
514 musb->int_usb &= ~MUSB_INTR_SUSPEND;
519 case OTG_STATE_B_IDLE:
520 musb->int_usb &= ~MUSB_INTR_SUSPEND;
523 WARNING("bogus %s RESUME (%s)\n",
525 otg_state_string(musb->xceiv->state));
530 /* see manual for the order of the tests */
531 if (int_usb & MUSB_INTR_SESSREQ) {
532 void __iomem *mbase = musb->mregs;
534 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
535 && (devctl & MUSB_DEVCTL_BDEVICE)) {
536 dev_dbg(musb->controller, "SessReq while on B state\n");
540 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
541 otg_state_string(musb->xceiv->state));
543 /* IRQ arrives from ID pin sense or (later, if VBUS power
544 * is removed) SRP. responses are time critical:
545 * - turn on VBUS (with silicon-specific mechanism)
546 * - go through A_WAIT_VRISE
547 * - ... to A_WAIT_BCON.
548 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
551 musb->ep0_stage = MUSB_EP0_START;
552 musb->xceiv->state = OTG_STATE_A_IDLE;
554 musb_platform_set_vbus(musb, 1);
556 handled = IRQ_HANDLED;
559 if (int_usb & MUSB_INTR_VBUSERROR) {
562 /* During connection as an A-Device, we may see a short
563 * current spikes causing voltage drop, because of cable
564 * and peripheral capacitance combined with vbus draw.
565 * (So: less common with truly self-powered devices, where
566 * vbus doesn't act like a power supply.)
568 * Such spikes are short; usually less than ~500 usec, max
569 * of ~2 msec. That is, they're not sustained overcurrent
570 * errors, though they're reported using VBUSERROR irqs.
572 * Workarounds: (a) hardware: use self powered devices.
573 * (b) software: ignore non-repeated VBUS errors.
575 * REVISIT: do delays from lots of DEBUG_KERNEL checks
576 * make trouble here, keeping VBUS < 4.4V ?
578 switch (musb->xceiv->state) {
579 case OTG_STATE_A_HOST:
580 /* recovery is dicey once we've gotten past the
581 * initial stages of enumeration, but if VBUS
582 * stayed ok at the other end of the link, and
583 * another reset is due (at least for high speed,
584 * to redo the chirp etc), it might work OK...
586 case OTG_STATE_A_WAIT_BCON:
587 case OTG_STATE_A_WAIT_VRISE:
588 if (musb->vbuserr_retry) {
589 void __iomem *mbase = musb->mregs;
591 musb->vbuserr_retry--;
593 devctl |= MUSB_DEVCTL_SESSION;
594 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596 musb->port1_status |=
597 USB_PORT_STAT_OVERCURRENT
598 | (USB_PORT_STAT_C_OVERCURRENT << 16);
605 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
606 otg_state_string(musb->xceiv->state),
609 switch (devctl & MUSB_DEVCTL_VBUS) {
610 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
611 s = "<SessEnd"; break;
612 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
613 s = "<AValid"; break;
614 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
615 s = "<VBusValid"; break;
616 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
620 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623 /* go through A_WAIT_VFALL then start a new session */
625 musb_platform_set_vbus(musb, 0);
626 handled = IRQ_HANDLED;
629 if (int_usb & MUSB_INTR_SUSPEND) {
630 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
631 otg_state_string(musb->xceiv->state), devctl);
632 handled = IRQ_HANDLED;
634 switch (musb->xceiv->state) {
635 case OTG_STATE_A_PERIPHERAL:
636 /* We also come here if the cable is removed, since
637 * this silicon doesn't report ID-no-longer-grounded.
639 * We depend on T(a_wait_bcon) to shut us down, and
640 * hope users don't do anything dicey during this
641 * undesired detour through A_WAIT_BCON.
644 usb_hcd_resume_root_hub(musb_to_hcd(musb));
645 musb_root_disconnect(musb);
646 musb_platform_try_idle(musb, jiffies
647 + msecs_to_jiffies(musb->a_wait_bcon
648 ? : OTG_TIME_A_WAIT_BCON));
651 case OTG_STATE_B_IDLE:
652 if (!musb->is_active)
654 case OTG_STATE_B_PERIPHERAL:
655 musb_g_suspend(musb);
656 musb->is_active = otg->gadget->b_hnp_enable;
657 if (musb->is_active) {
658 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
659 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
660 mod_timer(&musb->otg_timer, jiffies
662 OTG_TIME_B_ASE0_BRST));
665 case OTG_STATE_A_WAIT_BCON:
666 if (musb->a_wait_bcon != 0)
667 musb_platform_try_idle(musb, jiffies
668 + msecs_to_jiffies(musb->a_wait_bcon));
670 case OTG_STATE_A_HOST:
671 musb->xceiv->state = OTG_STATE_A_SUSPEND;
672 musb->is_active = otg->host->b_hnp_enable;
674 case OTG_STATE_B_HOST:
675 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
676 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
679 /* "should not happen" */
685 if (int_usb & MUSB_INTR_CONNECT) {
686 struct usb_hcd *hcd = musb_to_hcd(musb);
688 handled = IRQ_HANDLED;
691 musb->ep0_stage = MUSB_EP0_START;
693 /* flush endpoints when transitioning from Device Mode */
694 if (is_peripheral_active(musb)) {
695 /* REVISIT HNP; just force disconnect */
697 musb->intrtxe = musb->epmask;
698 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
699 musb->intrrxe = musb->epmask & 0xfffe;
700 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
701 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
702 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
703 |USB_PORT_STAT_HIGH_SPEED
704 |USB_PORT_STAT_ENABLE
706 musb->port1_status |= USB_PORT_STAT_CONNECTION
707 |(USB_PORT_STAT_C_CONNECTION << 16);
709 /* high vs full speed is just a guess until after reset */
710 if (devctl & MUSB_DEVCTL_LSDEV)
711 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
713 /* indicate new connection to OTG machine */
714 switch (musb->xceiv->state) {
715 case OTG_STATE_B_PERIPHERAL:
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
718 int_usb &= ~MUSB_INTR_SUSPEND;
721 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
723 case OTG_STATE_B_WAIT_ACON:
724 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
726 musb->xceiv->state = OTG_STATE_B_HOST;
727 hcd->self.is_b_host = 1;
728 musb->ignore_disconnect = 0;
729 del_timer(&musb->otg_timer);
732 if ((devctl & MUSB_DEVCTL_VBUS)
733 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
734 musb->xceiv->state = OTG_STATE_A_HOST;
735 hcd->self.is_b_host = 0;
740 /* poke the root hub */
743 usb_hcd_poll_rh_status(hcd);
745 usb_hcd_resume_root_hub(hcd);
747 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
748 otg_state_string(musb->xceiv->state), devctl);
751 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
752 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
753 otg_state_string(musb->xceiv->state),
754 MUSB_MODE(musb), devctl);
755 handled = IRQ_HANDLED;
757 switch (musb->xceiv->state) {
758 case OTG_STATE_A_HOST:
759 case OTG_STATE_A_SUSPEND:
760 usb_hcd_resume_root_hub(musb_to_hcd(musb));
761 musb_root_disconnect(musb);
762 if (musb->a_wait_bcon != 0)
763 musb_platform_try_idle(musb, jiffies
764 + msecs_to_jiffies(musb->a_wait_bcon));
766 case OTG_STATE_B_HOST:
767 /* REVISIT this behaves for "real disconnect"
768 * cases; make sure the other transitions from
769 * from B_HOST act right too. The B_HOST code
770 * in hnp_stop() is currently not used...
772 musb_root_disconnect(musb);
773 musb_to_hcd(musb)->self.is_b_host = 0;
774 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
776 musb_g_disconnect(musb);
778 case OTG_STATE_A_PERIPHERAL:
780 musb_root_disconnect(musb);
782 case OTG_STATE_B_WAIT_ACON:
784 case OTG_STATE_B_PERIPHERAL:
785 case OTG_STATE_B_IDLE:
786 musb_g_disconnect(musb);
789 WARNING("unhandled DISCONNECT transition (%s)\n",
790 otg_state_string(musb->xceiv->state));
795 /* mentor saves a bit: bus reset and babble share the same irq.
796 * only host sees babble; only peripheral sees bus reset.
798 if (int_usb & MUSB_INTR_RESET) {
799 handled = IRQ_HANDLED;
800 if ((devctl & MUSB_DEVCTL_HM) != 0) {
802 * Looks like non-HS BABBLE can be ignored, but
803 * HS BABBLE is an error condition. For HS the solution
804 * is to avoid babble in the first place and fix what
805 * caused BABBLE. When HS BABBLE happens we can only
808 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
809 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
811 ERR("Stopping host session -- babble\n");
812 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
815 dev_dbg(musb->controller, "BUS RESET as %s\n",
816 otg_state_string(musb->xceiv->state));
817 switch (musb->xceiv->state) {
818 case OTG_STATE_A_SUSPEND:
819 /* We need to ignore disconnect on suspend
820 * otherwise tusb 2.0 won't reconnect after a
821 * power cycle, which breaks otg compliance.
823 musb->ignore_disconnect = 1;
826 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
827 /* never use invalid T(a_wait_bcon) */
828 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
829 otg_state_string(musb->xceiv->state),
831 mod_timer(&musb->otg_timer, jiffies
832 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
834 case OTG_STATE_A_PERIPHERAL:
835 musb->ignore_disconnect = 0;
836 del_timer(&musb->otg_timer);
839 case OTG_STATE_B_WAIT_ACON:
840 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
841 otg_state_string(musb->xceiv->state));
842 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
845 case OTG_STATE_B_IDLE:
846 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
848 case OTG_STATE_B_PERIPHERAL:
852 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
853 otg_state_string(musb->xceiv->state));
859 /* REVISIT ... this would be for multiplexing periodic endpoints, or
860 * supporting transfer phasing to prevent exceeding ISO bandwidth
861 * limits of a given frame or microframe.
863 * It's not needed for peripheral side, which dedicates endpoints;
864 * though it _might_ use SOF irqs for other purposes.
866 * And it's not currently needed for host side, which also dedicates
867 * endpoints, relies on TX/RX interval registers, and isn't claimed
868 * to support ISO transfers yet.
870 if (int_usb & MUSB_INTR_SOF) {
871 void __iomem *mbase = musb->mregs;
872 struct musb_hw_ep *ep;
876 dev_dbg(musb->controller, "START_OF_FRAME\n");
877 handled = IRQ_HANDLED;
879 /* start any periodic Tx transfers waiting for current frame */
880 frame = musb_readw(mbase, MUSB_FRAME);
881 ep = musb->endpoints;
882 for (epnum = 1; (epnum < musb->nr_endpoints)
883 && (musb->epmask >= (1 << epnum));
886 * FIXME handle framecounter wraps (12 bits)
887 * eliminate duplicated StartUrb logic
889 if (ep->dwWaitFrame >= frame) {
891 pr_debug("SOF --> periodic TX%s on %d\n",
892 ep->tx_channel ? " DMA" : "",
895 musb_h_tx_start(musb, epnum);
897 cppi_hostdma_start(musb, epnum);
899 } /* end of for loop */
903 schedule_work(&musb->irq_work);
908 /*-------------------------------------------------------------------------*/
911 * Program the HDRC to start (enable interrupts, dma, etc.).
913 void musb_start(struct musb *musb)
915 void __iomem *regs = musb->mregs;
916 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
918 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
920 /* Set INT enable registers, enable interrupts */
921 musb->intrtxe = musb->epmask;
922 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
923 musb->intrrxe = musb->epmask & 0xfffe;
924 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
925 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
927 musb_writeb(regs, MUSB_TESTMODE, 0);
929 /* put into basic highspeed mode and start session */
930 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
932 /* ENSUSPEND wedges tusb */
933 /* | MUSB_POWER_ENSUSPEND */
937 devctl = musb_readb(regs, MUSB_DEVCTL);
938 devctl &= ~MUSB_DEVCTL_SESSION;
940 /* session started after:
941 * (a) ID-grounded irq, host mode;
942 * (b) vbus present/connect IRQ, peripheral mode;
943 * (c) peripheral initiates, using SRP
945 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
948 devctl |= MUSB_DEVCTL_SESSION;
950 musb_platform_enable(musb);
951 musb_writeb(regs, MUSB_DEVCTL, devctl);
955 static void musb_generic_disable(struct musb *musb)
957 void __iomem *mbase = musb->mregs;
960 /* disable interrupts */
961 musb_writeb(mbase, MUSB_INTRUSBE, 0);
963 musb_writew(mbase, MUSB_INTRTXE, 0);
965 musb_writew(mbase, MUSB_INTRRXE, 0);
968 musb_writeb(mbase, MUSB_DEVCTL, 0);
970 /* flush pending interrupts */
971 temp = musb_readb(mbase, MUSB_INTRUSB);
972 temp = musb_readw(mbase, MUSB_INTRTX);
973 temp = musb_readw(mbase, MUSB_INTRRX);
978 * Make the HDRC stop (disable interrupts, etc.);
979 * reversible by musb_start
980 * called on gadget driver unregister
981 * with controller locked, irqs blocked
982 * acts as a NOP unless some role activated the hardware
984 void musb_stop(struct musb *musb)
986 /* stop IRQs, timers, ... */
987 musb_platform_disable(musb);
988 musb_generic_disable(musb);
989 dev_dbg(musb->controller, "HDRC disabled\n");
992 * - mark host and/or peripheral drivers unusable/inactive
993 * - disable DMA (and enable it in HdrcStart)
994 * - make sure we can musb_start() after musb_stop(); with
995 * OTG mode, gadget driver module rmmod/modprobe cycles that
998 musb_platform_try_idle(musb, 0);
1001 static void musb_shutdown(struct platform_device *pdev)
1003 struct musb *musb = dev_to_musb(&pdev->dev);
1004 unsigned long flags;
1006 pm_runtime_get_sync(musb->controller);
1008 musb_gadget_cleanup(musb);
1010 spin_lock_irqsave(&musb->lock, flags);
1011 musb_platform_disable(musb);
1012 musb_generic_disable(musb);
1013 spin_unlock_irqrestore(&musb->lock, flags);
1015 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1016 musb_platform_exit(musb);
1018 pm_runtime_put(musb->controller);
1019 /* FIXME power down */
1023 /*-------------------------------------------------------------------------*/
1026 * The silicon either has hard-wired endpoint configurations, or else
1027 * "dynamic fifo" sizing. The driver has support for both, though at this
1028 * writing only the dynamic sizing is very well tested. Since we switched
1029 * away from compile-time hardware parameters, we can no longer rely on
1030 * dead code elimination to leave only the relevant one in the object file.
1032 * We don't currently use dynamic fifo setup capability to do anything
1033 * more than selecting one of a bunch of predefined configurations.
1035 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1036 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1037 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1038 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1039 || defined(CONFIG_USB_MUSB_AM35X) \
1040 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1041 || defined(CONFIG_USB_MUSB_DSPS) \
1042 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1043 static ushort fifo_mode = 4;
1044 #elif defined(CONFIG_USB_MUSB_UX500) \
1045 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1046 static ushort fifo_mode = 5;
1048 static ushort fifo_mode = 2;
1051 /* "modprobe ... fifo_mode=1" etc */
1052 module_param(fifo_mode, ushort, 0);
1053 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1056 * tables defining fifo_mode values. define more if you like.
1057 * for host side, make sure both halves of ep1 are set up.
1060 /* mode 0 - fits in 2KB */
1061 static struct musb_fifo_cfg mode_0_cfg[] = {
1062 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1063 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1064 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1065 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1066 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1069 /* mode 1 - fits in 4KB */
1070 static struct musb_fifo_cfg mode_1_cfg[] = {
1071 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1072 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1073 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1074 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1075 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1078 /* mode 2 - fits in 4KB */
1079 static struct musb_fifo_cfg mode_2_cfg[] = {
1080 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1085 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1088 /* mode 3 - fits in 4KB */
1089 static struct musb_fifo_cfg mode_3_cfg[] = {
1090 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1091 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1092 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1095 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1098 /* mode 4 - fits in 16KB */
1099 static struct musb_fifo_cfg mode_4_cfg[] = {
1100 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1107 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1108 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1109 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1110 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1111 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1112 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1113 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1114 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1117 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1118 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1119 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1120 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1121 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1122 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1123 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1124 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1125 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1126 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1129 /* mode 5 - fits in 8KB */
1130 static struct musb_fifo_cfg mode_5_cfg[] = {
1131 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1140 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1141 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1142 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1143 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1144 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1145 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1146 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1147 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1148 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1149 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1150 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1151 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1152 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1153 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1154 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1155 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1156 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1157 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1161 * configure a fifo; for non-shared endpoints, this may be called
1162 * once for a tx fifo and once for an rx fifo.
1164 * returns negative errno or offset for next fifo.
1167 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1168 const struct musb_fifo_cfg *cfg, u16 offset)
1170 void __iomem *mbase = musb->mregs;
1172 u16 maxpacket = cfg->maxpacket;
1173 u16 c_off = offset >> 3;
1176 /* expect hw_ep has already been zero-initialized */
1178 size = ffs(max(maxpacket, (u16) 8)) - 1;
1179 maxpacket = 1 << size;
1182 if (cfg->mode == BUF_DOUBLE) {
1183 if ((offset + (maxpacket << 1)) >
1184 (1 << (musb->config->ram_bits + 2)))
1186 c_size |= MUSB_FIFOSZ_DPB;
1188 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1192 /* configure the FIFO */
1193 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1195 /* EP0 reserved endpoint for control, bidirectional;
1196 * EP1 reserved for bulk, two unidirection halves.
1198 if (hw_ep->epnum == 1)
1199 musb->bulk_ep = hw_ep;
1200 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1201 switch (cfg->style) {
1203 musb_write_txfifosz(mbase, c_size);
1204 musb_write_txfifoadd(mbase, c_off);
1205 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1206 hw_ep->max_packet_sz_tx = maxpacket;
1209 musb_write_rxfifosz(mbase, c_size);
1210 musb_write_rxfifoadd(mbase, c_off);
1211 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1212 hw_ep->max_packet_sz_rx = maxpacket;
1215 musb_write_txfifosz(mbase, c_size);
1216 musb_write_txfifoadd(mbase, c_off);
1217 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1218 hw_ep->max_packet_sz_rx = maxpacket;
1220 musb_write_rxfifosz(mbase, c_size);
1221 musb_write_rxfifoadd(mbase, c_off);
1222 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1223 hw_ep->max_packet_sz_tx = maxpacket;
1225 hw_ep->is_shared_fifo = true;
1229 /* NOTE rx and tx endpoint irqs aren't managed separately,
1230 * which happens to be ok
1232 musb->epmask |= (1 << hw_ep->epnum);
1234 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1237 static struct musb_fifo_cfg ep0_cfg = {
1238 .style = FIFO_RXTX, .maxpacket = 64,
1241 static int ep_config_from_table(struct musb *musb)
1243 const struct musb_fifo_cfg *cfg;
1246 struct musb_hw_ep *hw_ep = musb->endpoints;
1248 if (musb->config->fifo_cfg) {
1249 cfg = musb->config->fifo_cfg;
1250 n = musb->config->fifo_cfg_size;
1254 switch (fifo_mode) {
1260 n = ARRAY_SIZE(mode_0_cfg);
1264 n = ARRAY_SIZE(mode_1_cfg);
1268 n = ARRAY_SIZE(mode_2_cfg);
1272 n = ARRAY_SIZE(mode_3_cfg);
1276 n = ARRAY_SIZE(mode_4_cfg);
1280 n = ARRAY_SIZE(mode_5_cfg);
1284 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1285 musb_driver_name, fifo_mode);
1289 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1290 /* assert(offset > 0) */
1292 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1293 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1296 for (i = 0; i < n; i++) {
1297 u8 epn = cfg->hw_ep_num;
1299 if (epn >= musb->config->num_eps) {
1300 pr_debug("%s: invalid ep %d\n",
1301 musb_driver_name, epn);
1304 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1306 pr_debug("%s: mem overrun, ep %d\n",
1307 musb_driver_name, epn);
1311 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1314 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1316 n + 1, musb->config->num_eps * 2 - 1,
1317 offset, (1 << (musb->config->ram_bits + 2)));
1319 if (!musb->bulk_ep) {
1320 pr_debug("%s: missing bulk\n", musb_driver_name);
1329 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1330 * @param musb the controller
1332 static int ep_config_from_hw(struct musb *musb)
1335 struct musb_hw_ep *hw_ep;
1336 void __iomem *mbase = musb->mregs;
1339 dev_dbg(musb->controller, "<== static silicon ep config\n");
1341 /* FIXME pick up ep0 maxpacket size */
1343 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1344 musb_ep_select(mbase, epnum);
1345 hw_ep = musb->endpoints + epnum;
1347 ret = musb_read_fifosize(musb, hw_ep, epnum);
1351 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1353 /* pick an RX/TX endpoint for bulk */
1354 if (hw_ep->max_packet_sz_tx < 512
1355 || hw_ep->max_packet_sz_rx < 512)
1358 /* REVISIT: this algorithm is lazy, we should at least
1359 * try to pick a double buffered endpoint.
1363 musb->bulk_ep = hw_ep;
1366 if (!musb->bulk_ep) {
1367 pr_debug("%s: missing bulk\n", musb_driver_name);
1374 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1376 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1377 * configure endpoints, or take their config from silicon
1379 static int musb_core_init(u16 musb_type, struct musb *musb)
1383 char aInfo[90], aRevision[32], aDate[12];
1384 void __iomem *mbase = musb->mregs;
1388 /* log core options (read using indexed model) */
1389 reg = musb_read_configdata(mbase);
1391 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1392 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1393 strcat(aInfo, ", dyn FIFOs");
1394 musb->dyn_fifo = true;
1396 if (reg & MUSB_CONFIGDATA_MPRXE) {
1397 strcat(aInfo, ", bulk combine");
1398 musb->bulk_combine = true;
1400 if (reg & MUSB_CONFIGDATA_MPTXE) {
1401 strcat(aInfo, ", bulk split");
1402 musb->bulk_split = true;
1404 if (reg & MUSB_CONFIGDATA_HBRXE) {
1405 strcat(aInfo, ", HB-ISO Rx");
1406 musb->hb_iso_rx = true;
1408 if (reg & MUSB_CONFIGDATA_HBTXE) {
1409 strcat(aInfo, ", HB-ISO Tx");
1410 musb->hb_iso_tx = true;
1412 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1413 strcat(aInfo, ", SoftConn");
1415 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1416 musb_driver_name, reg, aInfo);
1419 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1420 musb->is_multipoint = 1;
1423 musb->is_multipoint = 0;
1425 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1427 "%s: kernel must blacklist external hubs\n",
1432 /* log release info */
1433 musb->hwvers = musb_read_hwvers(mbase);
1434 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1435 MUSB_HWVERS_MINOR(musb->hwvers),
1436 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1437 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1438 musb_driver_name, type, aRevision, aDate);
1441 musb_configure_ep0(musb);
1443 /* discover endpoint configuration */
1444 musb->nr_endpoints = 1;
1448 status = ep_config_from_table(musb);
1450 status = ep_config_from_hw(musb);
1455 /* finish init, and print endpoint config */
1456 for (i = 0; i < musb->nr_endpoints; i++) {
1457 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1459 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1460 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1461 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1462 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1463 hw_ep->fifo_sync_va =
1464 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1467 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1469 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1472 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1473 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1474 hw_ep->rx_reinit = 1;
1475 hw_ep->tx_reinit = 1;
1477 if (hw_ep->max_packet_sz_tx) {
1478 dev_dbg(musb->controller,
1479 "%s: hw_ep %d%s, %smax %d\n",
1480 musb_driver_name, i,
1481 hw_ep->is_shared_fifo ? "shared" : "tx",
1482 hw_ep->tx_double_buffered
1483 ? "doublebuffer, " : "",
1484 hw_ep->max_packet_sz_tx);
1486 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1487 dev_dbg(musb->controller,
1488 "%s: hw_ep %d%s, %smax %d\n",
1489 musb_driver_name, i,
1491 hw_ep->rx_double_buffered
1492 ? "doublebuffer, " : "",
1493 hw_ep->max_packet_sz_rx);
1495 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1496 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1502 /*-------------------------------------------------------------------------*/
1505 * handle all the irqs defined by the HDRC core. for now we expect: other
1506 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1507 * will be assigned, and the irq will already have been acked.
1509 * called in irq context with spinlock held, irqs blocked
1511 irqreturn_t musb_interrupt(struct musb *musb)
1513 irqreturn_t retval = IRQ_NONE;
1518 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1520 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1521 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1522 musb->int_usb, musb->int_tx, musb->int_rx);
1524 /* the core can interrupt us for multiple reasons; docs have
1525 * a generic interrupt flowchart to follow
1528 retval |= musb_stage0_irq(musb, musb->int_usb,
1531 /* "stage 1" is handling endpoint irqs */
1533 /* handle endpoint 0 first */
1534 if (musb->int_tx & 1) {
1535 if (devctl & MUSB_DEVCTL_HM)
1536 retval |= musb_h_ep0_irq(musb);
1538 retval |= musb_g_ep0_irq(musb);
1541 /* RX on endpoints 1-15 */
1542 reg = musb->int_rx >> 1;
1546 /* musb_ep_select(musb->mregs, ep_num); */
1547 /* REVISIT just retval = ep->rx_irq(...) */
1548 retval = IRQ_HANDLED;
1549 if (devctl & MUSB_DEVCTL_HM)
1550 musb_host_rx(musb, ep_num);
1552 musb_g_rx(musb, ep_num);
1559 /* TX on endpoints 1-15 */
1560 reg = musb->int_tx >> 1;
1564 /* musb_ep_select(musb->mregs, ep_num); */
1565 /* REVISIT just retval |= ep->tx_irq(...) */
1566 retval = IRQ_HANDLED;
1567 if (devctl & MUSB_DEVCTL_HM)
1568 musb_host_tx(musb, ep_num);
1570 musb_g_tx(musb, ep_num);
1578 EXPORT_SYMBOL_GPL(musb_interrupt);
1580 #ifndef CONFIG_MUSB_PIO_ONLY
1581 static bool use_dma = 1;
1583 /* "modprobe ... use_dma=0" etc */
1584 module_param(use_dma, bool, 0);
1585 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1587 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1589 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1591 /* called with controller lock already held */
1594 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1595 if (!is_cppi_enabled()) {
1597 if (devctl & MUSB_DEVCTL_HM)
1598 musb_h_ep0_irq(musb);
1600 musb_g_ep0_irq(musb);
1604 /* endpoints 1..15 */
1606 if (devctl & MUSB_DEVCTL_HM)
1607 musb_host_tx(musb, epnum);
1609 musb_g_tx(musb, epnum);
1612 if (devctl & MUSB_DEVCTL_HM)
1613 musb_host_rx(musb, epnum);
1615 musb_g_rx(musb, epnum);
1619 EXPORT_SYMBOL_GPL(musb_dma_completion);
1625 /*-------------------------------------------------------------------------*/
1630 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1632 struct musb *musb = dev_to_musb(dev);
1633 unsigned long flags;
1636 spin_lock_irqsave(&musb->lock, flags);
1637 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1638 spin_unlock_irqrestore(&musb->lock, flags);
1644 musb_mode_store(struct device *dev, struct device_attribute *attr,
1645 const char *buf, size_t n)
1647 struct musb *musb = dev_to_musb(dev);
1648 unsigned long flags;
1651 spin_lock_irqsave(&musb->lock, flags);
1652 if (sysfs_streq(buf, "host"))
1653 status = musb_platform_set_mode(musb, MUSB_HOST);
1654 else if (sysfs_streq(buf, "peripheral"))
1655 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1656 else if (sysfs_streq(buf, "otg"))
1657 status = musb_platform_set_mode(musb, MUSB_OTG);
1660 spin_unlock_irqrestore(&musb->lock, flags);
1662 return (status == 0) ? n : status;
1664 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1667 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1668 const char *buf, size_t n)
1670 struct musb *musb = dev_to_musb(dev);
1671 unsigned long flags;
1674 if (sscanf(buf, "%lu", &val) < 1) {
1675 dev_err(dev, "Invalid VBUS timeout ms value\n");
1679 spin_lock_irqsave(&musb->lock, flags);
1680 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1681 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1682 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1683 musb->is_active = 0;
1684 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1685 spin_unlock_irqrestore(&musb->lock, flags);
1691 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1698 spin_lock_irqsave(&musb->lock, flags);
1699 val = musb->a_wait_bcon;
1700 /* FIXME get_vbus_status() is normally #defined as false...
1701 * and is effectively TUSB-specific.
1703 vbus = musb_platform_get_vbus_status(musb);
1704 spin_unlock_irqrestore(&musb->lock, flags);
1706 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1707 vbus ? "on" : "off", val);
1709 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1711 /* Gadget drivers can't know that a host is connected so they might want
1712 * to start SRP, but users can. This allows userspace to trigger SRP.
1715 musb_srp_store(struct device *dev, struct device_attribute *attr,
1716 const char *buf, size_t n)
1718 struct musb *musb = dev_to_musb(dev);
1721 if (sscanf(buf, "%hu", &srp) != 1
1723 dev_err(dev, "SRP: Value must be 1\n");
1728 musb_g_wakeup(musb);
1732 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1734 static struct attribute *musb_attributes[] = {
1735 &dev_attr_mode.attr,
1736 &dev_attr_vbus.attr,
1741 static const struct attribute_group musb_attr_group = {
1742 .attrs = musb_attributes,
1747 /* Only used to provide driver mode change events */
1748 static void musb_irq_work(struct work_struct *data)
1750 struct musb *musb = container_of(data, struct musb, irq_work);
1752 if (musb->xceiv->state != musb->xceiv_old_state) {
1753 musb->xceiv_old_state = musb->xceiv->state;
1754 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1758 /* --------------------------------------------------------------------------
1762 static struct musb *allocate_instance(struct device *dev,
1763 struct musb_hdrc_config *config, void __iomem *mbase)
1766 struct musb_hw_ep *ep;
1768 struct usb_hcd *hcd;
1770 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1773 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1775 musb = hcd_to_musb(hcd);
1776 INIT_LIST_HEAD(&musb->control);
1777 INIT_LIST_HEAD(&musb->in_bulk);
1778 INIT_LIST_HEAD(&musb->out_bulk);
1780 hcd->uses_new_polling = 1;
1783 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1784 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1785 dev_set_drvdata(dev, musb);
1786 musb->mregs = mbase;
1787 musb->ctrl_base = mbase;
1788 musb->nIrq = -ENODEV;
1789 musb->config = config;
1790 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1791 for (epnum = 0, ep = musb->endpoints;
1792 epnum < musb->config->num_eps;
1798 musb->controller = dev;
1803 static void musb_free(struct musb *musb)
1805 /* this has multiple entry modes. it handles fault cleanup after
1806 * probe(), where things may be partially set up, as well as rmmod
1807 * cleanup after everything's been de-activated.
1811 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1814 if (musb->nIrq >= 0) {
1816 disable_irq_wake(musb->nIrq);
1817 free_irq(musb->nIrq, musb);
1819 if (is_dma_capable() && musb->dma_controller) {
1820 struct dma_controller *c = musb->dma_controller;
1823 dma_controller_destroy(c);
1826 usb_put_hcd(musb_to_hcd(musb));
1830 * Perform generic per-controller initialization.
1832 * @dev: the controller (already clocked, etc)
1834 * @ctrl: virtual address of controller registers,
1835 * not yet corrected for platform-specific offsets
1838 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1842 struct musb_hdrc_platform_data *plat = dev->platform_data;
1843 struct usb_hcd *hcd;
1845 /* The driver might handle more features than the board; OK.
1846 * Fail when the board needs a feature that's not enabled.
1849 dev_dbg(dev, "no platform_data?\n");
1855 musb = allocate_instance(dev, plat->config, ctrl);
1861 pm_runtime_use_autosuspend(musb->controller);
1862 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1863 pm_runtime_enable(musb->controller);
1865 spin_lock_init(&musb->lock);
1866 musb->board_set_power = plat->set_power;
1867 musb->min_power = plat->min_power;
1868 musb->ops = plat->platform_ops;
1870 /* The musb_platform_init() call:
1871 * - adjusts musb->mregs
1872 * - sets the musb->isr
1873 * - may initialize an integrated tranceiver
1874 * - initializes musb->xceiv, usually by otg_get_phy()
1875 * - stops powering VBUS
1877 * There are various transceiver configurations. Blackfin,
1878 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1879 * external/discrete ones in various flavors (twl4030 family,
1880 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1882 status = musb_platform_init(musb);
1891 if (!musb->xceiv->io_ops) {
1892 musb->xceiv->io_dev = musb->controller;
1893 musb->xceiv->io_priv = musb->mregs;
1894 musb->xceiv->io_ops = &musb_ulpi_access;
1897 pm_runtime_get_sync(musb->controller);
1899 #ifndef CONFIG_MUSB_PIO_ONLY
1900 if (use_dma && dev->dma_mask) {
1901 struct dma_controller *c;
1903 c = dma_controller_create(musb, musb->mregs);
1904 musb->dma_controller = c;
1909 /* ideally this would be abstracted in platform setup */
1910 if (!is_dma_capable() || !musb->dma_controller)
1911 dev->dma_mask = NULL;
1913 /* be sure interrupts are disabled before connecting ISR */
1914 musb_platform_disable(musb);
1915 musb_generic_disable(musb);
1917 /* setup musb parts of the core (especially endpoints) */
1918 status = musb_core_init(plat->config->multipoint
1919 ? MUSB_CONTROLLER_MHDRC
1920 : MUSB_CONTROLLER_HDRC, musb);
1924 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1926 /* Init IRQ workqueue before request_irq */
1927 INIT_WORK(&musb->irq_work, musb_irq_work);
1929 /* attach to the IRQ */
1930 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1931 dev_err(dev, "request_irq %d failed!\n", nIrq);
1936 /* FIXME this handles wakeup irqs wrong */
1937 if (enable_irq_wake(nIrq) == 0) {
1939 device_init_wakeup(dev, 1);
1944 /* host side needs more setup */
1945 hcd = musb_to_hcd(musb);
1946 otg_set_host(musb->xceiv->otg, &hcd->self);
1947 hcd->self.otg_port = 1;
1948 musb->xceiv->otg->host = &hcd->self;
1949 hcd->power_budget = 2 * (plat->power ? : 250);
1951 /* program PHY to use external vBus if required */
1952 if (plat->extvbus) {
1953 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1954 busctl |= MUSB_ULPI_USE_EXTVBUS;
1955 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1958 MUSB_DEV_MODE(musb);
1959 musb->xceiv->otg->default_a = 0;
1960 musb->xceiv->state = OTG_STATE_B_IDLE;
1962 status = musb_gadget_setup(musb);
1967 status = musb_init_debugfs(musb);
1972 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
1977 pm_runtime_put(musb->controller);
1982 musb_exit_debugfs(musb);
1985 musb_gadget_cleanup(musb);
1988 pm_runtime_put_sync(musb->controller);
1992 device_init_wakeup(dev, 0);
1993 musb_platform_exit(musb);
1996 dev_err(musb->controller,
1997 "musb_init_controller failed with status %d\n", status);
2007 /*-------------------------------------------------------------------------*/
2009 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2010 * bridge to a platform device; this driver then suffices.
2012 static int musb_probe(struct platform_device *pdev)
2014 struct device *dev = &pdev->dev;
2015 int irq = platform_get_irq_byname(pdev, "mc");
2017 struct resource *iomem;
2020 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021 if (!iomem || irq <= 0)
2024 base = ioremap(iomem->start, resource_size(iomem));
2026 dev_err(dev, "ioremap failed\n");
2030 status = musb_init_controller(dev, irq, base);
2037 static int musb_remove(struct platform_device *pdev)
2039 struct device *dev = &pdev->dev;
2040 struct musb *musb = dev_to_musb(dev);
2041 void __iomem *ctrl_base = musb->ctrl_base;
2043 /* this gets called on rmmod.
2044 * - Host mode: host may still be active
2045 * - Peripheral mode: peripheral is deactivated (or never-activated)
2046 * - OTG mode: both roles are deactivated (or never-activated)
2048 musb_exit_debugfs(musb);
2049 musb_shutdown(pdev);
2053 device_init_wakeup(dev, 0);
2054 #ifndef CONFIG_MUSB_PIO_ONLY
2055 dma_set_mask(dev, *dev->parent->dma_mask);
2062 static void musb_save_context(struct musb *musb)
2065 void __iomem *musb_base = musb->mregs;
2068 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2069 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2070 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2071 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2072 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2073 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2074 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2076 for (i = 0; i < musb->config->num_eps; ++i) {
2077 struct musb_hw_ep *hw_ep;
2079 hw_ep = &musb->endpoints[i];
2087 musb_writeb(musb_base, MUSB_INDEX, i);
2088 musb->context.index_regs[i].txmaxp =
2089 musb_readw(epio, MUSB_TXMAXP);
2090 musb->context.index_regs[i].txcsr =
2091 musb_readw(epio, MUSB_TXCSR);
2092 musb->context.index_regs[i].rxmaxp =
2093 musb_readw(epio, MUSB_RXMAXP);
2094 musb->context.index_regs[i].rxcsr =
2095 musb_readw(epio, MUSB_RXCSR);
2097 if (musb->dyn_fifo) {
2098 musb->context.index_regs[i].txfifoadd =
2099 musb_read_txfifoadd(musb_base);
2100 musb->context.index_regs[i].rxfifoadd =
2101 musb_read_rxfifoadd(musb_base);
2102 musb->context.index_regs[i].txfifosz =
2103 musb_read_txfifosz(musb_base);
2104 musb->context.index_regs[i].rxfifosz =
2105 musb_read_rxfifosz(musb_base);
2108 musb->context.index_regs[i].txtype =
2109 musb_readb(epio, MUSB_TXTYPE);
2110 musb->context.index_regs[i].txinterval =
2111 musb_readb(epio, MUSB_TXINTERVAL);
2112 musb->context.index_regs[i].rxtype =
2113 musb_readb(epio, MUSB_RXTYPE);
2114 musb->context.index_regs[i].rxinterval =
2115 musb_readb(epio, MUSB_RXINTERVAL);
2117 musb->context.index_regs[i].txfunaddr =
2118 musb_read_txfunaddr(musb_base, i);
2119 musb->context.index_regs[i].txhubaddr =
2120 musb_read_txhubaddr(musb_base, i);
2121 musb->context.index_regs[i].txhubport =
2122 musb_read_txhubport(musb_base, i);
2124 musb->context.index_regs[i].rxfunaddr =
2125 musb_read_rxfunaddr(musb_base, i);
2126 musb->context.index_regs[i].rxhubaddr =
2127 musb_read_rxhubaddr(musb_base, i);
2128 musb->context.index_regs[i].rxhubport =
2129 musb_read_rxhubport(musb_base, i);
2133 static void musb_restore_context(struct musb *musb)
2136 void __iomem *musb_base = musb->mregs;
2137 void __iomem *ep_target_regs;
2140 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2141 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2142 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2143 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2144 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2145 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2146 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2147 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2149 for (i = 0; i < musb->config->num_eps; ++i) {
2150 struct musb_hw_ep *hw_ep;
2152 hw_ep = &musb->endpoints[i];
2160 musb_writeb(musb_base, MUSB_INDEX, i);
2161 musb_writew(epio, MUSB_TXMAXP,
2162 musb->context.index_regs[i].txmaxp);
2163 musb_writew(epio, MUSB_TXCSR,
2164 musb->context.index_regs[i].txcsr);
2165 musb_writew(epio, MUSB_RXMAXP,
2166 musb->context.index_regs[i].rxmaxp);
2167 musb_writew(epio, MUSB_RXCSR,
2168 musb->context.index_regs[i].rxcsr);
2170 if (musb->dyn_fifo) {
2171 musb_write_txfifosz(musb_base,
2172 musb->context.index_regs[i].txfifosz);
2173 musb_write_rxfifosz(musb_base,
2174 musb->context.index_regs[i].rxfifosz);
2175 musb_write_txfifoadd(musb_base,
2176 musb->context.index_regs[i].txfifoadd);
2177 musb_write_rxfifoadd(musb_base,
2178 musb->context.index_regs[i].rxfifoadd);
2181 musb_writeb(epio, MUSB_TXTYPE,
2182 musb->context.index_regs[i].txtype);
2183 musb_writeb(epio, MUSB_TXINTERVAL,
2184 musb->context.index_regs[i].txinterval);
2185 musb_writeb(epio, MUSB_RXTYPE,
2186 musb->context.index_regs[i].rxtype);
2187 musb_writeb(epio, MUSB_RXINTERVAL,
2189 musb->context.index_regs[i].rxinterval);
2190 musb_write_txfunaddr(musb_base, i,
2191 musb->context.index_regs[i].txfunaddr);
2192 musb_write_txhubaddr(musb_base, i,
2193 musb->context.index_regs[i].txhubaddr);
2194 musb_write_txhubport(musb_base, i,
2195 musb->context.index_regs[i].txhubport);
2198 musb_read_target_reg_base(i, musb_base);
2200 musb_write_rxfunaddr(ep_target_regs,
2201 musb->context.index_regs[i].rxfunaddr);
2202 musb_write_rxhubaddr(ep_target_regs,
2203 musb->context.index_regs[i].rxhubaddr);
2204 musb_write_rxhubport(ep_target_regs,
2205 musb->context.index_regs[i].rxhubport);
2207 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2210 static int musb_suspend(struct device *dev)
2212 struct musb *musb = dev_to_musb(dev);
2213 unsigned long flags;
2215 spin_lock_irqsave(&musb->lock, flags);
2217 if (is_peripheral_active(musb)) {
2218 /* FIXME force disconnect unless we know USB will wake
2219 * the system up quickly enough to respond ...
2221 } else if (is_host_active(musb)) {
2222 /* we know all the children are suspended; sometimes
2223 * they will even be wakeup-enabled.
2227 spin_unlock_irqrestore(&musb->lock, flags);
2231 static int musb_resume_noirq(struct device *dev)
2233 /* for static cmos like DaVinci, register values were preserved
2234 * unless for some reason the whole soc powered down or the USB
2235 * module got reset through the PSC (vs just being disabled).
2240 static int musb_runtime_suspend(struct device *dev)
2242 struct musb *musb = dev_to_musb(dev);
2244 musb_save_context(musb);
2249 static int musb_runtime_resume(struct device *dev)
2251 struct musb *musb = dev_to_musb(dev);
2252 static int first = 1;
2255 * When pm_runtime_get_sync called for the first time in driver
2256 * init, some of the structure is still not initialized which is
2257 * used in restore function. But clock needs to be
2258 * enabled before any register access, so
2259 * pm_runtime_get_sync has to be called.
2260 * Also context restore without save does not make
2264 musb_restore_context(musb);
2270 static const struct dev_pm_ops musb_dev_pm_ops = {
2271 .suspend = musb_suspend,
2272 .resume_noirq = musb_resume_noirq,
2273 .runtime_suspend = musb_runtime_suspend,
2274 .runtime_resume = musb_runtime_resume,
2277 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2279 #define MUSB_DEV_PM_OPS NULL
2282 static struct platform_driver musb_driver = {
2284 .name = (char *)musb_driver_name,
2285 .bus = &platform_bus_type,
2286 .owner = THIS_MODULE,
2287 .pm = MUSB_DEV_PM_OPS,
2289 .probe = musb_probe,
2290 .remove = musb_remove,
2291 .shutdown = musb_shutdown,
2294 /*-------------------------------------------------------------------------*/
2296 static int __init musb_init(void)
2301 pr_info("%s: version " MUSB_VERSION ", "
2304 "otg (peripheral+host)",
2306 return platform_driver_register(&musb_driver);
2308 module_init(musb_init);
2310 static void __exit musb_cleanup(void)
2312 platform_driver_unregister(&musb_driver);
2314 module_exit(musb_cleanup);