2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
136 void __iomem *addr = otg->io_priv;
141 /* Make sure the transceiver is not in low power mode */
142 power = musb_readb(addr, MUSB_POWER);
143 power &= ~MUSB_POWER_SUSPENDM;
144 musb_writeb(addr, MUSB_POWER, power);
146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
155 & MUSB_ULPI_REG_CMPLT)) {
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
165 return musb_readb(addr, MUSB_ULPI_REG_DATA);
168 static int musb_ulpi_write(struct otg_transceiver *otg,
169 u32 offset, u32 data)
171 void __iomem *addr = otg->io_priv;
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
186 & MUSB_ULPI_REG_CMPLT)) {
192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
193 r &= ~MUSB_ULPI_REG_CMPLT;
194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
199 #define musb_ulpi_read NULL
200 #define musb_ulpi_write NULL
203 static struct otg_io_access_ops musb_ulpi_access = {
204 .read = musb_ulpi_read,
205 .write = musb_ulpi_write,
208 /*-------------------------------------------------------------------------*/
210 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
213 * Load an endpoint's FIFO
215 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
217 struct musb *musb = hw_ep->musb;
218 void __iomem *fifo = hw_ep->fifo;
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
223 'T', hw_ep->epnum, fifo, len, src);
225 /* we can't assume unaligned reads work */
226 if (likely((0x01 & (unsigned long) src) == 0)) {
229 /* best case is 32bit-aligned source address */
230 if ((0x02 & (unsigned long) src) == 0) {
232 writesl(fifo, src + index, len >> 2);
233 index += len & ~0x03;
236 musb_writew(fifo, 0, *(u16 *)&src[index]);
241 writesw(fifo, src + index, len >> 1);
242 index += len & ~0x01;
246 musb_writeb(fifo, 0, src[index]);
249 writesb(fifo, src, len);
253 #if !defined(CONFIG_USB_MUSB_AM35X)
255 * Unload an endpoint's FIFO
257 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
259 struct musb *musb = hw_ep->musb;
260 void __iomem *fifo = hw_ep->fifo;
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
263 'R', hw_ep->epnum, fifo, len, dst);
265 /* we can't assume unaligned writes work */
266 if (likely((0x01 & (unsigned long) dst) == 0)) {
269 /* best case is 32bit-aligned destination address */
270 if ((0x02 & (unsigned long) dst) == 0) {
272 readsl(fifo, dst, len >> 2);
276 *(u16 *)&dst[index] = musb_readw(fifo, 0);
281 readsw(fifo, dst, len >> 1);
286 dst[index] = musb_readb(fifo, 0);
289 readsb(fifo, dst, len);
294 #endif /* normal PIO */
297 /*-------------------------------------------------------------------------*/
299 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
300 static const u8 musb_test_packet[53] = {
301 /* implicit SYNC then DATA0 to start */
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
309 /* JJJJJJJKKKKKKK x8 */
310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
313 /* JKKKKKKK x10, JK */
314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
316 /* implicit CRC16 then EOP to end */
319 void musb_load_testpacket(struct musb *musb)
321 void __iomem *regs = musb->endpoints[0].regs;
323 musb_ep_select(musb->mregs, 0);
324 musb_write_fifo(musb->control_ep,
325 sizeof(musb_test_packet), musb_test_packet);
326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
329 /*-------------------------------------------------------------------------*/
331 #ifdef CONFIG_USB_MUSB_OTG
334 * Handles OTG hnp timeouts, such as b_ase0_brst
336 void musb_otg_timer_func(unsigned long data)
338 struct musb *musb = (struct musb *)data;
341 spin_lock_irqsave(&musb->lock, flags);
342 switch (musb->xceiv->state) {
343 case OTG_STATE_B_WAIT_ACON:
344 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
345 musb_g_disconnect(musb);
346 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
349 case OTG_STATE_A_SUSPEND:
350 case OTG_STATE_A_WAIT_BCON:
351 dev_dbg(musb->controller, "HNP: %s timeout\n",
352 otg_state_string(musb->xceiv->state));
353 musb_platform_set_vbus(musb, 0);
354 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
357 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
358 otg_state_string(musb->xceiv->state));
360 musb->ignore_disconnect = 0;
361 spin_unlock_irqrestore(&musb->lock, flags);
365 * Stops the HNP transition. Caller must take care of locking.
367 void musb_hnp_stop(struct musb *musb)
369 struct usb_hcd *hcd = musb_to_hcd(musb);
370 void __iomem *mbase = musb->mregs;
373 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
375 switch (musb->xceiv->state) {
376 case OTG_STATE_A_PERIPHERAL:
377 musb_g_disconnect(musb);
378 dev_dbg(musb->controller, "HNP: back to %s\n",
379 otg_state_string(musb->xceiv->state));
381 case OTG_STATE_B_HOST:
382 dev_dbg(musb->controller, "HNP: Disabling HR\n");
383 hcd->self.is_b_host = 0;
384 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
386 reg = musb_readb(mbase, MUSB_POWER);
387 reg |= MUSB_POWER_SUSPENDM;
388 musb_writeb(mbase, MUSB_POWER, reg);
389 /* REVISIT: Start SESSION_REQUEST here? */
392 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
393 otg_state_string(musb->xceiv->state));
397 * When returning to A state after HNP, avoid hub_port_rebounce(),
398 * which cause occasional OPT A "Did not receive reset after connect"
401 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
407 * Interrupt Service Routine to record USB "global" interrupts.
408 * Since these do not happen often and signify things of
409 * paramount importance, it seems OK to check them individually;
410 * the order of the tests is specified in the manual
412 * @param musb instance pointer
413 * @param int_usb register contents
418 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
421 irqreturn_t handled = IRQ_NONE;
423 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
426 /* in host mode, the peripheral may issue remote wakeup.
427 * in peripheral mode, the host may resume the link.
428 * spurious RESUME irqs happen too, paired with SUSPEND.
430 if (int_usb & MUSB_INTR_RESUME) {
431 handled = IRQ_HANDLED;
432 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
434 if (devctl & MUSB_DEVCTL_HM) {
435 #ifdef CONFIG_USB_MUSB_HDRC_HCD
436 void __iomem *mbase = musb->mregs;
438 switch (musb->xceiv->state) {
439 case OTG_STATE_A_SUSPEND:
440 /* remote wakeup? later, GetPortStatus
441 * will stop RESUME signaling
444 if (power & MUSB_POWER_SUSPENDM) {
446 musb->int_usb &= ~MUSB_INTR_SUSPEND;
447 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
451 power &= ~MUSB_POWER_SUSPENDM;
452 musb_writeb(mbase, MUSB_POWER,
453 power | MUSB_POWER_RESUME);
455 musb->port1_status |=
456 (USB_PORT_STAT_C_SUSPEND << 16)
457 | MUSB_PORT_STAT_RESUME;
458 musb->rh_timer = jiffies
459 + msecs_to_jiffies(20);
461 musb->xceiv->state = OTG_STATE_A_HOST;
463 usb_hcd_resume_root_hub(musb_to_hcd(musb));
465 case OTG_STATE_B_WAIT_ACON:
466 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
471 WARNING("bogus %s RESUME (%s)\n",
473 otg_state_string(musb->xceiv->state));
477 switch (musb->xceiv->state) {
478 #ifdef CONFIG_USB_MUSB_HDRC_HCD
479 case OTG_STATE_A_SUSPEND:
480 /* possibly DISCONNECT is upcoming */
481 musb->xceiv->state = OTG_STATE_A_HOST;
482 usb_hcd_resume_root_hub(musb_to_hcd(musb));
485 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
486 case OTG_STATE_B_WAIT_ACON:
487 case OTG_STATE_B_PERIPHERAL:
488 /* disconnect while suspended? we may
489 * not get a disconnect irq...
491 if ((devctl & MUSB_DEVCTL_VBUS)
492 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
494 musb->int_usb |= MUSB_INTR_DISCONNECT;
495 musb->int_usb &= ~MUSB_INTR_SUSPEND;
500 case OTG_STATE_B_IDLE:
501 musb->int_usb &= ~MUSB_INTR_SUSPEND;
505 WARNING("bogus %s RESUME (%s)\n",
507 otg_state_string(musb->xceiv->state));
512 #ifdef CONFIG_USB_MUSB_HDRC_HCD
513 /* see manual for the order of the tests */
514 if (int_usb & MUSB_INTR_SESSREQ) {
515 void __iomem *mbase = musb->mregs;
517 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
518 && (devctl & MUSB_DEVCTL_BDEVICE)) {
519 dev_dbg(musb->controller, "SessReq while on B state\n");
523 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
524 otg_state_string(musb->xceiv->state));
526 /* IRQ arrives from ID pin sense or (later, if VBUS power
527 * is removed) SRP. responses are time critical:
528 * - turn on VBUS (with silicon-specific mechanism)
529 * - go through A_WAIT_VRISE
530 * - ... to A_WAIT_BCON.
531 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
533 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
534 musb->ep0_stage = MUSB_EP0_START;
535 musb->xceiv->state = OTG_STATE_A_IDLE;
537 musb_platform_set_vbus(musb, 1);
539 handled = IRQ_HANDLED;
542 if (int_usb & MUSB_INTR_VBUSERROR) {
545 /* During connection as an A-Device, we may see a short
546 * current spikes causing voltage drop, because of cable
547 * and peripheral capacitance combined with vbus draw.
548 * (So: less common with truly self-powered devices, where
549 * vbus doesn't act like a power supply.)
551 * Such spikes are short; usually less than ~500 usec, max
552 * of ~2 msec. That is, they're not sustained overcurrent
553 * errors, though they're reported using VBUSERROR irqs.
555 * Workarounds: (a) hardware: use self powered devices.
556 * (b) software: ignore non-repeated VBUS errors.
558 * REVISIT: do delays from lots of DEBUG_KERNEL checks
559 * make trouble here, keeping VBUS < 4.4V ?
561 switch (musb->xceiv->state) {
562 case OTG_STATE_A_HOST:
563 /* recovery is dicey once we've gotten past the
564 * initial stages of enumeration, but if VBUS
565 * stayed ok at the other end of the link, and
566 * another reset is due (at least for high speed,
567 * to redo the chirp etc), it might work OK...
569 case OTG_STATE_A_WAIT_BCON:
570 case OTG_STATE_A_WAIT_VRISE:
571 if (musb->vbuserr_retry) {
572 void __iomem *mbase = musb->mregs;
574 musb->vbuserr_retry--;
576 devctl |= MUSB_DEVCTL_SESSION;
577 musb_writeb(mbase, MUSB_DEVCTL, devctl);
579 musb->port1_status |=
580 USB_PORT_STAT_OVERCURRENT
581 | (USB_PORT_STAT_C_OVERCURRENT << 16);
588 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
589 otg_state_string(musb->xceiv->state),
592 switch (devctl & MUSB_DEVCTL_VBUS) {
593 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
594 s = "<SessEnd"; break;
595 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
596 s = "<AValid"; break;
597 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
598 s = "<VBusValid"; break;
599 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
603 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
606 /* go through A_WAIT_VFALL then start a new session */
608 musb_platform_set_vbus(musb, 0);
609 handled = IRQ_HANDLED;
613 if (int_usb & MUSB_INTR_SUSPEND) {
614 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
615 otg_state_string(musb->xceiv->state), devctl, power);
616 handled = IRQ_HANDLED;
618 switch (musb->xceiv->state) {
619 #ifdef CONFIG_USB_MUSB_OTG
620 case OTG_STATE_A_PERIPHERAL:
621 /* We also come here if the cable is removed, since
622 * this silicon doesn't report ID-no-longer-grounded.
624 * We depend on T(a_wait_bcon) to shut us down, and
625 * hope users don't do anything dicey during this
626 * undesired detour through A_WAIT_BCON.
629 usb_hcd_resume_root_hub(musb_to_hcd(musb));
630 musb_root_disconnect(musb);
631 musb_platform_try_idle(musb, jiffies
632 + msecs_to_jiffies(musb->a_wait_bcon
633 ? : OTG_TIME_A_WAIT_BCON));
637 case OTG_STATE_B_IDLE:
638 if (!musb->is_active)
640 case OTG_STATE_B_PERIPHERAL:
641 musb_g_suspend(musb);
642 musb->is_active = is_otg_enabled(musb)
643 && musb->xceiv->gadget->b_hnp_enable;
644 if (musb->is_active) {
645 #ifdef CONFIG_USB_MUSB_OTG
646 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
647 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
648 mod_timer(&musb->otg_timer, jiffies
650 OTG_TIME_B_ASE0_BRST));
654 case OTG_STATE_A_WAIT_BCON:
655 if (musb->a_wait_bcon != 0)
656 musb_platform_try_idle(musb, jiffies
657 + msecs_to_jiffies(musb->a_wait_bcon));
659 case OTG_STATE_A_HOST:
660 musb->xceiv->state = OTG_STATE_A_SUSPEND;
661 musb->is_active = is_otg_enabled(musb)
662 && musb->xceiv->host->b_hnp_enable;
664 case OTG_STATE_B_HOST:
665 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
666 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
669 /* "should not happen" */
675 #ifdef CONFIG_USB_MUSB_HDRC_HCD
676 if (int_usb & MUSB_INTR_CONNECT) {
677 struct usb_hcd *hcd = musb_to_hcd(musb);
679 handled = IRQ_HANDLED;
681 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
683 musb->ep0_stage = MUSB_EP0_START;
685 #ifdef CONFIG_USB_MUSB_OTG
686 /* flush endpoints when transitioning from Device Mode */
687 if (is_peripheral_active(musb)) {
688 /* REVISIT HNP; just force disconnect */
690 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
691 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
692 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
694 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
695 |USB_PORT_STAT_HIGH_SPEED
696 |USB_PORT_STAT_ENABLE
698 musb->port1_status |= USB_PORT_STAT_CONNECTION
699 |(USB_PORT_STAT_C_CONNECTION << 16);
701 /* high vs full speed is just a guess until after reset */
702 if (devctl & MUSB_DEVCTL_LSDEV)
703 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
705 /* indicate new connection to OTG machine */
706 switch (musb->xceiv->state) {
707 case OTG_STATE_B_PERIPHERAL:
708 if (int_usb & MUSB_INTR_SUSPEND) {
709 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
710 int_usb &= ~MUSB_INTR_SUSPEND;
713 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
715 case OTG_STATE_B_WAIT_ACON:
716 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
718 musb->xceiv->state = OTG_STATE_B_HOST;
719 hcd->self.is_b_host = 1;
720 musb->ignore_disconnect = 0;
721 del_timer(&musb->otg_timer);
724 if ((devctl & MUSB_DEVCTL_VBUS)
725 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
726 musb->xceiv->state = OTG_STATE_A_HOST;
727 hcd->self.is_b_host = 0;
732 /* poke the root hub */
735 usb_hcd_poll_rh_status(hcd);
737 usb_hcd_resume_root_hub(hcd);
739 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
740 otg_state_string(musb->xceiv->state), devctl);
742 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
744 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
745 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
746 otg_state_string(musb->xceiv->state),
747 MUSB_MODE(musb), devctl);
748 handled = IRQ_HANDLED;
750 switch (musb->xceiv->state) {
751 #ifdef CONFIG_USB_MUSB_HDRC_HCD
752 case OTG_STATE_A_HOST:
753 case OTG_STATE_A_SUSPEND:
754 usb_hcd_resume_root_hub(musb_to_hcd(musb));
755 musb_root_disconnect(musb);
756 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
757 musb_platform_try_idle(musb, jiffies
758 + msecs_to_jiffies(musb->a_wait_bcon));
761 #ifdef CONFIG_USB_MUSB_OTG
762 case OTG_STATE_B_HOST:
763 /* REVISIT this behaves for "real disconnect"
764 * cases; make sure the other transitions from
765 * from B_HOST act right too. The B_HOST code
766 * in hnp_stop() is currently not used...
768 musb_root_disconnect(musb);
769 musb_to_hcd(musb)->self.is_b_host = 0;
770 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
772 musb_g_disconnect(musb);
774 case OTG_STATE_A_PERIPHERAL:
776 musb_root_disconnect(musb);
778 case OTG_STATE_B_WAIT_ACON:
781 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
782 case OTG_STATE_B_PERIPHERAL:
783 case OTG_STATE_B_IDLE:
784 musb_g_disconnect(musb);
788 WARNING("unhandled DISCONNECT transition (%s)\n",
789 otg_state_string(musb->xceiv->state));
794 /* mentor saves a bit: bus reset and babble share the same irq.
795 * only host sees babble; only peripheral sees bus reset.
797 if (int_usb & MUSB_INTR_RESET) {
798 handled = IRQ_HANDLED;
799 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
801 * Looks like non-HS BABBLE can be ignored, but
802 * HS BABBLE is an error condition. For HS the solution
803 * is to avoid babble in the first place and fix what
804 * caused BABBLE. When HS BABBLE happens we can only
807 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
808 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
810 ERR("Stopping host session -- babble\n");
811 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
813 } else if (is_peripheral_capable()) {
814 dev_dbg(musb->controller, "BUS RESET as %s\n",
815 otg_state_string(musb->xceiv->state));
816 switch (musb->xceiv->state) {
817 #ifdef CONFIG_USB_OTG
818 case OTG_STATE_A_SUSPEND:
819 /* We need to ignore disconnect on suspend
820 * otherwise tusb 2.0 won't reconnect after a
821 * power cycle, which breaks otg compliance.
823 musb->ignore_disconnect = 1;
826 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
827 /* never use invalid T(a_wait_bcon) */
828 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
829 otg_state_string(musb->xceiv->state),
831 mod_timer(&musb->otg_timer, jiffies
832 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
834 case OTG_STATE_A_PERIPHERAL:
835 musb->ignore_disconnect = 0;
836 del_timer(&musb->otg_timer);
839 case OTG_STATE_B_WAIT_ACON:
840 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
841 otg_state_string(musb->xceiv->state));
842 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
846 case OTG_STATE_B_IDLE:
847 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
849 case OTG_STATE_B_PERIPHERAL:
853 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
854 otg_state_string(musb->xceiv->state));
860 /* REVISIT ... this would be for multiplexing periodic endpoints, or
861 * supporting transfer phasing to prevent exceeding ISO bandwidth
862 * limits of a given frame or microframe.
864 * It's not needed for peripheral side, which dedicates endpoints;
865 * though it _might_ use SOF irqs for other purposes.
867 * And it's not currently needed for host side, which also dedicates
868 * endpoints, relies on TX/RX interval registers, and isn't claimed
869 * to support ISO transfers yet.
871 if (int_usb & MUSB_INTR_SOF) {
872 void __iomem *mbase = musb->mregs;
873 struct musb_hw_ep *ep;
877 dev_dbg(musb->controller, "START_OF_FRAME\n");
878 handled = IRQ_HANDLED;
880 /* start any periodic Tx transfers waiting for current frame */
881 frame = musb_readw(mbase, MUSB_FRAME);
882 ep = musb->endpoints;
883 for (epnum = 1; (epnum < musb->nr_endpoints)
884 && (musb->epmask >= (1 << epnum));
887 * FIXME handle framecounter wraps (12 bits)
888 * eliminate duplicated StartUrb logic
890 if (ep->dwWaitFrame >= frame) {
892 pr_debug("SOF --> periodic TX%s on %d\n",
893 ep->tx_channel ? " DMA" : "",
896 musb_h_tx_start(musb, epnum);
898 cppi_hostdma_start(musb, epnum);
900 } /* end of for loop */
904 schedule_work(&musb->irq_work);
909 /*-------------------------------------------------------------------------*/
912 * Program the HDRC to start (enable interrupts, dma, etc.).
914 void musb_start(struct musb *musb)
916 void __iomem *regs = musb->mregs;
917 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
919 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
921 /* Set INT enable registers, enable interrupts */
922 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
923 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
924 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
926 musb_writeb(regs, MUSB_TESTMODE, 0);
928 /* put into basic highspeed mode and start session */
929 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
930 | MUSB_POWER_SOFTCONN
932 /* ENSUSPEND wedges tusb */
933 /* | MUSB_POWER_ENSUSPEND */
937 devctl = musb_readb(regs, MUSB_DEVCTL);
938 devctl &= ~MUSB_DEVCTL_SESSION;
940 if (is_otg_enabled(musb)) {
941 /* session started after:
942 * (a) ID-grounded irq, host mode;
943 * (b) vbus present/connect IRQ, peripheral mode;
944 * (c) peripheral initiates, using SRP
946 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
949 devctl |= MUSB_DEVCTL_SESSION;
951 } else if (is_host_enabled(musb)) {
952 /* assume ID pin is hard-wired to ground */
953 devctl |= MUSB_DEVCTL_SESSION;
955 } else /* peripheral is enabled */ {
956 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
959 musb_platform_enable(musb);
960 musb_writeb(regs, MUSB_DEVCTL, devctl);
964 static void musb_generic_disable(struct musb *musb)
966 void __iomem *mbase = musb->mregs;
969 /* disable interrupts */
970 musb_writeb(mbase, MUSB_INTRUSBE, 0);
971 musb_writew(mbase, MUSB_INTRTXE, 0);
972 musb_writew(mbase, MUSB_INTRRXE, 0);
975 musb_writeb(mbase, MUSB_DEVCTL, 0);
977 /* flush pending interrupts */
978 temp = musb_readb(mbase, MUSB_INTRUSB);
979 temp = musb_readw(mbase, MUSB_INTRTX);
980 temp = musb_readw(mbase, MUSB_INTRRX);
985 * Make the HDRC stop (disable interrupts, etc.);
986 * reversible by musb_start
987 * called on gadget driver unregister
988 * with controller locked, irqs blocked
989 * acts as a NOP unless some role activated the hardware
991 void musb_stop(struct musb *musb)
993 /* stop IRQs, timers, ... */
994 musb_platform_disable(musb);
995 musb_generic_disable(musb);
996 dev_dbg(musb->controller, "HDRC disabled\n");
999 * - mark host and/or peripheral drivers unusable/inactive
1000 * - disable DMA (and enable it in HdrcStart)
1001 * - make sure we can musb_start() after musb_stop(); with
1002 * OTG mode, gadget driver module rmmod/modprobe cycles that
1005 musb_platform_try_idle(musb, 0);
1008 static void musb_shutdown(struct platform_device *pdev)
1010 struct musb *musb = dev_to_musb(&pdev->dev);
1011 unsigned long flags;
1013 pm_runtime_get_sync(musb->controller);
1014 spin_lock_irqsave(&musb->lock, flags);
1015 musb_platform_disable(musb);
1016 musb_generic_disable(musb);
1017 spin_unlock_irqrestore(&musb->lock, flags);
1019 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1020 usb_remove_hcd(musb_to_hcd(musb));
1021 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1022 musb_platform_exit(musb);
1024 pm_runtime_put(musb->controller);
1025 /* FIXME power down */
1029 /*-------------------------------------------------------------------------*/
1032 * The silicon either has hard-wired endpoint configurations, or else
1033 * "dynamic fifo" sizing. The driver has support for both, though at this
1034 * writing only the dynamic sizing is very well tested. Since we switched
1035 * away from compile-time hardware parameters, we can no longer rely on
1036 * dead code elimination to leave only the relevant one in the object file.
1038 * We don't currently use dynamic fifo setup capability to do anything
1039 * more than selecting one of a bunch of predefined configurations.
1041 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1042 || defined(CONFIG_USB_MUSB_AM35X)
1043 static ushort __initdata fifo_mode = 4;
1044 #elif defined(CONFIG_USB_MUSB_UX500)
1045 static ushort __initdata fifo_mode = 5;
1047 static ushort __initdata fifo_mode = 2;
1050 /* "modprobe ... fifo_mode=1" etc */
1051 module_param(fifo_mode, ushort, 0);
1052 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1055 * tables defining fifo_mode values. define more if you like.
1056 * for host side, make sure both halves of ep1 are set up.
1059 /* mode 0 - fits in 2KB */
1060 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1061 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1064 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1065 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1068 /* mode 1 - fits in 4KB */
1069 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1070 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1071 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1072 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1073 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1074 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1077 /* mode 2 - fits in 4KB */
1078 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1079 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1082 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1083 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1084 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1087 /* mode 3 - fits in 4KB */
1088 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1089 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1090 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1091 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1092 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1093 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1094 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1097 /* mode 4 - fits in 16KB */
1098 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1099 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1100 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1101 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1110 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1111 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1112 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1113 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1116 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1117 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1118 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1119 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1120 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1121 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1122 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1123 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1124 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1125 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1128 /* mode 5 - fits in 8KB */
1129 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1130 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1141 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1142 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1143 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1144 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1145 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1146 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1147 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1148 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1149 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1150 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1151 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1152 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1153 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1154 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1155 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1156 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1160 * configure a fifo; for non-shared endpoints, this may be called
1161 * once for a tx fifo and once for an rx fifo.
1163 * returns negative errno or offset for next fifo.
1166 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1167 const struct musb_fifo_cfg *cfg, u16 offset)
1169 void __iomem *mbase = musb->mregs;
1171 u16 maxpacket = cfg->maxpacket;
1172 u16 c_off = offset >> 3;
1175 /* expect hw_ep has already been zero-initialized */
1177 size = ffs(max(maxpacket, (u16) 8)) - 1;
1178 maxpacket = 1 << size;
1181 if (cfg->mode == BUF_DOUBLE) {
1182 if ((offset + (maxpacket << 1)) >
1183 (1 << (musb->config->ram_bits + 2)))
1185 c_size |= MUSB_FIFOSZ_DPB;
1187 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1191 /* configure the FIFO */
1192 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1194 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1195 /* EP0 reserved endpoint for control, bidirectional;
1196 * EP1 reserved for bulk, two unidirection halves.
1198 if (hw_ep->epnum == 1)
1199 musb->bulk_ep = hw_ep;
1200 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1202 switch (cfg->style) {
1204 musb_write_txfifosz(mbase, c_size);
1205 musb_write_txfifoadd(mbase, c_off);
1206 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1207 hw_ep->max_packet_sz_tx = maxpacket;
1210 musb_write_rxfifosz(mbase, c_size);
1211 musb_write_rxfifoadd(mbase, c_off);
1212 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1213 hw_ep->max_packet_sz_rx = maxpacket;
1216 musb_write_txfifosz(mbase, c_size);
1217 musb_write_txfifoadd(mbase, c_off);
1218 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1219 hw_ep->max_packet_sz_rx = maxpacket;
1221 musb_write_rxfifosz(mbase, c_size);
1222 musb_write_rxfifoadd(mbase, c_off);
1223 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1224 hw_ep->max_packet_sz_tx = maxpacket;
1226 hw_ep->is_shared_fifo = true;
1230 /* NOTE rx and tx endpoint irqs aren't managed separately,
1231 * which happens to be ok
1233 musb->epmask |= (1 << hw_ep->epnum);
1235 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1238 static struct musb_fifo_cfg __initdata ep0_cfg = {
1239 .style = FIFO_RXTX, .maxpacket = 64,
1242 static int __init ep_config_from_table(struct musb *musb)
1244 const struct musb_fifo_cfg *cfg;
1247 struct musb_hw_ep *hw_ep = musb->endpoints;
1249 if (musb->config->fifo_cfg) {
1250 cfg = musb->config->fifo_cfg;
1251 n = musb->config->fifo_cfg_size;
1255 switch (fifo_mode) {
1261 n = ARRAY_SIZE(mode_0_cfg);
1265 n = ARRAY_SIZE(mode_1_cfg);
1269 n = ARRAY_SIZE(mode_2_cfg);
1273 n = ARRAY_SIZE(mode_3_cfg);
1277 n = ARRAY_SIZE(mode_4_cfg);
1281 n = ARRAY_SIZE(mode_5_cfg);
1285 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1286 musb_driver_name, fifo_mode);
1290 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1291 /* assert(offset > 0) */
1293 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1294 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1297 for (i = 0; i < n; i++) {
1298 u8 epn = cfg->hw_ep_num;
1300 if (epn >= musb->config->num_eps) {
1301 pr_debug("%s: invalid ep %d\n",
1302 musb_driver_name, epn);
1305 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1307 pr_debug("%s: mem overrun, ep %d\n",
1308 musb_driver_name, epn);
1312 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1315 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1317 n + 1, musb->config->num_eps * 2 - 1,
1318 offset, (1 << (musb->config->ram_bits + 2)));
1320 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1321 if (!musb->bulk_ep) {
1322 pr_debug("%s: missing bulk\n", musb_driver_name);
1332 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1333 * @param musb the controller
1335 static int __init ep_config_from_hw(struct musb *musb)
1338 struct musb_hw_ep *hw_ep;
1339 void *mbase = musb->mregs;
1342 dev_dbg(musb->controller, "<== static silicon ep config\n");
1344 /* FIXME pick up ep0 maxpacket size */
1346 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1347 musb_ep_select(mbase, epnum);
1348 hw_ep = musb->endpoints + epnum;
1350 ret = musb_read_fifosize(musb, hw_ep, epnum);
1354 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1356 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1357 /* pick an RX/TX endpoint for bulk */
1358 if (hw_ep->max_packet_sz_tx < 512
1359 || hw_ep->max_packet_sz_rx < 512)
1362 /* REVISIT: this algorithm is lazy, we should at least
1363 * try to pick a double buffered endpoint.
1367 musb->bulk_ep = hw_ep;
1371 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1372 if (!musb->bulk_ep) {
1373 pr_debug("%s: missing bulk\n", musb_driver_name);
1381 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1383 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1384 * configure endpoints, or take their config from silicon
1386 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1390 char aInfo[90], aRevision[32], aDate[12];
1391 void __iomem *mbase = musb->mregs;
1395 /* log core options (read using indexed model) */
1396 reg = musb_read_configdata(mbase);
1398 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1399 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1400 strcat(aInfo, ", dyn FIFOs");
1401 musb->dyn_fifo = true;
1403 if (reg & MUSB_CONFIGDATA_MPRXE) {
1404 strcat(aInfo, ", bulk combine");
1405 musb->bulk_combine = true;
1407 if (reg & MUSB_CONFIGDATA_MPTXE) {
1408 strcat(aInfo, ", bulk split");
1409 musb->bulk_split = true;
1411 if (reg & MUSB_CONFIGDATA_HBRXE) {
1412 strcat(aInfo, ", HB-ISO Rx");
1413 musb->hb_iso_rx = true;
1415 if (reg & MUSB_CONFIGDATA_HBTXE) {
1416 strcat(aInfo, ", HB-ISO Tx");
1417 musb->hb_iso_tx = true;
1419 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1420 strcat(aInfo, ", SoftConn");
1422 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1423 musb_driver_name, reg, aInfo);
1426 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1427 musb->is_multipoint = 1;
1430 musb->is_multipoint = 0;
1432 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1433 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1435 "%s: kernel must blacklist external hubs\n",
1441 /* log release info */
1442 musb->hwvers = musb_read_hwvers(mbase);
1443 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1444 MUSB_HWVERS_MINOR(musb->hwvers),
1445 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1446 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1447 musb_driver_name, type, aRevision, aDate);
1450 musb_configure_ep0(musb);
1452 /* discover endpoint configuration */
1453 musb->nr_endpoints = 1;
1457 status = ep_config_from_table(musb);
1459 status = ep_config_from_hw(musb);
1464 /* finish init, and print endpoint config */
1465 for (i = 0; i < musb->nr_endpoints; i++) {
1466 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1468 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1469 #ifdef CONFIG_USB_MUSB_TUSB6010
1470 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1471 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1472 hw_ep->fifo_sync_va =
1473 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1476 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1478 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1481 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1482 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1483 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1484 hw_ep->rx_reinit = 1;
1485 hw_ep->tx_reinit = 1;
1488 if (hw_ep->max_packet_sz_tx) {
1489 dev_dbg(musb->controller,
1490 "%s: hw_ep %d%s, %smax %d\n",
1491 musb_driver_name, i,
1492 hw_ep->is_shared_fifo ? "shared" : "tx",
1493 hw_ep->tx_double_buffered
1494 ? "doublebuffer, " : "",
1495 hw_ep->max_packet_sz_tx);
1497 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1498 dev_dbg(musb->controller,
1499 "%s: hw_ep %d%s, %smax %d\n",
1500 musb_driver_name, i,
1502 hw_ep->rx_double_buffered
1503 ? "doublebuffer, " : "",
1504 hw_ep->max_packet_sz_rx);
1506 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1507 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1513 /*-------------------------------------------------------------------------*/
1515 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1516 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
1517 defined(CONFIG_ARCH_U5500)
1519 static irqreturn_t generic_interrupt(int irq, void *__hci)
1521 unsigned long flags;
1522 irqreturn_t retval = IRQ_NONE;
1523 struct musb *musb = __hci;
1525 spin_lock_irqsave(&musb->lock, flags);
1527 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1528 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1529 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1531 if (musb->int_usb || musb->int_tx || musb->int_rx)
1532 retval = musb_interrupt(musb);
1534 spin_unlock_irqrestore(&musb->lock, flags);
1540 #define generic_interrupt NULL
1544 * handle all the irqs defined by the HDRC core. for now we expect: other
1545 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1546 * will be assigned, and the irq will already have been acked.
1548 * called in irq context with spinlock held, irqs blocked
1550 irqreturn_t musb_interrupt(struct musb *musb)
1552 irqreturn_t retval = IRQ_NONE;
1557 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1558 power = musb_readb(musb->mregs, MUSB_POWER);
1560 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1561 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1562 musb->int_usb, musb->int_tx, musb->int_rx);
1564 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1565 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1566 if (!musb->gadget_driver) {
1567 dev_dbg(musb->controller, "No gadget driver loaded\n");
1572 /* the core can interrupt us for multiple reasons; docs have
1573 * a generic interrupt flowchart to follow
1576 retval |= musb_stage0_irq(musb, musb->int_usb,
1579 /* "stage 1" is handling endpoint irqs */
1581 /* handle endpoint 0 first */
1582 if (musb->int_tx & 1) {
1583 if (devctl & MUSB_DEVCTL_HM)
1584 retval |= musb_h_ep0_irq(musb);
1586 retval |= musb_g_ep0_irq(musb);
1589 /* RX on endpoints 1-15 */
1590 reg = musb->int_rx >> 1;
1594 /* musb_ep_select(musb->mregs, ep_num); */
1595 /* REVISIT just retval = ep->rx_irq(...) */
1596 retval = IRQ_HANDLED;
1597 if (devctl & MUSB_DEVCTL_HM) {
1598 if (is_host_capable())
1599 musb_host_rx(musb, ep_num);
1601 if (is_peripheral_capable())
1602 musb_g_rx(musb, ep_num);
1610 /* TX on endpoints 1-15 */
1611 reg = musb->int_tx >> 1;
1615 /* musb_ep_select(musb->mregs, ep_num); */
1616 /* REVISIT just retval |= ep->tx_irq(...) */
1617 retval = IRQ_HANDLED;
1618 if (devctl & MUSB_DEVCTL_HM) {
1619 if (is_host_capable())
1620 musb_host_tx(musb, ep_num);
1622 if (is_peripheral_capable())
1623 musb_g_tx(musb, ep_num);
1632 EXPORT_SYMBOL_GPL(musb_interrupt);
1634 #ifndef CONFIG_MUSB_PIO_ONLY
1635 static int __initdata use_dma = 1;
1637 /* "modprobe ... use_dma=0" etc */
1638 module_param(use_dma, bool, 0);
1639 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1641 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1643 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1645 /* called with controller lock already held */
1648 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1649 if (!is_cppi_enabled()) {
1651 if (devctl & MUSB_DEVCTL_HM)
1652 musb_h_ep0_irq(musb);
1654 musb_g_ep0_irq(musb);
1658 /* endpoints 1..15 */
1660 if (devctl & MUSB_DEVCTL_HM) {
1661 if (is_host_capable())
1662 musb_host_tx(musb, epnum);
1664 if (is_peripheral_capable())
1665 musb_g_tx(musb, epnum);
1669 if (devctl & MUSB_DEVCTL_HM) {
1670 if (is_host_capable())
1671 musb_host_rx(musb, epnum);
1673 if (is_peripheral_capable())
1674 musb_g_rx(musb, epnum);
1684 /*-------------------------------------------------------------------------*/
1689 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1691 struct musb *musb = dev_to_musb(dev);
1692 unsigned long flags;
1695 spin_lock_irqsave(&musb->lock, flags);
1696 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1697 spin_unlock_irqrestore(&musb->lock, flags);
1703 musb_mode_store(struct device *dev, struct device_attribute *attr,
1704 const char *buf, size_t n)
1706 struct musb *musb = dev_to_musb(dev);
1707 unsigned long flags;
1710 spin_lock_irqsave(&musb->lock, flags);
1711 if (sysfs_streq(buf, "host"))
1712 status = musb_platform_set_mode(musb, MUSB_HOST);
1713 else if (sysfs_streq(buf, "peripheral"))
1714 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1715 else if (sysfs_streq(buf, "otg"))
1716 status = musb_platform_set_mode(musb, MUSB_OTG);
1719 spin_unlock_irqrestore(&musb->lock, flags);
1721 return (status == 0) ? n : status;
1723 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1726 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1727 const char *buf, size_t n)
1729 struct musb *musb = dev_to_musb(dev);
1730 unsigned long flags;
1733 if (sscanf(buf, "%lu", &val) < 1) {
1734 dev_err(dev, "Invalid VBUS timeout ms value\n");
1738 spin_lock_irqsave(&musb->lock, flags);
1739 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1740 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1741 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1742 musb->is_active = 0;
1743 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1744 spin_unlock_irqrestore(&musb->lock, flags);
1750 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1752 struct musb *musb = dev_to_musb(dev);
1753 unsigned long flags;
1757 spin_lock_irqsave(&musb->lock, flags);
1758 val = musb->a_wait_bcon;
1759 /* FIXME get_vbus_status() is normally #defined as false...
1760 * and is effectively TUSB-specific.
1762 vbus = musb_platform_get_vbus_status(musb);
1763 spin_unlock_irqrestore(&musb->lock, flags);
1765 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1766 vbus ? "on" : "off", val);
1768 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1770 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1772 /* Gadget drivers can't know that a host is connected so they might want
1773 * to start SRP, but users can. This allows userspace to trigger SRP.
1776 musb_srp_store(struct device *dev, struct device_attribute *attr,
1777 const char *buf, size_t n)
1779 struct musb *musb = dev_to_musb(dev);
1782 if (sscanf(buf, "%hu", &srp) != 1
1784 dev_err(dev, "SRP: Value must be 1\n");
1789 musb_g_wakeup(musb);
1793 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1795 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1797 static struct attribute *musb_attributes[] = {
1798 &dev_attr_mode.attr,
1799 &dev_attr_vbus.attr,
1800 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1806 static const struct attribute_group musb_attr_group = {
1807 .attrs = musb_attributes,
1812 /* Only used to provide driver mode change events */
1813 static void musb_irq_work(struct work_struct *data)
1815 struct musb *musb = container_of(data, struct musb, irq_work);
1816 static int old_state;
1818 if (musb->xceiv->state != old_state) {
1819 old_state = musb->xceiv->state;
1820 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1824 /* --------------------------------------------------------------------------
1828 static struct musb *__init
1829 allocate_instance(struct device *dev,
1830 struct musb_hdrc_config *config, void __iomem *mbase)
1833 struct musb_hw_ep *ep;
1835 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1836 struct usb_hcd *hcd;
1838 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1841 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1843 musb = hcd_to_musb(hcd);
1844 INIT_LIST_HEAD(&musb->control);
1845 INIT_LIST_HEAD(&musb->in_bulk);
1846 INIT_LIST_HEAD(&musb->out_bulk);
1848 hcd->uses_new_polling = 1;
1851 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1852 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1854 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1859 dev_set_drvdata(dev, musb);
1860 musb->mregs = mbase;
1861 musb->ctrl_base = mbase;
1862 musb->nIrq = -ENODEV;
1863 musb->config = config;
1864 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1865 for (epnum = 0, ep = musb->endpoints;
1866 epnum < musb->config->num_eps;
1872 musb->controller = dev;
1877 static void musb_free(struct musb *musb)
1879 /* this has multiple entry modes. it handles fault cleanup after
1880 * probe(), where things may be partially set up, as well as rmmod
1881 * cleanup after everything's been de-activated.
1885 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1888 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1889 musb_gadget_cleanup(musb);
1892 if (musb->nIrq >= 0) {
1894 disable_irq_wake(musb->nIrq);
1895 free_irq(musb->nIrq, musb);
1897 if (is_dma_capable() && musb->dma_controller) {
1898 struct dma_controller *c = musb->dma_controller;
1901 dma_controller_destroy(c);
1904 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1905 usb_put_hcd(musb_to_hcd(musb));
1912 * Perform generic per-controller initialization.
1914 * @pDevice: the controller (already clocked, etc)
1916 * @mregs: virtual address of controller registers,
1917 * not yet corrected for platform-specific offsets
1920 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1924 struct musb_hdrc_platform_data *plat = dev->platform_data;
1926 /* The driver might handle more features than the board; OK.
1927 * Fail when the board needs a feature that's not enabled.
1930 dev_dbg(dev, "no platform_data?\n");
1936 musb = allocate_instance(dev, plat->config, ctrl);
1942 pm_runtime_use_autosuspend(musb->controller);
1943 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1944 pm_runtime_enable(musb->controller);
1946 spin_lock_init(&musb->lock);
1947 musb->board_mode = plat->mode;
1948 musb->board_set_power = plat->set_power;
1949 musb->min_power = plat->min_power;
1950 musb->ops = plat->platform_ops;
1952 /* The musb_platform_init() call:
1953 * - adjusts musb->mregs and musb->isr if needed,
1954 * - may initialize an integrated tranceiver
1955 * - initializes musb->xceiv, usually by otg_get_transceiver()
1956 * - stops powering VBUS
1958 * There are various transceiver configurations. Blackfin,
1959 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1960 * external/discrete ones in various flavors (twl4030 family,
1961 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1963 musb->isr = generic_interrupt;
1964 status = musb_platform_init(musb);
1973 if (!musb->xceiv->io_ops) {
1974 musb->xceiv->io_priv = musb->mregs;
1975 musb->xceiv->io_ops = &musb_ulpi_access;
1978 #ifndef CONFIG_MUSB_PIO_ONLY
1979 if (use_dma && dev->dma_mask) {
1980 struct dma_controller *c;
1982 c = dma_controller_create(musb, musb->mregs);
1983 musb->dma_controller = c;
1988 /* ideally this would be abstracted in platform setup */
1989 if (!is_dma_capable() || !musb->dma_controller)
1990 dev->dma_mask = NULL;
1992 /* be sure interrupts are disabled before connecting ISR */
1993 musb_platform_disable(musb);
1994 musb_generic_disable(musb);
1996 /* setup musb parts of the core (especially endpoints) */
1997 status = musb_core_init(plat->config->multipoint
1998 ? MUSB_CONTROLLER_MHDRC
1999 : MUSB_CONTROLLER_HDRC, musb);
2003 #ifdef CONFIG_USB_MUSB_OTG
2004 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2007 /* Init IRQ workqueue before request_irq */
2008 INIT_WORK(&musb->irq_work, musb_irq_work);
2010 /* attach to the IRQ */
2011 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2012 dev_err(dev, "request_irq %d failed!\n", nIrq);
2017 /* FIXME this handles wakeup irqs wrong */
2018 if (enable_irq_wake(nIrq) == 0) {
2020 device_init_wakeup(dev, 1);
2025 /* host side needs more setup */
2026 if (is_host_enabled(musb)) {
2027 struct usb_hcd *hcd = musb_to_hcd(musb);
2029 otg_set_host(musb->xceiv, &hcd->self);
2031 if (is_otg_enabled(musb))
2032 hcd->self.otg_port = 1;
2033 musb->xceiv->host = &hcd->self;
2034 hcd->power_budget = 2 * (plat->power ? : 250);
2036 /* program PHY to use external vBus if required */
2037 if (plat->extvbus) {
2038 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2039 busctl |= MUSB_ULPI_USE_EXTVBUS;
2040 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2044 /* For the host-only role, we can activate right away.
2045 * (We expect the ID pin to be forcibly grounded!!)
2046 * Otherwise, wait till the gadget driver hooks up.
2048 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2049 struct usb_hcd *hcd = musb_to_hcd(musb);
2051 MUSB_HST_MODE(musb);
2052 musb->xceiv->default_a = 1;
2053 musb->xceiv->state = OTG_STATE_A_IDLE;
2055 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2057 hcd->self.uses_pio_for_control = 1;
2058 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2060 musb_readb(musb->mregs, MUSB_DEVCTL),
2061 (musb_readb(musb->mregs, MUSB_DEVCTL)
2062 & MUSB_DEVCTL_BDEVICE
2065 } else /* peripheral is enabled */ {
2066 MUSB_DEV_MODE(musb);
2067 musb->xceiv->default_a = 0;
2068 musb->xceiv->state = OTG_STATE_B_IDLE;
2070 status = musb_gadget_setup(musb);
2072 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2073 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2075 musb_readb(musb->mregs, MUSB_DEVCTL));
2081 pm_runtime_put(musb->controller);
2083 status = musb_init_debugfs(musb);
2088 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2093 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2095 switch (musb->board_mode) {
2096 case MUSB_HOST: s = "Host"; break;
2097 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2098 default: s = "OTG"; break;
2101 (is_dma_capable() && musb->dma_controller)
2108 musb_exit_debugfs(musb);
2111 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2112 usb_remove_hcd(musb_to_hcd(musb));
2114 musb_gadget_cleanup(musb);
2118 device_init_wakeup(dev, 0);
2119 musb_platform_exit(musb);
2122 dev_err(musb->controller,
2123 "musb_init_controller failed with status %d\n", status);
2133 /*-------------------------------------------------------------------------*/
2135 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2136 * bridge to a platform device; this driver then suffices.
2139 #ifndef CONFIG_MUSB_PIO_ONLY
2140 static u64 *orig_dma_mask;
2143 static int __init musb_probe(struct platform_device *pdev)
2145 struct device *dev = &pdev->dev;
2146 int irq = platform_get_irq_byname(pdev, "mc");
2148 struct resource *iomem;
2151 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2152 if (!iomem || irq <= 0)
2155 base = ioremap(iomem->start, resource_size(iomem));
2157 dev_err(dev, "ioremap failed\n");
2161 #ifndef CONFIG_MUSB_PIO_ONLY
2162 /* clobbered by use_dma=n */
2163 orig_dma_mask = dev->dma_mask;
2165 status = musb_init_controller(dev, irq, base);
2172 static int __exit musb_remove(struct platform_device *pdev)
2174 struct musb *musb = dev_to_musb(&pdev->dev);
2175 void __iomem *ctrl_base = musb->ctrl_base;
2177 /* this gets called on rmmod.
2178 * - Host mode: host may still be active
2179 * - Peripheral mode: peripheral is deactivated (or never-activated)
2180 * - OTG mode: both roles are deactivated (or never-activated)
2182 pm_runtime_get_sync(musb->controller);
2183 musb_exit_debugfs(musb);
2184 musb_shutdown(pdev);
2186 pm_runtime_put(musb->controller);
2189 device_init_wakeup(&pdev->dev, 0);
2190 #ifndef CONFIG_MUSB_PIO_ONLY
2191 pdev->dev.dma_mask = orig_dma_mask;
2198 static void musb_save_context(struct musb *musb)
2201 void __iomem *musb_base = musb->mregs;
2204 if (is_host_enabled(musb)) {
2205 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2206 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2207 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2209 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2210 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2211 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2212 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2213 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2214 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2216 for (i = 0; i < musb->config->num_eps; ++i) {
2217 epio = musb->endpoints[i].regs;
2218 musb->context.index_regs[i].txmaxp =
2219 musb_readw(epio, MUSB_TXMAXP);
2220 musb->context.index_regs[i].txcsr =
2221 musb_readw(epio, MUSB_TXCSR);
2222 musb->context.index_regs[i].rxmaxp =
2223 musb_readw(epio, MUSB_RXMAXP);
2224 musb->context.index_regs[i].rxcsr =
2225 musb_readw(epio, MUSB_RXCSR);
2227 if (musb->dyn_fifo) {
2228 musb->context.index_regs[i].txfifoadd =
2229 musb_read_txfifoadd(musb_base);
2230 musb->context.index_regs[i].rxfifoadd =
2231 musb_read_rxfifoadd(musb_base);
2232 musb->context.index_regs[i].txfifosz =
2233 musb_read_txfifosz(musb_base);
2234 musb->context.index_regs[i].rxfifosz =
2235 musb_read_rxfifosz(musb_base);
2237 if (is_host_enabled(musb)) {
2238 musb->context.index_regs[i].txtype =
2239 musb_readb(epio, MUSB_TXTYPE);
2240 musb->context.index_regs[i].txinterval =
2241 musb_readb(epio, MUSB_TXINTERVAL);
2242 musb->context.index_regs[i].rxtype =
2243 musb_readb(epio, MUSB_RXTYPE);
2244 musb->context.index_regs[i].rxinterval =
2245 musb_readb(epio, MUSB_RXINTERVAL);
2247 musb->context.index_regs[i].txfunaddr =
2248 musb_read_txfunaddr(musb_base, i);
2249 musb->context.index_regs[i].txhubaddr =
2250 musb_read_txhubaddr(musb_base, i);
2251 musb->context.index_regs[i].txhubport =
2252 musb_read_txhubport(musb_base, i);
2254 musb->context.index_regs[i].rxfunaddr =
2255 musb_read_rxfunaddr(musb_base, i);
2256 musb->context.index_regs[i].rxhubaddr =
2257 musb_read_rxhubaddr(musb_base, i);
2258 musb->context.index_regs[i].rxhubport =
2259 musb_read_rxhubport(musb_base, i);
2264 static void musb_restore_context(struct musb *musb)
2267 void __iomem *musb_base = musb->mregs;
2268 void __iomem *ep_target_regs;
2271 if (is_host_enabled(musb)) {
2272 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2273 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2274 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2276 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2277 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2278 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2279 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2280 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2282 for (i = 0; i < musb->config->num_eps; ++i) {
2283 epio = musb->endpoints[i].regs;
2284 musb_writew(epio, MUSB_TXMAXP,
2285 musb->context.index_regs[i].txmaxp);
2286 musb_writew(epio, MUSB_TXCSR,
2287 musb->context.index_regs[i].txcsr);
2288 musb_writew(epio, MUSB_RXMAXP,
2289 musb->context.index_regs[i].rxmaxp);
2290 musb_writew(epio, MUSB_RXCSR,
2291 musb->context.index_regs[i].rxcsr);
2293 if (musb->dyn_fifo) {
2294 musb_write_txfifosz(musb_base,
2295 musb->context.index_regs[i].txfifosz);
2296 musb_write_rxfifosz(musb_base,
2297 musb->context.index_regs[i].rxfifosz);
2298 musb_write_txfifoadd(musb_base,
2299 musb->context.index_regs[i].txfifoadd);
2300 musb_write_rxfifoadd(musb_base,
2301 musb->context.index_regs[i].rxfifoadd);
2304 if (is_host_enabled(musb)) {
2305 musb_writeb(epio, MUSB_TXTYPE,
2306 musb->context.index_regs[i].txtype);
2307 musb_writeb(epio, MUSB_TXINTERVAL,
2308 musb->context.index_regs[i].txinterval);
2309 musb_writeb(epio, MUSB_RXTYPE,
2310 musb->context.index_regs[i].rxtype);
2311 musb_writeb(epio, MUSB_RXINTERVAL,
2313 musb->context.index_regs[i].rxinterval);
2314 musb_write_txfunaddr(musb_base, i,
2315 musb->context.index_regs[i].txfunaddr);
2316 musb_write_txhubaddr(musb_base, i,
2317 musb->context.index_regs[i].txhubaddr);
2318 musb_write_txhubport(musb_base, i,
2319 musb->context.index_regs[i].txhubport);
2322 musb_read_target_reg_base(i, musb_base);
2324 musb_write_rxfunaddr(ep_target_regs,
2325 musb->context.index_regs[i].rxfunaddr);
2326 musb_write_rxhubaddr(ep_target_regs,
2327 musb->context.index_regs[i].rxhubaddr);
2328 musb_write_rxhubport(ep_target_regs,
2329 musb->context.index_regs[i].rxhubport);
2334 static int musb_suspend(struct device *dev)
2336 struct platform_device *pdev = to_platform_device(dev);
2337 unsigned long flags;
2338 struct musb *musb = dev_to_musb(&pdev->dev);
2340 spin_lock_irqsave(&musb->lock, flags);
2342 if (is_peripheral_active(musb)) {
2343 /* FIXME force disconnect unless we know USB will wake
2344 * the system up quickly enough to respond ...
2346 } else if (is_host_active(musb)) {
2347 /* we know all the children are suspended; sometimes
2348 * they will even be wakeup-enabled.
2352 musb_save_context(musb);
2354 spin_unlock_irqrestore(&musb->lock, flags);
2358 static int musb_resume_noirq(struct device *dev)
2360 struct platform_device *pdev = to_platform_device(dev);
2361 struct musb *musb = dev_to_musb(&pdev->dev);
2363 musb_restore_context(musb);
2365 /* for static cmos like DaVinci, register values were preserved
2366 * unless for some reason the whole soc powered down or the USB
2367 * module got reset through the PSC (vs just being disabled).
2372 static int musb_runtime_suspend(struct device *dev)
2374 struct musb *musb = dev_to_musb(dev);
2376 musb_save_context(musb);
2381 static int musb_runtime_resume(struct device *dev)
2383 struct musb *musb = dev_to_musb(dev);
2384 static int first = 1;
2387 * When pm_runtime_get_sync called for the first time in driver
2388 * init, some of the structure is still not initialized which is
2389 * used in restore function. But clock needs to be
2390 * enabled before any register access, so
2391 * pm_runtime_get_sync has to be called.
2392 * Also context restore without save does not make
2396 musb_restore_context(musb);
2402 static const struct dev_pm_ops musb_dev_pm_ops = {
2403 .suspend = musb_suspend,
2404 .resume_noirq = musb_resume_noirq,
2405 .runtime_suspend = musb_runtime_suspend,
2406 .runtime_resume = musb_runtime_resume,
2409 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2411 #define MUSB_DEV_PM_OPS NULL
2414 static struct platform_driver musb_driver = {
2416 .name = (char *)musb_driver_name,
2417 .bus = &platform_bus_type,
2418 .owner = THIS_MODULE,
2419 .pm = MUSB_DEV_PM_OPS,
2421 .remove = __exit_p(musb_remove),
2422 .shutdown = musb_shutdown,
2425 /*-------------------------------------------------------------------------*/
2427 static int __init musb_init(void)
2429 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2434 pr_info("%s: version " MUSB_VERSION ", "
2435 #ifdef CONFIG_MUSB_PIO_ONLY
2437 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2439 #elif defined(CONFIG_USB_INVENTRA_DMA)
2441 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2443 #elif defined(CONFIG_USB_UX500_DMA)
2449 #ifdef CONFIG_USB_MUSB_OTG
2450 "otg (peripheral+host)"
2451 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2453 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2458 return platform_driver_probe(&musb_driver, musb_probe);
2461 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2462 * and before usb gadget and host-side drivers start to register
2464 fs_initcall(musb_init);
2466 static void __exit musb_cleanup(void)
2468 platform_driver_unregister(&musb_driver);
2470 module_exit(musb_cleanup);