2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102 #include <linux/idr.h>
103 #include <linux/dma-mapping.h>
105 #include "musb_core.h"
107 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
110 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113 #define MUSB_VERSION "6.0"
115 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117 #define MUSB_DRIVER_NAME "musb-hdrc"
118 const char musb_driver_name[] = MUSB_DRIVER_NAME;
119 static DEFINE_IDA(musb_ida);
121 MODULE_DESCRIPTION(DRIVER_INFO);
122 MODULE_AUTHOR(DRIVER_AUTHOR);
123 MODULE_LICENSE("GPL");
124 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
127 /*-------------------------------------------------------------------------*/
129 static inline struct musb *dev_to_musb(struct device *dev)
131 return dev_get_drvdata(dev);
134 /*-------------------------------------------------------------------------*/
136 int musb_get_id(struct device *dev, gfp_t gfp_mask)
141 ret = ida_pre_get(&musb_ida, gfp_mask);
143 dev_err(dev, "failed to reserve resource for id\n");
147 ret = ida_get_new(&musb_ida, &id);
149 dev_err(dev, "failed to allocate a new id\n");
155 EXPORT_SYMBOL_GPL(musb_get_id);
157 void musb_put_id(struct device *dev, int id)
160 dev_dbg(dev, "removing id %d\n", id);
161 ida_remove(&musb_ida, id);
163 EXPORT_SYMBOL_GPL(musb_put_id);
165 #ifndef CONFIG_BLACKFIN
166 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
168 void __iomem *addr = phy->io_priv;
174 pm_runtime_get_sync(phy->io_dev);
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
181 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
182 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
185 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
186 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
187 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
189 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
190 & MUSB_ULPI_REG_CMPLT)) {
198 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
199 r &= ~MUSB_ULPI_REG_CMPLT;
200 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
202 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
205 pm_runtime_put(phy->io_dev);
210 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
212 void __iomem *addr = phy->io_priv;
218 pm_runtime_get_sync(phy->io_dev);
220 /* Make sure the transceiver is not in low power mode */
221 power = musb_readb(addr, MUSB_POWER);
222 power &= ~MUSB_POWER_SUSPENDM;
223 musb_writeb(addr, MUSB_POWER, power);
225 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
226 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
227 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
229 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
230 & MUSB_ULPI_REG_CMPLT)) {
238 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
239 r &= ~MUSB_ULPI_REG_CMPLT;
240 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
243 pm_runtime_put(phy->io_dev);
248 #define musb_ulpi_read NULL
249 #define musb_ulpi_write NULL
252 static struct usb_phy_io_ops musb_ulpi_access = {
253 .read = musb_ulpi_read,
254 .write = musb_ulpi_write,
257 /*-------------------------------------------------------------------------*/
259 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
262 * Load an endpoint's FIFO
264 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
266 struct musb *musb = hw_ep->musb;
267 void __iomem *fifo = hw_ep->fifo;
269 if (unlikely(len == 0))
274 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
275 'T', hw_ep->epnum, fifo, len, src);
277 /* we can't assume unaligned reads work */
278 if (likely((0x01 & (unsigned long) src) == 0)) {
281 /* best case is 32bit-aligned source address */
282 if ((0x02 & (unsigned long) src) == 0) {
284 writesl(fifo, src + index, len >> 2);
285 index += len & ~0x03;
288 musb_writew(fifo, 0, *(u16 *)&src[index]);
293 writesw(fifo, src + index, len >> 1);
294 index += len & ~0x01;
298 musb_writeb(fifo, 0, src[index]);
301 writesb(fifo, src, len);
305 #if !defined(CONFIG_USB_MUSB_AM35X)
307 * Unload an endpoint's FIFO
309 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
311 struct musb *musb = hw_ep->musb;
312 void __iomem *fifo = hw_ep->fifo;
314 if (unlikely(len == 0))
317 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
318 'R', hw_ep->epnum, fifo, len, dst);
320 /* we can't assume unaligned writes work */
321 if (likely((0x01 & (unsigned long) dst) == 0)) {
324 /* best case is 32bit-aligned destination address */
325 if ((0x02 & (unsigned long) dst) == 0) {
327 readsl(fifo, dst, len >> 2);
331 *(u16 *)&dst[index] = musb_readw(fifo, 0);
336 readsw(fifo, dst, len >> 1);
341 dst[index] = musb_readb(fifo, 0);
344 readsb(fifo, dst, len);
349 #endif /* normal PIO */
352 /*-------------------------------------------------------------------------*/
354 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
355 static const u8 musb_test_packet[53] = {
356 /* implicit SYNC then DATA0 to start */
359 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
361 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
363 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
364 /* JJJJJJJKKKKKKK x8 */
365 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
367 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
368 /* JKKKKKKK x10, JK */
369 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
371 /* implicit CRC16 then EOP to end */
374 void musb_load_testpacket(struct musb *musb)
376 void __iomem *regs = musb->endpoints[0].regs;
378 musb_ep_select(musb->mregs, 0);
379 musb_write_fifo(musb->control_ep,
380 sizeof(musb_test_packet), musb_test_packet);
381 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
384 /*-------------------------------------------------------------------------*/
387 * Handles OTG hnp timeouts, such as b_ase0_brst
389 static void musb_otg_timer_func(unsigned long data)
391 struct musb *musb = (struct musb *)data;
394 spin_lock_irqsave(&musb->lock, flags);
395 switch (musb->xceiv->state) {
396 case OTG_STATE_B_WAIT_ACON:
397 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
398 musb_g_disconnect(musb);
399 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
402 case OTG_STATE_A_SUSPEND:
403 case OTG_STATE_A_WAIT_BCON:
404 dev_dbg(musb->controller, "HNP: %s timeout\n",
405 otg_state_string(musb->xceiv->state));
406 musb_platform_set_vbus(musb, 0);
407 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
410 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
411 otg_state_string(musb->xceiv->state));
413 musb->ignore_disconnect = 0;
414 spin_unlock_irqrestore(&musb->lock, flags);
418 * Stops the HNP transition. Caller must take care of locking.
420 void musb_hnp_stop(struct musb *musb)
422 struct usb_hcd *hcd = musb_to_hcd(musb);
423 void __iomem *mbase = musb->mregs;
426 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
428 switch (musb->xceiv->state) {
429 case OTG_STATE_A_PERIPHERAL:
430 musb_g_disconnect(musb);
431 dev_dbg(musb->controller, "HNP: back to %s\n",
432 otg_state_string(musb->xceiv->state));
434 case OTG_STATE_B_HOST:
435 dev_dbg(musb->controller, "HNP: Disabling HR\n");
436 hcd->self.is_b_host = 0;
437 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
439 reg = musb_readb(mbase, MUSB_POWER);
440 reg |= MUSB_POWER_SUSPENDM;
441 musb_writeb(mbase, MUSB_POWER, reg);
442 /* REVISIT: Start SESSION_REQUEST here? */
445 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
446 otg_state_string(musb->xceiv->state));
450 * When returning to A state after HNP, avoid hub_port_rebounce(),
451 * which cause occasional OPT A "Did not receive reset after connect"
454 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
458 * Interrupt Service Routine to record USB "global" interrupts.
459 * Since these do not happen often and signify things of
460 * paramount importance, it seems OK to check them individually;
461 * the order of the tests is specified in the manual
463 * @param musb instance pointer
464 * @param int_usb register contents
469 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
472 struct usb_otg *otg = musb->xceiv->otg;
473 irqreturn_t handled = IRQ_NONE;
475 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
478 /* in host mode, the peripheral may issue remote wakeup.
479 * in peripheral mode, the host may resume the link.
480 * spurious RESUME irqs happen too, paired with SUSPEND.
482 if (int_usb & MUSB_INTR_RESUME) {
483 handled = IRQ_HANDLED;
484 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
486 if (devctl & MUSB_DEVCTL_HM) {
487 void __iomem *mbase = musb->mregs;
489 switch (musb->xceiv->state) {
490 case OTG_STATE_A_SUSPEND:
491 /* remote wakeup? later, GetPortStatus
492 * will stop RESUME signaling
495 if (power & MUSB_POWER_SUSPENDM) {
497 musb->int_usb &= ~MUSB_INTR_SUSPEND;
498 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
502 power &= ~MUSB_POWER_SUSPENDM;
503 musb_writeb(mbase, MUSB_POWER,
504 power | MUSB_POWER_RESUME);
506 musb->port1_status |=
507 (USB_PORT_STAT_C_SUSPEND << 16)
508 | MUSB_PORT_STAT_RESUME;
509 musb->rh_timer = jiffies
510 + msecs_to_jiffies(20);
512 musb->xceiv->state = OTG_STATE_A_HOST;
514 usb_hcd_resume_root_hub(musb_to_hcd(musb));
516 case OTG_STATE_B_WAIT_ACON:
517 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
522 WARNING("bogus %s RESUME (%s)\n",
524 otg_state_string(musb->xceiv->state));
527 switch (musb->xceiv->state) {
528 case OTG_STATE_A_SUSPEND:
529 /* possibly DISCONNECT is upcoming */
530 musb->xceiv->state = OTG_STATE_A_HOST;
531 usb_hcd_resume_root_hub(musb_to_hcd(musb));
533 case OTG_STATE_B_WAIT_ACON:
534 case OTG_STATE_B_PERIPHERAL:
535 /* disconnect while suspended? we may
536 * not get a disconnect irq...
538 if ((devctl & MUSB_DEVCTL_VBUS)
539 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
541 musb->int_usb |= MUSB_INTR_DISCONNECT;
542 musb->int_usb &= ~MUSB_INTR_SUSPEND;
547 case OTG_STATE_B_IDLE:
548 musb->int_usb &= ~MUSB_INTR_SUSPEND;
551 WARNING("bogus %s RESUME (%s)\n",
553 otg_state_string(musb->xceiv->state));
558 /* see manual for the order of the tests */
559 if (int_usb & MUSB_INTR_SESSREQ) {
560 void __iomem *mbase = musb->mregs;
562 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
563 && (devctl & MUSB_DEVCTL_BDEVICE)) {
564 dev_dbg(musb->controller, "SessReq while on B state\n");
568 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
569 otg_state_string(musb->xceiv->state));
571 /* IRQ arrives from ID pin sense or (later, if VBUS power
572 * is removed) SRP. responses are time critical:
573 * - turn on VBUS (with silicon-specific mechanism)
574 * - go through A_WAIT_VRISE
575 * - ... to A_WAIT_BCON.
576 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
578 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
579 musb->ep0_stage = MUSB_EP0_START;
580 musb->xceiv->state = OTG_STATE_A_IDLE;
582 musb_platform_set_vbus(musb, 1);
584 handled = IRQ_HANDLED;
587 if (int_usb & MUSB_INTR_VBUSERROR) {
590 /* During connection as an A-Device, we may see a short
591 * current spikes causing voltage drop, because of cable
592 * and peripheral capacitance combined with vbus draw.
593 * (So: less common with truly self-powered devices, where
594 * vbus doesn't act like a power supply.)
596 * Such spikes are short; usually less than ~500 usec, max
597 * of ~2 msec. That is, they're not sustained overcurrent
598 * errors, though they're reported using VBUSERROR irqs.
600 * Workarounds: (a) hardware: use self powered devices.
601 * (b) software: ignore non-repeated VBUS errors.
603 * REVISIT: do delays from lots of DEBUG_KERNEL checks
604 * make trouble here, keeping VBUS < 4.4V ?
606 switch (musb->xceiv->state) {
607 case OTG_STATE_A_HOST:
608 /* recovery is dicey once we've gotten past the
609 * initial stages of enumeration, but if VBUS
610 * stayed ok at the other end of the link, and
611 * another reset is due (at least for high speed,
612 * to redo the chirp etc), it might work OK...
614 case OTG_STATE_A_WAIT_BCON:
615 case OTG_STATE_A_WAIT_VRISE:
616 if (musb->vbuserr_retry) {
617 void __iomem *mbase = musb->mregs;
619 musb->vbuserr_retry--;
621 devctl |= MUSB_DEVCTL_SESSION;
622 musb_writeb(mbase, MUSB_DEVCTL, devctl);
624 musb->port1_status |=
625 USB_PORT_STAT_OVERCURRENT
626 | (USB_PORT_STAT_C_OVERCURRENT << 16);
633 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
634 otg_state_string(musb->xceiv->state),
637 switch (devctl & MUSB_DEVCTL_VBUS) {
638 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
639 s = "<SessEnd"; break;
640 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
641 s = "<AValid"; break;
642 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
643 s = "<VBusValid"; break;
644 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
648 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
651 /* go through A_WAIT_VFALL then start a new session */
653 musb_platform_set_vbus(musb, 0);
654 handled = IRQ_HANDLED;
657 if (int_usb & MUSB_INTR_SUSPEND) {
658 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
659 otg_state_string(musb->xceiv->state), devctl, power);
660 handled = IRQ_HANDLED;
662 switch (musb->xceiv->state) {
663 case OTG_STATE_A_PERIPHERAL:
664 /* We also come here if the cable is removed, since
665 * this silicon doesn't report ID-no-longer-grounded.
667 * We depend on T(a_wait_bcon) to shut us down, and
668 * hope users don't do anything dicey during this
669 * undesired detour through A_WAIT_BCON.
672 usb_hcd_resume_root_hub(musb_to_hcd(musb));
673 musb_root_disconnect(musb);
674 musb_platform_try_idle(musb, jiffies
675 + msecs_to_jiffies(musb->a_wait_bcon
676 ? : OTG_TIME_A_WAIT_BCON));
679 case OTG_STATE_B_IDLE:
680 if (!musb->is_active)
682 case OTG_STATE_B_PERIPHERAL:
683 musb_g_suspend(musb);
684 musb->is_active = otg->gadget->b_hnp_enable;
685 if (musb->is_active) {
686 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
687 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
688 mod_timer(&musb->otg_timer, jiffies
690 OTG_TIME_B_ASE0_BRST));
693 case OTG_STATE_A_WAIT_BCON:
694 if (musb->a_wait_bcon != 0)
695 musb_platform_try_idle(musb, jiffies
696 + msecs_to_jiffies(musb->a_wait_bcon));
698 case OTG_STATE_A_HOST:
699 musb->xceiv->state = OTG_STATE_A_SUSPEND;
700 musb->is_active = otg->host->b_hnp_enable;
702 case OTG_STATE_B_HOST:
703 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
704 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
707 /* "should not happen" */
713 if (int_usb & MUSB_INTR_CONNECT) {
714 struct usb_hcd *hcd = musb_to_hcd(musb);
716 handled = IRQ_HANDLED;
719 musb->ep0_stage = MUSB_EP0_START;
721 /* flush endpoints when transitioning from Device Mode */
722 if (is_peripheral_active(musb)) {
723 /* REVISIT HNP; just force disconnect */
725 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
726 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
727 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
728 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
729 |USB_PORT_STAT_HIGH_SPEED
730 |USB_PORT_STAT_ENABLE
732 musb->port1_status |= USB_PORT_STAT_CONNECTION
733 |(USB_PORT_STAT_C_CONNECTION << 16);
735 /* high vs full speed is just a guess until after reset */
736 if (devctl & MUSB_DEVCTL_LSDEV)
737 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
739 /* indicate new connection to OTG machine */
740 switch (musb->xceiv->state) {
741 case OTG_STATE_B_PERIPHERAL:
742 if (int_usb & MUSB_INTR_SUSPEND) {
743 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
744 int_usb &= ~MUSB_INTR_SUSPEND;
747 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
749 case OTG_STATE_B_WAIT_ACON:
750 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
752 musb->xceiv->state = OTG_STATE_B_HOST;
753 hcd->self.is_b_host = 1;
754 musb->ignore_disconnect = 0;
755 del_timer(&musb->otg_timer);
758 if ((devctl & MUSB_DEVCTL_VBUS)
759 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
760 musb->xceiv->state = OTG_STATE_A_HOST;
761 hcd->self.is_b_host = 0;
766 /* poke the root hub */
769 usb_hcd_poll_rh_status(hcd);
771 usb_hcd_resume_root_hub(hcd);
773 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
774 otg_state_string(musb->xceiv->state), devctl);
777 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
778 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
779 otg_state_string(musb->xceiv->state),
780 MUSB_MODE(musb), devctl);
781 handled = IRQ_HANDLED;
783 switch (musb->xceiv->state) {
784 case OTG_STATE_A_HOST:
785 case OTG_STATE_A_SUSPEND:
786 usb_hcd_resume_root_hub(musb_to_hcd(musb));
787 musb_root_disconnect(musb);
788 if (musb->a_wait_bcon != 0)
789 musb_platform_try_idle(musb, jiffies
790 + msecs_to_jiffies(musb->a_wait_bcon));
792 case OTG_STATE_B_HOST:
793 /* REVISIT this behaves for "real disconnect"
794 * cases; make sure the other transitions from
795 * from B_HOST act right too. The B_HOST code
796 * in hnp_stop() is currently not used...
798 musb_root_disconnect(musb);
799 musb_to_hcd(musb)->self.is_b_host = 0;
800 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
802 musb_g_disconnect(musb);
804 case OTG_STATE_A_PERIPHERAL:
806 musb_root_disconnect(musb);
808 case OTG_STATE_B_WAIT_ACON:
810 case OTG_STATE_B_PERIPHERAL:
811 case OTG_STATE_B_IDLE:
812 musb_g_disconnect(musb);
815 WARNING("unhandled DISCONNECT transition (%s)\n",
816 otg_state_string(musb->xceiv->state));
821 /* mentor saves a bit: bus reset and babble share the same irq.
822 * only host sees babble; only peripheral sees bus reset.
824 if (int_usb & MUSB_INTR_RESET) {
825 handled = IRQ_HANDLED;
826 if ((devctl & MUSB_DEVCTL_HM) != 0) {
828 * Looks like non-HS BABBLE can be ignored, but
829 * HS BABBLE is an error condition. For HS the solution
830 * is to avoid babble in the first place and fix what
831 * caused BABBLE. When HS BABBLE happens we can only
834 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
835 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
837 ERR("Stopping host session -- babble\n");
838 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
841 dev_dbg(musb->controller, "BUS RESET as %s\n",
842 otg_state_string(musb->xceiv->state));
843 switch (musb->xceiv->state) {
844 case OTG_STATE_A_SUSPEND:
845 /* We need to ignore disconnect on suspend
846 * otherwise tusb 2.0 won't reconnect after a
847 * power cycle, which breaks otg compliance.
849 musb->ignore_disconnect = 1;
852 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
853 /* never use invalid T(a_wait_bcon) */
854 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
855 otg_state_string(musb->xceiv->state),
857 mod_timer(&musb->otg_timer, jiffies
858 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
860 case OTG_STATE_A_PERIPHERAL:
861 musb->ignore_disconnect = 0;
862 del_timer(&musb->otg_timer);
865 case OTG_STATE_B_WAIT_ACON:
866 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
867 otg_state_string(musb->xceiv->state));
868 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
871 case OTG_STATE_B_IDLE:
872 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
874 case OTG_STATE_B_PERIPHERAL:
878 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
879 otg_state_string(musb->xceiv->state));
885 /* REVISIT ... this would be for multiplexing periodic endpoints, or
886 * supporting transfer phasing to prevent exceeding ISO bandwidth
887 * limits of a given frame or microframe.
889 * It's not needed for peripheral side, which dedicates endpoints;
890 * though it _might_ use SOF irqs for other purposes.
892 * And it's not currently needed for host side, which also dedicates
893 * endpoints, relies on TX/RX interval registers, and isn't claimed
894 * to support ISO transfers yet.
896 if (int_usb & MUSB_INTR_SOF) {
897 void __iomem *mbase = musb->mregs;
898 struct musb_hw_ep *ep;
902 dev_dbg(musb->controller, "START_OF_FRAME\n");
903 handled = IRQ_HANDLED;
905 /* start any periodic Tx transfers waiting for current frame */
906 frame = musb_readw(mbase, MUSB_FRAME);
907 ep = musb->endpoints;
908 for (epnum = 1; (epnum < musb->nr_endpoints)
909 && (musb->epmask >= (1 << epnum));
912 * FIXME handle framecounter wraps (12 bits)
913 * eliminate duplicated StartUrb logic
915 if (ep->dwWaitFrame >= frame) {
917 pr_debug("SOF --> periodic TX%s on %d\n",
918 ep->tx_channel ? " DMA" : "",
921 musb_h_tx_start(musb, epnum);
923 cppi_hostdma_start(musb, epnum);
925 } /* end of for loop */
929 schedule_work(&musb->irq_work);
934 /*-------------------------------------------------------------------------*/
937 * Program the HDRC to start (enable interrupts, dma, etc.).
939 void musb_start(struct musb *musb)
941 void __iomem *regs = musb->mregs;
942 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
944 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
946 /* Set INT enable registers, enable interrupts */
947 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
948 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
949 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
951 musb_writeb(regs, MUSB_TESTMODE, 0);
953 /* put into basic highspeed mode and start session */
954 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
956 /* ENSUSPEND wedges tusb */
957 /* | MUSB_POWER_ENSUSPEND */
961 devctl = musb_readb(regs, MUSB_DEVCTL);
962 devctl &= ~MUSB_DEVCTL_SESSION;
964 /* session started after:
965 * (a) ID-grounded irq, host mode;
966 * (b) vbus present/connect IRQ, peripheral mode;
967 * (c) peripheral initiates, using SRP
969 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
972 devctl |= MUSB_DEVCTL_SESSION;
974 musb_platform_enable(musb);
975 musb_writeb(regs, MUSB_DEVCTL, devctl);
979 static void musb_generic_disable(struct musb *musb)
981 void __iomem *mbase = musb->mregs;
984 /* disable interrupts */
985 musb_writeb(mbase, MUSB_INTRUSBE, 0);
986 musb_writew(mbase, MUSB_INTRTXE, 0);
987 musb_writew(mbase, MUSB_INTRRXE, 0);
990 musb_writeb(mbase, MUSB_DEVCTL, 0);
992 /* flush pending interrupts */
993 temp = musb_readb(mbase, MUSB_INTRUSB);
994 temp = musb_readw(mbase, MUSB_INTRTX);
995 temp = musb_readw(mbase, MUSB_INTRRX);
1000 * Make the HDRC stop (disable interrupts, etc.);
1001 * reversible by musb_start
1002 * called on gadget driver unregister
1003 * with controller locked, irqs blocked
1004 * acts as a NOP unless some role activated the hardware
1006 void musb_stop(struct musb *musb)
1008 /* stop IRQs, timers, ... */
1009 musb_platform_disable(musb);
1010 musb_generic_disable(musb);
1011 dev_dbg(musb->controller, "HDRC disabled\n");
1014 * - mark host and/or peripheral drivers unusable/inactive
1015 * - disable DMA (and enable it in HdrcStart)
1016 * - make sure we can musb_start() after musb_stop(); with
1017 * OTG mode, gadget driver module rmmod/modprobe cycles that
1020 musb_platform_try_idle(musb, 0);
1023 static void musb_shutdown(struct platform_device *pdev)
1025 struct musb *musb = dev_to_musb(&pdev->dev);
1026 unsigned long flags;
1028 pm_runtime_get_sync(musb->controller);
1030 musb_gadget_cleanup(musb);
1032 spin_lock_irqsave(&musb->lock, flags);
1033 musb_platform_disable(musb);
1034 musb_generic_disable(musb);
1035 spin_unlock_irqrestore(&musb->lock, flags);
1037 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1038 musb_platform_exit(musb);
1040 pm_runtime_put(musb->controller);
1041 /* FIXME power down */
1045 /*-------------------------------------------------------------------------*/
1048 * The silicon either has hard-wired endpoint configurations, or else
1049 * "dynamic fifo" sizing. The driver has support for both, though at this
1050 * writing only the dynamic sizing is very well tested. Since we switched
1051 * away from compile-time hardware parameters, we can no longer rely on
1052 * dead code elimination to leave only the relevant one in the object file.
1054 * We don't currently use dynamic fifo setup capability to do anything
1055 * more than selecting one of a bunch of predefined configurations.
1057 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1058 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1059 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1060 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1061 || defined(CONFIG_USB_MUSB_AM35X) \
1062 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1063 || defined(CONFIG_USB_MUSB_DSPS) \
1064 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1065 static ushort __devinitdata fifo_mode = 4;
1066 #elif defined(CONFIG_USB_MUSB_UX500) \
1067 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1068 static ushort __devinitdata fifo_mode = 5;
1070 static ushort __devinitdata fifo_mode = 2;
1073 /* "modprobe ... fifo_mode=1" etc */
1074 module_param(fifo_mode, ushort, 0);
1075 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1078 * tables defining fifo_mode values. define more if you like.
1079 * for host side, make sure both halves of ep1 are set up.
1082 /* mode 0 - fits in 2KB */
1083 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1084 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1087 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1088 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1091 /* mode 1 - fits in 4KB */
1092 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1093 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1095 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1096 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1097 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1100 /* mode 2 - fits in 4KB */
1101 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1102 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1107 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1110 /* mode 3 - fits in 4KB */
1111 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1112 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1113 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1114 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1117 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1120 /* mode 4 - fits in 16KB */
1121 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1122 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1123 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1124 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1125 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1126 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1127 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1128 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1129 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1130 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1139 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1140 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1141 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1142 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1143 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1144 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1145 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1146 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1147 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1148 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1151 /* mode 5 - fits in 8KB */
1152 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1153 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1154 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1155 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1156 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1157 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1158 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1159 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1162 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1163 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1164 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1165 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1166 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1167 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1168 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1169 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1170 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1171 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1172 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1173 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1174 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1175 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1176 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1177 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1178 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1179 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1183 * configure a fifo; for non-shared endpoints, this may be called
1184 * once for a tx fifo and once for an rx fifo.
1186 * returns negative errno or offset for next fifo.
1188 static int __devinit
1189 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1190 const struct musb_fifo_cfg *cfg, u16 offset)
1192 void __iomem *mbase = musb->mregs;
1194 u16 maxpacket = cfg->maxpacket;
1195 u16 c_off = offset >> 3;
1198 /* expect hw_ep has already been zero-initialized */
1200 size = ffs(max(maxpacket, (u16) 8)) - 1;
1201 maxpacket = 1 << size;
1204 if (cfg->mode == BUF_DOUBLE) {
1205 if ((offset + (maxpacket << 1)) >
1206 (1 << (musb->config->ram_bits + 2)))
1208 c_size |= MUSB_FIFOSZ_DPB;
1210 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1214 /* configure the FIFO */
1215 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1217 /* EP0 reserved endpoint for control, bidirectional;
1218 * EP1 reserved for bulk, two unidirection halves.
1220 if (hw_ep->epnum == 1)
1221 musb->bulk_ep = hw_ep;
1222 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1223 switch (cfg->style) {
1225 musb_write_txfifosz(mbase, c_size);
1226 musb_write_txfifoadd(mbase, c_off);
1227 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1228 hw_ep->max_packet_sz_tx = maxpacket;
1231 musb_write_rxfifosz(mbase, c_size);
1232 musb_write_rxfifoadd(mbase, c_off);
1233 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1234 hw_ep->max_packet_sz_rx = maxpacket;
1237 musb_write_txfifosz(mbase, c_size);
1238 musb_write_txfifoadd(mbase, c_off);
1239 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1240 hw_ep->max_packet_sz_rx = maxpacket;
1242 musb_write_rxfifosz(mbase, c_size);
1243 musb_write_rxfifoadd(mbase, c_off);
1244 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1245 hw_ep->max_packet_sz_tx = maxpacket;
1247 hw_ep->is_shared_fifo = true;
1251 /* NOTE rx and tx endpoint irqs aren't managed separately,
1252 * which happens to be ok
1254 musb->epmask |= (1 << hw_ep->epnum);
1256 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1259 static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1260 .style = FIFO_RXTX, .maxpacket = 64,
1263 static int __devinit ep_config_from_table(struct musb *musb)
1265 const struct musb_fifo_cfg *cfg;
1268 struct musb_hw_ep *hw_ep = musb->endpoints;
1270 if (musb->config->fifo_cfg) {
1271 cfg = musb->config->fifo_cfg;
1272 n = musb->config->fifo_cfg_size;
1276 switch (fifo_mode) {
1282 n = ARRAY_SIZE(mode_0_cfg);
1286 n = ARRAY_SIZE(mode_1_cfg);
1290 n = ARRAY_SIZE(mode_2_cfg);
1294 n = ARRAY_SIZE(mode_3_cfg);
1298 n = ARRAY_SIZE(mode_4_cfg);
1302 n = ARRAY_SIZE(mode_5_cfg);
1306 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1307 musb_driver_name, fifo_mode);
1311 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1312 /* assert(offset > 0) */
1314 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1315 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1318 for (i = 0; i < n; i++) {
1319 u8 epn = cfg->hw_ep_num;
1321 if (epn >= musb->config->num_eps) {
1322 pr_debug("%s: invalid ep %d\n",
1323 musb_driver_name, epn);
1326 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1328 pr_debug("%s: mem overrun, ep %d\n",
1329 musb_driver_name, epn);
1333 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1336 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1338 n + 1, musb->config->num_eps * 2 - 1,
1339 offset, (1 << (musb->config->ram_bits + 2)));
1341 if (!musb->bulk_ep) {
1342 pr_debug("%s: missing bulk\n", musb_driver_name);
1351 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1352 * @param musb the controller
1354 static int __devinit ep_config_from_hw(struct musb *musb)
1357 struct musb_hw_ep *hw_ep;
1358 void __iomem *mbase = musb->mregs;
1361 dev_dbg(musb->controller, "<== static silicon ep config\n");
1363 /* FIXME pick up ep0 maxpacket size */
1365 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1366 musb_ep_select(mbase, epnum);
1367 hw_ep = musb->endpoints + epnum;
1369 ret = musb_read_fifosize(musb, hw_ep, epnum);
1373 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1375 /* pick an RX/TX endpoint for bulk */
1376 if (hw_ep->max_packet_sz_tx < 512
1377 || hw_ep->max_packet_sz_rx < 512)
1380 /* REVISIT: this algorithm is lazy, we should at least
1381 * try to pick a double buffered endpoint.
1385 musb->bulk_ep = hw_ep;
1388 if (!musb->bulk_ep) {
1389 pr_debug("%s: missing bulk\n", musb_driver_name);
1396 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1398 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1399 * configure endpoints, or take their config from silicon
1401 static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1405 char aInfo[90], aRevision[32], aDate[12];
1406 void __iomem *mbase = musb->mregs;
1410 /* log core options (read using indexed model) */
1411 reg = musb_read_configdata(mbase);
1413 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1414 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1415 strcat(aInfo, ", dyn FIFOs");
1416 musb->dyn_fifo = true;
1418 if (reg & MUSB_CONFIGDATA_MPRXE) {
1419 strcat(aInfo, ", bulk combine");
1420 musb->bulk_combine = true;
1422 if (reg & MUSB_CONFIGDATA_MPTXE) {
1423 strcat(aInfo, ", bulk split");
1424 musb->bulk_split = true;
1426 if (reg & MUSB_CONFIGDATA_HBRXE) {
1427 strcat(aInfo, ", HB-ISO Rx");
1428 musb->hb_iso_rx = true;
1430 if (reg & MUSB_CONFIGDATA_HBTXE) {
1431 strcat(aInfo, ", HB-ISO Tx");
1432 musb->hb_iso_tx = true;
1434 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1435 strcat(aInfo, ", SoftConn");
1437 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1438 musb_driver_name, reg, aInfo);
1441 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1442 musb->is_multipoint = 1;
1445 musb->is_multipoint = 0;
1447 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1449 "%s: kernel must blacklist external hubs\n",
1454 /* log release info */
1455 musb->hwvers = musb_read_hwvers(mbase);
1456 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1457 MUSB_HWVERS_MINOR(musb->hwvers),
1458 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1459 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1460 musb_driver_name, type, aRevision, aDate);
1463 musb_configure_ep0(musb);
1465 /* discover endpoint configuration */
1466 musb->nr_endpoints = 1;
1470 status = ep_config_from_table(musb);
1472 status = ep_config_from_hw(musb);
1477 /* finish init, and print endpoint config */
1478 for (i = 0; i < musb->nr_endpoints; i++) {
1479 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1481 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1482 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1483 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1484 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1485 hw_ep->fifo_sync_va =
1486 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1489 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1491 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1494 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1495 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1496 hw_ep->rx_reinit = 1;
1497 hw_ep->tx_reinit = 1;
1499 if (hw_ep->max_packet_sz_tx) {
1500 dev_dbg(musb->controller,
1501 "%s: hw_ep %d%s, %smax %d\n",
1502 musb_driver_name, i,
1503 hw_ep->is_shared_fifo ? "shared" : "tx",
1504 hw_ep->tx_double_buffered
1505 ? "doublebuffer, " : "",
1506 hw_ep->max_packet_sz_tx);
1508 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1509 dev_dbg(musb->controller,
1510 "%s: hw_ep %d%s, %smax %d\n",
1511 musb_driver_name, i,
1513 hw_ep->rx_double_buffered
1514 ? "doublebuffer, " : "",
1515 hw_ep->max_packet_sz_rx);
1517 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1518 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1524 /*-------------------------------------------------------------------------*/
1526 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1527 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1529 static irqreturn_t generic_interrupt(int irq, void *__hci)
1531 unsigned long flags;
1532 irqreturn_t retval = IRQ_NONE;
1533 struct musb *musb = __hci;
1535 spin_lock_irqsave(&musb->lock, flags);
1537 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1538 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1539 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1541 if (musb->int_usb || musb->int_tx || musb->int_rx)
1542 retval = musb_interrupt(musb);
1544 spin_unlock_irqrestore(&musb->lock, flags);
1550 #define generic_interrupt NULL
1554 * handle all the irqs defined by the HDRC core. for now we expect: other
1555 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1556 * will be assigned, and the irq will already have been acked.
1558 * called in irq context with spinlock held, irqs blocked
1560 irqreturn_t musb_interrupt(struct musb *musb)
1562 irqreturn_t retval = IRQ_NONE;
1567 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1568 power = musb_readb(musb->mregs, MUSB_POWER);
1570 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1571 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1572 musb->int_usb, musb->int_tx, musb->int_rx);
1574 /* the core can interrupt us for multiple reasons; docs have
1575 * a generic interrupt flowchart to follow
1578 retval |= musb_stage0_irq(musb, musb->int_usb,
1581 /* "stage 1" is handling endpoint irqs */
1583 /* handle endpoint 0 first */
1584 if (musb->int_tx & 1) {
1585 if (devctl & MUSB_DEVCTL_HM)
1586 retval |= musb_h_ep0_irq(musb);
1588 retval |= musb_g_ep0_irq(musb);
1591 /* RX on endpoints 1-15 */
1592 reg = musb->int_rx >> 1;
1596 /* musb_ep_select(musb->mregs, ep_num); */
1597 /* REVISIT just retval = ep->rx_irq(...) */
1598 retval = IRQ_HANDLED;
1599 if (devctl & MUSB_DEVCTL_HM)
1600 musb_host_rx(musb, ep_num);
1602 musb_g_rx(musb, ep_num);
1609 /* TX on endpoints 1-15 */
1610 reg = musb->int_tx >> 1;
1614 /* musb_ep_select(musb->mregs, ep_num); */
1615 /* REVISIT just retval |= ep->tx_irq(...) */
1616 retval = IRQ_HANDLED;
1617 if (devctl & MUSB_DEVCTL_HM)
1618 musb_host_tx(musb, ep_num);
1620 musb_g_tx(musb, ep_num);
1628 EXPORT_SYMBOL_GPL(musb_interrupt);
1630 #ifndef CONFIG_MUSB_PIO_ONLY
1631 static bool __devinitdata use_dma = 1;
1633 /* "modprobe ... use_dma=0" etc */
1634 module_param(use_dma, bool, 0);
1635 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1637 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1639 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1641 /* called with controller lock already held */
1644 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1645 if (!is_cppi_enabled()) {
1647 if (devctl & MUSB_DEVCTL_HM)
1648 musb_h_ep0_irq(musb);
1650 musb_g_ep0_irq(musb);
1654 /* endpoints 1..15 */
1656 if (devctl & MUSB_DEVCTL_HM)
1657 musb_host_tx(musb, epnum);
1659 musb_g_tx(musb, epnum);
1662 if (devctl & MUSB_DEVCTL_HM)
1663 musb_host_rx(musb, epnum);
1665 musb_g_rx(musb, epnum);
1669 EXPORT_SYMBOL_GPL(musb_dma_completion);
1675 /*-------------------------------------------------------------------------*/
1680 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1682 struct musb *musb = dev_to_musb(dev);
1683 unsigned long flags;
1686 spin_lock_irqsave(&musb->lock, flags);
1687 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1688 spin_unlock_irqrestore(&musb->lock, flags);
1694 musb_mode_store(struct device *dev, struct device_attribute *attr,
1695 const char *buf, size_t n)
1697 struct musb *musb = dev_to_musb(dev);
1698 unsigned long flags;
1701 spin_lock_irqsave(&musb->lock, flags);
1702 if (sysfs_streq(buf, "host"))
1703 status = musb_platform_set_mode(musb, MUSB_HOST);
1704 else if (sysfs_streq(buf, "peripheral"))
1705 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1706 else if (sysfs_streq(buf, "otg"))
1707 status = musb_platform_set_mode(musb, MUSB_OTG);
1710 spin_unlock_irqrestore(&musb->lock, flags);
1712 return (status == 0) ? n : status;
1714 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1717 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1718 const char *buf, size_t n)
1720 struct musb *musb = dev_to_musb(dev);
1721 unsigned long flags;
1724 if (sscanf(buf, "%lu", &val) < 1) {
1725 dev_err(dev, "Invalid VBUS timeout ms value\n");
1729 spin_lock_irqsave(&musb->lock, flags);
1730 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1731 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1732 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1733 musb->is_active = 0;
1734 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1735 spin_unlock_irqrestore(&musb->lock, flags);
1741 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1743 struct musb *musb = dev_to_musb(dev);
1744 unsigned long flags;
1748 spin_lock_irqsave(&musb->lock, flags);
1749 val = musb->a_wait_bcon;
1750 /* FIXME get_vbus_status() is normally #defined as false...
1751 * and is effectively TUSB-specific.
1753 vbus = musb_platform_get_vbus_status(musb);
1754 spin_unlock_irqrestore(&musb->lock, flags);
1756 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1757 vbus ? "on" : "off", val);
1759 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1761 /* Gadget drivers can't know that a host is connected so they might want
1762 * to start SRP, but users can. This allows userspace to trigger SRP.
1765 musb_srp_store(struct device *dev, struct device_attribute *attr,
1766 const char *buf, size_t n)
1768 struct musb *musb = dev_to_musb(dev);
1771 if (sscanf(buf, "%hu", &srp) != 1
1773 dev_err(dev, "SRP: Value must be 1\n");
1778 musb_g_wakeup(musb);
1782 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1784 static struct attribute *musb_attributes[] = {
1785 &dev_attr_mode.attr,
1786 &dev_attr_vbus.attr,
1791 static const struct attribute_group musb_attr_group = {
1792 .attrs = musb_attributes,
1797 /* Only used to provide driver mode change events */
1798 static void musb_irq_work(struct work_struct *data)
1800 struct musb *musb = container_of(data, struct musb, irq_work);
1802 if (musb->xceiv->state != musb->xceiv_old_state) {
1803 musb->xceiv_old_state = musb->xceiv->state;
1804 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1808 /* --------------------------------------------------------------------------
1812 static struct musb *__devinit
1813 allocate_instance(struct device *dev,
1814 struct musb_hdrc_config *config, void __iomem *mbase)
1817 struct musb_hw_ep *ep;
1819 struct usb_hcd *hcd;
1821 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1824 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1826 musb = hcd_to_musb(hcd);
1827 INIT_LIST_HEAD(&musb->control);
1828 INIT_LIST_HEAD(&musb->in_bulk);
1829 INIT_LIST_HEAD(&musb->out_bulk);
1831 hcd->uses_new_polling = 1;
1834 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1835 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1836 dev_set_drvdata(dev, musb);
1837 musb->mregs = mbase;
1838 musb->ctrl_base = mbase;
1839 musb->nIrq = -ENODEV;
1840 musb->config = config;
1841 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1842 for (epnum = 0, ep = musb->endpoints;
1843 epnum < musb->config->num_eps;
1849 musb->controller = dev;
1854 static void musb_free(struct musb *musb)
1856 /* this has multiple entry modes. it handles fault cleanup after
1857 * probe(), where things may be partially set up, as well as rmmod
1858 * cleanup after everything's been de-activated.
1862 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1865 if (musb->nIrq >= 0) {
1867 disable_irq_wake(musb->nIrq);
1868 free_irq(musb->nIrq, musb);
1870 if (is_dma_capable() && musb->dma_controller) {
1871 struct dma_controller *c = musb->dma_controller;
1874 dma_controller_destroy(c);
1877 usb_put_hcd(musb_to_hcd(musb));
1881 * Perform generic per-controller initialization.
1883 * @dev: the controller (already clocked, etc)
1885 * @ctrl: virtual address of controller registers,
1886 * not yet corrected for platform-specific offsets
1888 static int __devinit
1889 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1893 struct musb_hdrc_platform_data *plat = dev->platform_data;
1894 struct usb_hcd *hcd;
1896 /* The driver might handle more features than the board; OK.
1897 * Fail when the board needs a feature that's not enabled.
1900 dev_dbg(dev, "no platform_data?\n");
1906 musb = allocate_instance(dev, plat->config, ctrl);
1912 pm_runtime_use_autosuspend(musb->controller);
1913 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1914 pm_runtime_enable(musb->controller);
1916 spin_lock_init(&musb->lock);
1917 musb->board_set_power = plat->set_power;
1918 musb->min_power = plat->min_power;
1919 musb->ops = plat->platform_ops;
1921 /* The musb_platform_init() call:
1922 * - adjusts musb->mregs and musb->isr if needed,
1923 * - may initialize an integrated tranceiver
1924 * - initializes musb->xceiv, usually by otg_get_phy()
1925 * - stops powering VBUS
1927 * There are various transceiver configurations. Blackfin,
1928 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1929 * external/discrete ones in various flavors (twl4030 family,
1930 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1932 musb->isr = generic_interrupt;
1933 status = musb_platform_init(musb);
1942 if (!musb->xceiv->io_ops) {
1943 musb->xceiv->io_dev = musb->controller;
1944 musb->xceiv->io_priv = musb->mregs;
1945 musb->xceiv->io_ops = &musb_ulpi_access;
1948 pm_runtime_get_sync(musb->controller);
1950 #ifndef CONFIG_MUSB_PIO_ONLY
1951 if (use_dma && dev->dma_mask) {
1952 struct dma_controller *c;
1954 c = dma_controller_create(musb, musb->mregs);
1955 musb->dma_controller = c;
1960 /* ideally this would be abstracted in platform setup */
1961 if (!is_dma_capable() || !musb->dma_controller)
1962 dev->dma_mask = NULL;
1964 /* be sure interrupts are disabled before connecting ISR */
1965 musb_platform_disable(musb);
1966 musb_generic_disable(musb);
1968 /* setup musb parts of the core (especially endpoints) */
1969 status = musb_core_init(plat->config->multipoint
1970 ? MUSB_CONTROLLER_MHDRC
1971 : MUSB_CONTROLLER_HDRC, musb);
1975 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1977 /* Init IRQ workqueue before request_irq */
1978 INIT_WORK(&musb->irq_work, musb_irq_work);
1980 /* attach to the IRQ */
1981 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1982 dev_err(dev, "request_irq %d failed!\n", nIrq);
1987 /* FIXME this handles wakeup irqs wrong */
1988 if (enable_irq_wake(nIrq) == 0) {
1990 device_init_wakeup(dev, 1);
1995 /* host side needs more setup */
1996 hcd = musb_to_hcd(musb);
1997 otg_set_host(musb->xceiv->otg, &hcd->self);
1998 hcd->self.otg_port = 1;
1999 musb->xceiv->otg->host = &hcd->self;
2000 hcd->power_budget = 2 * (plat->power ? : 250);
2002 /* program PHY to use external vBus if required */
2003 if (plat->extvbus) {
2004 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2005 busctl |= MUSB_ULPI_USE_EXTVBUS;
2006 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2009 MUSB_DEV_MODE(musb);
2010 musb->xceiv->otg->default_a = 0;
2011 musb->xceiv->state = OTG_STATE_B_IDLE;
2013 status = musb_gadget_setup(musb);
2018 status = musb_init_debugfs(musb);
2023 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2028 pm_runtime_put(musb->controller);
2033 musb_exit_debugfs(musb);
2036 musb_gadget_cleanup(musb);
2039 pm_runtime_put_sync(musb->controller);
2043 device_init_wakeup(dev, 0);
2044 musb_platform_exit(musb);
2047 dev_err(musb->controller,
2048 "musb_init_controller failed with status %d\n", status);
2058 /*-------------------------------------------------------------------------*/
2060 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2061 * bridge to a platform device; this driver then suffices.
2063 static int __devinit musb_probe(struct platform_device *pdev)
2065 struct device *dev = &pdev->dev;
2066 int irq = platform_get_irq_byname(pdev, "mc");
2068 struct resource *iomem;
2071 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2072 if (!iomem || irq <= 0)
2075 base = ioremap(iomem->start, resource_size(iomem));
2077 dev_err(dev, "ioremap failed\n");
2081 status = musb_init_controller(dev, irq, base);
2088 static int __devexit musb_remove(struct platform_device *pdev)
2090 struct device *dev = &pdev->dev;
2091 struct musb *musb = dev_to_musb(dev);
2092 void __iomem *ctrl_base = musb->ctrl_base;
2094 /* this gets called on rmmod.
2095 * - Host mode: host may still be active
2096 * - Peripheral mode: peripheral is deactivated (or never-activated)
2097 * - OTG mode: both roles are deactivated (or never-activated)
2099 musb_exit_debugfs(musb);
2100 musb_shutdown(pdev);
2104 device_init_wakeup(dev, 0);
2105 #ifndef CONFIG_MUSB_PIO_ONLY
2106 dma_set_mask(dev, *dev->parent->dma_mask);
2113 static void musb_save_context(struct musb *musb)
2116 void __iomem *musb_base = musb->mregs;
2119 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2120 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2121 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2122 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2123 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2124 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2125 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2126 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2127 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2129 for (i = 0; i < musb->config->num_eps; ++i) {
2130 struct musb_hw_ep *hw_ep;
2132 hw_ep = &musb->endpoints[i];
2140 musb_writeb(musb_base, MUSB_INDEX, i);
2141 musb->context.index_regs[i].txmaxp =
2142 musb_readw(epio, MUSB_TXMAXP);
2143 musb->context.index_regs[i].txcsr =
2144 musb_readw(epio, MUSB_TXCSR);
2145 musb->context.index_regs[i].rxmaxp =
2146 musb_readw(epio, MUSB_RXMAXP);
2147 musb->context.index_regs[i].rxcsr =
2148 musb_readw(epio, MUSB_RXCSR);
2150 if (musb->dyn_fifo) {
2151 musb->context.index_regs[i].txfifoadd =
2152 musb_read_txfifoadd(musb_base);
2153 musb->context.index_regs[i].rxfifoadd =
2154 musb_read_rxfifoadd(musb_base);
2155 musb->context.index_regs[i].txfifosz =
2156 musb_read_txfifosz(musb_base);
2157 musb->context.index_regs[i].rxfifosz =
2158 musb_read_rxfifosz(musb_base);
2161 musb->context.index_regs[i].txtype =
2162 musb_readb(epio, MUSB_TXTYPE);
2163 musb->context.index_regs[i].txinterval =
2164 musb_readb(epio, MUSB_TXINTERVAL);
2165 musb->context.index_regs[i].rxtype =
2166 musb_readb(epio, MUSB_RXTYPE);
2167 musb->context.index_regs[i].rxinterval =
2168 musb_readb(epio, MUSB_RXINTERVAL);
2170 musb->context.index_regs[i].txfunaddr =
2171 musb_read_txfunaddr(musb_base, i);
2172 musb->context.index_regs[i].txhubaddr =
2173 musb_read_txhubaddr(musb_base, i);
2174 musb->context.index_regs[i].txhubport =
2175 musb_read_txhubport(musb_base, i);
2177 musb->context.index_regs[i].rxfunaddr =
2178 musb_read_rxfunaddr(musb_base, i);
2179 musb->context.index_regs[i].rxhubaddr =
2180 musb_read_rxhubaddr(musb_base, i);
2181 musb->context.index_regs[i].rxhubport =
2182 musb_read_rxhubport(musb_base, i);
2186 static void musb_restore_context(struct musb *musb)
2189 void __iomem *musb_base = musb->mregs;
2190 void __iomem *ep_target_regs;
2193 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2194 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2195 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2196 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2197 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2198 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2199 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2200 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2202 for (i = 0; i < musb->config->num_eps; ++i) {
2203 struct musb_hw_ep *hw_ep;
2205 hw_ep = &musb->endpoints[i];
2213 musb_writeb(musb_base, MUSB_INDEX, i);
2214 musb_writew(epio, MUSB_TXMAXP,
2215 musb->context.index_regs[i].txmaxp);
2216 musb_writew(epio, MUSB_TXCSR,
2217 musb->context.index_regs[i].txcsr);
2218 musb_writew(epio, MUSB_RXMAXP,
2219 musb->context.index_regs[i].rxmaxp);
2220 musb_writew(epio, MUSB_RXCSR,
2221 musb->context.index_regs[i].rxcsr);
2223 if (musb->dyn_fifo) {
2224 musb_write_txfifosz(musb_base,
2225 musb->context.index_regs[i].txfifosz);
2226 musb_write_rxfifosz(musb_base,
2227 musb->context.index_regs[i].rxfifosz);
2228 musb_write_txfifoadd(musb_base,
2229 musb->context.index_regs[i].txfifoadd);
2230 musb_write_rxfifoadd(musb_base,
2231 musb->context.index_regs[i].rxfifoadd);
2234 musb_writeb(epio, MUSB_TXTYPE,
2235 musb->context.index_regs[i].txtype);
2236 musb_writeb(epio, MUSB_TXINTERVAL,
2237 musb->context.index_regs[i].txinterval);
2238 musb_writeb(epio, MUSB_RXTYPE,
2239 musb->context.index_regs[i].rxtype);
2240 musb_writeb(epio, MUSB_RXINTERVAL,
2242 musb->context.index_regs[i].rxinterval);
2243 musb_write_txfunaddr(musb_base, i,
2244 musb->context.index_regs[i].txfunaddr);
2245 musb_write_txhubaddr(musb_base, i,
2246 musb->context.index_regs[i].txhubaddr);
2247 musb_write_txhubport(musb_base, i,
2248 musb->context.index_regs[i].txhubport);
2251 musb_read_target_reg_base(i, musb_base);
2253 musb_write_rxfunaddr(ep_target_regs,
2254 musb->context.index_regs[i].rxfunaddr);
2255 musb_write_rxhubaddr(ep_target_regs,
2256 musb->context.index_regs[i].rxhubaddr);
2257 musb_write_rxhubport(ep_target_regs,
2258 musb->context.index_regs[i].rxhubport);
2260 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2263 static int musb_suspend(struct device *dev)
2265 struct musb *musb = dev_to_musb(dev);
2266 unsigned long flags;
2268 spin_lock_irqsave(&musb->lock, flags);
2270 if (is_peripheral_active(musb)) {
2271 /* FIXME force disconnect unless we know USB will wake
2272 * the system up quickly enough to respond ...
2274 } else if (is_host_active(musb)) {
2275 /* we know all the children are suspended; sometimes
2276 * they will even be wakeup-enabled.
2280 spin_unlock_irqrestore(&musb->lock, flags);
2284 static int musb_resume_noirq(struct device *dev)
2286 /* for static cmos like DaVinci, register values were preserved
2287 * unless for some reason the whole soc powered down or the USB
2288 * module got reset through the PSC (vs just being disabled).
2293 static int musb_runtime_suspend(struct device *dev)
2295 struct musb *musb = dev_to_musb(dev);
2297 musb_save_context(musb);
2302 static int musb_runtime_resume(struct device *dev)
2304 struct musb *musb = dev_to_musb(dev);
2305 static int first = 1;
2308 * When pm_runtime_get_sync called for the first time in driver
2309 * init, some of the structure is still not initialized which is
2310 * used in restore function. But clock needs to be
2311 * enabled before any register access, so
2312 * pm_runtime_get_sync has to be called.
2313 * Also context restore without save does not make
2317 musb_restore_context(musb);
2323 static const struct dev_pm_ops musb_dev_pm_ops = {
2324 .suspend = musb_suspend,
2325 .resume_noirq = musb_resume_noirq,
2326 .runtime_suspend = musb_runtime_suspend,
2327 .runtime_resume = musb_runtime_resume,
2330 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2332 #define MUSB_DEV_PM_OPS NULL
2335 static struct platform_driver musb_driver = {
2337 .name = (char *)musb_driver_name,
2338 .bus = &platform_bus_type,
2339 .owner = THIS_MODULE,
2340 .pm = MUSB_DEV_PM_OPS,
2342 .probe = musb_probe,
2343 .remove = __devexit_p(musb_remove),
2344 .shutdown = musb_shutdown,
2347 /*-------------------------------------------------------------------------*/
2349 static int __init musb_init(void)
2354 pr_info("%s: version " MUSB_VERSION ", "
2357 "otg (peripheral+host)",
2359 return platform_driver_register(&musb_driver);
2361 module_init(musb_init);
2363 static void __exit musb_cleanup(void)
2365 platform_driver_unregister(&musb_driver);
2367 module_exit(musb_cleanup);