1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver core code
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
43 * RESULT: one device may be perceived as blocking another one.
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
60 * - platform_device for addressing, irq, and platform_data
61 * - platform_data is mostly for board-specific information
62 * (plus recentrly, SOC or family details)
64 * Most of the conditional compilation will (someday) vanish.
67 #include <linux/module.h>
68 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/slab.h>
71 #include <linux/list.h>
72 #include <linux/kobject.h>
73 #include <linux/prefetch.h>
74 #include <linux/platform_device.h>
76 #include <linux/iopoll.h>
77 #include <linux/dma-mapping.h>
78 #include <linux/usb.h>
79 #include <linux/usb/of.h>
81 #include "musb_core.h"
82 #include "musb_trace.h"
84 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
87 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
88 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
90 #define MUSB_VERSION "6.0"
92 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
94 #define MUSB_DRIVER_NAME "musb-hdrc"
95 const char musb_driver_name[] = MUSB_DRIVER_NAME;
97 MODULE_DESCRIPTION(DRIVER_INFO);
98 MODULE_AUTHOR(DRIVER_AUTHOR);
99 MODULE_LICENSE("GPL");
100 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
103 /*-------------------------------------------------------------------------*/
105 static inline struct musb *dev_to_musb(struct device *dev)
107 return dev_get_drvdata(dev);
110 enum musb_mode musb_get_mode(struct device *dev)
112 enum usb_dr_mode mode;
114 mode = usb_get_dr_mode(dev);
116 case USB_DR_MODE_HOST:
118 case USB_DR_MODE_PERIPHERAL:
119 return MUSB_PERIPHERAL;
120 case USB_DR_MODE_OTG:
121 case USB_DR_MODE_UNKNOWN:
126 EXPORT_SYMBOL_GPL(musb_get_mode);
128 /*-------------------------------------------------------------------------*/
130 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
132 void __iomem *addr = phy->io_priv;
138 pm_runtime_get_sync(phy->io_dev);
140 /* Make sure the transceiver is not in low power mode */
141 power = musb_readb(addr, MUSB_POWER);
142 power &= ~MUSB_POWER_SUSPENDM;
143 musb_writeb(addr, MUSB_POWER, power);
145 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
146 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
149 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
150 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
151 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
153 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
154 & MUSB_ULPI_REG_CMPLT)) {
162 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
163 r &= ~MUSB_ULPI_REG_CMPLT;
164 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
166 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
169 pm_runtime_put(phy->io_dev);
174 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
176 void __iomem *addr = phy->io_priv;
182 pm_runtime_get_sync(phy->io_dev);
184 /* Make sure the transceiver is not in low power mode */
185 power = musb_readb(addr, MUSB_POWER);
186 power &= ~MUSB_POWER_SUSPENDM;
187 musb_writeb(addr, MUSB_POWER, power);
189 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
190 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
191 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
193 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
194 & MUSB_ULPI_REG_CMPLT)) {
202 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
203 r &= ~MUSB_ULPI_REG_CMPLT;
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
207 pm_runtime_put(phy->io_dev);
212 static struct usb_phy_io_ops musb_ulpi_access = {
213 .read = musb_ulpi_read,
214 .write = musb_ulpi_write,
217 /*-------------------------------------------------------------------------*/
219 static u32 musb_default_fifo_offset(u8 epnum)
221 return 0x20 + (epnum * 4);
224 /* "flat" mapping: each endpoint has its own i/o address */
225 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
229 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
231 return 0x100 + (0x10 * epnum) + offset;
234 /* "indexed" mapping: INDEX register controls register bank select */
235 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
237 musb_writeb(mbase, MUSB_INDEX, epnum);
240 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
242 return 0x10 + offset;
245 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
247 return 0x80 + (0x08 * epnum) + offset;
250 static u8 musb_default_readb(void __iomem *addr, u32 offset)
252 u8 data = __raw_readb(addr + offset);
254 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
258 static void musb_default_writeb(void __iomem *addr, u32 offset, u8 data)
260 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
261 __raw_writeb(data, addr + offset);
264 static u16 musb_default_readw(void __iomem *addr, u32 offset)
266 u16 data = __raw_readw(addr + offset);
268 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
272 static void musb_default_writew(void __iomem *addr, u32 offset, u16 data)
274 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
275 __raw_writew(data, addr + offset);
278 static u16 musb_default_get_toggle(struct musb_qh *qh, int is_out)
280 void __iomem *epio = qh->hw_ep->regs;
284 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
286 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
291 static u16 musb_default_set_toggle(struct musb_qh *qh, int is_out,
297 toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
300 csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE
301 | MUSB_TXCSR_H_DATATOGGLE)
302 : MUSB_TXCSR_CLRDATATOG;
304 csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE
305 | MUSB_RXCSR_H_DATATOGGLE) : 0;
311 * Load an endpoint's FIFO
313 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
316 struct musb *musb = hw_ep->musb;
317 void __iomem *fifo = hw_ep->fifo;
319 if (unlikely(len == 0))
324 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
325 'T', hw_ep->epnum, fifo, len, src);
327 /* we can't assume unaligned reads work */
328 if (likely((0x01 & (unsigned long) src) == 0)) {
331 /* best case is 32bit-aligned source address */
332 if ((0x02 & (unsigned long) src) == 0) {
334 iowrite32_rep(fifo, src + index, len >> 2);
335 index += len & ~0x03;
338 __raw_writew(*(u16 *)&src[index], fifo);
343 iowrite16_rep(fifo, src + index, len >> 1);
344 index += len & ~0x01;
348 __raw_writeb(src[index], fifo);
351 iowrite8_rep(fifo, src, len);
356 * Unload an endpoint's FIFO
358 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
360 struct musb *musb = hw_ep->musb;
361 void __iomem *fifo = hw_ep->fifo;
363 if (unlikely(len == 0))
366 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
367 'R', hw_ep->epnum, fifo, len, dst);
369 /* we can't assume unaligned writes work */
370 if (likely((0x01 & (unsigned long) dst) == 0)) {
373 /* best case is 32bit-aligned destination address */
374 if ((0x02 & (unsigned long) dst) == 0) {
376 ioread32_rep(fifo, dst, len >> 2);
380 *(u16 *)&dst[index] = __raw_readw(fifo);
385 ioread16_rep(fifo, dst, len >> 1);
390 dst[index] = __raw_readb(fifo);
393 ioread8_rep(fifo, dst, len);
398 * Old style IO functions
400 u8 (*musb_readb)(void __iomem *addr, u32 offset);
401 EXPORT_SYMBOL_GPL(musb_readb);
403 void (*musb_writeb)(void __iomem *addr, u32 offset, u8 data);
404 EXPORT_SYMBOL_GPL(musb_writeb);
406 u8 (*musb_clearb)(void __iomem *addr, u32 offset);
407 EXPORT_SYMBOL_GPL(musb_clearb);
409 u16 (*musb_readw)(void __iomem *addr, u32 offset);
410 EXPORT_SYMBOL_GPL(musb_readw);
412 void (*musb_writew)(void __iomem *addr, u32 offset, u16 data);
413 EXPORT_SYMBOL_GPL(musb_writew);
415 u16 (*musb_clearw)(void __iomem *addr, u32 offset);
416 EXPORT_SYMBOL_GPL(musb_clearw);
418 u32 musb_readl(void __iomem *addr, u32 offset)
420 u32 data = __raw_readl(addr + offset);
422 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
425 EXPORT_SYMBOL_GPL(musb_readl);
427 void musb_writel(void __iomem *addr, u32 offset, u32 data)
429 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
430 __raw_writel(data, addr + offset);
432 EXPORT_SYMBOL_GPL(musb_writel);
434 #ifndef CONFIG_MUSB_PIO_ONLY
435 struct dma_controller *
436 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
437 EXPORT_SYMBOL(musb_dma_controller_create);
439 void (*musb_dma_controller_destroy)(struct dma_controller *c);
440 EXPORT_SYMBOL(musb_dma_controller_destroy);
444 * New style IO functions
446 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
448 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
451 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
453 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
456 static u8 musb_read_devctl(struct musb *musb)
458 return musb_readb(musb->mregs, MUSB_DEVCTL);
462 * musb_set_host - set and initialize host mode
463 * @musb: musb controller driver data
465 * At least some musb revisions need to enable devctl session bit in
466 * peripheral mode to switch to host mode. Initializes things to host
467 * mode and sets A_IDLE. SoC glue needs to advance state further
468 * based on phy provided VBUS state.
470 * Note that the SoC glue code may need to wait for musb to settle
471 * on enable before calling this to avoid babble.
473 int musb_set_host(struct musb *musb)
481 devctl = musb_read_devctl(musb);
482 if (!(devctl & MUSB_DEVCTL_BDEVICE)) {
483 trace_musb_state(musb, devctl, "Already in host mode");
487 devctl |= MUSB_DEVCTL_SESSION;
488 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
490 error = readx_poll_timeout(musb_read_devctl, musb, devctl,
491 !(devctl & MUSB_DEVCTL_BDEVICE), 5000,
494 dev_err(musb->controller, "%s: could not set host: %02x\n",
500 devctl = musb_read_devctl(musb);
501 trace_musb_state(musb, devctl, "Host mode set");
505 musb_set_state(musb, OTG_STATE_A_IDLE);
510 EXPORT_SYMBOL_GPL(musb_set_host);
513 * musb_set_peripheral - set and initialize peripheral mode
514 * @musb: musb controller driver data
516 * Clears devctl session bit and initializes things for peripheral
517 * mode and sets B_IDLE. SoC glue needs to advance state further
518 * based on phy provided VBUS state.
520 int musb_set_peripheral(struct musb *musb)
528 devctl = musb_read_devctl(musb);
529 if (devctl & MUSB_DEVCTL_BDEVICE) {
530 trace_musb_state(musb, devctl, "Already in peripheral mode");
534 devctl &= ~MUSB_DEVCTL_SESSION;
535 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
537 error = readx_poll_timeout(musb_read_devctl, musb, devctl,
538 devctl & MUSB_DEVCTL_BDEVICE, 5000,
541 dev_err(musb->controller, "%s: could not set peripheral: %02x\n",
547 devctl = musb_read_devctl(musb);
548 trace_musb_state(musb, devctl, "Peripheral mode set");
552 musb_set_state(musb, OTG_STATE_B_IDLE);
557 EXPORT_SYMBOL_GPL(musb_set_peripheral);
559 /*-------------------------------------------------------------------------*/
561 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
562 static const u8 musb_test_packet[53] = {
563 /* implicit SYNC then DATA0 to start */
566 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
568 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
570 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
571 /* JJJJJJJKKKKKKK x8 */
572 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
574 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
575 /* JKKKKKKK x10, JK */
576 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
578 /* implicit CRC16 then EOP to end */
581 void musb_load_testpacket(struct musb *musb)
583 void __iomem *regs = musb->endpoints[0].regs;
585 musb_ep_select(musb->mregs, 0);
586 musb_write_fifo(musb->control_ep,
587 sizeof(musb_test_packet), musb_test_packet);
588 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
591 /*-------------------------------------------------------------------------*/
594 * Handles OTG hnp timeouts, such as b_ase0_brst
596 static void musb_otg_timer_func(struct timer_list *t)
598 struct musb *musb = from_timer(musb, t, otg_timer);
601 spin_lock_irqsave(&musb->lock, flags);
602 switch (musb_get_state(musb)) {
603 case OTG_STATE_B_WAIT_ACON:
605 "HNP: b_wait_acon timeout; back to b_peripheral");
606 musb_g_disconnect(musb);
607 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
610 case OTG_STATE_A_SUSPEND:
611 case OTG_STATE_A_WAIT_BCON:
612 musb_dbg(musb, "HNP: %s timeout",
613 musb_otg_state_string(musb));
614 musb_platform_set_vbus(musb, 0);
615 musb_set_state(musb, OTG_STATE_A_WAIT_VFALL);
618 musb_dbg(musb, "HNP: Unhandled mode %s",
619 musb_otg_state_string(musb));
621 spin_unlock_irqrestore(&musb->lock, flags);
625 * Stops the HNP transition. Caller must take care of locking.
627 void musb_hnp_stop(struct musb *musb)
629 struct usb_hcd *hcd = musb->hcd;
630 void __iomem *mbase = musb->mregs;
633 musb_dbg(musb, "HNP: stop from %s", musb_otg_state_string(musb));
635 switch (musb_get_state(musb)) {
636 case OTG_STATE_A_PERIPHERAL:
637 musb_g_disconnect(musb);
638 musb_dbg(musb, "HNP: back to %s", musb_otg_state_string(musb));
640 case OTG_STATE_B_HOST:
641 musb_dbg(musb, "HNP: Disabling HR");
643 hcd->self.is_b_host = 0;
644 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
646 reg = musb_readb(mbase, MUSB_POWER);
647 reg |= MUSB_POWER_SUSPENDM;
648 musb_writeb(mbase, MUSB_POWER, reg);
649 /* REVISIT: Start SESSION_REQUEST here? */
652 musb_dbg(musb, "HNP: Stopping in unknown state %s",
653 musb_otg_state_string(musb));
657 * When returning to A state after HNP, avoid hub_port_rebounce(),
658 * which cause occasional OPT A "Did not receive reset after connect"
661 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
664 static void musb_recover_from_babble(struct musb *musb);
666 static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
668 musb_dbg(musb, "RESUME (%s)", musb_otg_state_string(musb));
670 if (devctl & MUSB_DEVCTL_HM) {
671 switch (musb_get_state(musb)) {
672 case OTG_STATE_A_SUSPEND:
674 musb->port1_status |=
675 (USB_PORT_STAT_C_SUSPEND << 16)
676 | MUSB_PORT_STAT_RESUME;
677 musb->rh_timer = jiffies
678 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
679 musb_set_state(musb, OTG_STATE_A_HOST);
681 musb_host_resume_root_hub(musb);
682 schedule_delayed_work(&musb->finish_resume_work,
683 msecs_to_jiffies(USB_RESUME_TIMEOUT));
685 case OTG_STATE_B_WAIT_ACON:
686 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
691 WARNING("bogus %s RESUME (%s)\n",
693 musb_otg_state_string(musb));
696 switch (musb_get_state(musb)) {
697 case OTG_STATE_A_SUSPEND:
698 /* possibly DISCONNECT is upcoming */
699 musb_set_state(musb, OTG_STATE_A_HOST);
700 musb_host_resume_root_hub(musb);
702 case OTG_STATE_B_WAIT_ACON:
703 case OTG_STATE_B_PERIPHERAL:
704 /* disconnect while suspended? we may
705 * not get a disconnect irq...
707 if ((devctl & MUSB_DEVCTL_VBUS)
708 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
710 musb->int_usb |= MUSB_INTR_DISCONNECT;
711 musb->int_usb &= ~MUSB_INTR_SUSPEND;
716 case OTG_STATE_B_IDLE:
717 musb->int_usb &= ~MUSB_INTR_SUSPEND;
720 WARNING("bogus %s RESUME (%s)\n",
722 musb_otg_state_string(musb));
727 /* return IRQ_HANDLED to tell the caller to return immediately */
728 static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
730 void __iomem *mbase = musb->mregs;
732 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
733 && (devctl & MUSB_DEVCTL_BDEVICE)) {
734 musb_dbg(musb, "SessReq while on B state");
738 musb_dbg(musb, "SESSION_REQUEST (%s)", musb_otg_state_string(musb));
740 /* IRQ arrives from ID pin sense or (later, if VBUS power
741 * is removed) SRP. responses are time critical:
742 * - turn on VBUS (with silicon-specific mechanism)
743 * - go through A_WAIT_VRISE
744 * - ... to A_WAIT_BCON.
745 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
747 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
748 musb->ep0_stage = MUSB_EP0_START;
749 musb_set_state(musb, OTG_STATE_A_IDLE);
751 musb_platform_set_vbus(musb, 1);
756 static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
760 /* During connection as an A-Device, we may see a short
761 * current spikes causing voltage drop, because of cable
762 * and peripheral capacitance combined with vbus draw.
763 * (So: less common with truly self-powered devices, where
764 * vbus doesn't act like a power supply.)
766 * Such spikes are short; usually less than ~500 usec, max
767 * of ~2 msec. That is, they're not sustained overcurrent
768 * errors, though they're reported using VBUSERROR irqs.
770 * Workarounds: (a) hardware: use self powered devices.
771 * (b) software: ignore non-repeated VBUS errors.
773 * REVISIT: do delays from lots of DEBUG_KERNEL checks
774 * make trouble here, keeping VBUS < 4.4V ?
776 switch (musb_get_state(musb)) {
777 case OTG_STATE_A_HOST:
778 /* recovery is dicey once we've gotten past the
779 * initial stages of enumeration, but if VBUS
780 * stayed ok at the other end of the link, and
781 * another reset is due (at least for high speed,
782 * to redo the chirp etc), it might work OK...
784 case OTG_STATE_A_WAIT_BCON:
785 case OTG_STATE_A_WAIT_VRISE:
786 if (musb->vbuserr_retry) {
787 void __iomem *mbase = musb->mregs;
789 musb->vbuserr_retry--;
791 devctl |= MUSB_DEVCTL_SESSION;
792 musb_writeb(mbase, MUSB_DEVCTL, devctl);
794 musb->port1_status |=
795 USB_PORT_STAT_OVERCURRENT
796 | (USB_PORT_STAT_C_OVERCURRENT << 16);
803 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
804 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
805 musb_otg_state_string(musb),
808 switch (devctl & MUSB_DEVCTL_VBUS) {
809 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
810 s = "<SessEnd"; break;
811 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
812 s = "<AValid"; break;
813 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
814 s = "<VBusValid"; break;
815 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
819 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
822 /* go through A_WAIT_VFALL then start a new session */
824 musb_platform_set_vbus(musb, 0);
827 static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
829 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
830 musb_otg_state_string(musb), devctl);
832 switch (musb_get_state(musb)) {
833 case OTG_STATE_A_PERIPHERAL:
834 /* We also come here if the cable is removed, since
835 * this silicon doesn't report ID-no-longer-grounded.
837 * We depend on T(a_wait_bcon) to shut us down, and
838 * hope users don't do anything dicey during this
839 * undesired detour through A_WAIT_BCON.
842 musb_host_resume_root_hub(musb);
843 musb_root_disconnect(musb);
844 musb_platform_try_idle(musb, jiffies
845 + msecs_to_jiffies(musb->a_wait_bcon
846 ? : OTG_TIME_A_WAIT_BCON));
849 case OTG_STATE_B_IDLE:
850 if (!musb->is_active)
853 case OTG_STATE_B_PERIPHERAL:
854 musb_g_suspend(musb);
855 musb->is_active = musb->g.b_hnp_enable;
856 if (musb->is_active) {
857 musb_set_state(musb, OTG_STATE_B_WAIT_ACON);
858 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
859 mod_timer(&musb->otg_timer, jiffies
861 OTG_TIME_B_ASE0_BRST));
864 case OTG_STATE_A_WAIT_BCON:
865 if (musb->a_wait_bcon != 0)
866 musb_platform_try_idle(musb, jiffies
867 + msecs_to_jiffies(musb->a_wait_bcon));
869 case OTG_STATE_A_HOST:
870 musb_set_state(musb, OTG_STATE_A_SUSPEND);
871 musb->is_active = musb->hcd->self.b_hnp_enable;
873 case OTG_STATE_B_HOST:
874 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
875 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
878 /* "should not happen" */
884 static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
886 struct usb_hcd *hcd = musb->hcd;
889 musb->ep0_stage = MUSB_EP0_START;
891 musb->intrtxe = musb->epmask;
892 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
893 musb->intrrxe = musb->epmask & 0xfffe;
894 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
895 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
896 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
897 |USB_PORT_STAT_HIGH_SPEED
898 |USB_PORT_STAT_ENABLE
900 musb->port1_status |= USB_PORT_STAT_CONNECTION
901 |(USB_PORT_STAT_C_CONNECTION << 16);
903 /* high vs full speed is just a guess until after reset */
904 if (devctl & MUSB_DEVCTL_LSDEV)
905 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
907 /* indicate new connection to OTG machine */
908 switch (musb_get_state(musb)) {
909 case OTG_STATE_B_PERIPHERAL:
910 if (int_usb & MUSB_INTR_SUSPEND) {
911 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
912 int_usb &= ~MUSB_INTR_SUSPEND;
915 musb_dbg(musb, "CONNECT as b_peripheral???");
917 case OTG_STATE_B_WAIT_ACON:
918 musb_dbg(musb, "HNP: CONNECT, now b_host");
920 musb_set_state(musb, OTG_STATE_B_HOST);
922 musb->hcd->self.is_b_host = 1;
923 del_timer(&musb->otg_timer);
926 if ((devctl & MUSB_DEVCTL_VBUS)
927 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
928 musb_set_state(musb, OTG_STATE_A_HOST);
930 hcd->self.is_b_host = 0;
935 musb_host_poke_root_hub(musb);
937 musb_dbg(musb, "CONNECT (%s) devctl %02x",
938 musb_otg_state_string(musb), devctl);
941 static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
943 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
944 musb_otg_state_string(musb),
945 MUSB_MODE(musb), devctl);
947 switch (musb_get_state(musb)) {
948 case OTG_STATE_A_HOST:
949 case OTG_STATE_A_SUSPEND:
950 musb_host_resume_root_hub(musb);
951 musb_root_disconnect(musb);
952 if (musb->a_wait_bcon != 0)
953 musb_platform_try_idle(musb, jiffies
954 + msecs_to_jiffies(musb->a_wait_bcon));
956 case OTG_STATE_B_HOST:
957 /* REVISIT this behaves for "real disconnect"
958 * cases; make sure the other transitions from
959 * from B_HOST act right too. The B_HOST code
960 * in hnp_stop() is currently not used...
962 musb_root_disconnect(musb);
964 musb->hcd->self.is_b_host = 0;
965 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
967 musb_g_disconnect(musb);
969 case OTG_STATE_A_PERIPHERAL:
971 musb_root_disconnect(musb);
973 case OTG_STATE_B_WAIT_ACON:
974 case OTG_STATE_B_PERIPHERAL:
975 case OTG_STATE_B_IDLE:
976 musb_g_disconnect(musb);
979 WARNING("unhandled DISCONNECT transition (%s)\n",
980 musb_otg_state_string(musb));
986 * mentor saves a bit: bus reset and babble share the same irq.
987 * only host sees babble; only peripheral sees bus reset.
989 static void musb_handle_intr_reset(struct musb *musb)
991 if (is_host_active(musb)) {
993 * When BABBLE happens what we can depends on which
994 * platform MUSB is running, because some platforms
995 * implemented proprietary means for 'recovering' from
996 * Babble conditions. One such platform is AM335x. In
997 * most cases, however, the only thing we can do is
1000 dev_err(musb->controller, "Babble\n");
1001 musb_recover_from_babble(musb);
1003 musb_dbg(musb, "BUS RESET as %s", musb_otg_state_string(musb));
1004 switch (musb_get_state(musb)) {
1005 case OTG_STATE_A_SUSPEND:
1008 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
1009 /* never use invalid T(a_wait_bcon) */
1010 musb_dbg(musb, "HNP: in %s, %d msec timeout",
1011 musb_otg_state_string(musb),
1012 TA_WAIT_BCON(musb));
1013 mod_timer(&musb->otg_timer, jiffies
1014 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
1016 case OTG_STATE_A_PERIPHERAL:
1017 del_timer(&musb->otg_timer);
1020 case OTG_STATE_B_WAIT_ACON:
1021 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
1022 musb_otg_state_string(musb));
1023 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
1026 case OTG_STATE_B_IDLE:
1027 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
1029 case OTG_STATE_B_PERIPHERAL:
1033 musb_dbg(musb, "Unhandled BUS RESET as %s",
1034 musb_otg_state_string(musb));
1040 * Interrupt Service Routine to record USB "global" interrupts.
1041 * Since these do not happen often and signify things of
1042 * paramount importance, it seems OK to check them individually;
1043 * the order of the tests is specified in the manual
1045 * @param musb instance pointer
1046 * @param int_usb register contents
1050 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
1053 irqreturn_t handled = IRQ_NONE;
1055 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
1057 /* in host mode, the peripheral may issue remote wakeup.
1058 * in peripheral mode, the host may resume the link.
1059 * spurious RESUME irqs happen too, paired with SUSPEND.
1061 if (int_usb & MUSB_INTR_RESUME) {
1062 musb_handle_intr_resume(musb, devctl);
1063 handled = IRQ_HANDLED;
1066 /* see manual for the order of the tests */
1067 if (int_usb & MUSB_INTR_SESSREQ) {
1068 if (musb_handle_intr_sessreq(musb, devctl))
1070 handled = IRQ_HANDLED;
1073 if (int_usb & MUSB_INTR_VBUSERROR) {
1074 musb_handle_intr_vbuserr(musb, devctl);
1075 handled = IRQ_HANDLED;
1078 if (int_usb & MUSB_INTR_SUSPEND) {
1079 musb_handle_intr_suspend(musb, devctl);
1080 handled = IRQ_HANDLED;
1083 if (int_usb & MUSB_INTR_CONNECT) {
1084 musb_handle_intr_connect(musb, devctl, int_usb);
1085 handled = IRQ_HANDLED;
1088 if (int_usb & MUSB_INTR_DISCONNECT) {
1089 musb_handle_intr_disconnect(musb, devctl);
1090 handled = IRQ_HANDLED;
1093 if (int_usb & MUSB_INTR_RESET) {
1094 musb_handle_intr_reset(musb);
1095 handled = IRQ_HANDLED;
1099 /* REVISIT ... this would be for multiplexing periodic endpoints, or
1100 * supporting transfer phasing to prevent exceeding ISO bandwidth
1101 * limits of a given frame or microframe.
1103 * It's not needed for peripheral side, which dedicates endpoints;
1104 * though it _might_ use SOF irqs for other purposes.
1106 * And it's not currently needed for host side, which also dedicates
1107 * endpoints, relies on TX/RX interval registers, and isn't claimed
1108 * to support ISO transfers yet.
1110 if (int_usb & MUSB_INTR_SOF) {
1111 void __iomem *mbase = musb->mregs;
1112 struct musb_hw_ep *ep;
1116 dev_dbg(musb->controller, "START_OF_FRAME\n");
1117 handled = IRQ_HANDLED;
1119 /* start any periodic Tx transfers waiting for current frame */
1120 frame = musb_readw(mbase, MUSB_FRAME);
1121 ep = musb->endpoints;
1122 for (epnum = 1; (epnum < musb->nr_endpoints)
1123 && (musb->epmask >= (1 << epnum));
1126 * FIXME handle framecounter wraps (12 bits)
1127 * eliminate duplicated StartUrb logic
1129 if (ep->dwWaitFrame >= frame) {
1130 ep->dwWaitFrame = 0;
1131 pr_debug("SOF --> periodic TX%s on %d\n",
1132 ep->tx_channel ? " DMA" : "",
1134 if (!ep->tx_channel)
1135 musb_h_tx_start(musb, epnum);
1137 cppi_hostdma_start(musb, epnum);
1139 } /* end of for loop */
1143 schedule_delayed_work(&musb->irq_work, 0);
1148 /*-------------------------------------------------------------------------*/
1150 static void musb_disable_interrupts(struct musb *musb)
1152 void __iomem *mbase = musb->mregs;
1154 /* disable interrupts */
1155 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1157 musb_writew(mbase, MUSB_INTRTXE, 0);
1159 musb_writew(mbase, MUSB_INTRRXE, 0);
1161 /* flush pending interrupts */
1162 musb_clearb(mbase, MUSB_INTRUSB);
1163 musb_clearw(mbase, MUSB_INTRTX);
1164 musb_clearw(mbase, MUSB_INTRRX);
1167 static void musb_enable_interrupts(struct musb *musb)
1169 void __iomem *regs = musb->mregs;
1171 /* Set INT enable registers, enable interrupts */
1172 musb->intrtxe = musb->epmask;
1173 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1174 musb->intrrxe = musb->epmask & 0xfffe;
1175 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1176 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1181 * Program the HDRC to start (enable interrupts, dma, etc.).
1183 void musb_start(struct musb *musb)
1185 void __iomem *regs = musb->mregs;
1186 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1189 musb_dbg(musb, "<== devctl %02x", devctl);
1191 musb_enable_interrupts(musb);
1192 musb_writeb(regs, MUSB_TESTMODE, 0);
1194 power = MUSB_POWER_ISOUPDATE;
1196 * treating UNKNOWN as unspecified maximum speed, in which case
1197 * we will default to high-speed.
1199 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1200 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1201 power |= MUSB_POWER_HSENAB;
1202 musb_writeb(regs, MUSB_POWER, power);
1204 musb->is_active = 0;
1205 devctl = musb_readb(regs, MUSB_DEVCTL);
1206 devctl &= ~MUSB_DEVCTL_SESSION;
1208 /* session started after:
1209 * (a) ID-grounded irq, host mode;
1210 * (b) vbus present/connect IRQ, peripheral mode;
1211 * (c) peripheral initiates, using SRP
1213 if (musb->port_mode != MUSB_HOST &&
1214 musb_get_state(musb) != OTG_STATE_A_WAIT_BCON &&
1215 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1216 musb->is_active = 1;
1218 devctl |= MUSB_DEVCTL_SESSION;
1221 musb_platform_enable(musb);
1222 musb_writeb(regs, MUSB_DEVCTL, devctl);
1226 * Make the HDRC stop (disable interrupts, etc.);
1227 * reversible by musb_start
1228 * called on gadget driver unregister
1229 * with controller locked, irqs blocked
1230 * acts as a NOP unless some role activated the hardware
1232 void musb_stop(struct musb *musb)
1234 /* stop IRQs, timers, ... */
1235 musb_platform_disable(musb);
1236 musb_disable_interrupts(musb);
1237 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1240 * - mark host and/or peripheral drivers unusable/inactive
1241 * - disable DMA (and enable it in HdrcStart)
1242 * - make sure we can musb_start() after musb_stop(); with
1243 * OTG mode, gadget driver module rmmod/modprobe cycles that
1246 musb_platform_try_idle(musb, 0);
1249 /*-------------------------------------------------------------------------*/
1252 * The silicon either has hard-wired endpoint configurations, or else
1253 * "dynamic fifo" sizing. The driver has support for both, though at this
1254 * writing only the dynamic sizing is very well tested. Since we switched
1255 * away from compile-time hardware parameters, we can no longer rely on
1256 * dead code elimination to leave only the relevant one in the object file.
1258 * We don't currently use dynamic fifo setup capability to do anything
1259 * more than selecting one of a bunch of predefined configurations.
1261 static ushort fifo_mode;
1263 /* "modprobe ... fifo_mode=1" etc */
1264 module_param(fifo_mode, ushort, 0);
1265 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1268 * tables defining fifo_mode values. define more if you like.
1269 * for host side, make sure both halves of ep1 are set up.
1272 /* mode 0 - fits in 2KB */
1273 static struct musb_fifo_cfg mode_0_cfg[] = {
1274 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1275 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1276 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1277 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1278 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1281 /* mode 1 - fits in 4KB */
1282 static struct musb_fifo_cfg mode_1_cfg[] = {
1283 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1284 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1285 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1286 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1287 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1290 /* mode 2 - fits in 4KB */
1291 static struct musb_fifo_cfg mode_2_cfg[] = {
1292 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1293 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1294 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1295 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1296 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1297 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
1300 /* mode 3 - fits in 4KB */
1301 static struct musb_fifo_cfg mode_3_cfg[] = {
1302 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1303 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1304 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1305 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1306 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1307 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1310 /* mode 4 - fits in 16KB */
1311 static struct musb_fifo_cfg mode_4_cfg[] = {
1312 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1313 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1314 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1315 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1316 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1317 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1318 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1319 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1320 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1321 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1322 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1323 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1324 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1325 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1326 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1327 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1328 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1329 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1330 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1331 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1332 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1333 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1334 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1335 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1336 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1337 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1338 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1341 /* mode 5 - fits in 8KB */
1342 static struct musb_fifo_cfg mode_5_cfg[] = {
1343 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1344 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1345 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1346 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1347 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1348 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1349 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1350 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1351 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1352 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1353 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1354 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1355 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1356 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1357 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1358 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1359 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1360 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1361 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1362 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1363 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1364 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1365 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1366 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1367 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1368 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1369 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1373 * configure a fifo; for non-shared endpoints, this may be called
1374 * once for a tx fifo and once for an rx fifo.
1376 * returns negative errno or offset for next fifo.
1379 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1380 const struct musb_fifo_cfg *cfg, u16 offset)
1382 void __iomem *mbase = musb->mregs;
1384 u16 maxpacket = cfg->maxpacket;
1385 u16 c_off = offset >> 3;
1388 /* expect hw_ep has already been zero-initialized */
1390 size = ffs(max(maxpacket, (u16) 8)) - 1;
1391 maxpacket = 1 << size;
1394 if (cfg->mode == BUF_DOUBLE) {
1395 if ((offset + (maxpacket << 1)) >
1396 (1 << (musb->config->ram_bits + 2)))
1398 c_size |= MUSB_FIFOSZ_DPB;
1400 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1404 /* configure the FIFO */
1405 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1407 /* EP0 reserved endpoint for control, bidirectional;
1408 * EP1 reserved for bulk, two unidirectional halves.
1410 if (hw_ep->epnum == 1)
1411 musb->bulk_ep = hw_ep;
1412 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1413 switch (cfg->style) {
1415 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1416 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1417 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1418 hw_ep->max_packet_sz_tx = maxpacket;
1421 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1422 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1423 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1424 hw_ep->max_packet_sz_rx = maxpacket;
1427 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1428 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1429 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1430 hw_ep->max_packet_sz_rx = maxpacket;
1432 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1433 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1434 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1435 hw_ep->max_packet_sz_tx = maxpacket;
1437 hw_ep->is_shared_fifo = true;
1441 /* NOTE rx and tx endpoint irqs aren't managed separately,
1442 * which happens to be ok
1444 musb->epmask |= (1 << hw_ep->epnum);
1446 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1449 static struct musb_fifo_cfg ep0_cfg = {
1450 .style = FIFO_RXTX, .maxpacket = 64,
1453 static int ep_config_from_table(struct musb *musb)
1455 const struct musb_fifo_cfg *cfg;
1458 struct musb_hw_ep *hw_ep = musb->endpoints;
1460 if (musb->config->fifo_cfg) {
1461 cfg = musb->config->fifo_cfg;
1462 n = musb->config->fifo_cfg_size;
1466 switch (fifo_mode) {
1472 n = ARRAY_SIZE(mode_0_cfg);
1476 n = ARRAY_SIZE(mode_1_cfg);
1480 n = ARRAY_SIZE(mode_2_cfg);
1484 n = ARRAY_SIZE(mode_3_cfg);
1488 n = ARRAY_SIZE(mode_4_cfg);
1492 n = ARRAY_SIZE(mode_5_cfg);
1496 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1500 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1501 /* assert(offset > 0) */
1503 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1504 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1507 for (i = 0; i < n; i++) {
1508 u8 epn = cfg->hw_ep_num;
1510 if (epn >= musb->config->num_eps) {
1511 pr_debug("%s: invalid ep %d\n",
1512 musb_driver_name, epn);
1515 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1517 pr_debug("%s: mem overrun, ep %d\n",
1518 musb_driver_name, epn);
1522 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1525 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1527 n + 1, musb->config->num_eps * 2 - 1,
1528 offset, (1 << (musb->config->ram_bits + 2)));
1530 if (!musb->bulk_ep) {
1531 pr_debug("%s: missing bulk\n", musb_driver_name);
1540 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1541 * @param musb the controller
1543 static int ep_config_from_hw(struct musb *musb)
1546 struct musb_hw_ep *hw_ep;
1547 void __iomem *mbase = musb->mregs;
1550 musb_dbg(musb, "<== static silicon ep config");
1552 /* FIXME pick up ep0 maxpacket size */
1554 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1555 musb_ep_select(mbase, epnum);
1556 hw_ep = musb->endpoints + epnum;
1558 ret = musb_read_fifosize(musb, hw_ep, epnum);
1562 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1564 /* pick an RX/TX endpoint for bulk */
1565 if (hw_ep->max_packet_sz_tx < 512
1566 || hw_ep->max_packet_sz_rx < 512)
1569 /* REVISIT: this algorithm is lazy, we should at least
1570 * try to pick a double buffered endpoint.
1574 musb->bulk_ep = hw_ep;
1577 if (!musb->bulk_ep) {
1578 pr_debug("%s: missing bulk\n", musb_driver_name);
1585 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1587 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1588 * configure endpoints, or take their config from silicon
1590 static int musb_core_init(u16 musb_type, struct musb *musb)
1595 void __iomem *mbase = musb->mregs;
1599 /* log core options (read using indexed model) */
1600 reg = musb_read_configdata(mbase);
1602 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1603 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1604 strcat(aInfo, ", dyn FIFOs");
1605 musb->dyn_fifo = true;
1607 if (reg & MUSB_CONFIGDATA_MPRXE) {
1608 strcat(aInfo, ", bulk combine");
1609 musb->bulk_combine = true;
1611 if (reg & MUSB_CONFIGDATA_MPTXE) {
1612 strcat(aInfo, ", bulk split");
1613 musb->bulk_split = true;
1615 if (reg & MUSB_CONFIGDATA_HBRXE) {
1616 strcat(aInfo, ", HB-ISO Rx");
1617 musb->hb_iso_rx = true;
1619 if (reg & MUSB_CONFIGDATA_HBTXE) {
1620 strcat(aInfo, ", HB-ISO Tx");
1621 musb->hb_iso_tx = true;
1623 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1624 strcat(aInfo, ", SoftConn");
1626 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1628 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1629 musb->is_multipoint = 1;
1632 musb->is_multipoint = 0;
1634 if (IS_ENABLED(CONFIG_USB) &&
1635 !IS_ENABLED(CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB)) {
1636 pr_err("%s: kernel must disable external hubs, please fix the configuration\n",
1641 /* log release info */
1642 musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
1643 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1644 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1645 MUSB_HWVERS_MINOR(musb->hwvers),
1646 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1649 musb_configure_ep0(musb);
1651 /* discover endpoint configuration */
1652 musb->nr_endpoints = 1;
1656 status = ep_config_from_table(musb);
1658 status = ep_config_from_hw(musb);
1663 /* finish init, and print endpoint config */
1664 for (i = 0; i < musb->nr_endpoints; i++) {
1665 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1667 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1668 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1669 if (musb->ops->quirks & MUSB_IN_TUSB) {
1670 hw_ep->fifo_async = musb->async + 0x400 +
1671 musb->io.fifo_offset(i);
1672 hw_ep->fifo_sync = musb->sync + 0x400 +
1673 musb->io.fifo_offset(i);
1674 hw_ep->fifo_sync_va =
1675 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1678 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1680 hw_ep->conf = mbase + 0x400 +
1681 (((i - 1) & 0xf) << 2);
1685 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1686 hw_ep->rx_reinit = 1;
1687 hw_ep->tx_reinit = 1;
1689 if (hw_ep->max_packet_sz_tx) {
1690 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1691 musb_driver_name, i,
1692 hw_ep->is_shared_fifo ? "shared" : "tx",
1693 hw_ep->tx_double_buffered
1694 ? "doublebuffer, " : "",
1695 hw_ep->max_packet_sz_tx);
1697 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1698 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1699 musb_driver_name, i,
1701 hw_ep->rx_double_buffered
1702 ? "doublebuffer, " : "",
1703 hw_ep->max_packet_sz_rx);
1705 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1706 musb_dbg(musb, "hw_ep %d not configured", i);
1712 /*-------------------------------------------------------------------------*/
1715 * handle all the irqs defined by the HDRC core. for now we expect: other
1716 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1717 * will be assigned, and the irq will already have been acked.
1719 * called in irq context with spinlock held, irqs blocked
1721 irqreturn_t musb_interrupt(struct musb *musb)
1723 irqreturn_t retval = IRQ_NONE;
1724 unsigned long status;
1725 unsigned long epnum;
1728 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1731 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1733 trace_musb_isr(musb);
1736 * According to Mentor Graphics' documentation, flowchart on page 98,
1737 * IRQ should be handled as follows:
1740 * . Session Request IRQ
1745 * . Reset/Babble IRQ
1746 * . SOF IRQ (we're not using this one)
1751 * We will be following that flowchart in order to avoid any problems
1752 * that might arise with internal Finite State Machine.
1756 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1758 if (musb->int_tx & 1) {
1759 if (is_host_active(musb))
1760 retval |= musb_h_ep0_irq(musb);
1762 retval |= musb_g_ep0_irq(musb);
1764 /* we have just handled endpoint 0 IRQ, clear it */
1765 musb->int_tx &= ~BIT(0);
1768 status = musb->int_tx;
1770 for_each_set_bit(epnum, &status, 16) {
1771 retval = IRQ_HANDLED;
1772 if (is_host_active(musb))
1773 musb_host_tx(musb, epnum);
1775 musb_g_tx(musb, epnum);
1778 status = musb->int_rx;
1780 for_each_set_bit(epnum, &status, 16) {
1781 retval = IRQ_HANDLED;
1782 if (is_host_active(musb))
1783 musb_host_rx(musb, epnum);
1785 musb_g_rx(musb, epnum);
1790 EXPORT_SYMBOL_GPL(musb_interrupt);
1792 #ifndef CONFIG_MUSB_PIO_ONLY
1793 static bool use_dma = true;
1795 /* "modprobe ... use_dma=0" etc */
1796 module_param(use_dma, bool, 0644);
1797 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1799 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1801 /* called with controller lock already held */
1804 if (!is_cppi_enabled(musb)) {
1806 if (is_host_active(musb))
1807 musb_h_ep0_irq(musb);
1809 musb_g_ep0_irq(musb);
1812 /* endpoints 1..15 */
1814 if (is_host_active(musb))
1815 musb_host_tx(musb, epnum);
1817 musb_g_tx(musb, epnum);
1820 if (is_host_active(musb))
1821 musb_host_rx(musb, epnum);
1823 musb_g_rx(musb, epnum);
1827 EXPORT_SYMBOL_GPL(musb_dma_completion);
1833 static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1836 * musb_mailbox - optional phy notifier function
1837 * @status phy state change
1839 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1840 * disabled at the point the phy_callback is registered or unregistered.
1842 int musb_mailbox(enum musb_vbus_id_status status)
1844 if (musb_phy_callback)
1845 return musb_phy_callback(status);
1849 EXPORT_SYMBOL_GPL(musb_mailbox);
1851 /*-------------------------------------------------------------------------*/
1854 mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1856 struct musb *musb = dev_to_musb(dev);
1857 unsigned long flags;
1860 spin_lock_irqsave(&musb->lock, flags);
1861 ret = sprintf(buf, "%s\n", musb_otg_state_string(musb));
1862 spin_unlock_irqrestore(&musb->lock, flags);
1868 mode_store(struct device *dev, struct device_attribute *attr,
1869 const char *buf, size_t n)
1871 struct musb *musb = dev_to_musb(dev);
1872 unsigned long flags;
1875 spin_lock_irqsave(&musb->lock, flags);
1876 if (sysfs_streq(buf, "host"))
1877 status = musb_platform_set_mode(musb, MUSB_HOST);
1878 else if (sysfs_streq(buf, "peripheral"))
1879 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1880 else if (sysfs_streq(buf, "otg"))
1881 status = musb_platform_set_mode(musb, MUSB_OTG);
1884 spin_unlock_irqrestore(&musb->lock, flags);
1886 return (status == 0) ? n : status;
1888 static DEVICE_ATTR_RW(mode);
1891 vbus_store(struct device *dev, struct device_attribute *attr,
1892 const char *buf, size_t n)
1894 struct musb *musb = dev_to_musb(dev);
1895 unsigned long flags;
1898 if (sscanf(buf, "%lu", &val) < 1) {
1899 dev_err(dev, "Invalid VBUS timeout ms value\n");
1903 spin_lock_irqsave(&musb->lock, flags);
1904 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1905 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1906 if (musb_get_state(musb) == OTG_STATE_A_WAIT_BCON)
1907 musb->is_active = 0;
1908 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1909 spin_unlock_irqrestore(&musb->lock, flags);
1915 vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1917 struct musb *musb = dev_to_musb(dev);
1918 unsigned long flags;
1923 pm_runtime_get_sync(dev);
1924 spin_lock_irqsave(&musb->lock, flags);
1925 val = musb->a_wait_bcon;
1926 vbus = musb_platform_get_vbus_status(musb);
1928 /* Use default MUSB method by means of DEVCTL register */
1929 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1930 if ((devctl & MUSB_DEVCTL_VBUS)
1931 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1936 spin_unlock_irqrestore(&musb->lock, flags);
1937 pm_runtime_put_sync(dev);
1939 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1940 vbus ? "on" : "off", val);
1942 static DEVICE_ATTR_RW(vbus);
1944 /* Gadget drivers can't know that a host is connected so they might want
1945 * to start SRP, but users can. This allows userspace to trigger SRP.
1947 static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
1948 const char *buf, size_t n)
1950 struct musb *musb = dev_to_musb(dev);
1953 if (sscanf(buf, "%hu", &srp) != 1
1955 dev_err(dev, "SRP: Value must be 1\n");
1960 musb_g_wakeup(musb);
1964 static DEVICE_ATTR_WO(srp);
1966 static struct attribute *musb_attrs[] = {
1967 &dev_attr_mode.attr,
1968 &dev_attr_vbus.attr,
1972 ATTRIBUTE_GROUPS(musb);
1974 #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1975 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1976 MUSB_DEVCTL_SESSION)
1977 #define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \
1978 (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1979 MUSB_DEVCTL_SESSION)
1980 #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1981 MUSB_DEVCTL_SESSION)
1983 static bool musb_state_needs_recheck(struct musb *musb, u8 devctl,
1986 if (musb->quirk_retries && !musb->flush_irq_work) {
1987 trace_musb_state(musb, devctl, desc);
1988 schedule_delayed_work(&musb->irq_work,
1989 msecs_to_jiffies(1000));
1990 musb->quirk_retries--;
1999 * Check the musb devctl session bit to determine if we want to
2000 * allow PM runtime for the device. In general, we want to keep things
2001 * active when the session bit is set except after host disconnect.
2003 * Only called from musb_irq_work. If this ever needs to get called
2004 * elsewhere, proper locking must be implemented for musb->session.
2006 static void musb_pm_runtime_check_session(struct musb *musb)
2011 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2013 /* Handle session status quirks first */
2014 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
2016 switch (devctl & ~s) {
2017 case MUSB_QUIRK_B_DISCONNECT_99:
2018 musb_state_needs_recheck(musb, devctl,
2019 "Poll devctl in case of suspend after disconnect");
2021 case MUSB_QUIRK_B_INVALID_VBUS_91:
2022 if (musb_state_needs_recheck(musb, devctl,
2023 "Poll devctl on invalid vbus, assume no session"))
2026 case MUSB_QUIRK_A_DISCONNECT_19:
2027 if (musb_state_needs_recheck(musb, devctl,
2028 "Poll devctl on possible host mode disconnect"))
2032 trace_musb_state(musb, devctl, "Allow PM on possible host mode disconnect");
2033 pm_runtime_mark_last_busy(musb->controller);
2034 pm_runtime_put_autosuspend(musb->controller);
2035 musb->session = false;
2041 /* No need to do anything if session has not changed */
2042 s = devctl & MUSB_DEVCTL_SESSION;
2043 if (s == musb->session)
2046 /* Block PM or allow PM? */
2048 trace_musb_state(musb, devctl, "Block PM on active session");
2049 error = pm_runtime_get_sync(musb->controller);
2051 dev_err(musb->controller, "Could not enable: %i\n",
2053 musb->quirk_retries = 3;
2056 * We can get a spurious MUSB_INTR_SESSREQ interrupt on start-up
2057 * in B-peripheral mode with nothing connected and the session
2058 * bit clears silently. Check status again in 3 seconds.
2060 if (devctl & MUSB_DEVCTL_BDEVICE)
2061 schedule_delayed_work(&musb->irq_work,
2062 msecs_to_jiffies(3000));
2064 trace_musb_state(musb, devctl, "Allow PM with no session");
2065 pm_runtime_mark_last_busy(musb->controller);
2066 pm_runtime_put_autosuspend(musb->controller);
2072 /* Only used to provide driver mode change events */
2073 static void musb_irq_work(struct work_struct *data)
2075 struct musb *musb = container_of(data, struct musb, irq_work.work);
2078 error = pm_runtime_resume_and_get(musb->controller);
2080 dev_err(musb->controller, "Could not enable: %i\n", error);
2085 musb_pm_runtime_check_session(musb);
2087 if (musb_get_state(musb) != musb->xceiv_old_state) {
2088 musb->xceiv_old_state = musb_get_state(musb);
2089 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2092 pm_runtime_mark_last_busy(musb->controller);
2093 pm_runtime_put_autosuspend(musb->controller);
2096 static void musb_recover_from_babble(struct musb *musb)
2101 musb_disable_interrupts(musb);
2104 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
2105 * it some slack and wait for 10us.
2109 ret = musb_platform_recover(musb);
2111 musb_enable_interrupts(musb);
2115 /* drop session bit */
2116 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2117 devctl &= ~MUSB_DEVCTL_SESSION;
2118 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2120 /* tell usbcore about it */
2121 musb_root_disconnect(musb);
2124 * When a babble condition occurs, the musb controller
2125 * removes the session bit and the endpoint config is lost.
2128 ret = ep_config_from_table(musb);
2130 ret = ep_config_from_hw(musb);
2132 /* restart session */
2137 /* --------------------------------------------------------------------------
2141 static struct musb *allocate_instance(struct device *dev,
2142 const struct musb_hdrc_config *config, void __iomem *mbase)
2145 struct musb_hw_ep *ep;
2149 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2153 INIT_LIST_HEAD(&musb->control);
2154 INIT_LIST_HEAD(&musb->in_bulk);
2155 INIT_LIST_HEAD(&musb->out_bulk);
2156 INIT_LIST_HEAD(&musb->pending_list);
2158 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2159 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2160 musb->mregs = mbase;
2161 musb->ctrl_base = mbase;
2162 musb->nIrq = -ENODEV;
2163 musb->config = config;
2164 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2165 for (epnum = 0, ep = musb->endpoints;
2166 epnum < musb->config->num_eps;
2172 musb->controller = dev;
2174 ret = musb_host_alloc(musb);
2178 dev_set_drvdata(dev, musb);
2186 static void musb_free(struct musb *musb)
2188 /* this has multiple entry modes. it handles fault cleanup after
2189 * probe(), where things may be partially set up, as well as rmmod
2190 * cleanup after everything's been de-activated.
2193 if (musb->nIrq >= 0) {
2195 disable_irq_wake(musb->nIrq);
2196 free_irq(musb->nIrq, musb);
2199 musb_host_free(musb);
2202 struct musb_pending_work {
2203 int (*callback)(struct musb *musb, void *data);
2205 struct list_head node;
2210 * Called from musb_runtime_resume(), musb_resume(), and
2211 * musb_queue_resume_work(). Callers must take musb->lock.
2213 static int musb_run_resume_work(struct musb *musb)
2215 struct musb_pending_work *w, *_w;
2216 unsigned long flags;
2219 spin_lock_irqsave(&musb->list_lock, flags);
2220 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2222 error = w->callback(musb, w->data);
2224 dev_err(musb->controller,
2225 "resume callback %p failed: %i\n",
2226 w->callback, error);
2230 devm_kfree(musb->controller, w);
2232 spin_unlock_irqrestore(&musb->list_lock, flags);
2239 * Called to run work if device is active or else queue the work to happen
2240 * on resume. Caller must take musb->lock and must hold an RPM reference.
2242 * Note that we cowardly refuse queuing work after musb PM runtime
2243 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2246 int musb_queue_resume_work(struct musb *musb,
2247 int (*callback)(struct musb *musb, void *data),
2250 struct musb_pending_work *w;
2251 unsigned long flags;
2255 if (WARN_ON(!callback))
2258 spin_lock_irqsave(&musb->list_lock, flags);
2259 is_suspended = musb->is_runtime_suspended;
2262 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2268 w->callback = callback;
2271 list_add_tail(&w->node, &musb->pending_list);
2276 spin_unlock_irqrestore(&musb->list_lock, flags);
2279 error = callback(musb, data);
2283 EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2285 static void musb_deassert_reset(struct work_struct *work)
2288 unsigned long flags;
2290 musb = container_of(work, struct musb, deassert_reset_work.work);
2292 spin_lock_irqsave(&musb->lock, flags);
2294 if (musb->port1_status & USB_PORT_STAT_RESET)
2295 musb_port_reset(musb, false);
2297 spin_unlock_irqrestore(&musb->lock, flags);
2301 * Perform generic per-controller initialization.
2303 * @dev: the controller (already clocked, etc)
2305 * @ctrl: virtual address of controller registers,
2306 * not yet corrected for platform-specific offsets
2309 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2313 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2315 /* The driver might handle more features than the board; OK.
2316 * Fail when the board needs a feature that's not enabled.
2319 dev_err(dev, "no platform_data?\n");
2325 musb = allocate_instance(dev, plat->config, ctrl);
2331 spin_lock_init(&musb->lock);
2332 spin_lock_init(&musb->list_lock);
2333 musb->board_set_power = plat->set_power;
2334 musb->min_power = plat->min_power;
2335 musb->ops = plat->platform_ops;
2336 musb->port_mode = plat->mode;
2339 * Initialize the default IO functions. At least omap2430 needs
2340 * these early. We initialize the platform specific IO functions
2343 musb_readb = musb_default_readb;
2344 musb_writeb = musb_default_writeb;
2345 musb_readw = musb_default_readw;
2346 musb_writew = musb_default_writew;
2348 /* The musb_platform_init() call:
2349 * - adjusts musb->mregs
2350 * - sets the musb->isr
2351 * - may initialize an integrated transceiver
2352 * - initializes musb->xceiv, usually by otg_get_phy()
2353 * - stops powering VBUS
2355 * There are various transceiver configurations.
2356 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2357 * external/discrete ones in various flavors (twl4030 family,
2358 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2360 status = musb_platform_init(musb);
2370 /* Most devices use indexed offset or flat offset */
2371 if (musb->ops->quirks & MUSB_INDEXED_EP) {
2372 musb->io.ep_offset = musb_indexed_ep_offset;
2373 musb->io.ep_select = musb_indexed_ep_select;
2375 musb->io.ep_offset = musb_flat_ep_offset;
2376 musb->io.ep_select = musb_flat_ep_select;
2379 if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
2380 musb->g.quirk_avoids_skb_reserve = 1;
2382 /* At least tusb6010 has its own offsets */
2383 if (musb->ops->ep_offset)
2384 musb->io.ep_offset = musb->ops->ep_offset;
2385 if (musb->ops->ep_select)
2386 musb->io.ep_select = musb->ops->ep_select;
2388 if (musb->ops->fifo_mode)
2389 fifo_mode = musb->ops->fifo_mode;
2393 if (musb->ops->fifo_offset)
2394 musb->io.fifo_offset = musb->ops->fifo_offset;
2396 musb->io.fifo_offset = musb_default_fifo_offset;
2398 if (musb->ops->busctl_offset)
2399 musb->io.busctl_offset = musb->ops->busctl_offset;
2401 musb->io.busctl_offset = musb_default_busctl_offset;
2403 if (musb->ops->readb)
2404 musb_readb = musb->ops->readb;
2405 if (musb->ops->writeb)
2406 musb_writeb = musb->ops->writeb;
2407 if (musb->ops->clearb)
2408 musb_clearb = musb->ops->clearb;
2410 musb_clearb = musb_readb;
2412 if (musb->ops->readw)
2413 musb_readw = musb->ops->readw;
2414 if (musb->ops->writew)
2415 musb_writew = musb->ops->writew;
2416 if (musb->ops->clearw)
2417 musb_clearw = musb->ops->clearw;
2419 musb_clearw = musb_readw;
2421 #ifndef CONFIG_MUSB_PIO_ONLY
2422 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2423 dev_err(dev, "DMA controller not set\n");
2427 musb_dma_controller_create = musb->ops->dma_init;
2428 musb_dma_controller_destroy = musb->ops->dma_exit;
2431 if (musb->ops->read_fifo)
2432 musb->io.read_fifo = musb->ops->read_fifo;
2434 musb->io.read_fifo = musb_default_read_fifo;
2436 if (musb->ops->write_fifo)
2437 musb->io.write_fifo = musb->ops->write_fifo;
2439 musb->io.write_fifo = musb_default_write_fifo;
2441 if (musb->ops->get_toggle)
2442 musb->io.get_toggle = musb->ops->get_toggle;
2444 musb->io.get_toggle = musb_default_get_toggle;
2446 if (musb->ops->set_toggle)
2447 musb->io.set_toggle = musb->ops->set_toggle;
2449 musb->io.set_toggle = musb_default_set_toggle;
2451 if (IS_ENABLED(CONFIG_USB_PHY) && musb->xceiv && !musb->xceiv->io_ops) {
2452 musb->xceiv->io_dev = musb->controller;
2453 musb->xceiv->io_priv = musb->mregs;
2454 musb->xceiv->io_ops = &musb_ulpi_access;
2457 if (musb->ops->phy_callback)
2458 musb_phy_callback = musb->ops->phy_callback;
2461 * We need musb_read/write functions initialized for PM.
2462 * Note that at least 2430 glue needs autosuspend delay
2463 * somewhere above 300 ms for the hardware to idle properly
2464 * after disconnecting the cable in host mode. Let's use
2465 * 500 ms for some margin.
2467 pm_runtime_use_autosuspend(musb->controller);
2468 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2469 pm_runtime_enable(musb->controller);
2470 pm_runtime_get_sync(musb->controller);
2472 status = usb_phy_init(musb->xceiv);
2474 goto err_usb_phy_init;
2476 if (use_dma && dev->dma_mask) {
2477 musb->dma_controller =
2478 musb_dma_controller_create(musb, musb->mregs);
2479 if (IS_ERR(musb->dma_controller)) {
2480 status = PTR_ERR(musb->dma_controller);
2485 /* be sure interrupts are disabled before connecting ISR */
2486 musb_platform_disable(musb);
2487 musb_disable_interrupts(musb);
2488 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2490 /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
2491 musb_writeb(musb->mregs, MUSB_POWER, 0);
2493 /* Init IRQ workqueue before request_irq */
2494 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2495 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2496 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2498 /* setup musb parts of the core (especially endpoints) */
2499 status = musb_core_init(plat->config->multipoint
2500 ? MUSB_CONTROLLER_MHDRC
2501 : MUSB_CONTROLLER_HDRC, musb);
2505 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
2507 /* attach to the IRQ */
2508 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
2509 dev_err(dev, "request_irq %d failed!\n", nIrq);
2514 /* FIXME this handles wakeup irqs wrong */
2515 if (enable_irq_wake(nIrq) == 0) {
2517 device_init_wakeup(dev, 1);
2522 /* program PHY to use external vBus if required */
2523 if (plat->extvbus) {
2524 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2525 busctl |= MUSB_ULPI_USE_EXTVBUS;
2526 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2529 MUSB_DEV_MODE(musb);
2530 musb_set_state(musb, OTG_STATE_B_IDLE);
2532 switch (musb->port_mode) {
2534 status = musb_host_setup(musb, plat->power);
2537 status = musb_platform_set_mode(musb, MUSB_HOST);
2539 case MUSB_PERIPHERAL:
2540 status = musb_gadget_setup(musb);
2543 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2546 status = musb_host_setup(musb, plat->power);
2549 status = musb_gadget_setup(musb);
2551 musb_host_cleanup(musb);
2554 status = musb_platform_set_mode(musb, MUSB_OTG);
2557 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2564 musb_init_debugfs(musb);
2566 musb->is_initialized = 1;
2567 pm_runtime_mark_last_busy(musb->controller);
2568 pm_runtime_put_autosuspend(musb->controller);
2573 cancel_delayed_work_sync(&musb->irq_work);
2574 cancel_delayed_work_sync(&musb->finish_resume_work);
2575 cancel_delayed_work_sync(&musb->deassert_reset_work);
2576 if (musb->dma_controller)
2577 musb_dma_controller_destroy(musb->dma_controller);
2580 usb_phy_shutdown(musb->xceiv);
2583 pm_runtime_dont_use_autosuspend(musb->controller);
2584 pm_runtime_put_sync(musb->controller);
2585 pm_runtime_disable(musb->controller);
2589 device_init_wakeup(dev, 0);
2590 musb_platform_exit(musb);
2593 dev_err_probe(musb->controller, status, "%s failed\n", __func__);
2603 /*-------------------------------------------------------------------------*/
2605 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2606 * bridge to a platform device; this driver then suffices.
2608 static int musb_probe(struct platform_device *pdev)
2610 struct device *dev = &pdev->dev;
2611 int irq = platform_get_irq_byname(pdev, "mc");
2617 base = devm_platform_ioremap_resource(pdev, 0);
2619 return PTR_ERR(base);
2621 return musb_init_controller(dev, irq, base);
2624 static void musb_remove(struct platform_device *pdev)
2626 struct device *dev = &pdev->dev;
2627 struct musb *musb = dev_to_musb(dev);
2628 unsigned long flags;
2630 /* this gets called on rmmod.
2631 * - Host mode: host may still be active
2632 * - Peripheral mode: peripheral is deactivated (or never-activated)
2633 * - OTG mode: both roles are deactivated (or never-activated)
2635 musb_exit_debugfs(musb);
2637 cancel_delayed_work_sync(&musb->irq_work);
2638 cancel_delayed_work_sync(&musb->finish_resume_work);
2639 cancel_delayed_work_sync(&musb->deassert_reset_work);
2640 pm_runtime_get_sync(musb->controller);
2641 musb_host_cleanup(musb);
2642 musb_gadget_cleanup(musb);
2644 musb_platform_disable(musb);
2645 spin_lock_irqsave(&musb->lock, flags);
2646 musb_disable_interrupts(musb);
2647 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2648 spin_unlock_irqrestore(&musb->lock, flags);
2649 musb_platform_exit(musb);
2651 pm_runtime_dont_use_autosuspend(musb->controller);
2652 pm_runtime_put_sync(musb->controller);
2653 pm_runtime_disable(musb->controller);
2654 musb_phy_callback = NULL;
2655 if (musb->dma_controller)
2656 musb_dma_controller_destroy(musb->dma_controller);
2657 usb_phy_shutdown(musb->xceiv);
2659 device_init_wakeup(dev, 0);
2664 static void musb_save_context(struct musb *musb)
2667 void __iomem *musb_base = musb->mregs;
2670 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2671 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2672 musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
2673 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2674 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2675 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2676 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2678 for (i = 0; i < musb->config->num_eps; ++i) {
2679 epio = musb->endpoints[i].regs;
2683 musb_writeb(musb_base, MUSB_INDEX, i);
2684 musb->context.index_regs[i].txmaxp =
2685 musb_readw(epio, MUSB_TXMAXP);
2686 musb->context.index_regs[i].txcsr =
2687 musb_readw(epio, MUSB_TXCSR);
2688 musb->context.index_regs[i].rxmaxp =
2689 musb_readw(epio, MUSB_RXMAXP);
2690 musb->context.index_regs[i].rxcsr =
2691 musb_readw(epio, MUSB_RXCSR);
2693 if (musb->dyn_fifo) {
2694 musb->context.index_regs[i].txfifoadd =
2695 musb_readw(musb_base, MUSB_TXFIFOADD);
2696 musb->context.index_regs[i].rxfifoadd =
2697 musb_readw(musb_base, MUSB_RXFIFOADD);
2698 musb->context.index_regs[i].txfifosz =
2699 musb_readb(musb_base, MUSB_TXFIFOSZ);
2700 musb->context.index_regs[i].rxfifosz =
2701 musb_readb(musb_base, MUSB_RXFIFOSZ);
2704 musb->context.index_regs[i].txtype =
2705 musb_readb(epio, MUSB_TXTYPE);
2706 musb->context.index_regs[i].txinterval =
2707 musb_readb(epio, MUSB_TXINTERVAL);
2708 musb->context.index_regs[i].rxtype =
2709 musb_readb(epio, MUSB_RXTYPE);
2710 musb->context.index_regs[i].rxinterval =
2711 musb_readb(epio, MUSB_RXINTERVAL);
2713 musb->context.index_regs[i].txfunaddr =
2714 musb_read_txfunaddr(musb, i);
2715 musb->context.index_regs[i].txhubaddr =
2716 musb_read_txhubaddr(musb, i);
2717 musb->context.index_regs[i].txhubport =
2718 musb_read_txhubport(musb, i);
2720 musb->context.index_regs[i].rxfunaddr =
2721 musb_read_rxfunaddr(musb, i);
2722 musb->context.index_regs[i].rxhubaddr =
2723 musb_read_rxhubaddr(musb, i);
2724 musb->context.index_regs[i].rxhubport =
2725 musb_read_rxhubport(musb, i);
2729 static void musb_restore_context(struct musb *musb)
2732 void __iomem *musb_base = musb->mregs;
2736 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2737 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2738 musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
2740 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2741 power = musb_readb(musb_base, MUSB_POWER);
2742 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2743 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2744 power |= musb->context.power;
2745 musb_writeb(musb_base, MUSB_POWER, power);
2747 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2748 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2749 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2750 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2751 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2753 for (i = 0; i < musb->config->num_eps; ++i) {
2754 epio = musb->endpoints[i].regs;
2758 musb_writeb(musb_base, MUSB_INDEX, i);
2759 musb_writew(epio, MUSB_TXMAXP,
2760 musb->context.index_regs[i].txmaxp);
2761 musb_writew(epio, MUSB_TXCSR,
2762 musb->context.index_regs[i].txcsr);
2763 musb_writew(epio, MUSB_RXMAXP,
2764 musb->context.index_regs[i].rxmaxp);
2765 musb_writew(epio, MUSB_RXCSR,
2766 musb->context.index_regs[i].rxcsr);
2768 if (musb->dyn_fifo) {
2769 musb_writeb(musb_base, MUSB_TXFIFOSZ,
2770 musb->context.index_regs[i].txfifosz);
2771 musb_writeb(musb_base, MUSB_RXFIFOSZ,
2772 musb->context.index_regs[i].rxfifosz);
2773 musb_writew(musb_base, MUSB_TXFIFOADD,
2774 musb->context.index_regs[i].txfifoadd);
2775 musb_writew(musb_base, MUSB_RXFIFOADD,
2776 musb->context.index_regs[i].rxfifoadd);
2779 musb_writeb(epio, MUSB_TXTYPE,
2780 musb->context.index_regs[i].txtype);
2781 musb_writeb(epio, MUSB_TXINTERVAL,
2782 musb->context.index_regs[i].txinterval);
2783 musb_writeb(epio, MUSB_RXTYPE,
2784 musb->context.index_regs[i].rxtype);
2785 musb_writeb(epio, MUSB_RXINTERVAL,
2787 musb->context.index_regs[i].rxinterval);
2788 musb_write_txfunaddr(musb, i,
2789 musb->context.index_regs[i].txfunaddr);
2790 musb_write_txhubaddr(musb, i,
2791 musb->context.index_regs[i].txhubaddr);
2792 musb_write_txhubport(musb, i,
2793 musb->context.index_regs[i].txhubport);
2795 musb_write_rxfunaddr(musb, i,
2796 musb->context.index_regs[i].rxfunaddr);
2797 musb_write_rxhubaddr(musb, i,
2798 musb->context.index_regs[i].rxhubaddr);
2799 musb_write_rxhubport(musb, i,
2800 musb->context.index_regs[i].rxhubport);
2802 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2805 static int musb_suspend(struct device *dev)
2807 struct musb *musb = dev_to_musb(dev);
2808 unsigned long flags;
2811 ret = pm_runtime_get_sync(dev);
2813 pm_runtime_put_noidle(dev);
2817 musb_platform_disable(musb);
2818 musb_disable_interrupts(musb);
2820 musb->flush_irq_work = true;
2821 while (flush_delayed_work(&musb->irq_work))
2823 musb->flush_irq_work = false;
2825 if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
2826 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2828 WARN_ON(!list_empty(&musb->pending_list));
2830 spin_lock_irqsave(&musb->lock, flags);
2832 if (is_peripheral_active(musb)) {
2833 /* FIXME force disconnect unless we know USB will wake
2834 * the system up quickly enough to respond ...
2836 } else if (is_host_active(musb)) {
2837 /* we know all the children are suspended; sometimes
2838 * they will even be wakeup-enabled.
2842 musb_save_context(musb);
2844 spin_unlock_irqrestore(&musb->lock, flags);
2848 static int musb_resume(struct device *dev)
2850 struct musb *musb = dev_to_musb(dev);
2851 unsigned long flags;
2857 * For static cmos like DaVinci, register values were preserved
2858 * unless for some reason the whole soc powered down or the USB
2859 * module got reset through the PSC (vs just being disabled).
2861 * For the DSPS glue layer though, a full register restore has to
2862 * be done. As it shouldn't harm other platforms, we do it
2866 musb_restore_context(musb);
2868 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2869 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2870 if ((devctl & mask) != (musb->context.devctl & mask))
2871 musb->port1_status = 0;
2873 musb_enable_interrupts(musb);
2874 musb_platform_enable(musb);
2876 /* session might be disabled in suspend */
2877 if (musb->port_mode == MUSB_HOST &&
2878 !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
2879 devctl |= MUSB_DEVCTL_SESSION;
2880 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2883 spin_lock_irqsave(&musb->lock, flags);
2884 error = musb_run_resume_work(musb);
2886 dev_err(musb->controller, "resume work failed with %i\n",
2888 spin_unlock_irqrestore(&musb->lock, flags);
2890 pm_runtime_mark_last_busy(dev);
2891 pm_runtime_put_autosuspend(dev);
2896 static int musb_runtime_suspend(struct device *dev)
2898 struct musb *musb = dev_to_musb(dev);
2900 musb_save_context(musb);
2901 musb->is_runtime_suspended = 1;
2906 static int musb_runtime_resume(struct device *dev)
2908 struct musb *musb = dev_to_musb(dev);
2909 unsigned long flags;
2913 * When pm_runtime_get_sync called for the first time in driver
2914 * init, some of the structure is still not initialized which is
2915 * used in restore function. But clock needs to be
2916 * enabled before any register access, so
2917 * pm_runtime_get_sync has to be called.
2918 * Also context restore without save does not make
2921 if (!musb->is_initialized)
2924 musb_restore_context(musb);
2926 spin_lock_irqsave(&musb->lock, flags);
2927 error = musb_run_resume_work(musb);
2929 dev_err(musb->controller, "resume work failed with %i\n",
2931 musb->is_runtime_suspended = 0;
2932 spin_unlock_irqrestore(&musb->lock, flags);
2937 static const struct dev_pm_ops musb_dev_pm_ops = {
2938 .suspend = musb_suspend,
2939 .resume = musb_resume,
2940 .runtime_suspend = musb_runtime_suspend,
2941 .runtime_resume = musb_runtime_resume,
2944 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2946 #define MUSB_DEV_PM_OPS NULL
2949 static struct platform_driver musb_driver = {
2951 .name = musb_driver_name,
2952 .bus = &platform_bus_type,
2953 .pm = MUSB_DEV_PM_OPS,
2954 .dev_groups = musb_groups,
2956 .probe = musb_probe,
2957 .remove_new = musb_remove,
2960 module_platform_driver(musb_driver);