2 * Texas Instruments AM35x "glue layer"
4 * Copyright (c) 2010, by Texas Instruments
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/clk.h>
32 #include <linux/platform_device.h>
33 #include <linux/dma-mapping.h>
35 #include <plat/control.h>
38 #include "musb_core.h"
41 * AM35x specific definitions
43 /* USB 2.0 OTG module registers */
44 #define USB_REVISION_REG 0x00
45 #define USB_CTRL_REG 0x04
46 #define USB_STAT_REG 0x08
47 #define USB_EMULATION_REG 0x0c
49 #define USB_AUTOREQ_REG 0x14
50 #define USB_SRP_FIX_TIME_REG 0x18
51 #define USB_TEARDOWN_REG 0x1c
52 #define EP_INTR_SRC_REG 0x20
53 #define EP_INTR_SRC_SET_REG 0x24
54 #define EP_INTR_SRC_CLEAR_REG 0x28
55 #define EP_INTR_MASK_REG 0x2c
56 #define EP_INTR_MASK_SET_REG 0x30
57 #define EP_INTR_MASK_CLEAR_REG 0x34
58 #define EP_INTR_SRC_MASKED_REG 0x38
59 #define CORE_INTR_SRC_REG 0x40
60 #define CORE_INTR_SRC_SET_REG 0x44
61 #define CORE_INTR_SRC_CLEAR_REG 0x48
62 #define CORE_INTR_MASK_REG 0x4c
63 #define CORE_INTR_MASK_SET_REG 0x50
64 #define CORE_INTR_MASK_CLEAR_REG 0x54
65 #define CORE_INTR_SRC_MASKED_REG 0x58
67 #define USB_END_OF_INTR_REG 0x60
69 /* Control register bits */
70 #define AM35X_SOFT_RESET_MASK 1
72 /* USB interrupt register bits */
73 #define AM35X_INTR_USB_SHIFT 16
74 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
75 #define AM35X_INTR_DRVVBUS 0x100
76 #define AM35X_INTR_RX_SHIFT 16
77 #define AM35X_INTR_TX_SHIFT 0
78 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
79 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
80 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
81 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
83 #define USB_MENTOR_CORE_OFFSET 0x400
87 struct platform_device *musb;
92 static inline void phy_on(void)
94 unsigned long timeout = jiffies + msecs_to_jiffies(100);
98 * Start the on-chip PHY and its PLL.
100 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
102 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
103 devconf2 |= CONF2_PHY_PLLON;
105 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
107 DBG(1, "Waiting for PHY clock good...\n");
108 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
112 if (time_after(jiffies, timeout)) {
113 DBG(1, "musb PHY clock good timed out\n");
119 static inline void phy_off(void)
124 * Power down the on-chip PHY.
126 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
128 devconf2 &= ~CONF2_PHY_PLLON;
129 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
130 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
134 * am35x_musb_enable - enable interrupts
136 static void am35x_musb_enable(struct musb *musb)
138 void __iomem *reg_base = musb->ctrl_base;
141 /* Workaround: setup IRQs through both register sets. */
142 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
143 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
145 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
146 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
148 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
149 if (is_otg_enabled(musb))
150 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
151 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
155 * am35x_musb_disable - disable HDRC and flush interrupts
157 static void am35x_musb_disable(struct musb *musb)
159 void __iomem *reg_base = musb->ctrl_base;
161 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
162 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
163 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
164 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
165 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
168 #ifdef CONFIG_USB_MUSB_HDRC_HCD
169 #define portstate(stmt) stmt
171 #define portstate(stmt)
174 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
176 WARN_ON(is_on && is_peripheral_active(musb));
179 #define POLL_SECONDS 2
181 static struct timer_list otg_workaround;
183 static void otg_timer(unsigned long _musb)
185 struct musb *musb = (void *)_musb;
186 void __iomem *mregs = musb->mregs;
191 * We poll because AM35x's won't expose several OTG-critical
192 * status change events (from the transceiver) otherwise.
194 devctl = musb_readb(mregs, MUSB_DEVCTL);
195 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
197 spin_lock_irqsave(&musb->lock, flags);
198 switch (musb->xceiv->state) {
199 case OTG_STATE_A_WAIT_BCON:
200 devctl &= ~MUSB_DEVCTL_SESSION;
201 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
203 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
204 if (devctl & MUSB_DEVCTL_BDEVICE) {
205 musb->xceiv->state = OTG_STATE_B_IDLE;
208 musb->xceiv->state = OTG_STATE_A_IDLE;
212 case OTG_STATE_A_WAIT_VFALL:
213 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
214 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
215 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
217 case OTG_STATE_B_IDLE:
218 if (!is_peripheral_enabled(musb))
221 devctl = musb_readb(mregs, MUSB_DEVCTL);
222 if (devctl & MUSB_DEVCTL_BDEVICE)
223 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
225 musb->xceiv->state = OTG_STATE_A_IDLE;
230 spin_unlock_irqrestore(&musb->lock, flags);
233 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
235 static unsigned long last_timer;
237 if (!is_otg_enabled(musb))
241 timeout = jiffies + msecs_to_jiffies(3);
243 /* Never idle if active, or when VBUS timeout is not set as host */
244 if (musb->is_active || (musb->a_wait_bcon == 0 &&
245 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
246 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
247 del_timer(&otg_workaround);
248 last_timer = jiffies;
252 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
253 DBG(4, "Longer idle timer already pending, ignoring...\n");
256 last_timer = timeout;
258 DBG(4, "%s inactive, starting idle timer for %u ms\n",
259 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
260 mod_timer(&otg_workaround, timeout);
263 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
265 struct musb *musb = hci;
266 void __iomem *reg_base = musb->ctrl_base;
268 irqreturn_t ret = IRQ_NONE;
269 u32 epintr, usbintr, lvl_intr;
271 spin_lock_irqsave(&musb->lock, flags);
273 /* Get endpoint interrupts */
274 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
277 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
280 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
282 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
285 /* Get usb core interrupts */
286 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
287 if (!usbintr && !epintr)
291 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
294 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
297 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
298 * AM35x's missing ID change IRQ. We need an ID change IRQ to
299 * switch appropriately between halves of the OTG state machine.
300 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
301 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
302 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
304 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
305 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
306 void __iomem *mregs = musb->mregs;
307 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
310 err = is_host_enabled(musb) && (musb->int_usb &
311 MUSB_INTR_VBUSERROR);
314 * The Mentor core doesn't debounce VBUS as needed
315 * to cope with device connect current spikes. This
316 * means it's not uncommon for bus-powered devices
317 * to get VBUS errors during enumeration.
319 * This is a workaround, but newer RTL from Mentor
320 * seems to allow a better one: "re"-starting sessions
321 * without waiting for VBUS to stop registering in
324 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
325 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
326 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
327 WARNING("VBUS error workaround (delay coming)\n");
328 } else if (is_host_enabled(musb) && drvvbus) {
330 musb->xceiv->default_a = 1;
331 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
332 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
333 del_timer(&otg_workaround);
337 musb->xceiv->default_a = 0;
338 musb->xceiv->state = OTG_STATE_B_IDLE;
339 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
342 /* NOTE: this must complete power-on within 100 ms. */
343 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
344 drvvbus ? "on" : "off",
345 otg_state_string(musb),
351 if (musb->int_tx || musb->int_rx || musb->int_usb)
352 ret |= musb_interrupt(musb);
355 /* EOI needs to be written for the IRQ to be re-asserted. */
356 if (ret == IRQ_HANDLED || epintr || usbintr) {
357 /* clear level interrupt */
358 lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
359 lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
360 omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
362 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
365 /* Poll for ID change */
366 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
367 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
369 spin_unlock_irqrestore(&musb->lock, flags);
374 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
376 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
378 devconf2 &= ~CONF2_OTGMODE;
380 #ifdef CONFIG_USB_MUSB_HDRC_HCD
381 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
382 devconf2 |= CONF2_FORCE_HOST;
385 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
386 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
387 devconf2 |= CONF2_FORCE_DEVICE;
390 #ifdef CONFIG_USB_MUSB_OTG
391 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
392 devconf2 |= CONF2_NO_OVERRIDE;
396 DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
399 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
403 static int am35x_musb_init(struct musb *musb)
405 void __iomem *reg_base = musb->ctrl_base;
406 u32 rev, lvl_intr, sw_reset;
408 musb->mregs += USB_MENTOR_CORE_OFFSET;
410 /* Returns zero if e.g. not clocked */
411 rev = musb_readl(reg_base, USB_REVISION_REG);
415 usb_nop_xceiv_register();
416 musb->xceiv = otg_get_transceiver();
420 if (is_host_enabled(musb))
421 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
423 musb->board_set_vbus = am35x_musb_set_vbus;
426 sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
428 sw_reset |= AM35XX_USBOTGSS_SW_RST;
429 omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
431 sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
432 omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
434 /* Reset the controller */
435 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
437 /* Start the on-chip PHY and its PLL. */
442 musb->isr = am35x_musb_interrupt;
444 /* clear level interrupt */
445 lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
446 lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
447 omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
452 static int am35x_musb_exit(struct musb *musb)
454 if (is_host_enabled(musb))
455 del_timer_sync(&otg_workaround);
459 otg_put_transceiver(musb->xceiv);
460 usb_nop_xceiv_unregister();
466 void musb_platform_save_context(struct musb *musb,
467 struct musb_context_registers *musb_context)
472 void musb_platform_restore_context(struct musb *musb,
473 struct musb_context_registers *musb_context)
479 /* AM35x supports only 32bit read operation */
480 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
482 void __iomem *fifo = hw_ep->fifo;
486 /* Read for 32bit-aligned destination address */
487 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
488 readsl(fifo, dst, len >> 2);
493 * Now read the remaining 1 to 3 byte or complete length if
497 for (i = 0; i < (len >> 2); i++) {
498 *(u32 *) dst = musb_readl(fifo, 0);
504 val = musb_readl(fifo, 0);
505 memcpy(dst, &val, len);
509 static const struct musb_platform_ops am35x_ops = {
510 .init = am35x_musb_init,
511 .exit = am35x_musb_exit,
513 .enable = am35x_musb_enable,
514 .disable = am35x_musb_disable,
516 .set_mode = am35x_musb_set_mode,
517 .try_idle = am35x_musb_try_idle,
519 .set_vbus = am35x_musb_set_vbus,
522 static u64 am35x_dmamask = DMA_BIT_MASK(32);
524 static int __init am35x_probe(struct platform_device *pdev)
526 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
527 struct platform_device *musb;
528 struct am35x_glue *glue;
535 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
537 dev_err(&pdev->dev, "failed to allocate glue context\n");
541 musb = platform_device_alloc("musb-hdrc", -1);
543 dev_err(&pdev->dev, "failed to allocate musb device\n");
547 phy_clk = clk_get(&pdev->dev, "fck");
548 if (IS_ERR(phy_clk)) {
549 dev_err(&pdev->dev, "failed to get PHY clock\n");
550 ret = PTR_ERR(phy_clk);
554 clk = clk_get(&pdev->dev, "ick");
556 dev_err(&pdev->dev, "failed to get clock\n");
561 ret = clk_enable(phy_clk);
563 dev_err(&pdev->dev, "failed to enable PHY clock\n");
567 ret = clk_enable(clk);
569 dev_err(&pdev->dev, "failed to enable clock\n");
573 musb->dev.parent = &pdev->dev;
574 musb->dev.dma_mask = &am35x_dmamask;
575 musb->dev.coherent_dma_mask = am35x_dmamask;
577 glue->dev = &pdev->dev;
579 glue->phy_clk = phy_clk;
582 pdata->platform_ops = &am35x_ops;
584 platform_set_drvdata(pdev, glue);
586 ret = platform_device_add_resources(musb, pdev->resource,
587 pdev->num_resources);
589 dev_err(&pdev->dev, "failed to add resources\n");
593 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
595 dev_err(&pdev->dev, "failed to add platform_data\n");
599 ret = platform_device_add(musb);
601 dev_err(&pdev->dev, "failed to register musb device\n");
611 clk_disable(phy_clk);
620 platform_device_put(musb);
629 static int __exit am35x_remove(struct platform_device *pdev)
631 struct am35x_glue *glue = platform_get_drvdata(pdev);
633 platform_device_del(glue->musb);
634 platform_device_put(glue->musb);
635 clk_disable(glue->clk);
636 clk_disable(glue->phy_clk);
638 clk_put(glue->phy_clk);
644 static struct platform_driver am35x_driver = {
645 .remove = __exit_p(am35x_remove),
647 .name = "musb-am35x",
651 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
652 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
653 MODULE_LICENSE("GPL v2");
655 static int __init am35x_init(void)
657 return platform_driver_probe(&am35x_driver, am35x_probe);
659 subsys_initcall(am35x_init);
661 static void __exit am35x_exit(void)
663 platform_driver_unregister(&am35x_driver);
665 module_exit(am35x_exit);