2 * mtu3_core.c - hardware access layer and gadget init/exit of
3 * MediaTek usb3 Dual-Role Controller Driver
5 * Copyright (C) 2016 MediaTek Inc.
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/platform_device.h>
28 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
30 struct mtu3_fifo_info *fifo = mep->fifo;
31 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
34 /* ensure that @mep->fifo_seg_size is power of two */
35 num_bits = roundup_pow_of_two(num_bits);
36 if (num_bits > fifo->limit)
39 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
40 num_bits = num_bits * (mep->slot + 1);
41 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
42 fifo->limit, 0, num_bits, 0);
43 if (start_bit >= fifo->limit)
46 bitmap_set(fifo->bitmap, start_bit, num_bits);
47 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
48 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
50 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
51 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
53 return mep->fifo_addr;
56 static void ep_fifo_free(struct mtu3_ep *mep)
58 struct mtu3_fifo_info *fifo = mep->fifo;
59 u32 addr = mep->fifo_addr;
60 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
63 if (unlikely(addr < fifo->base || bits > fifo->limit))
66 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
67 bitmap_clear(fifo->bitmap, start_bit, bits);
69 mep->fifo_seg_size = 0;
71 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
72 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
75 /* enable/disable U3D SS function */
76 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
78 /* If usb3_en==0, LTSSM will go to SS.Disable state */
80 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
82 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
84 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
87 /* set/clear U3D HS device soft connect */
88 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
91 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
92 SOFT_CONN | SUSPENDM_ENABLE);
94 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
95 SOFT_CONN | SUSPENDM_ENABLE);
97 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
100 /* only port0 of U2/U3 supports device mode */
101 static int mtu3_device_enable(struct mtu3 *mtu)
103 void __iomem *ibase = mtu->ippc_base;
106 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
109 check_clk = SSUSB_U3_MAC_RST_B_STS;
110 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
111 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
112 SSUSB_U3_PORT_HOST_SEL));
114 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
115 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
116 SSUSB_U2_PORT_HOST_SEL));
117 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
119 return ssusb_check_clocks(mtu->ssusb, check_clk);
122 static void mtu3_device_disable(struct mtu3 *mtu)
124 void __iomem *ibase = mtu->ippc_base;
127 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
128 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
130 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
131 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
132 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
133 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
136 /* reset U3D's device module. */
137 static void mtu3_device_reset(struct mtu3 *mtu)
139 void __iomem *ibase = mtu->ippc_base;
141 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
143 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
146 /* disable all interrupts */
147 static void mtu3_intr_disable(struct mtu3 *mtu)
149 void __iomem *mbase = mtu->mac_base;
151 /* Disable level 1 interrupts */
152 mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
153 /* Disable endpoint interrupts */
154 mtu3_writel(mbase, U3D_EPIECR, ~0x0);
157 static void mtu3_intr_status_clear(struct mtu3 *mtu)
159 void __iomem *mbase = mtu->mac_base;
161 /* Clear EP0 and Tx/Rx EPn interrupts status */
162 mtu3_writel(mbase, U3D_EPISR, ~0x0);
163 /* Clear U2 USB common interrupts status */
164 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
165 /* Clear U3 LTSSM interrupts status */
166 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
167 /* Clear speed change interrupt status */
168 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
171 /* enable system global interrupt */
172 static void mtu3_intr_enable(struct mtu3 *mtu)
174 void __iomem *mbase = mtu->mac_base;
177 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
178 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
179 mtu3_writel(mbase, U3D_LV1IESR, value);
181 /* Enable U2 common USB interrupts */
182 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
183 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
186 /* Enable U3 LTSSM interrupts */
187 value = HOT_RST_INTR | WARM_RST_INTR | VBUS_RISE_INTR |
188 VBUS_FALL_INTR | ENTER_U3_INTR | EXIT_U3_INTR;
189 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
192 /* Enable QMU interrupts. */
193 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
194 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
195 mtu3_writel(mbase, U3D_QIESR1, value);
197 /* Enable speed change interrupt */
198 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
201 /* set/clear the stall and toggle bits for non-ep0 */
202 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
204 struct mtu3 *mtu = mep->mtu;
205 void __iomem *mbase = mtu->mac_base;
206 u8 epnum = mep->epnum;
209 if (mep->is_in) { /* TX */
210 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
214 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
215 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
217 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
221 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
222 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
226 mtu3_setbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
227 mtu3_clrbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
228 mep->flags &= ~MTU3_EP_STALL;
230 mep->flags |= MTU3_EP_STALL;
233 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
234 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
237 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
239 if (mtu->is_u3_ip && (mtu->max_speed == USB_SPEED_SUPER))
240 mtu3_ss_func_set(mtu, is_on);
242 mtu3_hs_softconn_set(mtu, is_on);
244 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
245 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
248 void mtu3_start(struct mtu3 *mtu)
250 void __iomem *mbase = mtu->mac_base;
252 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
253 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
255 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
258 * When disable U2 port, USB2_CSR's register will be reset to
259 * default value after re-enable it again(HS is enabled by default).
260 * So if force mac to work as FS, disable HS function.
262 if (mtu->max_speed == USB_SPEED_FULL)
263 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
265 /* Initialize the default interrupts */
266 mtu3_intr_enable(mtu);
269 if (mtu->softconnect)
270 mtu3_dev_on_off(mtu, 1);
273 void mtu3_stop(struct mtu3 *mtu)
275 dev_dbg(mtu->dev, "%s\n", __func__);
277 mtu3_intr_disable(mtu);
278 mtu3_intr_status_clear(mtu);
280 if (mtu->softconnect)
281 mtu3_dev_on_off(mtu, 0);
284 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
288 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
289 int interval, int burst, int mult)
291 void __iomem *mbase = mtu->mac_base;
292 int epnum = mep->epnum;
293 u32 csr0, csr1, csr2;
294 int fifo_sgsz, fifo_addr;
297 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
299 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
302 fifo_sgsz = ilog2(mep->fifo_seg_size);
303 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
304 mep->fifo_seg_size, mep->fifo_size);
307 csr0 = TX_TXMAXPKTSZ(mep->maxp);
310 num_pkts = (burst + 1) * (mult + 1) - 1;
311 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
312 csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult);
314 csr2 = TX_FIFOADDR(fifo_addr >> 4);
315 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
318 case USB_ENDPOINT_XFER_BULK:
319 csr1 |= TX_TYPE(TYPE_BULK);
321 case USB_ENDPOINT_XFER_ISOC:
322 csr1 |= TX_TYPE(TYPE_ISO);
323 csr2 |= TX_BINTERVAL(interval);
325 case USB_ENDPOINT_XFER_INT:
326 csr1 |= TX_TYPE(TYPE_INT);
327 csr2 |= TX_BINTERVAL(interval);
331 /* Enable QMU Done interrupt */
332 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
334 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
335 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
336 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
338 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
339 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
340 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
341 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
343 csr0 = RX_RXMAXPKTSZ(mep->maxp);
346 num_pkts = (burst + 1) * (mult + 1) - 1;
347 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
348 csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult);
350 csr2 = RX_FIFOADDR(fifo_addr >> 4);
351 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
354 case USB_ENDPOINT_XFER_BULK:
355 csr1 |= RX_TYPE(TYPE_BULK);
357 case USB_ENDPOINT_XFER_ISOC:
358 csr1 |= RX_TYPE(TYPE_ISO);
359 csr2 |= RX_BINTERVAL(interval);
361 case USB_ENDPOINT_XFER_INT:
362 csr1 |= RX_TYPE(TYPE_INT);
363 csr2 |= RX_BINTERVAL(interval);
367 /*Enable QMU Done interrupt */
368 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
370 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
371 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
372 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
374 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
375 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
376 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
377 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
380 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
381 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
382 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
383 fifo_sgsz, mep->fifo_seg_size);
389 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
391 void __iomem *mbase = mtu->mac_base;
392 int epnum = mep->epnum;
395 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
396 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
397 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
398 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
400 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
401 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
402 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
403 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
408 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
413 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
415 * 2. when supports only HS, the fifo is shared for all EPs, and
416 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
417 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
418 * so the total fifo size is 64B + @EPNTXFFSZ;
419 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
420 * starts from offset 64 and are divided into two equal parts for
421 * TX or RX EPs for simplification.
423 static void get_ep_fifo_config(struct mtu3 *mtu)
425 struct mtu3_fifo_info *tx_fifo;
426 struct mtu3_fifo_info *rx_fifo;
430 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
431 tx_fifo = &mtu->tx_fifo;
433 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
434 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
436 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
437 rx_fifo = &mtu->rx_fifo;
439 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
440 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
441 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
443 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
444 tx_fifo = &mtu->tx_fifo;
445 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
446 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
447 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
449 rx_fifo = &mtu->rx_fifo;
451 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
452 rx_fifo->limit = tx_fifo->limit;
453 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
454 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
457 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
458 __func__, tx_fifo->base, tx_fifo->limit,
459 rx_fifo->base, rx_fifo->limit);
462 void mtu3_ep0_setup(struct mtu3 *mtu)
464 u32 maxpacket = mtu->g.ep0->maxpacket;
467 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
469 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
470 csr &= ~EP0_MAXPKTSZ_MSK;
471 csr |= EP0_MAXPKTSZ(maxpacket);
473 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
475 /* Enable EP0 interrupt */
476 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
479 static int mtu3_mem_alloc(struct mtu3 *mtu)
481 void __iomem *mbase = mtu->mac_base;
482 struct mtu3_ep *ep_array;
483 int in_ep_num, out_ep_num;
484 u32 cap_epinfo, cap_dev;
488 mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID);
490 cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
491 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev);
493 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
494 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
495 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
497 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
498 mtu->is_u3_ip ? "U3" : "U2");
499 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
500 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
501 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
503 /* one for ep0, another is reserved */
504 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
505 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
506 if (ep_array == NULL)
509 mtu->ep_array = ep_array;
510 mtu->in_eps = ep_array;
511 mtu->out_eps = &ep_array[mtu->num_eps];
512 /* ep0 uses in_eps[0], out_eps[0] is reserved */
513 mtu->ep0 = mtu->in_eps;
517 for (i = 1; i < mtu->num_eps; i++) {
518 struct mtu3_ep *mep = mtu->in_eps + i;
520 mep->fifo = &mtu->tx_fifo;
521 mep = mtu->out_eps + i;
522 mep->fifo = &mtu->rx_fifo;
525 get_ep_fifo_config(mtu);
527 ret = mtu3_qmu_init(mtu);
529 kfree(mtu->ep_array);
534 static void mtu3_mem_free(struct mtu3 *mtu)
537 kfree(mtu->ep_array);
540 static void mtu3_set_speed(struct mtu3 *mtu)
542 void __iomem *mbase = mtu->mac_base;
544 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
545 mtu->max_speed = USB_SPEED_HIGH;
547 if (mtu->max_speed == USB_SPEED_FULL) {
548 /* disable U3 SS function */
549 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
550 /* disable HS function */
551 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
552 } else if (mtu->max_speed == USB_SPEED_HIGH) {
553 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
554 /* HS/FS detected by HW */
555 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
558 dev_info(mtu->dev, "max_speed: %s\n",
559 usb_speed_string(mtu->max_speed));
562 static void mtu3_regs_init(struct mtu3 *mtu)
565 void __iomem *mbase = mtu->mac_base;
567 /* be sure interrupts are disabled before registration of ISR */
568 mtu3_intr_disable(mtu);
569 mtu3_intr_status_clear(mtu);
572 /* disable LGO_U1/U2 by default */
573 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
574 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE |
575 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
576 /* device responses to u3_exit from host automatically */
577 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
582 /* delay about 0.1us from detecting reset to send chirp-K */
583 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
584 /* U2/U3 detected by HW */
585 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
586 /* enable QMU 16B checksum */
587 mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN);
588 /* vbus detected by HW */
589 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
592 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
594 void __iomem *mbase = mtu->mac_base;
595 enum usb_device_speed udev_speed;
600 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
601 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
602 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
603 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
605 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
608 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
611 case MTU3_SPEED_FULL:
612 udev_speed = USB_SPEED_FULL;
613 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
614 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
615 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
616 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
617 LPM_BESL_STALL | LPM_BESLD_STALL);
619 case MTU3_SPEED_HIGH:
620 udev_speed = USB_SPEED_HIGH;
621 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
622 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
623 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
624 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
625 LPM_BESL_STALL | LPM_BESLD_STALL);
627 case MTU3_SPEED_SUPER:
628 udev_speed = USB_SPEED_SUPER;
632 udev_speed = USB_SPEED_UNKNOWN;
635 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
637 mtu->g.speed = udev_speed;
638 mtu->g.ep0->maxpacket = maxpkt;
639 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
641 if (udev_speed == USB_SPEED_UNKNOWN)
642 mtu3_gadget_disconnect(mtu);
649 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
651 void __iomem *mbase = mtu->mac_base;
654 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
655 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
656 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
657 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
659 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
660 mtu3_gadget_reset(mtu);
662 if (ltssm & VBUS_FALL_INTR)
663 mtu3_ss_func_set(mtu, false);
665 if (ltssm & VBUS_RISE_INTR)
666 mtu3_ss_func_set(mtu, true);
668 if (ltssm & EXIT_U3_INTR)
669 mtu3_gadget_resume(mtu);
671 if (ltssm & ENTER_U3_INTR)
672 mtu3_gadget_suspend(mtu);
677 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
679 void __iomem *mbase = mtu->mac_base;
682 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
683 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
684 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
685 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
687 if (u2comm & SUSPEND_INTR)
688 mtu3_gadget_suspend(mtu);
690 if (u2comm & RESUME_INTR)
691 mtu3_gadget_resume(mtu);
693 if (u2comm & RESET_INTR)
694 mtu3_gadget_reset(mtu);
699 static irqreturn_t mtu3_irq(int irq, void *data)
701 struct mtu3 *mtu = (struct mtu3 *)data;
705 spin_lock_irqsave(&mtu->lock, flags);
707 /* U3D_LV1ISR is RU */
708 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
709 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
711 if (level1 & EP_CTRL_INTR)
714 if (level1 & MAC2_INTR)
715 mtu3_u2_common_isr(mtu);
717 if (level1 & MAC3_INTR)
718 mtu3_u3_ltssm_isr(mtu);
720 if (level1 & BMU_INTR)
723 if (level1 & QMU_INTR)
726 spin_unlock_irqrestore(&mtu->lock, flags);
731 static int mtu3_hw_init(struct mtu3 *mtu)
735 mtu3_device_reset(mtu);
737 ret = mtu3_device_enable(mtu);
739 dev_err(mtu->dev, "device enable failed %d\n", ret);
743 ret = mtu3_mem_alloc(mtu);
752 static void mtu3_hw_exit(struct mtu3 *mtu)
754 mtu3_device_disable(mtu);
758 /*-------------------------------------------------------------------------*/
760 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
762 struct device *dev = ssusb->dev;
763 struct platform_device *pdev = to_platform_device(dev);
764 struct mtu3 *mtu = NULL;
765 struct resource *res;
768 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
772 mtu->irq = platform_get_irq(pdev, 0);
774 dev_err(dev, "fail to get irq number\n");
777 dev_info(dev, "irq %d\n", mtu->irq);
779 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
780 mtu->mac_base = devm_ioremap_resource(dev, res);
781 if (IS_ERR(mtu->mac_base)) {
782 dev_err(dev, "error mapping memory for dev mac\n");
783 return PTR_ERR(mtu->mac_base);
786 spin_lock_init(&mtu->lock);
788 mtu->ippc_base = ssusb->ippc_base;
789 ssusb->mac_base = mtu->mac_base;
792 mtu->max_speed = usb_get_maximum_speed(dev);
794 /* check the max_speed parameter */
795 switch (mtu->max_speed) {
798 case USB_SPEED_SUPER:
801 dev_err(dev, "invalid max_speed: %s\n",
802 usb_speed_string(mtu->max_speed));
804 case USB_SPEED_UNKNOWN:
806 mtu->max_speed = USB_SPEED_SUPER;
810 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
811 mtu->mac_base, mtu->ippc_base);
813 ret = mtu3_hw_init(mtu);
815 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
819 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
821 dev_err(dev, "request irq %d failed!\n", mtu->irq);
825 device_init_wakeup(dev, true);
827 ret = mtu3_gadget_setup(mtu);
829 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
833 /* init as host mode, power down device IP for power saving */
834 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
837 dev_dbg(dev, " %s() done...\n", __func__);
842 device_init_wakeup(dev, false);
847 dev_err(dev, " %s() fail...\n", __func__);
852 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
854 struct mtu3 *mtu = ssusb->u3d;
856 mtu3_gadget_cleanup(mtu);
857 device_init_wakeup(ssusb->dev, false);