1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/slab.h>
17 #include <linux/dmi.h>
18 #include <linux/dma-mapping.h>
21 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 /* TODO: copied from ehci-hcd.c - can this be refactored? */
42 * xhci_handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
48 * Returns negative errno, or zero on success
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
54 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
60 if (result == ~(u32)0) /* card removed */
72 * Disable interrupts and begin the xHCI halting process.
74 void xhci_quiesce(struct xhci_hcd *xhci)
81 halted = readl(&xhci->op_regs->status) & STS_HALT;
85 cmd = readl(&xhci->op_regs->command);
87 writel(cmd, &xhci->op_regs->command);
91 * Force HC into halt state.
93 * Disable any IRQs and clear the run/stop bit.
94 * HC will complete any current and actively pipelined transactions, and
95 * should halt within 16 ms of the run/stop bit being cleared.
96 * Read HC Halted bit in the status register to see when the HC is finished.
98 int xhci_halt(struct xhci_hcd *xhci)
101 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
104 ret = xhci_handshake(&xhci->op_regs->status,
105 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
107 xhci_warn(xhci, "Host halt failed, %d\n", ret);
110 xhci->xhc_state |= XHCI_STATE_HALTED;
111 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
116 * Set the run bit and wait for the host to be running.
118 int xhci_start(struct xhci_hcd *xhci)
123 temp = readl(&xhci->op_regs->command);
125 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
127 writel(temp, &xhci->op_regs->command);
130 * Wait for the HCHalted Status bit to be 0 to indicate the host is
133 ret = xhci_handshake(&xhci->op_regs->status,
134 STS_HALT, 0, XHCI_MAX_HALT_USEC);
135 if (ret == -ETIMEDOUT)
136 xhci_err(xhci, "Host took too long to start, "
137 "waited %u microseconds.\n",
140 /* clear state flags. Including dying, halted or removing */
149 * This resets pipelines, timers, counters, state machines, etc.
150 * Transactions will be terminated immediately, and operational registers
151 * will be set to their defaults.
153 int xhci_reset(struct xhci_hcd *xhci)
159 state = readl(&xhci->op_regs->status);
161 if (state == ~(u32)0) {
162 xhci_warn(xhci, "Host not accessible, reset failed.\n");
166 if ((state & STS_HALT) == 0) {
167 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
171 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
172 command = readl(&xhci->op_regs->command);
173 command |= CMD_RESET;
174 writel(command, &xhci->op_regs->command);
176 /* Existing Intel xHCI controllers require a delay of 1 mS,
177 * after setting the CMD_RESET bit, and before accessing any
178 * HC registers. This allows the HC to complete the
179 * reset operation and be ready for HC register access.
180 * Without this delay, the subsequent HC register access,
181 * may result in a system hang very rarely.
183 if (xhci->quirks & XHCI_INTEL_HOST)
186 ret = xhci_handshake(&xhci->op_regs->command,
187 CMD_RESET, 0, 10 * 1000 * 1000);
191 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
192 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
194 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
195 "Wait for controller to be ready for doorbell rings");
197 * xHCI cannot write to any doorbells or operational registers other
198 * than status until the "Controller Not Ready" flag is cleared.
200 ret = xhci_handshake(&xhci->op_regs->status,
201 STS_CNR, 0, 10 * 1000 * 1000);
203 for (i = 0; i < 2; i++) {
204 xhci->bus_state[i].port_c_suspend = 0;
205 xhci->bus_state[i].suspended_ports = 0;
206 xhci->bus_state[i].resuming_ports = 0;
212 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
214 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
219 * Some Renesas controllers get into a weird state if they are
220 * reset while programmed with 64bit addresses (they will preserve
221 * the top half of the address in internal, non visible
222 * registers). You end up with half the address coming from the
223 * kernel, and the other half coming from the firmware. Also,
224 * changing the programming leads to extra accesses even if the
225 * controller is supposed to be halted. The controller ends up with
226 * a fatal fault, and is then ripe for being properly reset.
228 * Special care is taken to only apply this if the device is behind
229 * an iommu. Doing anything when there is no iommu is definitely
232 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !dev->iommu_group)
235 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
237 /* Clear HSEIE so that faults do not get signaled */
238 val = readl(&xhci->op_regs->command);
240 writel(val, &xhci->op_regs->command);
242 /* Clear HSE (aka FATAL) */
243 val = readl(&xhci->op_regs->status);
245 writel(val, &xhci->op_regs->status);
247 /* Now zero the registers, and brace for impact */
248 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
249 if (upper_32_bits(val))
250 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
251 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
252 if (upper_32_bits(val))
253 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
255 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
256 struct xhci_intr_reg __iomem *ir;
258 ir = &xhci->run_regs->ir_set[i];
259 val = xhci_read_64(xhci, &ir->erst_base);
260 if (upper_32_bits(val))
261 xhci_write_64(xhci, 0, &ir->erst_base);
262 val= xhci_read_64(xhci, &ir->erst_dequeue);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &ir->erst_dequeue);
267 /* Wait for the fault to appear. It will be cleared on reset */
268 err = xhci_handshake(&xhci->op_regs->status,
269 STS_FATAL, STS_FATAL,
272 xhci_info(xhci, "Fault detected\n");
275 #ifdef CONFIG_USB_PCI
279 static int xhci_setup_msi(struct xhci_hcd *xhci)
283 * TODO:Check with MSI Soc for sysdev
285 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
287 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
289 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
290 "failed to allocate MSI entry");
294 ret = request_irq(pdev->irq, xhci_msi_irq,
295 0, "xhci_hcd", xhci_to_hcd(xhci));
297 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
298 "disable MSI interrupt");
299 pci_free_irq_vectors(pdev);
308 static int xhci_setup_msix(struct xhci_hcd *xhci)
311 struct usb_hcd *hcd = xhci_to_hcd(xhci);
312 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
315 * calculate number of msi-x vectors supported.
316 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
317 * with max number of interrupters based on the xhci HCSPARAMS1.
318 * - num_online_cpus: maximum msi-x vectors per CPUs core.
319 * Add additional 1 vector to ensure always available interrupt.
321 xhci->msix_count = min(num_online_cpus() + 1,
322 HCS_MAX_INTRS(xhci->hcs_params1));
324 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
327 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
328 "Failed to enable MSI-X");
332 for (i = 0; i < xhci->msix_count; i++) {
333 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
334 "xhci_hcd", xhci_to_hcd(xhci));
339 hcd->msix_enabled = 1;
343 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
345 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
346 pci_free_irq_vectors(pdev);
350 /* Free any IRQs and disable MSI-X */
351 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
353 struct usb_hcd *hcd = xhci_to_hcd(xhci);
354 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
356 if (xhci->quirks & XHCI_PLAT)
359 /* return if using legacy interrupt */
363 if (hcd->msix_enabled) {
366 for (i = 0; i < xhci->msix_count; i++)
367 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
369 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
372 pci_free_irq_vectors(pdev);
373 hcd->msix_enabled = 0;
376 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
378 struct usb_hcd *hcd = xhci_to_hcd(xhci);
380 if (hcd->msix_enabled) {
381 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
384 for (i = 0; i < xhci->msix_count; i++)
385 synchronize_irq(pci_irq_vector(pdev, i));
389 static int xhci_try_enable_msi(struct usb_hcd *hcd)
391 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
392 struct pci_dev *pdev;
395 /* The xhci platform device has set up IRQs through usb_add_hcd. */
396 if (xhci->quirks & XHCI_PLAT)
399 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
401 * Some Fresco Logic host controllers advertise MSI, but fail to
402 * generate interrupts. Don't even try to enable MSI.
404 if (xhci->quirks & XHCI_BROKEN_MSI)
407 /* unregister the legacy interrupt */
409 free_irq(hcd->irq, hcd);
412 ret = xhci_setup_msix(xhci);
414 /* fall back to msi*/
415 ret = xhci_setup_msi(xhci);
418 hcd->msi_enabled = 1;
423 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
428 if (!strlen(hcd->irq_descr))
429 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
430 hcd->driver->description, hcd->self.busnum);
432 /* fall back to legacy interrupt*/
433 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
434 hcd->irq_descr, hcd);
436 xhci_err(xhci, "request interrupt %d failed\n",
440 hcd->irq = pdev->irq;
446 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
451 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
455 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
461 static void compliance_mode_recovery(struct timer_list *t)
463 struct xhci_hcd *xhci;
465 struct xhci_hub *rhub;
469 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
470 rhub = &xhci->usb3_rhub;
472 for (i = 0; i < rhub->num_ports; i++) {
473 temp = readl(rhub->ports[i]->addr);
474 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
476 * Compliance Mode Detected. Letting USB Core
477 * handle the Warm Reset
479 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
480 "Compliance mode detected->port %d",
482 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
483 "Attempting compliance mode recovery");
484 hcd = xhci->shared_hcd;
486 if (hcd->state == HC_STATE_SUSPENDED)
487 usb_hcd_resume_root_hub(hcd);
489 usb_hcd_poll_rh_status(hcd);
493 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
494 mod_timer(&xhci->comp_mode_recovery_timer,
495 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
499 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
500 * that causes ports behind that hardware to enter compliance mode sometimes.
501 * The quirk creates a timer that polls every 2 seconds the link state of
502 * each host controller's port and recovers it by issuing a Warm reset
503 * if Compliance mode is detected, otherwise the port will become "dead" (no
504 * device connections or disconnections will be detected anymore). Becasue no
505 * status event is generated when entering compliance mode (per xhci spec),
506 * this quirk is needed on systems that have the failing hardware installed.
508 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
510 xhci->port_status_u0 = 0;
511 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
513 xhci->comp_mode_recovery_timer.expires = jiffies +
514 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
516 add_timer(&xhci->comp_mode_recovery_timer);
517 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
518 "Compliance mode recovery timer initialized");
522 * This function identifies the systems that have installed the SN65LVPE502CP
523 * USB3.0 re-driver and that need the Compliance Mode Quirk.
525 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
527 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
529 const char *dmi_product_name, *dmi_sys_vendor;
531 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
532 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
533 if (!dmi_product_name || !dmi_sys_vendor)
536 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
539 if (strstr(dmi_product_name, "Z420") ||
540 strstr(dmi_product_name, "Z620") ||
541 strstr(dmi_product_name, "Z820") ||
542 strstr(dmi_product_name, "Z1 Workstation"))
548 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
550 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
555 * Initialize memory for HCD and xHC (one-time init).
557 * Program the PAGESIZE register, initialize the device context array, create
558 * device contexts (?), set up a command ring segment (or two?), create event
559 * ring (one for now).
561 static int xhci_init(struct usb_hcd *hcd)
563 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
566 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
567 spin_lock_init(&xhci->lock);
568 if (xhci->hci_version == 0x95 && link_quirk) {
569 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
570 "QUIRK: Not clearing Link TRB chain bits.");
571 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
573 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
574 "xHCI doesn't need link TRB QUIRK");
576 retval = xhci_mem_init(xhci, GFP_KERNEL);
577 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
579 /* Initializing Compliance Mode Recovery Data If Needed */
580 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
581 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
582 compliance_mode_recovery_timer_init(xhci);
588 /*-------------------------------------------------------------------------*/
591 static int xhci_run_finished(struct xhci_hcd *xhci)
593 if (xhci_start(xhci)) {
597 xhci->shared_hcd->state = HC_STATE_RUNNING;
598 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
600 if (xhci->quirks & XHCI_NEC_HOST)
601 xhci_ring_cmd_db(xhci);
603 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
604 "Finished xhci_run for USB3 roothub");
609 * Start the HC after it was halted.
611 * This function is called by the USB core when the HC driver is added.
612 * Its opposite is xhci_stop().
614 * xhci_init() must be called once before this function can be called.
615 * Reset the HC, enable device slot contexts, program DCBAAP, and
616 * set command ring pointer and event ring pointer.
618 * Setup MSI-X vectors and enable interrupts.
620 int xhci_run(struct usb_hcd *hcd)
625 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
627 /* Start the xHCI host controller running only after the USB 2.0 roothub
631 hcd->uses_new_polling = 1;
632 if (!usb_hcd_is_primary_hcd(hcd))
633 return xhci_run_finished(xhci);
635 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
637 ret = xhci_try_enable_msi(hcd);
641 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
642 temp_64 &= ~ERST_PTR_MASK;
643 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
644 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
646 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
647 "// Set the interrupt modulation register");
648 temp = readl(&xhci->ir_set->irq_control);
649 temp &= ~ER_IRQ_INTERVAL_MASK;
650 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
651 writel(temp, &xhci->ir_set->irq_control);
653 /* Set the HCD state before we enable the irqs */
654 temp = readl(&xhci->op_regs->command);
656 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
657 "// Enable interrupts, cmd = 0x%x.", temp);
658 writel(temp, &xhci->op_regs->command);
660 temp = readl(&xhci->ir_set->irq_pending);
661 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
662 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
663 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
664 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
666 if (xhci->quirks & XHCI_NEC_HOST) {
667 struct xhci_command *command;
669 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
673 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
674 TRB_TYPE(TRB_NEC_GET_FW));
676 xhci_free_command(xhci, command);
678 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
679 "Finished xhci_run for USB2 roothub");
683 xhci_debugfs_init(xhci);
687 EXPORT_SYMBOL_GPL(xhci_run);
692 * This function is called by the USB core when the HC driver is removed.
693 * Its opposite is xhci_run().
695 * Disable device contexts, disable IRQs, and quiesce the HC.
696 * Reset the HC, finish any completed transactions, and cleanup memory.
698 static void xhci_stop(struct usb_hcd *hcd)
701 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
703 mutex_lock(&xhci->mutex);
705 /* Only halt host and free memory after both hcds are removed */
706 if (!usb_hcd_is_primary_hcd(hcd)) {
707 /* usb core will free this hcd shortly, unset pointer */
708 xhci->shared_hcd = NULL;
709 mutex_unlock(&xhci->mutex);
715 spin_lock_irq(&xhci->lock);
716 xhci->xhc_state |= XHCI_STATE_HALTED;
717 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
720 spin_unlock_irq(&xhci->lock);
722 xhci_cleanup_msix(xhci);
724 /* Deleting Compliance Mode Recovery Timer */
725 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
726 (!(xhci_all_ports_seen_u0(xhci)))) {
727 del_timer_sync(&xhci->comp_mode_recovery_timer);
728 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
729 "%s: compliance mode recovery timer deleted",
733 if (xhci->quirks & XHCI_AMD_PLL_FIX)
736 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
737 "// Disabling event ring interrupts");
738 temp = readl(&xhci->op_regs->status);
739 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
740 temp = readl(&xhci->ir_set->irq_pending);
741 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
743 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
744 xhci_mem_cleanup(xhci);
745 xhci_debugfs_exit(xhci);
746 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
747 "xhci_stop completed - status = %x",
748 readl(&xhci->op_regs->status));
749 mutex_unlock(&xhci->mutex);
753 * Shutdown HC (not bus-specific)
755 * This is called when the machine is rebooting or halting. We assume that the
756 * machine will be powered off, and the HC's internal state will be reset.
757 * Don't bother to free memory.
759 * This will only ever be called with the main usb_hcd (the USB3 roothub).
761 static void xhci_shutdown(struct usb_hcd *hcd)
763 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
765 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
766 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
768 spin_lock_irq(&xhci->lock);
770 /* Workaround for spurious wakeups at shutdown with HSW */
771 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
773 spin_unlock_irq(&xhci->lock);
775 xhci_cleanup_msix(xhci);
777 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
778 "xhci_shutdown completed - status = %x",
779 readl(&xhci->op_regs->status));
781 /* Yet another workaround for spurious wakeups at shutdown with HSW */
782 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
783 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
787 static void xhci_save_registers(struct xhci_hcd *xhci)
789 xhci->s3.command = readl(&xhci->op_regs->command);
790 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
791 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
792 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
793 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
794 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
795 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
796 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
797 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
800 static void xhci_restore_registers(struct xhci_hcd *xhci)
802 writel(xhci->s3.command, &xhci->op_regs->command);
803 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
804 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
805 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
806 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
807 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
808 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
809 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
810 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
813 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
817 /* step 2: initialize command ring buffer */
818 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
819 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
820 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
821 xhci->cmd_ring->dequeue) &
822 (u64) ~CMD_RING_RSVD_BITS) |
823 xhci->cmd_ring->cycle_state;
824 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
825 "// Setting command ring address to 0x%llx",
826 (long unsigned long) val_64);
827 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
831 * The whole command ring must be cleared to zero when we suspend the host.
833 * The host doesn't save the command ring pointer in the suspend well, so we
834 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
835 * aligned, because of the reserved bits in the command ring dequeue pointer
836 * register. Therefore, we can't just set the dequeue pointer back in the
837 * middle of the ring (TRBs are 16-byte aligned).
839 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
841 struct xhci_ring *ring;
842 struct xhci_segment *seg;
844 ring = xhci->cmd_ring;
848 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
849 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
850 cpu_to_le32(~TRB_CYCLE);
852 } while (seg != ring->deq_seg);
854 /* Reset the software enqueue and dequeue pointers */
855 ring->deq_seg = ring->first_seg;
856 ring->dequeue = ring->first_seg->trbs;
857 ring->enq_seg = ring->deq_seg;
858 ring->enqueue = ring->dequeue;
860 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
862 * Ring is now zeroed, so the HW should look for change of ownership
863 * when the cycle bit is set to 1.
865 ring->cycle_state = 1;
868 * Reset the hardware dequeue pointer.
869 * Yes, this will need to be re-written after resume, but we're paranoid
870 * and want to make sure the hardware doesn't access bogus memory
871 * because, say, the BIOS or an SMI started the host without changing
872 * the command ring pointers.
874 xhci_set_cmd_ring_deq(xhci);
877 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
879 struct xhci_port **ports;
884 spin_lock_irqsave(&xhci->lock, flags);
886 /* disable usb3 ports Wake bits */
887 port_index = xhci->usb3_rhub.num_ports;
888 ports = xhci->usb3_rhub.ports;
889 while (port_index--) {
890 t1 = readl(ports[port_index]->addr);
891 t1 = xhci_port_state_to_neutral(t1);
892 t2 = t1 & ~PORT_WAKE_BITS;
894 writel(t2, ports[port_index]->addr);
897 /* disable usb2 ports Wake bits */
898 port_index = xhci->usb2_rhub.num_ports;
899 ports = xhci->usb2_rhub.ports;
900 while (port_index--) {
901 t1 = readl(ports[port_index]->addr);
902 t1 = xhci_port_state_to_neutral(t1);
903 t2 = t1 & ~PORT_WAKE_BITS;
905 writel(t2, ports[port_index]->addr);
908 spin_unlock_irqrestore(&xhci->lock, flags);
911 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
913 struct xhci_port **ports;
918 status = readl(&xhci->op_regs->status);
919 if (status & STS_EINT)
922 * Checking STS_EINT is not enough as there is a lag between a change
923 * bit being set and the Port Status Change Event that it generated
924 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
927 port_index = xhci->usb2_rhub.num_ports;
928 ports = xhci->usb2_rhub.ports;
929 while (port_index--) {
930 portsc = readl(ports[port_index]->addr);
931 if (portsc & PORT_CHANGE_MASK ||
932 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
935 port_index = xhci->usb3_rhub.num_ports;
936 ports = xhci->usb3_rhub.ports;
937 while (port_index--) {
938 portsc = readl(ports[port_index]->addr);
939 if (portsc & PORT_CHANGE_MASK ||
940 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
947 * Stop HC (not bus-specific)
949 * This is called when the machine transition into S3/S4 mode.
952 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
955 unsigned int delay = XHCI_MAX_HALT_USEC;
956 struct usb_hcd *hcd = xhci_to_hcd(xhci);
962 if (hcd->state != HC_STATE_SUSPENDED ||
963 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
966 xhci_dbc_suspend(xhci);
968 /* Clear root port wake on bits if wakeup not allowed. */
970 xhci_disable_port_wake_on_bits(xhci);
972 /* Don't poll the roothubs on bus suspend. */
973 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
974 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
975 del_timer_sync(&hcd->rh_timer);
976 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
977 del_timer_sync(&xhci->shared_hcd->rh_timer);
979 if (xhci->quirks & XHCI_SUSPEND_DELAY)
980 usleep_range(1000, 1500);
982 spin_lock_irq(&xhci->lock);
983 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
984 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
985 /* step 1: stop endpoint */
986 /* skipped assuming that port suspend has done */
988 /* step 2: clear Run/Stop bit */
989 command = readl(&xhci->op_regs->command);
991 writel(command, &xhci->op_regs->command);
993 /* Some chips from Fresco Logic need an extraordinary delay */
994 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
996 if (xhci_handshake(&xhci->op_regs->status,
997 STS_HALT, STS_HALT, delay)) {
998 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
999 spin_unlock_irq(&xhci->lock);
1002 xhci_clear_command_ring(xhci);
1004 /* step 3: save registers */
1005 xhci_save_registers(xhci);
1007 /* step 4: set CSS flag */
1008 command = readl(&xhci->op_regs->command);
1010 writel(command, &xhci->op_regs->command);
1011 if (xhci_handshake(&xhci->op_regs->status,
1012 STS_SAVE, 0, 10 * 1000)) {
1013 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1014 spin_unlock_irq(&xhci->lock);
1017 spin_unlock_irq(&xhci->lock);
1020 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1021 * is about to be suspended.
1023 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1024 (!(xhci_all_ports_seen_u0(xhci)))) {
1025 del_timer_sync(&xhci->comp_mode_recovery_timer);
1026 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1027 "%s: compliance mode recovery timer deleted",
1031 /* step 5: remove core well power */
1032 /* synchronize irq when using MSI-X */
1033 xhci_msix_sync_irqs(xhci);
1037 EXPORT_SYMBOL_GPL(xhci_suspend);
1040 * start xHC (not bus-specific)
1042 * This is called when the machine transition from S3/S4 mode.
1045 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1047 u32 command, temp = 0;
1048 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1049 struct usb_hcd *secondary_hcd;
1051 bool comp_timer_running = false;
1056 /* Wait a bit if either of the roothubs need to settle from the
1057 * transition into bus suspend.
1059 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1060 time_before(jiffies,
1061 xhci->bus_state[1].next_statechange))
1064 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1065 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1067 spin_lock_irq(&xhci->lock);
1068 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1072 /* step 1: restore register */
1073 xhci_restore_registers(xhci);
1074 /* step 2: initialize command ring buffer */
1075 xhci_set_cmd_ring_deq(xhci);
1076 /* step 3: restore state and start state*/
1077 /* step 3: set CRS flag */
1078 command = readl(&xhci->op_regs->command);
1080 writel(command, &xhci->op_regs->command);
1082 * Some controllers take up to 55+ ms to complete the controller
1083 * restore so setting the timeout to 100ms. Xhci specification
1084 * doesn't mention any timeout value.
1086 if (xhci_handshake(&xhci->op_regs->status,
1087 STS_RESTORE, 0, 100 * 1000)) {
1088 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1089 spin_unlock_irq(&xhci->lock);
1092 temp = readl(&xhci->op_regs->status);
1095 /* If restore operation fails, re-initialize the HC during resume */
1096 if ((temp & STS_SRE) || hibernated) {
1098 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1099 !(xhci_all_ports_seen_u0(xhci))) {
1100 del_timer_sync(&xhci->comp_mode_recovery_timer);
1101 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1102 "Compliance Mode Recovery Timer deleted!");
1105 /* Let the USB core know _both_ roothubs lost power. */
1106 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1107 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1109 xhci_dbg(xhci, "Stop HCD\n");
1111 xhci_zero_64b_regs(xhci);
1113 spin_unlock_irq(&xhci->lock);
1114 xhci_cleanup_msix(xhci);
1116 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1117 temp = readl(&xhci->op_regs->status);
1118 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1119 temp = readl(&xhci->ir_set->irq_pending);
1120 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1122 xhci_dbg(xhci, "cleaning up memory\n");
1123 xhci_mem_cleanup(xhci);
1124 xhci_debugfs_exit(xhci);
1125 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1126 readl(&xhci->op_regs->status));
1128 /* USB core calls the PCI reinit and start functions twice:
1129 * first with the primary HCD, and then with the secondary HCD.
1130 * If we don't do the same, the host will never be started.
1132 if (!usb_hcd_is_primary_hcd(hcd))
1133 secondary_hcd = hcd;
1135 secondary_hcd = xhci->shared_hcd;
1137 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1138 retval = xhci_init(hcd->primary_hcd);
1141 comp_timer_running = true;
1143 xhci_dbg(xhci, "Start the primary HCD\n");
1144 retval = xhci_run(hcd->primary_hcd);
1146 xhci_dbg(xhci, "Start the secondary HCD\n");
1147 retval = xhci_run(secondary_hcd);
1149 hcd->state = HC_STATE_SUSPENDED;
1150 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1154 /* step 4: set Run/Stop bit */
1155 command = readl(&xhci->op_regs->command);
1157 writel(command, &xhci->op_regs->command);
1158 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1161 /* step 5: walk topology and initialize portsc,
1162 * portpmsc and portli
1164 /* this is done in bus_resume */
1166 /* step 6: restart each of the previously
1167 * Running endpoints by ringing their doorbells
1170 spin_unlock_irq(&xhci->lock);
1172 xhci_dbc_resume(xhci);
1176 /* Resume root hubs only when have pending events. */
1177 if (xhci_pending_portevent(xhci)) {
1178 usb_hcd_resume_root_hub(xhci->shared_hcd);
1179 usb_hcd_resume_root_hub(hcd);
1184 * If system is subject to the Quirk, Compliance Mode Timer needs to
1185 * be re-initialized Always after a system resume. Ports are subject
1186 * to suffer the Compliance Mode issue again. It doesn't matter if
1187 * ports have entered previously to U0 before system's suspension.
1189 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1190 compliance_mode_recovery_timer_init(xhci);
1192 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1193 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1195 /* Re-enable port polling. */
1196 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1197 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1198 usb_hcd_poll_rh_status(xhci->shared_hcd);
1199 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1200 usb_hcd_poll_rh_status(hcd);
1204 EXPORT_SYMBOL_GPL(xhci_resume);
1205 #endif /* CONFIG_PM */
1207 /*-------------------------------------------------------------------------*/
1210 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1211 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1212 * value to right shift 1 for the bitmask.
1214 * Index = (epnum * 2) + direction - 1,
1215 * where direction = 0 for OUT, 1 for IN.
1216 * For control endpoints, the IN index is used (OUT index is unused), so
1217 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1219 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1222 if (usb_endpoint_xfer_control(desc))
1223 index = (unsigned int) (usb_endpoint_num(desc)*2);
1225 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1226 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1230 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1231 * address from the XHCI endpoint index.
1233 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1235 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1236 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1237 return direction | number;
1240 /* Find the flag for this endpoint (for use in the control context). Use the
1241 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1244 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1246 return 1 << (xhci_get_endpoint_index(desc) + 1);
1249 /* Find the flag for this endpoint (for use in the control context). Use the
1250 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1253 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1255 return 1 << (ep_index + 1);
1258 /* Compute the last valid endpoint context index. Basically, this is the
1259 * endpoint index plus one. For slot contexts with more than valid endpoint,
1260 * we find the most significant bit set in the added contexts flags.
1261 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1262 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1264 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1266 return fls(added_ctxs) - 1;
1269 /* Returns 1 if the arguments are OK;
1270 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1272 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1273 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1275 struct xhci_hcd *xhci;
1276 struct xhci_virt_device *virt_dev;
1278 if (!hcd || (check_ep && !ep) || !udev) {
1279 pr_debug("xHCI %s called with invalid args\n", func);
1282 if (!udev->parent) {
1283 pr_debug("xHCI %s called for root hub\n", func);
1287 xhci = hcd_to_xhci(hcd);
1288 if (check_virt_dev) {
1289 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1290 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1295 virt_dev = xhci->devs[udev->slot_id];
1296 if (virt_dev->udev != udev) {
1297 xhci_dbg(xhci, "xHCI %s called with udev and "
1298 "virt_dev does not match\n", func);
1303 if (xhci->xhc_state & XHCI_STATE_HALTED)
1309 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1310 struct usb_device *udev, struct xhci_command *command,
1311 bool ctx_change, bool must_succeed);
1314 * Full speed devices may have a max packet size greater than 8 bytes, but the
1315 * USB core doesn't know that until it reads the first 8 bytes of the
1316 * descriptor. If the usb_device's max packet size changes after that point,
1317 * we need to issue an evaluate context command and wait on it.
1319 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1320 unsigned int ep_index, struct urb *urb)
1322 struct xhci_container_ctx *out_ctx;
1323 struct xhci_input_control_ctx *ctrl_ctx;
1324 struct xhci_ep_ctx *ep_ctx;
1325 struct xhci_command *command;
1326 int max_packet_size;
1327 int hw_max_packet_size;
1330 out_ctx = xhci->devs[slot_id]->out_ctx;
1331 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1332 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1333 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1334 if (hw_max_packet_size != max_packet_size) {
1335 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1336 "Max Packet Size for ep 0 changed.");
1337 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1338 "Max packet size in usb_device = %d",
1340 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1341 "Max packet size in xHCI HW = %d",
1342 hw_max_packet_size);
1343 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1344 "Issuing evaluate context command.");
1346 /* Set up the input context flags for the command */
1347 /* FIXME: This won't work if a non-default control endpoint
1348 * changes max packet sizes.
1351 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1355 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1356 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1358 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1361 goto command_cleanup;
1363 /* Set up the modified control endpoint 0 */
1364 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1365 xhci->devs[slot_id]->out_ctx, ep_index);
1367 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1368 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1369 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1371 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1372 ctrl_ctx->drop_flags = 0;
1374 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1377 /* Clean up the input context for later use by bandwidth
1380 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1382 kfree(command->completion);
1389 * non-error returns are a promise to giveback() the urb later
1390 * we drop ownership so next owner (or urb unlink) can get it
1392 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1394 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1395 unsigned long flags;
1397 unsigned int slot_id, ep_index;
1398 unsigned int *ep_state;
1399 struct urb_priv *urb_priv;
1402 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1403 true, true, __func__) <= 0)
1406 slot_id = urb->dev->slot_id;
1407 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1408 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1410 if (!HCD_HW_ACCESSIBLE(hcd)) {
1411 if (!in_interrupt())
1412 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1416 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1417 num_tds = urb->number_of_packets;
1418 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1419 urb->transfer_buffer_length > 0 &&
1420 urb->transfer_flags & URB_ZERO_PACKET &&
1421 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1426 urb_priv = kzalloc(sizeof(struct urb_priv) +
1427 num_tds * sizeof(struct xhci_td), mem_flags);
1431 urb_priv->num_tds = num_tds;
1432 urb_priv->num_tds_done = 0;
1433 urb->hcpriv = urb_priv;
1435 trace_xhci_urb_enqueue(urb);
1437 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1438 /* Check to see if the max packet size for the default control
1439 * endpoint changed during FS device enumeration
1441 if (urb->dev->speed == USB_SPEED_FULL) {
1442 ret = xhci_check_maxpacket(xhci, slot_id,
1445 xhci_urb_free_priv(urb_priv);
1452 spin_lock_irqsave(&xhci->lock, flags);
1454 if (xhci->xhc_state & XHCI_STATE_DYING) {
1455 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1456 urb->ep->desc.bEndpointAddress, urb);
1460 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1461 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1466 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1467 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1472 switch (usb_endpoint_type(&urb->ep->desc)) {
1474 case USB_ENDPOINT_XFER_CONTROL:
1475 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1478 case USB_ENDPOINT_XFER_BULK:
1479 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1482 case USB_ENDPOINT_XFER_INT:
1483 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1486 case USB_ENDPOINT_XFER_ISOC:
1487 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1493 xhci_urb_free_priv(urb_priv);
1496 spin_unlock_irqrestore(&xhci->lock, flags);
1501 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1502 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1503 * should pick up where it left off in the TD, unless a Set Transfer Ring
1504 * Dequeue Pointer is issued.
1506 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1507 * the ring. Since the ring is a contiguous structure, they can't be physically
1508 * removed. Instead, there are two options:
1510 * 1) If the HC is in the middle of processing the URB to be canceled, we
1511 * simply move the ring's dequeue pointer past those TRBs using the Set
1512 * Transfer Ring Dequeue Pointer command. This will be the common case,
1513 * when drivers timeout on the last submitted URB and attempt to cancel.
1515 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1516 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1517 * HC will need to invalidate the any TRBs it has cached after the stop
1518 * endpoint command, as noted in the xHCI 0.95 errata.
1520 * 3) The TD may have completed by the time the Stop Endpoint Command
1521 * completes, so software needs to handle that case too.
1523 * This function should protect against the TD enqueueing code ringing the
1524 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1525 * It also needs to account for multiple cancellations on happening at the same
1526 * time for the same endpoint.
1528 * Note that this function can be called in any context, or so says
1529 * usb_hcd_unlink_urb()
1531 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1533 unsigned long flags;
1536 struct xhci_hcd *xhci;
1537 struct urb_priv *urb_priv;
1539 unsigned int ep_index;
1540 struct xhci_ring *ep_ring;
1541 struct xhci_virt_ep *ep;
1542 struct xhci_command *command;
1543 struct xhci_virt_device *vdev;
1545 xhci = hcd_to_xhci(hcd);
1546 spin_lock_irqsave(&xhci->lock, flags);
1548 trace_xhci_urb_dequeue(urb);
1550 /* Make sure the URB hasn't completed or been unlinked already */
1551 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1555 /* give back URB now if we can't queue it for cancel */
1556 vdev = xhci->devs[urb->dev->slot_id];
1557 urb_priv = urb->hcpriv;
1558 if (!vdev || !urb_priv)
1561 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1562 ep = &vdev->eps[ep_index];
1563 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1564 if (!ep || !ep_ring)
1567 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1568 temp = readl(&xhci->op_regs->status);
1569 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1574 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1575 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1576 "HC halted, freeing TD manually.");
1577 for (i = urb_priv->num_tds_done;
1578 i < urb_priv->num_tds;
1580 td = &urb_priv->td[i];
1581 if (!list_empty(&td->td_list))
1582 list_del_init(&td->td_list);
1583 if (!list_empty(&td->cancelled_td_list))
1584 list_del_init(&td->cancelled_td_list);
1589 i = urb_priv->num_tds_done;
1590 if (i < urb_priv->num_tds)
1591 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1592 "Cancel URB %p, dev %s, ep 0x%x, "
1593 "starting at offset 0x%llx",
1594 urb, urb->dev->devpath,
1595 urb->ep->desc.bEndpointAddress,
1596 (unsigned long long) xhci_trb_virt_to_dma(
1597 urb_priv->td[i].start_seg,
1598 urb_priv->td[i].first_trb));
1600 for (; i < urb_priv->num_tds; i++) {
1601 td = &urb_priv->td[i];
1602 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1605 /* Queue a stop endpoint command, but only if this is
1606 * the first cancellation to be handled.
1608 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1609 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1614 ep->ep_state |= EP_STOP_CMD_PENDING;
1615 ep->stop_cmd_timer.expires = jiffies +
1616 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1617 add_timer(&ep->stop_cmd_timer);
1618 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1620 xhci_ring_cmd_db(xhci);
1623 spin_unlock_irqrestore(&xhci->lock, flags);
1628 xhci_urb_free_priv(urb_priv);
1629 usb_hcd_unlink_urb_from_ep(hcd, urb);
1630 spin_unlock_irqrestore(&xhci->lock, flags);
1631 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1635 /* Drop an endpoint from a new bandwidth configuration for this device.
1636 * Only one call to this function is allowed per endpoint before
1637 * check_bandwidth() or reset_bandwidth() must be called.
1638 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1639 * add the endpoint to the schedule with possibly new parameters denoted by a
1640 * different endpoint descriptor in usb_host_endpoint.
1641 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1644 * The USB core will not allow URBs to be queued to an endpoint that is being
1645 * disabled, so there's no need for mutual exclusion to protect
1646 * the xhci->devs[slot_id] structure.
1648 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1649 struct usb_host_endpoint *ep)
1651 struct xhci_hcd *xhci;
1652 struct xhci_container_ctx *in_ctx, *out_ctx;
1653 struct xhci_input_control_ctx *ctrl_ctx;
1654 unsigned int ep_index;
1655 struct xhci_ep_ctx *ep_ctx;
1657 u32 new_add_flags, new_drop_flags;
1660 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1663 xhci = hcd_to_xhci(hcd);
1664 if (xhci->xhc_state & XHCI_STATE_DYING)
1667 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1668 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1669 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1670 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1671 __func__, drop_flag);
1675 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1676 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1677 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1679 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1684 ep_index = xhci_get_endpoint_index(&ep->desc);
1685 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1686 /* If the HC already knows the endpoint is disabled,
1687 * or the HCD has noted it is disabled, ignore this request
1689 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1690 le32_to_cpu(ctrl_ctx->drop_flags) &
1691 xhci_get_endpoint_flag(&ep->desc)) {
1692 /* Do not warn when called after a usb_device_reset */
1693 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1694 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1699 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1700 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1702 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1703 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1705 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1707 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1709 if (xhci->quirks & XHCI_MTK_HOST)
1710 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1712 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1713 (unsigned int) ep->desc.bEndpointAddress,
1715 (unsigned int) new_drop_flags,
1716 (unsigned int) new_add_flags);
1720 /* Add an endpoint to a new possible bandwidth configuration for this device.
1721 * Only one call to this function is allowed per endpoint before
1722 * check_bandwidth() or reset_bandwidth() must be called.
1723 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1724 * add the endpoint to the schedule with possibly new parameters denoted by a
1725 * different endpoint descriptor in usb_host_endpoint.
1726 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1729 * The USB core will not allow URBs to be queued to an endpoint until the
1730 * configuration or alt setting is installed in the device, so there's no need
1731 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1733 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1734 struct usb_host_endpoint *ep)
1736 struct xhci_hcd *xhci;
1737 struct xhci_container_ctx *in_ctx;
1738 unsigned int ep_index;
1739 struct xhci_input_control_ctx *ctrl_ctx;
1741 u32 new_add_flags, new_drop_flags;
1742 struct xhci_virt_device *virt_dev;
1745 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1747 /* So we won't queue a reset ep command for a root hub */
1751 xhci = hcd_to_xhci(hcd);
1752 if (xhci->xhc_state & XHCI_STATE_DYING)
1755 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1756 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1757 /* FIXME when we have to issue an evaluate endpoint command to
1758 * deal with ep0 max packet size changing once we get the
1761 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1762 __func__, added_ctxs);
1766 virt_dev = xhci->devs[udev->slot_id];
1767 in_ctx = virt_dev->in_ctx;
1768 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1770 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1775 ep_index = xhci_get_endpoint_index(&ep->desc);
1776 /* If this endpoint is already in use, and the upper layers are trying
1777 * to add it again without dropping it, reject the addition.
1779 if (virt_dev->eps[ep_index].ring &&
1780 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1781 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1782 "without dropping it.\n",
1783 (unsigned int) ep->desc.bEndpointAddress);
1787 /* If the HCD has already noted the endpoint is enabled,
1788 * ignore this request.
1790 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1791 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1797 * Configuration and alternate setting changes must be done in
1798 * process context, not interrupt context (or so documenation
1799 * for usb_set_interface() and usb_set_configuration() claim).
1801 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1802 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1803 __func__, ep->desc.bEndpointAddress);
1807 if (xhci->quirks & XHCI_MTK_HOST) {
1808 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1810 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1811 virt_dev->eps[ep_index].new_ring = NULL;
1816 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1817 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1819 /* If xhci_endpoint_disable() was called for this endpoint, but the
1820 * xHC hasn't been notified yet through the check_bandwidth() call,
1821 * this re-adds a new state for the endpoint from the new endpoint
1822 * descriptors. We must drop and re-add this endpoint, so we leave the
1825 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1827 /* Store the usb_device pointer for later use */
1830 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1832 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1833 (unsigned int) ep->desc.bEndpointAddress,
1835 (unsigned int) new_drop_flags,
1836 (unsigned int) new_add_flags);
1840 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1842 struct xhci_input_control_ctx *ctrl_ctx;
1843 struct xhci_ep_ctx *ep_ctx;
1844 struct xhci_slot_ctx *slot_ctx;
1847 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1849 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1854 /* When a device's add flag and drop flag are zero, any subsequent
1855 * configure endpoint command will leave that endpoint's state
1856 * untouched. Make sure we don't leave any old state in the input
1857 * endpoint contexts.
1859 ctrl_ctx->drop_flags = 0;
1860 ctrl_ctx->add_flags = 0;
1861 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1862 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1863 /* Endpoint 0 is always valid */
1864 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1865 for (i = 1; i < 31; i++) {
1866 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1867 ep_ctx->ep_info = 0;
1868 ep_ctx->ep_info2 = 0;
1870 ep_ctx->tx_info = 0;
1874 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1875 struct usb_device *udev, u32 *cmd_status)
1879 switch (*cmd_status) {
1880 case COMP_COMMAND_ABORTED:
1881 case COMP_COMMAND_RING_STOPPED:
1882 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1885 case COMP_RESOURCE_ERROR:
1886 dev_warn(&udev->dev,
1887 "Not enough host controller resources for new device state.\n");
1889 /* FIXME: can we allocate more resources for the HC? */
1891 case COMP_BANDWIDTH_ERROR:
1892 case COMP_SECONDARY_BANDWIDTH_ERROR:
1893 dev_warn(&udev->dev,
1894 "Not enough bandwidth for new device state.\n");
1896 /* FIXME: can we go back to the old state? */
1898 case COMP_TRB_ERROR:
1899 /* the HCD set up something wrong */
1900 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1902 "and endpoint is not disabled.\n");
1905 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1906 dev_warn(&udev->dev,
1907 "ERROR: Incompatible device for endpoint configure command.\n");
1911 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1912 "Successful Endpoint Configure command");
1916 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1924 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1925 struct usb_device *udev, u32 *cmd_status)
1929 switch (*cmd_status) {
1930 case COMP_COMMAND_ABORTED:
1931 case COMP_COMMAND_RING_STOPPED:
1932 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1935 case COMP_PARAMETER_ERROR:
1936 dev_warn(&udev->dev,
1937 "WARN: xHCI driver setup invalid evaluate context command.\n");
1940 case COMP_SLOT_NOT_ENABLED_ERROR:
1941 dev_warn(&udev->dev,
1942 "WARN: slot not enabled for evaluate context command.\n");
1945 case COMP_CONTEXT_STATE_ERROR:
1946 dev_warn(&udev->dev,
1947 "WARN: invalid context state for evaluate context command.\n");
1950 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1951 dev_warn(&udev->dev,
1952 "ERROR: Incompatible device for evaluate context command.\n");
1955 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1956 /* Max Exit Latency too large error */
1957 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1961 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1962 "Successful evaluate context command");
1966 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1974 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1975 struct xhci_input_control_ctx *ctrl_ctx)
1977 u32 valid_add_flags;
1978 u32 valid_drop_flags;
1980 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1981 * (bit 1). The default control endpoint is added during the Address
1982 * Device command and is never removed until the slot is disabled.
1984 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1985 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1987 /* Use hweight32 to count the number of ones in the add flags, or
1988 * number of endpoints added. Don't count endpoints that are changed
1989 * (both added and dropped).
1991 return hweight32(valid_add_flags) -
1992 hweight32(valid_add_flags & valid_drop_flags);
1995 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1996 struct xhci_input_control_ctx *ctrl_ctx)
1998 u32 valid_add_flags;
1999 u32 valid_drop_flags;
2001 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2002 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2004 return hweight32(valid_drop_flags) -
2005 hweight32(valid_add_flags & valid_drop_flags);
2009 * We need to reserve the new number of endpoints before the configure endpoint
2010 * command completes. We can't subtract the dropped endpoints from the number
2011 * of active endpoints until the command completes because we can oversubscribe
2012 * the host in this case:
2014 * - the first configure endpoint command drops more endpoints than it adds
2015 * - a second configure endpoint command that adds more endpoints is queued
2016 * - the first configure endpoint command fails, so the config is unchanged
2017 * - the second command may succeed, even though there isn't enough resources
2019 * Must be called with xhci->lock held.
2021 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2022 struct xhci_input_control_ctx *ctrl_ctx)
2026 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2027 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2028 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2029 "Not enough ep ctxs: "
2030 "%u active, need to add %u, limit is %u.",
2031 xhci->num_active_eps, added_eps,
2032 xhci->limit_active_eps);
2035 xhci->num_active_eps += added_eps;
2036 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2037 "Adding %u ep ctxs, %u now active.", added_eps,
2038 xhci->num_active_eps);
2043 * The configure endpoint was failed by the xHC for some other reason, so we
2044 * need to revert the resources that failed configuration would have used.
2046 * Must be called with xhci->lock held.
2048 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2049 struct xhci_input_control_ctx *ctrl_ctx)
2053 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2054 xhci->num_active_eps -= num_failed_eps;
2055 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2056 "Removing %u failed ep ctxs, %u now active.",
2058 xhci->num_active_eps);
2062 * Now that the command has completed, clean up the active endpoint count by
2063 * subtracting out the endpoints that were dropped (but not changed).
2065 * Must be called with xhci->lock held.
2067 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2068 struct xhci_input_control_ctx *ctrl_ctx)
2070 u32 num_dropped_eps;
2072 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2073 xhci->num_active_eps -= num_dropped_eps;
2074 if (num_dropped_eps)
2075 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2076 "Removing %u dropped ep ctxs, %u now active.",
2078 xhci->num_active_eps);
2081 static unsigned int xhci_get_block_size(struct usb_device *udev)
2083 switch (udev->speed) {
2085 case USB_SPEED_FULL:
2087 case USB_SPEED_HIGH:
2089 case USB_SPEED_SUPER:
2090 case USB_SPEED_SUPER_PLUS:
2092 case USB_SPEED_UNKNOWN:
2093 case USB_SPEED_WIRELESS:
2095 /* Should never happen */
2101 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2103 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2105 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2110 /* If we are changing a LS/FS device under a HS hub,
2111 * make sure (if we are activating a new TT) that the HS bus has enough
2112 * bandwidth for this new TT.
2114 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2115 struct xhci_virt_device *virt_dev,
2118 struct xhci_interval_bw_table *bw_table;
2119 struct xhci_tt_bw_info *tt_info;
2121 /* Find the bandwidth table for the root port this TT is attached to. */
2122 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2123 tt_info = virt_dev->tt_info;
2124 /* If this TT already had active endpoints, the bandwidth for this TT
2125 * has already been added. Removing all periodic endpoints (and thus
2126 * making the TT enactive) will only decrease the bandwidth used.
2130 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2131 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2135 /* Not sure why we would have no new active endpoints...
2137 * Maybe because of an Evaluate Context change for a hub update or a
2138 * control endpoint 0 max packet size change?
2139 * FIXME: skip the bandwidth calculation in that case.
2144 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2145 struct xhci_virt_device *virt_dev)
2147 unsigned int bw_reserved;
2149 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2150 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2153 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2154 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2161 * This algorithm is a very conservative estimate of the worst-case scheduling
2162 * scenario for any one interval. The hardware dynamically schedules the
2163 * packets, so we can't tell which microframe could be the limiting factor in
2164 * the bandwidth scheduling. This only takes into account periodic endpoints.
2166 * Obviously, we can't solve an NP complete problem to find the minimum worst
2167 * case scenario. Instead, we come up with an estimate that is no less than
2168 * the worst case bandwidth used for any one microframe, but may be an
2171 * We walk the requirements for each endpoint by interval, starting with the
2172 * smallest interval, and place packets in the schedule where there is only one
2173 * possible way to schedule packets for that interval. In order to simplify
2174 * this algorithm, we record the largest max packet size for each interval, and
2175 * assume all packets will be that size.
2177 * For interval 0, we obviously must schedule all packets for each interval.
2178 * The bandwidth for interval 0 is just the amount of data to be transmitted
2179 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2180 * the number of packets).
2182 * For interval 1, we have two possible microframes to schedule those packets
2183 * in. For this algorithm, if we can schedule the same number of packets for
2184 * each possible scheduling opportunity (each microframe), we will do so. The
2185 * remaining number of packets will be saved to be transmitted in the gaps in
2186 * the next interval's scheduling sequence.
2188 * As we move those remaining packets to be scheduled with interval 2 packets,
2189 * we have to double the number of remaining packets to transmit. This is
2190 * because the intervals are actually powers of 2, and we would be transmitting
2191 * the previous interval's packets twice in this interval. We also have to be
2192 * sure that when we look at the largest max packet size for this interval, we
2193 * also look at the largest max packet size for the remaining packets and take
2194 * the greater of the two.
2196 * The algorithm continues to evenly distribute packets in each scheduling
2197 * opportunity, and push the remaining packets out, until we get to the last
2198 * interval. Then those packets and their associated overhead are just added
2199 * to the bandwidth used.
2201 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2202 struct xhci_virt_device *virt_dev,
2205 unsigned int bw_reserved;
2206 unsigned int max_bandwidth;
2207 unsigned int bw_used;
2208 unsigned int block_size;
2209 struct xhci_interval_bw_table *bw_table;
2210 unsigned int packet_size = 0;
2211 unsigned int overhead = 0;
2212 unsigned int packets_transmitted = 0;
2213 unsigned int packets_remaining = 0;
2216 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2217 return xhci_check_ss_bw(xhci, virt_dev);
2219 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2220 max_bandwidth = HS_BW_LIMIT;
2221 /* Convert percent of bus BW reserved to blocks reserved */
2222 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2224 max_bandwidth = FS_BW_LIMIT;
2225 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2228 bw_table = virt_dev->bw_table;
2229 /* We need to translate the max packet size and max ESIT payloads into
2230 * the units the hardware uses.
2232 block_size = xhci_get_block_size(virt_dev->udev);
2234 /* If we are manipulating a LS/FS device under a HS hub, double check
2235 * that the HS bus has enough bandwidth if we are activing a new TT.
2237 if (virt_dev->tt_info) {
2238 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2239 "Recalculating BW for rootport %u",
2240 virt_dev->real_port);
2241 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2242 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2243 "newly activated TT.\n");
2246 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2247 "Recalculating BW for TT slot %u port %u",
2248 virt_dev->tt_info->slot_id,
2249 virt_dev->tt_info->ttport);
2251 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2252 "Recalculating BW for rootport %u",
2253 virt_dev->real_port);
2256 /* Add in how much bandwidth will be used for interval zero, or the
2257 * rounded max ESIT payload + number of packets * largest overhead.
2259 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2260 bw_table->interval_bw[0].num_packets *
2261 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2263 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2264 unsigned int bw_added;
2265 unsigned int largest_mps;
2266 unsigned int interval_overhead;
2269 * How many packets could we transmit in this interval?
2270 * If packets didn't fit in the previous interval, we will need
2271 * to transmit that many packets twice within this interval.
2273 packets_remaining = 2 * packets_remaining +
2274 bw_table->interval_bw[i].num_packets;
2276 /* Find the largest max packet size of this or the previous
2279 if (list_empty(&bw_table->interval_bw[i].endpoints))
2282 struct xhci_virt_ep *virt_ep;
2283 struct list_head *ep_entry;
2285 ep_entry = bw_table->interval_bw[i].endpoints.next;
2286 virt_ep = list_entry(ep_entry,
2287 struct xhci_virt_ep, bw_endpoint_list);
2288 /* Convert to blocks, rounding up */
2289 largest_mps = DIV_ROUND_UP(
2290 virt_ep->bw_info.max_packet_size,
2293 if (largest_mps > packet_size)
2294 packet_size = largest_mps;
2296 /* Use the larger overhead of this or the previous interval. */
2297 interval_overhead = xhci_get_largest_overhead(
2298 &bw_table->interval_bw[i]);
2299 if (interval_overhead > overhead)
2300 overhead = interval_overhead;
2302 /* How many packets can we evenly distribute across
2303 * (1 << (i + 1)) possible scheduling opportunities?
2305 packets_transmitted = packets_remaining >> (i + 1);
2307 /* Add in the bandwidth used for those scheduled packets */
2308 bw_added = packets_transmitted * (overhead + packet_size);
2310 /* How many packets do we have remaining to transmit? */
2311 packets_remaining = packets_remaining % (1 << (i + 1));
2313 /* What largest max packet size should those packets have? */
2314 /* If we've transmitted all packets, don't carry over the
2315 * largest packet size.
2317 if (packets_remaining == 0) {
2320 } else if (packets_transmitted > 0) {
2321 /* Otherwise if we do have remaining packets, and we've
2322 * scheduled some packets in this interval, take the
2323 * largest max packet size from endpoints with this
2326 packet_size = largest_mps;
2327 overhead = interval_overhead;
2329 /* Otherwise carry over packet_size and overhead from the last
2330 * time we had a remainder.
2332 bw_used += bw_added;
2333 if (bw_used > max_bandwidth) {
2334 xhci_warn(xhci, "Not enough bandwidth. "
2335 "Proposed: %u, Max: %u\n",
2336 bw_used, max_bandwidth);
2341 * Ok, we know we have some packets left over after even-handedly
2342 * scheduling interval 15. We don't know which microframes they will
2343 * fit into, so we over-schedule and say they will be scheduled every
2346 if (packets_remaining > 0)
2347 bw_used += overhead + packet_size;
2349 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2350 unsigned int port_index = virt_dev->real_port - 1;
2352 /* OK, we're manipulating a HS device attached to a
2353 * root port bandwidth domain. Include the number of active TTs
2354 * in the bandwidth used.
2356 bw_used += TT_HS_OVERHEAD *
2357 xhci->rh_bw[port_index].num_active_tts;
2360 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2361 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2362 "Available: %u " "percent",
2363 bw_used, max_bandwidth, bw_reserved,
2364 (max_bandwidth - bw_used - bw_reserved) * 100 /
2367 bw_used += bw_reserved;
2368 if (bw_used > max_bandwidth) {
2369 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2370 bw_used, max_bandwidth);
2374 bw_table->bw_used = bw_used;
2378 static bool xhci_is_async_ep(unsigned int ep_type)
2380 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2381 ep_type != ISOC_IN_EP &&
2382 ep_type != INT_IN_EP);
2385 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2387 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2390 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2392 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2394 if (ep_bw->ep_interval == 0)
2395 return SS_OVERHEAD_BURST +
2396 (ep_bw->mult * ep_bw->num_packets *
2397 (SS_OVERHEAD + mps));
2398 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2399 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2400 1 << ep_bw->ep_interval);
2404 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2405 struct xhci_bw_info *ep_bw,
2406 struct xhci_interval_bw_table *bw_table,
2407 struct usb_device *udev,
2408 struct xhci_virt_ep *virt_ep,
2409 struct xhci_tt_bw_info *tt_info)
2411 struct xhci_interval_bw *interval_bw;
2412 int normalized_interval;
2414 if (xhci_is_async_ep(ep_bw->type))
2417 if (udev->speed >= USB_SPEED_SUPER) {
2418 if (xhci_is_sync_in_ep(ep_bw->type))
2419 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2420 xhci_get_ss_bw_consumed(ep_bw);
2422 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2423 xhci_get_ss_bw_consumed(ep_bw);
2427 /* SuperSpeed endpoints never get added to intervals in the table, so
2428 * this check is only valid for HS/FS/LS devices.
2430 if (list_empty(&virt_ep->bw_endpoint_list))
2432 /* For LS/FS devices, we need to translate the interval expressed in
2433 * microframes to frames.
2435 if (udev->speed == USB_SPEED_HIGH)
2436 normalized_interval = ep_bw->ep_interval;
2438 normalized_interval = ep_bw->ep_interval - 3;
2440 if (normalized_interval == 0)
2441 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2442 interval_bw = &bw_table->interval_bw[normalized_interval];
2443 interval_bw->num_packets -= ep_bw->num_packets;
2444 switch (udev->speed) {
2446 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2448 case USB_SPEED_FULL:
2449 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2451 case USB_SPEED_HIGH:
2452 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2454 case USB_SPEED_SUPER:
2455 case USB_SPEED_SUPER_PLUS:
2456 case USB_SPEED_UNKNOWN:
2457 case USB_SPEED_WIRELESS:
2458 /* Should never happen because only LS/FS/HS endpoints will get
2459 * added to the endpoint list.
2464 tt_info->active_eps -= 1;
2465 list_del_init(&virt_ep->bw_endpoint_list);
2468 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2469 struct xhci_bw_info *ep_bw,
2470 struct xhci_interval_bw_table *bw_table,
2471 struct usb_device *udev,
2472 struct xhci_virt_ep *virt_ep,
2473 struct xhci_tt_bw_info *tt_info)
2475 struct xhci_interval_bw *interval_bw;
2476 struct xhci_virt_ep *smaller_ep;
2477 int normalized_interval;
2479 if (xhci_is_async_ep(ep_bw->type))
2482 if (udev->speed == USB_SPEED_SUPER) {
2483 if (xhci_is_sync_in_ep(ep_bw->type))
2484 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2485 xhci_get_ss_bw_consumed(ep_bw);
2487 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2488 xhci_get_ss_bw_consumed(ep_bw);
2492 /* For LS/FS devices, we need to translate the interval expressed in
2493 * microframes to frames.
2495 if (udev->speed == USB_SPEED_HIGH)
2496 normalized_interval = ep_bw->ep_interval;
2498 normalized_interval = ep_bw->ep_interval - 3;
2500 if (normalized_interval == 0)
2501 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2502 interval_bw = &bw_table->interval_bw[normalized_interval];
2503 interval_bw->num_packets += ep_bw->num_packets;
2504 switch (udev->speed) {
2506 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2508 case USB_SPEED_FULL:
2509 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2511 case USB_SPEED_HIGH:
2512 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2514 case USB_SPEED_SUPER:
2515 case USB_SPEED_SUPER_PLUS:
2516 case USB_SPEED_UNKNOWN:
2517 case USB_SPEED_WIRELESS:
2518 /* Should never happen because only LS/FS/HS endpoints will get
2519 * added to the endpoint list.
2525 tt_info->active_eps += 1;
2526 /* Insert the endpoint into the list, largest max packet size first. */
2527 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2529 if (ep_bw->max_packet_size >=
2530 smaller_ep->bw_info.max_packet_size) {
2531 /* Add the new ep before the smaller endpoint */
2532 list_add_tail(&virt_ep->bw_endpoint_list,
2533 &smaller_ep->bw_endpoint_list);
2537 /* Add the new endpoint at the end of the list. */
2538 list_add_tail(&virt_ep->bw_endpoint_list,
2539 &interval_bw->endpoints);
2542 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2543 struct xhci_virt_device *virt_dev,
2546 struct xhci_root_port_bw_info *rh_bw_info;
2547 if (!virt_dev->tt_info)
2550 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2551 if (old_active_eps == 0 &&
2552 virt_dev->tt_info->active_eps != 0) {
2553 rh_bw_info->num_active_tts += 1;
2554 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2555 } else if (old_active_eps != 0 &&
2556 virt_dev->tt_info->active_eps == 0) {
2557 rh_bw_info->num_active_tts -= 1;
2558 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2562 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2563 struct xhci_virt_device *virt_dev,
2564 struct xhci_container_ctx *in_ctx)
2566 struct xhci_bw_info ep_bw_info[31];
2568 struct xhci_input_control_ctx *ctrl_ctx;
2569 int old_active_eps = 0;
2571 if (virt_dev->tt_info)
2572 old_active_eps = virt_dev->tt_info->active_eps;
2574 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2576 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2581 for (i = 0; i < 31; i++) {
2582 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2585 /* Make a copy of the BW info in case we need to revert this */
2586 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2587 sizeof(ep_bw_info[i]));
2588 /* Drop the endpoint from the interval table if the endpoint is
2589 * being dropped or changed.
2591 if (EP_IS_DROPPED(ctrl_ctx, i))
2592 xhci_drop_ep_from_interval_table(xhci,
2593 &virt_dev->eps[i].bw_info,
2599 /* Overwrite the information stored in the endpoints' bw_info */
2600 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2601 for (i = 0; i < 31; i++) {
2602 /* Add any changed or added endpoints to the interval table */
2603 if (EP_IS_ADDED(ctrl_ctx, i))
2604 xhci_add_ep_to_interval_table(xhci,
2605 &virt_dev->eps[i].bw_info,
2612 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2613 /* Ok, this fits in the bandwidth we have.
2614 * Update the number of active TTs.
2616 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2620 /* We don't have enough bandwidth for this, revert the stored info. */
2621 for (i = 0; i < 31; i++) {
2622 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2625 /* Drop the new copies of any added or changed endpoints from
2626 * the interval table.
2628 if (EP_IS_ADDED(ctrl_ctx, i)) {
2629 xhci_drop_ep_from_interval_table(xhci,
2630 &virt_dev->eps[i].bw_info,
2636 /* Revert the endpoint back to its old information */
2637 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2638 sizeof(ep_bw_info[i]));
2639 /* Add any changed or dropped endpoints back into the table */
2640 if (EP_IS_DROPPED(ctrl_ctx, i))
2641 xhci_add_ep_to_interval_table(xhci,
2642 &virt_dev->eps[i].bw_info,
2652 /* Issue a configure endpoint command or evaluate context command
2653 * and wait for it to finish.
2655 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2656 struct usb_device *udev,
2657 struct xhci_command *command,
2658 bool ctx_change, bool must_succeed)
2661 unsigned long flags;
2662 struct xhci_input_control_ctx *ctrl_ctx;
2663 struct xhci_virt_device *virt_dev;
2664 struct xhci_slot_ctx *slot_ctx;
2669 spin_lock_irqsave(&xhci->lock, flags);
2671 if (xhci->xhc_state & XHCI_STATE_DYING) {
2672 spin_unlock_irqrestore(&xhci->lock, flags);
2676 virt_dev = xhci->devs[udev->slot_id];
2678 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2680 spin_unlock_irqrestore(&xhci->lock, flags);
2681 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2686 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2687 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2688 spin_unlock_irqrestore(&xhci->lock, flags);
2689 xhci_warn(xhci, "Not enough host resources, "
2690 "active endpoint contexts = %u\n",
2691 xhci->num_active_eps);
2694 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2695 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2696 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2697 xhci_free_host_resources(xhci, ctrl_ctx);
2698 spin_unlock_irqrestore(&xhci->lock, flags);
2699 xhci_warn(xhci, "Not enough bandwidth\n");
2703 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2704 trace_xhci_configure_endpoint(slot_ctx);
2707 ret = xhci_queue_configure_endpoint(xhci, command,
2708 command->in_ctx->dma,
2709 udev->slot_id, must_succeed);
2711 ret = xhci_queue_evaluate_context(xhci, command,
2712 command->in_ctx->dma,
2713 udev->slot_id, must_succeed);
2715 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2716 xhci_free_host_resources(xhci, ctrl_ctx);
2717 spin_unlock_irqrestore(&xhci->lock, flags);
2718 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2719 "FIXME allocate a new ring segment");
2722 xhci_ring_cmd_db(xhci);
2723 spin_unlock_irqrestore(&xhci->lock, flags);
2725 /* Wait for the configure endpoint command to complete */
2726 wait_for_completion(command->completion);
2729 ret = xhci_configure_endpoint_result(xhci, udev,
2732 ret = xhci_evaluate_context_result(xhci, udev,
2735 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2736 spin_lock_irqsave(&xhci->lock, flags);
2737 /* If the command failed, remove the reserved resources.
2738 * Otherwise, clean up the estimate to include dropped eps.
2741 xhci_free_host_resources(xhci, ctrl_ctx);
2743 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2744 spin_unlock_irqrestore(&xhci->lock, flags);
2749 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2750 struct xhci_virt_device *vdev, int i)
2752 struct xhci_virt_ep *ep = &vdev->eps[i];
2754 if (ep->ep_state & EP_HAS_STREAMS) {
2755 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2756 xhci_get_endpoint_address(i));
2757 xhci_free_stream_info(xhci, ep->stream_info);
2758 ep->stream_info = NULL;
2759 ep->ep_state &= ~EP_HAS_STREAMS;
2763 /* Called after one or more calls to xhci_add_endpoint() or
2764 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2765 * to call xhci_reset_bandwidth().
2767 * Since we are in the middle of changing either configuration or
2768 * installing a new alt setting, the USB core won't allow URBs to be
2769 * enqueued for any endpoint on the old config or interface. Nothing
2770 * else should be touching the xhci->devs[slot_id] structure, so we
2771 * don't need to take the xhci->lock for manipulating that.
2773 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2777 struct xhci_hcd *xhci;
2778 struct xhci_virt_device *virt_dev;
2779 struct xhci_input_control_ctx *ctrl_ctx;
2780 struct xhci_slot_ctx *slot_ctx;
2781 struct xhci_command *command;
2783 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2786 xhci = hcd_to_xhci(hcd);
2787 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2788 (xhci->xhc_state & XHCI_STATE_REMOVING))
2791 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2792 virt_dev = xhci->devs[udev->slot_id];
2794 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2798 command->in_ctx = virt_dev->in_ctx;
2800 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2801 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2803 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2806 goto command_cleanup;
2808 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2809 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2810 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2812 /* Don't issue the command if there's no endpoints to update. */
2813 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2814 ctrl_ctx->drop_flags == 0) {
2816 goto command_cleanup;
2818 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2819 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2820 for (i = 31; i >= 1; i--) {
2821 __le32 le32 = cpu_to_le32(BIT(i));
2823 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2824 || (ctrl_ctx->add_flags & le32) || i == 1) {
2825 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2826 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2831 ret = xhci_configure_endpoint(xhci, udev, command,
2834 /* Callee should call reset_bandwidth() */
2835 goto command_cleanup;
2837 /* Free any rings that were dropped, but not changed. */
2838 for (i = 1; i < 31; i++) {
2839 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2840 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2841 xhci_free_endpoint_ring(xhci, virt_dev, i);
2842 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2845 xhci_zero_in_ctx(xhci, virt_dev);
2847 * Install any rings for completely new endpoints or changed endpoints,
2848 * and free any old rings from changed endpoints.
2850 for (i = 1; i < 31; i++) {
2851 if (!virt_dev->eps[i].new_ring)
2853 /* Only free the old ring if it exists.
2854 * It may not if this is the first add of an endpoint.
2856 if (virt_dev->eps[i].ring) {
2857 xhci_free_endpoint_ring(xhci, virt_dev, i);
2859 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2860 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2861 virt_dev->eps[i].new_ring = NULL;
2864 kfree(command->completion);
2870 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2872 struct xhci_hcd *xhci;
2873 struct xhci_virt_device *virt_dev;
2876 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2879 xhci = hcd_to_xhci(hcd);
2881 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2882 virt_dev = xhci->devs[udev->slot_id];
2883 /* Free any rings allocated for added endpoints */
2884 for (i = 0; i < 31; i++) {
2885 if (virt_dev->eps[i].new_ring) {
2886 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2887 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2888 virt_dev->eps[i].new_ring = NULL;
2891 xhci_zero_in_ctx(xhci, virt_dev);
2894 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2895 struct xhci_container_ctx *in_ctx,
2896 struct xhci_container_ctx *out_ctx,
2897 struct xhci_input_control_ctx *ctrl_ctx,
2898 u32 add_flags, u32 drop_flags)
2900 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2901 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2902 xhci_slot_copy(xhci, in_ctx, out_ctx);
2903 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2906 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2907 unsigned int slot_id, unsigned int ep_index,
2908 struct xhci_dequeue_state *deq_state)
2910 struct xhci_input_control_ctx *ctrl_ctx;
2911 struct xhci_container_ctx *in_ctx;
2912 struct xhci_ep_ctx *ep_ctx;
2916 in_ctx = xhci->devs[slot_id]->in_ctx;
2917 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2919 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2924 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2925 xhci->devs[slot_id]->out_ctx, ep_index);
2926 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2927 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2928 deq_state->new_deq_ptr);
2930 xhci_warn(xhci, "WARN Cannot submit config ep after "
2931 "reset ep command\n");
2932 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2933 deq_state->new_deq_seg,
2934 deq_state->new_deq_ptr);
2937 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2939 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2940 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2941 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2942 added_ctxs, added_ctxs);
2945 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2946 unsigned int stream_id, struct xhci_td *td)
2948 struct xhci_dequeue_state deq_state;
2949 struct usb_device *udev = td->urb->dev;
2951 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2952 "Cleaning up stalled endpoint ring");
2953 /* We need to move the HW's dequeue pointer past this TD,
2954 * or it will attempt to resend it on the next doorbell ring.
2956 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2957 ep_index, stream_id, td, &deq_state);
2959 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2962 /* HW with the reset endpoint quirk will use the saved dequeue state to
2963 * issue a configure endpoint command later.
2965 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2966 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2967 "Queueing new dequeue state");
2968 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2969 ep_index, &deq_state);
2971 /* Better hope no one uses the input context between now and the
2972 * reset endpoint completion!
2973 * XXX: No idea how this hardware will react when stream rings
2976 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2977 "Setting up input context for "
2978 "configure endpoint command");
2979 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2980 ep_index, &deq_state);
2985 * Called after usb core issues a clear halt control message.
2986 * The host side of the halt should already be cleared by a reset endpoint
2987 * command issued when the STALL event was received.
2989 * The reset endpoint command may only be issued to endpoints in the halted
2990 * state. For software that wishes to reset the data toggle or sequence number
2991 * of an endpoint that isn't in the halted state this function will issue a
2992 * configure endpoint command with the Drop and Add bits set for the target
2993 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
2996 static void xhci_endpoint_reset(struct usb_hcd *hcd,
2997 struct usb_host_endpoint *host_ep)
2999 struct xhci_hcd *xhci;
3000 struct usb_device *udev;
3001 struct xhci_virt_device *vdev;
3002 struct xhci_virt_ep *ep;
3003 struct xhci_input_control_ctx *ctrl_ctx;
3004 struct xhci_command *stop_cmd, *cfg_cmd;
3005 unsigned int ep_index;
3006 unsigned long flags;
3009 xhci = hcd_to_xhci(hcd);
3010 if (!host_ep->hcpriv)
3012 udev = (struct usb_device *) host_ep->hcpriv;
3013 vdev = xhci->devs[udev->slot_id];
3014 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3015 ep = &vdev->eps[ep_index];
3017 /* Bail out if toggle is already being cleared by a endpoint reset */
3018 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3019 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3022 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3023 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3024 usb_endpoint_xfer_isoc(&host_ep->desc))
3027 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3029 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3032 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3036 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3040 spin_lock_irqsave(&xhci->lock, flags);
3042 /* block queuing new trbs and ringing ep doorbell */
3043 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3046 * Make sure endpoint ring is empty before resetting the toggle/seq.
3047 * Driver is required to synchronously cancel all transfer request.
3048 * Stop the endpoint to force xHC to update the output context
3051 if (!list_empty(&ep->ring->td_list)) {
3052 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3053 spin_unlock_irqrestore(&xhci->lock, flags);
3054 xhci_free_command(xhci, cfg_cmd);
3057 xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
3058 xhci_ring_cmd_db(xhci);
3059 spin_unlock_irqrestore(&xhci->lock, flags);
3061 wait_for_completion(stop_cmd->completion);
3063 spin_lock_irqsave(&xhci->lock, flags);
3065 /* config ep command clears toggle if add and drop ep flags are set */
3066 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3067 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3068 ctrl_ctx, ep_flag, ep_flag);
3069 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3071 xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3072 udev->slot_id, false);
3073 xhci_ring_cmd_db(xhci);
3074 spin_unlock_irqrestore(&xhci->lock, flags);
3076 wait_for_completion(cfg_cmd->completion);
3078 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3079 xhci_free_command(xhci, cfg_cmd);
3081 xhci_free_command(xhci, stop_cmd);
3084 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3085 struct usb_device *udev, struct usb_host_endpoint *ep,
3086 unsigned int slot_id)
3089 unsigned int ep_index;
3090 unsigned int ep_state;
3094 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3097 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3098 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3099 " descriptor for ep 0x%x does not support streams\n",
3100 ep->desc.bEndpointAddress);
3104 ep_index = xhci_get_endpoint_index(&ep->desc);
3105 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3106 if (ep_state & EP_HAS_STREAMS ||
3107 ep_state & EP_GETTING_STREAMS) {
3108 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3109 "already has streams set up.\n",
3110 ep->desc.bEndpointAddress);
3111 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3112 "dynamic stream context array reallocation.\n");
3115 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3116 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3117 "endpoint 0x%x; URBs are pending.\n",
3118 ep->desc.bEndpointAddress);
3124 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3125 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3127 unsigned int max_streams;
3129 /* The stream context array size must be a power of two */
3130 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3132 * Find out how many primary stream array entries the host controller
3133 * supports. Later we may use secondary stream arrays (similar to 2nd
3134 * level page entries), but that's an optional feature for xHCI host
3135 * controllers. xHCs must support at least 4 stream IDs.
3137 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3138 if (*num_stream_ctxs > max_streams) {
3139 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3141 *num_stream_ctxs = max_streams;
3142 *num_streams = max_streams;
3146 /* Returns an error code if one of the endpoint already has streams.
3147 * This does not change any data structures, it only checks and gathers
3150 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3151 struct usb_device *udev,
3152 struct usb_host_endpoint **eps, unsigned int num_eps,
3153 unsigned int *num_streams, u32 *changed_ep_bitmask)
3155 unsigned int max_streams;
3156 unsigned int endpoint_flag;
3160 for (i = 0; i < num_eps; i++) {
3161 ret = xhci_check_streams_endpoint(xhci, udev,
3162 eps[i], udev->slot_id);
3166 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3167 if (max_streams < (*num_streams - 1)) {
3168 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3169 eps[i]->desc.bEndpointAddress,
3171 *num_streams = max_streams+1;
3174 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3175 if (*changed_ep_bitmask & endpoint_flag)
3177 *changed_ep_bitmask |= endpoint_flag;
3182 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3183 struct usb_device *udev,
3184 struct usb_host_endpoint **eps, unsigned int num_eps)
3186 u32 changed_ep_bitmask = 0;
3187 unsigned int slot_id;
3188 unsigned int ep_index;
3189 unsigned int ep_state;
3192 slot_id = udev->slot_id;
3193 if (!xhci->devs[slot_id])
3196 for (i = 0; i < num_eps; i++) {
3197 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3198 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3199 /* Are streams already being freed for the endpoint? */
3200 if (ep_state & EP_GETTING_NO_STREAMS) {
3201 xhci_warn(xhci, "WARN Can't disable streams for "
3203 "streams are being disabled already\n",
3204 eps[i]->desc.bEndpointAddress);
3207 /* Are there actually any streams to free? */
3208 if (!(ep_state & EP_HAS_STREAMS) &&
3209 !(ep_state & EP_GETTING_STREAMS)) {
3210 xhci_warn(xhci, "WARN Can't disable streams for "
3212 "streams are already disabled!\n",
3213 eps[i]->desc.bEndpointAddress);
3214 xhci_warn(xhci, "WARN xhci_free_streams() called "
3215 "with non-streams endpoint\n");
3218 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3220 return changed_ep_bitmask;
3224 * The USB device drivers use this function (through the HCD interface in USB
3225 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3226 * coordinate mass storage command queueing across multiple endpoints (basically
3227 * a stream ID == a task ID).
3229 * Setting up streams involves allocating the same size stream context array
3230 * for each endpoint and issuing a configure endpoint command for all endpoints.
3232 * Don't allow the call to succeed if one endpoint only supports one stream
3233 * (which means it doesn't support streams at all).
3235 * Drivers may get less stream IDs than they asked for, if the host controller
3236 * hardware or endpoints claim they can't support the number of requested
3239 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3240 struct usb_host_endpoint **eps, unsigned int num_eps,
3241 unsigned int num_streams, gfp_t mem_flags)
3244 struct xhci_hcd *xhci;
3245 struct xhci_virt_device *vdev;
3246 struct xhci_command *config_cmd;
3247 struct xhci_input_control_ctx *ctrl_ctx;
3248 unsigned int ep_index;
3249 unsigned int num_stream_ctxs;
3250 unsigned int max_packet;
3251 unsigned long flags;
3252 u32 changed_ep_bitmask = 0;
3257 /* Add one to the number of streams requested to account for
3258 * stream 0 that is reserved for xHCI usage.
3261 xhci = hcd_to_xhci(hcd);
3262 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3265 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3266 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3267 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3268 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3272 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3276 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3278 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3280 xhci_free_command(xhci, config_cmd);
3284 /* Check to make sure all endpoints are not already configured for
3285 * streams. While we're at it, find the maximum number of streams that
3286 * all the endpoints will support and check for duplicate endpoints.
3288 spin_lock_irqsave(&xhci->lock, flags);
3289 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3290 num_eps, &num_streams, &changed_ep_bitmask);
3292 xhci_free_command(xhci, config_cmd);
3293 spin_unlock_irqrestore(&xhci->lock, flags);
3296 if (num_streams <= 1) {
3297 xhci_warn(xhci, "WARN: endpoints can't handle "
3298 "more than one stream.\n");
3299 xhci_free_command(xhci, config_cmd);
3300 spin_unlock_irqrestore(&xhci->lock, flags);
3303 vdev = xhci->devs[udev->slot_id];
3304 /* Mark each endpoint as being in transition, so
3305 * xhci_urb_enqueue() will reject all URBs.
3307 for (i = 0; i < num_eps; i++) {
3308 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3309 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3311 spin_unlock_irqrestore(&xhci->lock, flags);
3313 /* Setup internal data structures and allocate HW data structures for
3314 * streams (but don't install the HW structures in the input context
3315 * until we're sure all memory allocation succeeded).
3317 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3318 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3319 num_stream_ctxs, num_streams);
3321 for (i = 0; i < num_eps; i++) {
3322 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3323 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3324 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3327 max_packet, mem_flags);
3328 if (!vdev->eps[ep_index].stream_info)
3330 /* Set maxPstreams in endpoint context and update deq ptr to
3331 * point to stream context array. FIXME
3335 /* Set up the input context for a configure endpoint command. */
3336 for (i = 0; i < num_eps; i++) {
3337 struct xhci_ep_ctx *ep_ctx;
3339 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3340 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3342 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3343 vdev->out_ctx, ep_index);
3344 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3345 vdev->eps[ep_index].stream_info);
3347 /* Tell the HW to drop its old copy of the endpoint context info
3348 * and add the updated copy from the input context.
3350 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3351 vdev->out_ctx, ctrl_ctx,
3352 changed_ep_bitmask, changed_ep_bitmask);
3354 /* Issue and wait for the configure endpoint command */
3355 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3358 /* xHC rejected the configure endpoint command for some reason, so we
3359 * leave the old ring intact and free our internal streams data
3365 spin_lock_irqsave(&xhci->lock, flags);
3366 for (i = 0; i < num_eps; i++) {
3367 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3368 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3369 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3370 udev->slot_id, ep_index);
3371 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3373 xhci_free_command(xhci, config_cmd);
3374 spin_unlock_irqrestore(&xhci->lock, flags);
3376 /* Subtract 1 for stream 0, which drivers can't use */
3377 return num_streams - 1;
3380 /* If it didn't work, free the streams! */
3381 for (i = 0; i < num_eps; i++) {
3382 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3383 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3384 vdev->eps[ep_index].stream_info = NULL;
3385 /* FIXME Unset maxPstreams in endpoint context and
3386 * update deq ptr to point to normal string ring.
3388 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3389 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3390 xhci_endpoint_zero(xhci, vdev, eps[i]);
3392 xhci_free_command(xhci, config_cmd);
3396 /* Transition the endpoint from using streams to being a "normal" endpoint
3399 * Modify the endpoint context state, submit a configure endpoint command,
3400 * and free all endpoint rings for streams if that completes successfully.
3402 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3403 struct usb_host_endpoint **eps, unsigned int num_eps,
3407 struct xhci_hcd *xhci;
3408 struct xhci_virt_device *vdev;
3409 struct xhci_command *command;
3410 struct xhci_input_control_ctx *ctrl_ctx;
3411 unsigned int ep_index;
3412 unsigned long flags;
3413 u32 changed_ep_bitmask;
3415 xhci = hcd_to_xhci(hcd);
3416 vdev = xhci->devs[udev->slot_id];
3418 /* Set up a configure endpoint command to remove the streams rings */
3419 spin_lock_irqsave(&xhci->lock, flags);
3420 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3421 udev, eps, num_eps);
3422 if (changed_ep_bitmask == 0) {
3423 spin_unlock_irqrestore(&xhci->lock, flags);
3427 /* Use the xhci_command structure from the first endpoint. We may have
3428 * allocated too many, but the driver may call xhci_free_streams() for
3429 * each endpoint it grouped into one call to xhci_alloc_streams().
3431 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3432 command = vdev->eps[ep_index].stream_info->free_streams_command;
3433 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3435 spin_unlock_irqrestore(&xhci->lock, flags);
3436 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3441 for (i = 0; i < num_eps; i++) {
3442 struct xhci_ep_ctx *ep_ctx;
3444 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3445 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3446 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3447 EP_GETTING_NO_STREAMS;
3449 xhci_endpoint_copy(xhci, command->in_ctx,
3450 vdev->out_ctx, ep_index);
3451 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3452 &vdev->eps[ep_index]);
3454 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3455 vdev->out_ctx, ctrl_ctx,
3456 changed_ep_bitmask, changed_ep_bitmask);
3457 spin_unlock_irqrestore(&xhci->lock, flags);
3459 /* Issue and wait for the configure endpoint command,
3460 * which must succeed.
3462 ret = xhci_configure_endpoint(xhci, udev, command,
3465 /* xHC rejected the configure endpoint command for some reason, so we
3466 * leave the streams rings intact.
3471 spin_lock_irqsave(&xhci->lock, flags);
3472 for (i = 0; i < num_eps; i++) {
3473 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3474 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3475 vdev->eps[ep_index].stream_info = NULL;
3476 /* FIXME Unset maxPstreams in endpoint context and
3477 * update deq ptr to point to normal string ring.
3479 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3480 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3482 spin_unlock_irqrestore(&xhci->lock, flags);
3488 * Deletes endpoint resources for endpoints that were active before a Reset
3489 * Device command, or a Disable Slot command. The Reset Device command leaves
3490 * the control endpoint intact, whereas the Disable Slot command deletes it.
3492 * Must be called with xhci->lock held.
3494 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3495 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3498 unsigned int num_dropped_eps = 0;
3499 unsigned int drop_flags = 0;
3501 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3502 if (virt_dev->eps[i].ring) {
3503 drop_flags |= 1 << i;
3507 xhci->num_active_eps -= num_dropped_eps;
3508 if (num_dropped_eps)
3509 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3510 "Dropped %u ep ctxs, flags = 0x%x, "
3512 num_dropped_eps, drop_flags,
3513 xhci->num_active_eps);
3517 * This submits a Reset Device Command, which will set the device state to 0,
3518 * set the device address to 0, and disable all the endpoints except the default
3519 * control endpoint. The USB core should come back and call
3520 * xhci_address_device(), and then re-set up the configuration. If this is
3521 * called because of a usb_reset_and_verify_device(), then the old alternate
3522 * settings will be re-installed through the normal bandwidth allocation
3525 * Wait for the Reset Device command to finish. Remove all structures
3526 * associated with the endpoints that were disabled. Clear the input device
3527 * structure? Reset the control endpoint 0 max packet size?
3529 * If the virt_dev to be reset does not exist or does not match the udev,
3530 * it means the device is lost, possibly due to the xHC restore error and
3531 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3532 * re-allocate the device.
3534 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3535 struct usb_device *udev)
3538 unsigned long flags;
3539 struct xhci_hcd *xhci;
3540 unsigned int slot_id;
3541 struct xhci_virt_device *virt_dev;
3542 struct xhci_command *reset_device_cmd;
3543 struct xhci_slot_ctx *slot_ctx;
3544 int old_active_eps = 0;
3546 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3549 xhci = hcd_to_xhci(hcd);
3550 slot_id = udev->slot_id;
3551 virt_dev = xhci->devs[slot_id];
3553 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3554 "not exist. Re-allocate the device\n", slot_id);
3555 ret = xhci_alloc_dev(hcd, udev);
3562 if (virt_dev->tt_info)
3563 old_active_eps = virt_dev->tt_info->active_eps;
3565 if (virt_dev->udev != udev) {
3566 /* If the virt_dev and the udev does not match, this virt_dev
3567 * may belong to another udev.
3568 * Re-allocate the device.
3570 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3571 "not match the udev. Re-allocate the device\n",
3573 ret = xhci_alloc_dev(hcd, udev);
3580 /* If device is not setup, there is no point in resetting it */
3581 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3582 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3583 SLOT_STATE_DISABLED)
3586 trace_xhci_discover_or_reset_device(slot_ctx);
3588 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3589 /* Allocate the command structure that holds the struct completion.
3590 * Assume we're in process context, since the normal device reset
3591 * process has to wait for the device anyway. Storage devices are
3592 * reset as part of error handling, so use GFP_NOIO instead of
3595 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3596 if (!reset_device_cmd) {
3597 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3601 /* Attempt to submit the Reset Device command to the command ring */
3602 spin_lock_irqsave(&xhci->lock, flags);
3604 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3606 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3607 spin_unlock_irqrestore(&xhci->lock, flags);
3608 goto command_cleanup;
3610 xhci_ring_cmd_db(xhci);
3611 spin_unlock_irqrestore(&xhci->lock, flags);
3613 /* Wait for the Reset Device command to finish */
3614 wait_for_completion(reset_device_cmd->completion);
3616 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3617 * unless we tried to reset a slot ID that wasn't enabled,
3618 * or the device wasn't in the addressed or configured state.
3620 ret = reset_device_cmd->status;
3622 case COMP_COMMAND_ABORTED:
3623 case COMP_COMMAND_RING_STOPPED:
3624 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3626 goto command_cleanup;
3627 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3628 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3629 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3631 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3632 xhci_dbg(xhci, "Not freeing device rings.\n");
3633 /* Don't treat this as an error. May change my mind later. */
3635 goto command_cleanup;
3637 xhci_dbg(xhci, "Successful reset device command.\n");
3640 if (xhci_is_vendor_info_code(xhci, ret))
3642 xhci_warn(xhci, "Unknown completion code %u for "
3643 "reset device command.\n", ret);
3645 goto command_cleanup;
3648 /* Free up host controller endpoint resources */
3649 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3650 spin_lock_irqsave(&xhci->lock, flags);
3651 /* Don't delete the default control endpoint resources */
3652 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3653 spin_unlock_irqrestore(&xhci->lock, flags);
3656 /* Everything but endpoint 0 is disabled, so free the rings. */
3657 for (i = 1; i < 31; i++) {
3658 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3660 if (ep->ep_state & EP_HAS_STREAMS) {
3661 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3662 xhci_get_endpoint_address(i));
3663 xhci_free_stream_info(xhci, ep->stream_info);
3664 ep->stream_info = NULL;
3665 ep->ep_state &= ~EP_HAS_STREAMS;
3669 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3670 xhci_free_endpoint_ring(xhci, virt_dev, i);
3672 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3673 xhci_drop_ep_from_interval_table(xhci,
3674 &virt_dev->eps[i].bw_info,
3679 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3681 /* If necessary, update the number of active TTs on this root port */
3682 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3686 xhci_free_command(xhci, reset_device_cmd);
3691 * At this point, the struct usb_device is about to go away, the device has
3692 * disconnected, and all traffic has been stopped and the endpoints have been
3693 * disabled. Free any HC data structures associated with that device.
3695 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3697 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3698 struct xhci_virt_device *virt_dev;
3699 struct xhci_slot_ctx *slot_ctx;
3702 #ifndef CONFIG_USB_DEFAULT_PERSIST
3704 * We called pm_runtime_get_noresume when the device was attached.
3705 * Decrement the counter here to allow controller to runtime suspend
3706 * if no devices remain.
3708 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3709 pm_runtime_put_noidle(hcd->self.controller);
3712 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3713 /* If the host is halted due to driver unload, we still need to free the
3716 if (ret <= 0 && ret != -ENODEV)
3719 virt_dev = xhci->devs[udev->slot_id];
3720 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3721 trace_xhci_free_dev(slot_ctx);
3723 /* Stop any wayward timer functions (which may grab the lock) */
3724 for (i = 0; i < 31; i++) {
3725 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3726 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3728 xhci_debugfs_remove_slot(xhci, udev->slot_id);
3729 virt_dev->udev = NULL;
3730 ret = xhci_disable_slot(xhci, udev->slot_id);
3732 xhci_free_virt_device(xhci, udev->slot_id);
3735 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3737 struct xhci_command *command;
3738 unsigned long flags;
3742 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3746 spin_lock_irqsave(&xhci->lock, flags);
3747 /* Don't disable the slot if the host controller is dead. */
3748 state = readl(&xhci->op_regs->status);
3749 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3750 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3751 spin_unlock_irqrestore(&xhci->lock, flags);
3756 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3759 spin_unlock_irqrestore(&xhci->lock, flags);
3763 xhci_ring_cmd_db(xhci);
3764 spin_unlock_irqrestore(&xhci->lock, flags);
3769 * Checks if we have enough host controller resources for the default control
3772 * Must be called with xhci->lock held.
3774 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3776 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3777 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3778 "Not enough ep ctxs: "
3779 "%u active, need to add 1, limit is %u.",
3780 xhci->num_active_eps, xhci->limit_active_eps);
3783 xhci->num_active_eps += 1;
3784 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3785 "Adding 1 ep ctx, %u now active.",
3786 xhci->num_active_eps);
3792 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3793 * timed out, or allocating memory failed. Returns 1 on success.
3795 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3797 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3798 struct xhci_virt_device *vdev;
3799 struct xhci_slot_ctx *slot_ctx;
3800 unsigned long flags;
3802 struct xhci_command *command;
3804 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3808 spin_lock_irqsave(&xhci->lock, flags);
3809 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3811 spin_unlock_irqrestore(&xhci->lock, flags);
3812 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3813 xhci_free_command(xhci, command);
3816 xhci_ring_cmd_db(xhci);
3817 spin_unlock_irqrestore(&xhci->lock, flags);
3819 wait_for_completion(command->completion);
3820 slot_id = command->slot_id;
3822 if (!slot_id || command->status != COMP_SUCCESS) {
3823 xhci_err(xhci, "Error while assigning device slot ID\n");
3824 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3826 readl(&xhci->cap_regs->hcs_params1)));
3827 xhci_free_command(xhci, command);
3831 xhci_free_command(xhci, command);
3833 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3834 spin_lock_irqsave(&xhci->lock, flags);
3835 ret = xhci_reserve_host_control_ep_resources(xhci);
3837 spin_unlock_irqrestore(&xhci->lock, flags);
3838 xhci_warn(xhci, "Not enough host resources, "
3839 "active endpoint contexts = %u\n",
3840 xhci->num_active_eps);
3843 spin_unlock_irqrestore(&xhci->lock, flags);
3845 /* Use GFP_NOIO, since this function can be called from
3846 * xhci_discover_or_reset_device(), which may be called as part of
3847 * mass storage driver error handling.
3849 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3850 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3853 vdev = xhci->devs[slot_id];
3854 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3855 trace_xhci_alloc_dev(slot_ctx);
3857 udev->slot_id = slot_id;
3859 xhci_debugfs_create_slot(xhci, slot_id);
3861 #ifndef CONFIG_USB_DEFAULT_PERSIST
3863 * If resetting upon resume, we can't put the controller into runtime
3864 * suspend if there is a device attached.
3866 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3867 pm_runtime_get_noresume(hcd->self.controller);
3870 /* Is this a LS or FS device under a HS hub? */
3871 /* Hub or peripherial? */
3875 ret = xhci_disable_slot(xhci, udev->slot_id);
3877 xhci_free_virt_device(xhci, udev->slot_id);
3883 * Issue an Address Device command and optionally send a corresponding
3884 * SetAddress request to the device.
3886 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3887 enum xhci_setup_dev setup)
3889 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3890 unsigned long flags;
3891 struct xhci_virt_device *virt_dev;
3893 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3894 struct xhci_slot_ctx *slot_ctx;
3895 struct xhci_input_control_ctx *ctrl_ctx;
3897 struct xhci_command *command = NULL;
3899 mutex_lock(&xhci->mutex);
3901 if (xhci->xhc_state) { /* dying, removing or halted */
3906 if (!udev->slot_id) {
3907 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3908 "Bad Slot ID %d", udev->slot_id);
3913 virt_dev = xhci->devs[udev->slot_id];
3915 if (WARN_ON(!virt_dev)) {
3917 * In plug/unplug torture test with an NEC controller,
3918 * a zero-dereference was observed once due to virt_dev = 0.
3919 * Print useful debug rather than crash if it is observed again!
3921 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3926 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3927 trace_xhci_setup_device_slot(slot_ctx);
3929 if (setup == SETUP_CONTEXT_ONLY) {
3930 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3931 SLOT_STATE_DEFAULT) {
3932 xhci_dbg(xhci, "Slot already in default state\n");
3937 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3943 command->in_ctx = virt_dev->in_ctx;
3945 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3946 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3948 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3954 * If this is the first Set Address since device plug-in or
3955 * virt_device realloaction after a resume with an xHCI power loss,
3956 * then set up the slot context.
3958 if (!slot_ctx->dev_info)
3959 xhci_setup_addressable_virt_dev(xhci, udev);
3960 /* Otherwise, update the control endpoint ring enqueue pointer. */
3962 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3963 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3964 ctrl_ctx->drop_flags = 0;
3966 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3967 le32_to_cpu(slot_ctx->dev_info) >> 27);
3969 spin_lock_irqsave(&xhci->lock, flags);
3970 trace_xhci_setup_device(virt_dev);
3971 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3972 udev->slot_id, setup);
3974 spin_unlock_irqrestore(&xhci->lock, flags);
3975 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3976 "FIXME: allocate a command ring segment");
3979 xhci_ring_cmd_db(xhci);
3980 spin_unlock_irqrestore(&xhci->lock, flags);
3982 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3983 wait_for_completion(command->completion);
3985 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3986 * the SetAddress() "recovery interval" required by USB and aborting the
3987 * command on a timeout.
3989 switch (command->status) {
3990 case COMP_COMMAND_ABORTED:
3991 case COMP_COMMAND_RING_STOPPED:
3992 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3995 case COMP_CONTEXT_STATE_ERROR:
3996 case COMP_SLOT_NOT_ENABLED_ERROR:
3997 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3998 act, udev->slot_id);
4001 case COMP_USB_TRANSACTION_ERROR:
4002 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4004 mutex_unlock(&xhci->mutex);
4005 ret = xhci_disable_slot(xhci, udev->slot_id);
4007 xhci_alloc_dev(hcd, udev);
4008 kfree(command->completion);
4011 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4012 dev_warn(&udev->dev,
4013 "ERROR: Incompatible device for setup %s command\n", act);
4017 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4018 "Successful setup %s command", act);
4022 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4023 act, command->status);
4024 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4030 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4031 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4032 "Op regs DCBAA ptr = %#016llx", temp_64);
4033 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4034 "Slot ID %d dcbaa entry @%p = %#016llx",
4036 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4037 (unsigned long long)
4038 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4039 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4040 "Output Context DMA address = %#08llx",
4041 (unsigned long long)virt_dev->out_ctx->dma);
4042 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4043 le32_to_cpu(slot_ctx->dev_info) >> 27);
4045 * USB core uses address 1 for the roothubs, so we add one to the
4046 * address given back to us by the HC.
4048 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4049 le32_to_cpu(slot_ctx->dev_info) >> 27);
4050 /* Zero the input context control for later use */
4051 ctrl_ctx->add_flags = 0;
4052 ctrl_ctx->drop_flags = 0;
4054 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4055 "Internal device address = %d",
4056 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4058 mutex_unlock(&xhci->mutex);
4060 kfree(command->completion);
4066 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4068 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4071 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4073 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4077 * Transfer the port index into real index in the HW port status
4078 * registers. Caculate offset between the port's PORTSC register
4079 * and port status base. Divide the number of per port register
4080 * to get the real index. The raw port number bases 1.
4082 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4084 struct xhci_hub *rhub;
4086 rhub = xhci_get_rhub(hcd);
4087 return rhub->ports[port1 - 1]->hw_portnum + 1;
4091 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4092 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4094 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4095 struct usb_device *udev, u16 max_exit_latency)
4097 struct xhci_virt_device *virt_dev;
4098 struct xhci_command *command;
4099 struct xhci_input_control_ctx *ctrl_ctx;
4100 struct xhci_slot_ctx *slot_ctx;
4101 unsigned long flags;
4104 spin_lock_irqsave(&xhci->lock, flags);
4106 virt_dev = xhci->devs[udev->slot_id];
4109 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4110 * xHC was re-initialized. Exit latency will be set later after
4111 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4114 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4115 spin_unlock_irqrestore(&xhci->lock, flags);
4119 /* Attempt to issue an Evaluate Context command to change the MEL. */
4120 command = xhci->lpm_command;
4121 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4123 spin_unlock_irqrestore(&xhci->lock, flags);
4124 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4129 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4130 spin_unlock_irqrestore(&xhci->lock, flags);
4132 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4133 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4134 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4135 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4136 slot_ctx->dev_state = 0;
4138 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4139 "Set up evaluate context for LPM MEL change.");
4141 /* Issue and wait for the evaluate context command. */
4142 ret = xhci_configure_endpoint(xhci, udev, command,
4146 spin_lock_irqsave(&xhci->lock, flags);
4147 virt_dev->current_mel = max_exit_latency;
4148 spin_unlock_irqrestore(&xhci->lock, flags);
4155 /* BESL to HIRD Encoding array for USB2 LPM */
4156 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4157 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4159 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4160 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4161 struct usb_device *udev)
4163 int u2del, besl, besl_host;
4164 int besl_device = 0;
4167 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4168 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4170 if (field & USB_BESL_SUPPORT) {
4171 for (besl_host = 0; besl_host < 16; besl_host++) {
4172 if (xhci_besl_encoding[besl_host] >= u2del)
4175 /* Use baseline BESL value as default */
4176 if (field & USB_BESL_BASELINE_VALID)
4177 besl_device = USB_GET_BESL_BASELINE(field);
4178 else if (field & USB_BESL_DEEP_VALID)
4179 besl_device = USB_GET_BESL_DEEP(field);
4184 besl_host = (u2del - 51) / 75 + 1;
4187 besl = besl_host + besl_device;
4194 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4195 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4202 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4204 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4205 l1 = udev->l1_params.timeout / 256;
4207 /* device has preferred BESLD */
4208 if (field & USB_BESL_DEEP_VALID) {
4209 besld = USB_GET_BESL_DEEP(field);
4213 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4216 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4217 struct usb_device *udev, int enable)
4219 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4220 struct xhci_port **ports;
4221 __le32 __iomem *pm_addr, *hlpm_addr;
4222 u32 pm_val, hlpm_val, field;
4223 unsigned int port_num;
4224 unsigned long flags;
4225 int hird, exit_latency;
4228 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4232 if (!udev->parent || udev->parent->parent ||
4233 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4236 if (udev->usb2_hw_lpm_capable != 1)
4239 spin_lock_irqsave(&xhci->lock, flags);
4241 ports = xhci->usb2_rhub.ports;
4242 port_num = udev->portnum - 1;
4243 pm_addr = ports[port_num]->addr + PORTPMSC;
4244 pm_val = readl(pm_addr);
4245 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4246 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4248 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4249 enable ? "enable" : "disable", port_num + 1);
4251 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4252 /* Host supports BESL timeout instead of HIRD */
4253 if (udev->usb2_hw_lpm_besl_capable) {
4254 /* if device doesn't have a preferred BESL value use a
4255 * default one which works with mixed HIRD and BESL
4256 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4258 if ((field & USB_BESL_SUPPORT) &&
4259 (field & USB_BESL_BASELINE_VALID))
4260 hird = USB_GET_BESL_BASELINE(field);
4262 hird = udev->l1_params.besl;
4264 exit_latency = xhci_besl_encoding[hird];
4265 spin_unlock_irqrestore(&xhci->lock, flags);
4267 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4268 * input context for link powermanagement evaluate
4269 * context commands. It is protected by hcd->bandwidth
4270 * mutex and is shared by all devices. We need to set
4271 * the max ext latency in USB 2 BESL LPM as well, so
4272 * use the same mutex and xhci_change_max_exit_latency()
4274 mutex_lock(hcd->bandwidth_mutex);
4275 ret = xhci_change_max_exit_latency(xhci, udev,
4277 mutex_unlock(hcd->bandwidth_mutex);
4281 spin_lock_irqsave(&xhci->lock, flags);
4283 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4284 writel(hlpm_val, hlpm_addr);
4288 hird = xhci_calculate_hird_besl(xhci, udev);
4291 pm_val &= ~PORT_HIRD_MASK;
4292 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4293 writel(pm_val, pm_addr);
4294 pm_val = readl(pm_addr);
4296 writel(pm_val, pm_addr);
4300 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4301 writel(pm_val, pm_addr);
4304 if (udev->usb2_hw_lpm_besl_capable) {
4305 spin_unlock_irqrestore(&xhci->lock, flags);
4306 mutex_lock(hcd->bandwidth_mutex);
4307 xhci_change_max_exit_latency(xhci, udev, 0);
4308 mutex_unlock(hcd->bandwidth_mutex);
4313 spin_unlock_irqrestore(&xhci->lock, flags);
4317 /* check if a usb2 port supports a given extened capability protocol
4318 * only USB2 ports extended protocol capability values are cached.
4319 * Return 1 if capability is supported
4321 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4322 unsigned capability)
4324 u32 port_offset, port_count;
4327 for (i = 0; i < xhci->num_ext_caps; i++) {
4328 if (xhci->ext_caps[i] & capability) {
4329 /* port offsets starts at 1 */
4330 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4331 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4332 if (port >= port_offset &&
4333 port < port_offset + port_count)
4340 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4342 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4343 int portnum = udev->portnum - 1;
4345 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4349 /* we only support lpm for non-hub device connected to root hub yet */
4350 if (!udev->parent || udev->parent->parent ||
4351 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4354 if (xhci->hw_lpm_support == 1 &&
4355 xhci_check_usb2_port_capability(
4356 xhci, portnum, XHCI_HLC)) {
4357 udev->usb2_hw_lpm_capable = 1;
4358 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4359 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4360 if (xhci_check_usb2_port_capability(xhci, portnum,
4362 udev->usb2_hw_lpm_besl_capable = 1;
4368 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4370 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4371 static unsigned long long xhci_service_interval_to_ns(
4372 struct usb_endpoint_descriptor *desc)
4374 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4377 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4378 enum usb3_link_state state)
4380 unsigned long long sel;
4381 unsigned long long pel;
4382 unsigned int max_sel_pel;
4387 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4388 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4389 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4390 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4394 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4395 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4396 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4400 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4402 return USB3_LPM_DISABLED;
4405 if (sel <= max_sel_pel && pel <= max_sel_pel)
4406 return USB3_LPM_DEVICE_INITIATED;
4408 if (sel > max_sel_pel)
4409 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4410 "due to long SEL %llu ms\n",
4413 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4414 "due to long PEL %llu ms\n",
4416 return USB3_LPM_DISABLED;
4419 /* The U1 timeout should be the maximum of the following values:
4420 * - For control endpoints, U1 system exit latency (SEL) * 3
4421 * - For bulk endpoints, U1 SEL * 5
4422 * - For interrupt endpoints:
4423 * - Notification EPs, U1 SEL * 3
4424 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4425 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4427 static unsigned long long xhci_calculate_intel_u1_timeout(
4428 struct usb_device *udev,
4429 struct usb_endpoint_descriptor *desc)
4431 unsigned long long timeout_ns;
4435 ep_type = usb_endpoint_type(desc);
4437 case USB_ENDPOINT_XFER_CONTROL:
4438 timeout_ns = udev->u1_params.sel * 3;
4440 case USB_ENDPOINT_XFER_BULK:
4441 timeout_ns = udev->u1_params.sel * 5;
4443 case USB_ENDPOINT_XFER_INT:
4444 intr_type = usb_endpoint_interrupt_type(desc);
4445 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4446 timeout_ns = udev->u1_params.sel * 3;
4449 /* Otherwise the calculation is the same as isoc eps */
4451 case USB_ENDPOINT_XFER_ISOC:
4452 timeout_ns = xhci_service_interval_to_ns(desc);
4453 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4454 if (timeout_ns < udev->u1_params.sel * 2)
4455 timeout_ns = udev->u1_params.sel * 2;
4464 /* Returns the hub-encoded U1 timeout value. */
4465 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4466 struct usb_device *udev,
4467 struct usb_endpoint_descriptor *desc)
4469 unsigned long long timeout_ns;
4471 if (xhci->quirks & XHCI_INTEL_HOST)
4472 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4474 timeout_ns = udev->u1_params.sel;
4476 /* The U1 timeout is encoded in 1us intervals.
4477 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4479 if (timeout_ns == USB3_LPM_DISABLED)
4482 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4484 /* If the necessary timeout value is bigger than what we can set in the
4485 * USB 3.0 hub, we have to disable hub-initiated U1.
4487 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4489 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4490 "due to long timeout %llu ms\n", timeout_ns);
4491 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4494 /* The U2 timeout should be the maximum of:
4495 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4496 * - largest bInterval of any active periodic endpoint (to avoid going
4497 * into lower power link states between intervals).
4498 * - the U2 Exit Latency of the device
4500 static unsigned long long xhci_calculate_intel_u2_timeout(
4501 struct usb_device *udev,
4502 struct usb_endpoint_descriptor *desc)
4504 unsigned long long timeout_ns;
4505 unsigned long long u2_del_ns;
4507 timeout_ns = 10 * 1000 * 1000;
4509 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4510 (xhci_service_interval_to_ns(desc) > timeout_ns))
4511 timeout_ns = xhci_service_interval_to_ns(desc);
4513 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4514 if (u2_del_ns > timeout_ns)
4515 timeout_ns = u2_del_ns;
4520 /* Returns the hub-encoded U2 timeout value. */
4521 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4522 struct usb_device *udev,
4523 struct usb_endpoint_descriptor *desc)
4525 unsigned long long timeout_ns;
4527 if (xhci->quirks & XHCI_INTEL_HOST)
4528 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4530 timeout_ns = udev->u2_params.sel;
4532 /* The U2 timeout is encoded in 256us intervals */
4533 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4534 /* If the necessary timeout value is bigger than what we can set in the
4535 * USB 3.0 hub, we have to disable hub-initiated U2.
4537 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4539 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4540 "due to long timeout %llu ms\n", timeout_ns);
4541 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4544 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4545 struct usb_device *udev,
4546 struct usb_endpoint_descriptor *desc,
4547 enum usb3_link_state state,
4550 if (state == USB3_LPM_U1)
4551 return xhci_calculate_u1_timeout(xhci, udev, desc);
4552 else if (state == USB3_LPM_U2)
4553 return xhci_calculate_u2_timeout(xhci, udev, desc);
4555 return USB3_LPM_DISABLED;
4558 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4559 struct usb_device *udev,
4560 struct usb_endpoint_descriptor *desc,
4561 enum usb3_link_state state,
4566 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4567 desc, state, timeout);
4569 /* If we found we can't enable hub-initiated LPM, or
4570 * the U1 or U2 exit latency was too high to allow
4571 * device-initiated LPM as well, just stop searching.
4573 if (alt_timeout == USB3_LPM_DISABLED ||
4574 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4575 *timeout = alt_timeout;
4578 if (alt_timeout > *timeout)
4579 *timeout = alt_timeout;
4583 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4584 struct usb_device *udev,
4585 struct usb_host_interface *alt,
4586 enum usb3_link_state state,
4591 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4592 if (xhci_update_timeout_for_endpoint(xhci, udev,
4593 &alt->endpoint[j].desc, state, timeout))
4600 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4601 enum usb3_link_state state)
4603 struct usb_device *parent;
4604 unsigned int num_hubs;
4606 if (state == USB3_LPM_U2)
4609 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4610 for (parent = udev->parent, num_hubs = 0; parent->parent;
4611 parent = parent->parent)
4617 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4618 " below second-tier hub.\n");
4619 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4620 "to decrease power consumption.\n");
4624 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4625 struct usb_device *udev,
4626 enum usb3_link_state state)
4628 if (xhci->quirks & XHCI_INTEL_HOST)
4629 return xhci_check_intel_tier_policy(udev, state);
4634 /* Returns the U1 or U2 timeout that should be enabled.
4635 * If the tier check or timeout setting functions return with a non-zero exit
4636 * code, that means the timeout value has been finalized and we shouldn't look
4637 * at any more endpoints.
4639 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4640 struct usb_device *udev, enum usb3_link_state state)
4642 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4643 struct usb_host_config *config;
4646 u16 timeout = USB3_LPM_DISABLED;
4648 if (state == USB3_LPM_U1)
4650 else if (state == USB3_LPM_U2)
4653 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4658 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4661 /* Gather some information about the currently installed configuration
4662 * and alternate interface settings.
4664 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4668 config = udev->actconfig;
4672 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4673 struct usb_driver *driver;
4674 struct usb_interface *intf = config->interface[i];
4679 /* Check if any currently bound drivers want hub-initiated LPM
4682 if (intf->dev.driver) {
4683 driver = to_usb_driver(intf->dev.driver);
4684 if (driver && driver->disable_hub_initiated_lpm) {
4685 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4686 "at request of driver %s\n",
4687 state_name, driver->name);
4688 return xhci_get_timeout_no_hub_lpm(udev, state);
4692 /* Not sure how this could happen... */
4693 if (!intf->cur_altsetting)
4696 if (xhci_update_timeout_for_interface(xhci, udev,
4697 intf->cur_altsetting,
4704 static int calculate_max_exit_latency(struct usb_device *udev,
4705 enum usb3_link_state state_changed,
4706 u16 hub_encoded_timeout)
4708 unsigned long long u1_mel_us = 0;
4709 unsigned long long u2_mel_us = 0;
4710 unsigned long long mel_us = 0;
4716 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4717 hub_encoded_timeout == USB3_LPM_DISABLED);
4718 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4719 hub_encoded_timeout == USB3_LPM_DISABLED);
4721 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4722 hub_encoded_timeout != USB3_LPM_DISABLED);
4723 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4724 hub_encoded_timeout != USB3_LPM_DISABLED);
4726 /* If U1 was already enabled and we're not disabling it,
4727 * or we're going to enable U1, account for the U1 max exit latency.
4729 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4731 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4732 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4734 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4736 if (u1_mel_us > u2_mel_us)
4740 /* xHCI host controller max exit latency field is only 16 bits wide. */
4741 if (mel_us > MAX_EXIT) {
4742 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4743 "is too big.\n", mel_us);
4749 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4750 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4751 struct usb_device *udev, enum usb3_link_state state)
4753 struct xhci_hcd *xhci;
4754 u16 hub_encoded_timeout;
4758 xhci = hcd_to_xhci(hcd);
4759 /* The LPM timeout values are pretty host-controller specific, so don't
4760 * enable hub-initiated timeouts unless the vendor has provided
4761 * information about their timeout algorithm.
4763 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4764 !xhci->devs[udev->slot_id])
4765 return USB3_LPM_DISABLED;
4767 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4768 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4770 /* Max Exit Latency is too big, disable LPM. */
4771 hub_encoded_timeout = USB3_LPM_DISABLED;
4775 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4778 return hub_encoded_timeout;
4781 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4782 struct usb_device *udev, enum usb3_link_state state)
4784 struct xhci_hcd *xhci;
4787 xhci = hcd_to_xhci(hcd);
4788 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4789 !xhci->devs[udev->slot_id])
4792 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4793 return xhci_change_max_exit_latency(xhci, udev, mel);
4795 #else /* CONFIG_PM */
4797 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4798 struct usb_device *udev, int enable)
4803 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4808 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4809 struct usb_device *udev, enum usb3_link_state state)
4811 return USB3_LPM_DISABLED;
4814 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4815 struct usb_device *udev, enum usb3_link_state state)
4819 #endif /* CONFIG_PM */
4821 /*-------------------------------------------------------------------------*/
4823 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4824 * internal data structures for the device.
4826 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4827 struct usb_tt *tt, gfp_t mem_flags)
4829 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4830 struct xhci_virt_device *vdev;
4831 struct xhci_command *config_cmd;
4832 struct xhci_input_control_ctx *ctrl_ctx;
4833 struct xhci_slot_ctx *slot_ctx;
4834 unsigned long flags;
4835 unsigned think_time;
4838 /* Ignore root hubs */
4842 vdev = xhci->devs[hdev->slot_id];
4844 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4848 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
4852 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4854 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4856 xhci_free_command(xhci, config_cmd);
4860 spin_lock_irqsave(&xhci->lock, flags);
4861 if (hdev->speed == USB_SPEED_HIGH &&
4862 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4863 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4864 xhci_free_command(xhci, config_cmd);
4865 spin_unlock_irqrestore(&xhci->lock, flags);
4869 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4870 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4871 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4872 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4874 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4875 * but it may be already set to 1 when setup an xHCI virtual
4876 * device, so clear it anyway.
4879 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4880 else if (hdev->speed == USB_SPEED_FULL)
4881 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4883 if (xhci->hci_version > 0x95) {
4884 xhci_dbg(xhci, "xHCI version %x needs hub "
4885 "TT think time and number of ports\n",
4886 (unsigned int) xhci->hci_version);
4887 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4888 /* Set TT think time - convert from ns to FS bit times.
4889 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4890 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4892 * xHCI 1.0: this field shall be 0 if the device is not a
4895 think_time = tt->think_time;
4896 if (think_time != 0)
4897 think_time = (think_time / 666) - 1;
4898 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4899 slot_ctx->tt_info |=
4900 cpu_to_le32(TT_THINK_TIME(think_time));
4902 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4903 "TT think time or number of ports\n",
4904 (unsigned int) xhci->hci_version);
4906 slot_ctx->dev_state = 0;
4907 spin_unlock_irqrestore(&xhci->lock, flags);
4909 xhci_dbg(xhci, "Set up %s for hub device.\n",
4910 (xhci->hci_version > 0x95) ?
4911 "configure endpoint" : "evaluate context");
4913 /* Issue and wait for the configure endpoint or
4914 * evaluate context command.
4916 if (xhci->hci_version > 0x95)
4917 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4920 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4923 xhci_free_command(xhci, config_cmd);
4927 static int xhci_get_frame(struct usb_hcd *hcd)
4929 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4930 /* EHCI mods by the periodic size. Why? */
4931 return readl(&xhci->run_regs->microframe_index) >> 3;
4934 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4936 struct xhci_hcd *xhci;
4938 * TODO: Check with DWC3 clients for sysdev according to
4941 struct device *dev = hcd->self.sysdev;
4942 unsigned int minor_rev;
4945 /* Accept arbitrarily long scatter-gather lists */
4946 hcd->self.sg_tablesize = ~0;
4948 /* support to build packet from discontinuous buffers */
4949 hcd->self.no_sg_constraint = 1;
4951 /* XHCI controllers don't stop the ep queue on short packets :| */
4952 hcd->self.no_stop_on_short = 1;
4954 xhci = hcd_to_xhci(hcd);
4956 if (usb_hcd_is_primary_hcd(hcd)) {
4957 xhci->main_hcd = hcd;
4958 xhci->usb2_rhub.hcd = hcd;
4959 /* Mark the first roothub as being USB 2.0.
4960 * The xHCI driver will register the USB 3.0 roothub.
4962 hcd->speed = HCD_USB2;
4963 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4965 * USB 2.0 roothub under xHCI has an integrated TT,
4966 * (rate matching hub) as opposed to having an OHCI/UHCI
4967 * companion controller.
4972 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
4973 * minor revision instead of sbrn
4975 minor_rev = xhci->usb3_rhub.min_rev;
4977 hcd->speed = HCD_USB31;
4978 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4980 xhci_info(xhci, "Host supports USB 3.%x %s SuperSpeed\n",
4982 minor_rev ? "Enhanced" : "");
4984 xhci->usb3_rhub.hcd = hcd;
4985 /* xHCI private pointer was set in xhci_pci_probe for the second
4986 * registered roothub.
4991 mutex_init(&xhci->mutex);
4992 xhci->cap_regs = hcd->regs;
4993 xhci->op_regs = hcd->regs +
4994 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4995 xhci->run_regs = hcd->regs +
4996 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4997 /* Cache read-only capability registers */
4998 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4999 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5000 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5001 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5002 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5003 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5004 if (xhci->hci_version > 0x100)
5005 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5007 xhci->quirks |= quirks;
5009 get_quirks(dev, xhci);
5011 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5012 * success event after a short transfer. This quirk will ignore such
5015 if (xhci->hci_version > 0x96)
5016 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5018 /* Make sure the HC is halted. */
5019 retval = xhci_halt(xhci);
5023 xhci_zero_64b_regs(xhci);
5025 xhci_dbg(xhci, "Resetting HCD\n");
5026 /* Reset the internal HC memory state and registers. */
5027 retval = xhci_reset(xhci);
5030 xhci_dbg(xhci, "Reset complete\n");
5033 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5034 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5035 * address memory pointers actually. So, this driver clears the AC64
5036 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5037 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5039 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5040 xhci->hcc_params &= ~BIT(0);
5042 /* Set dma_mask and coherent_dma_mask to 64-bits,
5043 * if xHC supports 64-bit addressing */
5044 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5045 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5046 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5047 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5050 * This is to avoid error in cases where a 32-bit USB
5051 * controller is used on a 64-bit capable system.
5053 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5056 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5057 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5060 xhci_dbg(xhci, "Calling HCD init\n");
5061 /* Initialize HCD and host controller data structures. */
5062 retval = xhci_init(hcd);
5065 xhci_dbg(xhci, "Called HCD init\n");
5067 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5068 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5072 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5074 static const struct hc_driver xhci_hc_driver = {
5075 .description = "xhci-hcd",
5076 .product_desc = "xHCI Host Controller",
5077 .hcd_priv_size = sizeof(struct xhci_hcd),
5080 * generic hardware linkage
5083 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5086 * basic lifecycle operations
5088 .reset = NULL, /* set in xhci_init_driver() */
5091 .shutdown = xhci_shutdown,
5094 * managing i/o requests and associated device resources
5096 .urb_enqueue = xhci_urb_enqueue,
5097 .urb_dequeue = xhci_urb_dequeue,
5098 .alloc_dev = xhci_alloc_dev,
5099 .free_dev = xhci_free_dev,
5100 .alloc_streams = xhci_alloc_streams,
5101 .free_streams = xhci_free_streams,
5102 .add_endpoint = xhci_add_endpoint,
5103 .drop_endpoint = xhci_drop_endpoint,
5104 .endpoint_reset = xhci_endpoint_reset,
5105 .check_bandwidth = xhci_check_bandwidth,
5106 .reset_bandwidth = xhci_reset_bandwidth,
5107 .address_device = xhci_address_device,
5108 .enable_device = xhci_enable_device,
5109 .update_hub_device = xhci_update_hub_device,
5110 .reset_device = xhci_discover_or_reset_device,
5113 * scheduling support
5115 .get_frame_number = xhci_get_frame,
5120 .hub_control = xhci_hub_control,
5121 .hub_status_data = xhci_hub_status_data,
5122 .bus_suspend = xhci_bus_suspend,
5123 .bus_resume = xhci_bus_resume,
5124 .get_resuming_ports = xhci_get_resuming_ports,
5127 * call back when device connected and addressed
5129 .update_device = xhci_update_device,
5130 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5131 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5132 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5133 .find_raw_port_number = xhci_find_raw_port_number,
5136 void xhci_init_driver(struct hc_driver *drv,
5137 const struct xhci_driver_overrides *over)
5141 /* Copy the generic table to drv then apply the overrides */
5142 *drv = xhci_hc_driver;
5145 drv->hcd_priv_size += over->extra_priv_size;
5147 drv->reset = over->reset;
5149 drv->start = over->start;
5152 EXPORT_SYMBOL_GPL(xhci_init_driver);
5154 MODULE_DESCRIPTION(DRIVER_DESC);
5155 MODULE_AUTHOR(DRIVER_AUTHOR);
5156 MODULE_LICENSE("GPL");
5158 static int __init xhci_hcd_init(void)
5161 * Check the compiler generated sizes of structures that must be laid
5162 * out in specific ways for hardware access.
5164 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5165 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5166 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5167 /* xhci_device_control has eight fields, and also
5168 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5170 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5171 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5172 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5173 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5174 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5175 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5176 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5181 xhci_debugfs_create_root();
5187 * If an init function is provided, an exit function must also be provided
5188 * to allow module unload.
5190 static void __exit xhci_hcd_fini(void)
5192 xhci_debugfs_remove_root();
5195 module_init(xhci_hcd_init);
5196 module_exit(xhci_hcd_fini);