1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/slab.h>
17 #include <linux/dmi.h>
18 #include <linux/dma-mapping.h>
21 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
55 /* TODO: copied from ehci-hcd.c - can this be refactored? */
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
75 if (result == ~(u32)0) /* card removed */
87 * Disable interrupts and begin the xHCI halting process.
89 void xhci_quiesce(struct xhci_hcd *xhci)
96 halted = readl(&xhci->op_regs->status) & STS_HALT;
100 cmd = readl(&xhci->op_regs->command);
102 writel(cmd, &xhci->op_regs->command);
106 * Force HC into halt state.
108 * Disable any IRQs and clear the run/stop bit.
109 * HC will complete any current and actively pipelined transactions, and
110 * should halt within 16 ms of the run/stop bit being cleared.
111 * Read HC Halted bit in the status register to see when the HC is finished.
113 int xhci_halt(struct xhci_hcd *xhci)
116 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
119 ret = xhci_handshake(&xhci->op_regs->status,
120 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
122 xhci_warn(xhci, "Host halt failed, %d\n", ret);
125 xhci->xhc_state |= XHCI_STATE_HALTED;
126 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
131 * Set the run bit and wait for the host to be running.
133 int xhci_start(struct xhci_hcd *xhci)
138 temp = readl(&xhci->op_regs->command);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
142 writel(temp, &xhci->op_regs->command);
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
155 /* clear state flags. Including dying, halted or removing */
164 * This resets pipelines, timers, counters, state machines, etc.
165 * Transactions will be terminated immediately, and operational registers
166 * will be set to their defaults.
168 int xhci_reset(struct xhci_hcd *xhci)
174 state = readl(&xhci->op_regs->status);
176 if (state == ~(u32)0) {
177 xhci_warn(xhci, "Host not accessible, reset failed.\n");
181 if ((state & STS_HALT) == 0) {
182 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
186 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
187 command = readl(&xhci->op_regs->command);
188 command |= CMD_RESET;
189 writel(command, &xhci->op_regs->command);
191 /* Existing Intel xHCI controllers require a delay of 1 mS,
192 * after setting the CMD_RESET bit, and before accessing any
193 * HC registers. This allows the HC to complete the
194 * reset operation and be ready for HC register access.
195 * Without this delay, the subsequent HC register access,
196 * may result in a system hang very rarely.
198 if (xhci->quirks & XHCI_INTEL_HOST)
201 ret = xhci_handshake(&xhci->op_regs->command,
202 CMD_RESET, 0, 10 * 1000 * 1000);
206 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
207 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
209 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
210 "Wait for controller to be ready for doorbell rings");
212 * xHCI cannot write to any doorbells or operational registers other
213 * than status until the "Controller Not Ready" flag is cleared.
215 ret = xhci_handshake(&xhci->op_regs->status,
216 STS_CNR, 0, 10 * 1000 * 1000);
218 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
219 xhci->usb2_rhub.bus_state.suspended_ports = 0;
220 xhci->usb2_rhub.bus_state.resuming_ports = 0;
221 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
222 xhci->usb3_rhub.bus_state.suspended_ports = 0;
223 xhci->usb3_rhub.bus_state.resuming_ports = 0;
228 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
235 * Some Renesas controllers get into a weird state if they are
236 * reset while programmed with 64bit addresses (they will preserve
237 * the top half of the address in internal, non visible
238 * registers). You end up with half the address coming from the
239 * kernel, and the other half coming from the firmware. Also,
240 * changing the programming leads to extra accesses even if the
241 * controller is supposed to be halted. The controller ends up with
242 * a fatal fault, and is then ripe for being properly reset.
244 * Special care is taken to only apply this if the device is behind
245 * an iommu. Doing anything when there is no iommu is definitely
248 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
251 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
253 /* Clear HSEIE so that faults do not get signaled */
254 val = readl(&xhci->op_regs->command);
256 writel(val, &xhci->op_regs->command);
258 /* Clear HSE (aka FATAL) */
259 val = readl(&xhci->op_regs->status);
261 writel(val, &xhci->op_regs->status);
263 /* Now zero the registers, and brace for impact */
264 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
265 if (upper_32_bits(val))
266 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
267 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
268 if (upper_32_bits(val))
269 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
271 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
272 struct xhci_intr_reg __iomem *ir;
274 ir = &xhci->run_regs->ir_set[i];
275 val = xhci_read_64(xhci, &ir->erst_base);
276 if (upper_32_bits(val))
277 xhci_write_64(xhci, 0, &ir->erst_base);
278 val= xhci_read_64(xhci, &ir->erst_dequeue);
279 if (upper_32_bits(val))
280 xhci_write_64(xhci, 0, &ir->erst_dequeue);
283 /* Wait for the fault to appear. It will be cleared on reset */
284 err = xhci_handshake(&xhci->op_regs->status,
285 STS_FATAL, STS_FATAL,
288 xhci_info(xhci, "Fault detected\n");
291 #ifdef CONFIG_USB_PCI
295 static int xhci_setup_msi(struct xhci_hcd *xhci)
299 * TODO:Check with MSI Soc for sysdev
301 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
303 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
305 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
306 "failed to allocate MSI entry");
310 ret = request_irq(pdev->irq, xhci_msi_irq,
311 0, "xhci_hcd", xhci_to_hcd(xhci));
313 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
314 "disable MSI interrupt");
315 pci_free_irq_vectors(pdev);
324 static int xhci_setup_msix(struct xhci_hcd *xhci)
327 struct usb_hcd *hcd = xhci_to_hcd(xhci);
328 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
331 * calculate number of msi-x vectors supported.
332 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
333 * with max number of interrupters based on the xhci HCSPARAMS1.
334 * - num_online_cpus: maximum msi-x vectors per CPUs core.
335 * Add additional 1 vector to ensure always available interrupt.
337 xhci->msix_count = min(num_online_cpus() + 1,
338 HCS_MAX_INTRS(xhci->hcs_params1));
340 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
343 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
344 "Failed to enable MSI-X");
348 for (i = 0; i < xhci->msix_count; i++) {
349 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
350 "xhci_hcd", xhci_to_hcd(xhci));
355 hcd->msix_enabled = 1;
359 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
361 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
362 pci_free_irq_vectors(pdev);
366 /* Free any IRQs and disable MSI-X */
367 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
369 struct usb_hcd *hcd = xhci_to_hcd(xhci);
370 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
372 if (xhci->quirks & XHCI_PLAT)
375 /* return if using legacy interrupt */
379 if (hcd->msix_enabled) {
382 for (i = 0; i < xhci->msix_count; i++)
383 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
385 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
388 pci_free_irq_vectors(pdev);
389 hcd->msix_enabled = 0;
392 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
394 struct usb_hcd *hcd = xhci_to_hcd(xhci);
396 if (hcd->msix_enabled) {
397 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
400 for (i = 0; i < xhci->msix_count; i++)
401 synchronize_irq(pci_irq_vector(pdev, i));
405 static int xhci_try_enable_msi(struct usb_hcd *hcd)
407 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
408 struct pci_dev *pdev;
411 /* The xhci platform device has set up IRQs through usb_add_hcd. */
412 if (xhci->quirks & XHCI_PLAT)
415 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
417 * Some Fresco Logic host controllers advertise MSI, but fail to
418 * generate interrupts. Don't even try to enable MSI.
420 if (xhci->quirks & XHCI_BROKEN_MSI)
423 /* unregister the legacy interrupt */
425 free_irq(hcd->irq, hcd);
428 ret = xhci_setup_msix(xhci);
430 /* fall back to msi*/
431 ret = xhci_setup_msi(xhci);
434 hcd->msi_enabled = 1;
439 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
444 if (!strlen(hcd->irq_descr))
445 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
446 hcd->driver->description, hcd->self.busnum);
448 /* fall back to legacy interrupt*/
449 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
450 hcd->irq_descr, hcd);
452 xhci_err(xhci, "request interrupt %d failed\n",
456 hcd->irq = pdev->irq;
462 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
467 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
471 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
477 static void compliance_mode_recovery(struct timer_list *t)
479 struct xhci_hcd *xhci;
481 struct xhci_hub *rhub;
485 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
486 rhub = &xhci->usb3_rhub;
488 for (i = 0; i < rhub->num_ports; i++) {
489 temp = readl(rhub->ports[i]->addr);
490 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
492 * Compliance Mode Detected. Letting USB Core
493 * handle the Warm Reset
495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
496 "Compliance mode detected->port %d",
498 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
499 "Attempting compliance mode recovery");
500 hcd = xhci->shared_hcd;
502 if (hcd->state == HC_STATE_SUSPENDED)
503 usb_hcd_resume_root_hub(hcd);
505 usb_hcd_poll_rh_status(hcd);
509 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
510 mod_timer(&xhci->comp_mode_recovery_timer,
511 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
515 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
516 * that causes ports behind that hardware to enter compliance mode sometimes.
517 * The quirk creates a timer that polls every 2 seconds the link state of
518 * each host controller's port and recovers it by issuing a Warm reset
519 * if Compliance mode is detected, otherwise the port will become "dead" (no
520 * device connections or disconnections will be detected anymore). Becasue no
521 * status event is generated when entering compliance mode (per xhci spec),
522 * this quirk is needed on systems that have the failing hardware installed.
524 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
526 xhci->port_status_u0 = 0;
527 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
529 xhci->comp_mode_recovery_timer.expires = jiffies +
530 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
532 add_timer(&xhci->comp_mode_recovery_timer);
533 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
534 "Compliance mode recovery timer initialized");
538 * This function identifies the systems that have installed the SN65LVPE502CP
539 * USB3.0 re-driver and that need the Compliance Mode Quirk.
541 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
543 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
545 const char *dmi_product_name, *dmi_sys_vendor;
547 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
548 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
549 if (!dmi_product_name || !dmi_sys_vendor)
552 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
555 if (strstr(dmi_product_name, "Z420") ||
556 strstr(dmi_product_name, "Z620") ||
557 strstr(dmi_product_name, "Z820") ||
558 strstr(dmi_product_name, "Z1 Workstation"))
564 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
566 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
571 * Initialize memory for HCD and xHC (one-time init).
573 * Program the PAGESIZE register, initialize the device context array, create
574 * device contexts (?), set up a command ring segment (or two?), create event
575 * ring (one for now).
577 static int xhci_init(struct usb_hcd *hcd)
579 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
582 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
583 spin_lock_init(&xhci->lock);
584 if (xhci->hci_version == 0x95 && link_quirk) {
585 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
586 "QUIRK: Not clearing Link TRB chain bits.");
587 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
589 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
590 "xHCI doesn't need link TRB QUIRK");
592 retval = xhci_mem_init(xhci, GFP_KERNEL);
593 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
595 /* Initializing Compliance Mode Recovery Data If Needed */
596 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
597 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
598 compliance_mode_recovery_timer_init(xhci);
604 /*-------------------------------------------------------------------------*/
607 static int xhci_run_finished(struct xhci_hcd *xhci)
609 if (xhci_start(xhci)) {
613 xhci->shared_hcd->state = HC_STATE_RUNNING;
614 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
616 if (xhci->quirks & XHCI_NEC_HOST)
617 xhci_ring_cmd_db(xhci);
619 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
620 "Finished xhci_run for USB3 roothub");
625 * Start the HC after it was halted.
627 * This function is called by the USB core when the HC driver is added.
628 * Its opposite is xhci_stop().
630 * xhci_init() must be called once before this function can be called.
631 * Reset the HC, enable device slot contexts, program DCBAAP, and
632 * set command ring pointer and event ring pointer.
634 * Setup MSI-X vectors and enable interrupts.
636 int xhci_run(struct usb_hcd *hcd)
641 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
643 /* Start the xHCI host controller running only after the USB 2.0 roothub
647 hcd->uses_new_polling = 1;
648 if (!usb_hcd_is_primary_hcd(hcd))
649 return xhci_run_finished(xhci);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
653 ret = xhci_try_enable_msi(hcd);
657 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
658 temp_64 &= ~ERST_PTR_MASK;
659 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
660 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
662 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
663 "// Set the interrupt modulation register");
664 temp = readl(&xhci->ir_set->irq_control);
665 temp &= ~ER_IRQ_INTERVAL_MASK;
666 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
667 writel(temp, &xhci->ir_set->irq_control);
669 /* Set the HCD state before we enable the irqs */
670 temp = readl(&xhci->op_regs->command);
672 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
673 "// Enable interrupts, cmd = 0x%x.", temp);
674 writel(temp, &xhci->op_regs->command);
676 temp = readl(&xhci->ir_set->irq_pending);
677 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
678 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
679 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
680 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
682 if (xhci->quirks & XHCI_NEC_HOST) {
683 struct xhci_command *command;
685 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
689 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
690 TRB_TYPE(TRB_NEC_GET_FW));
692 xhci_free_command(xhci, command);
694 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
695 "Finished xhci_run for USB2 roothub");
699 xhci_debugfs_init(xhci);
703 EXPORT_SYMBOL_GPL(xhci_run);
708 * This function is called by the USB core when the HC driver is removed.
709 * Its opposite is xhci_run().
711 * Disable device contexts, disable IRQs, and quiesce the HC.
712 * Reset the HC, finish any completed transactions, and cleanup memory.
714 static void xhci_stop(struct usb_hcd *hcd)
717 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
719 mutex_lock(&xhci->mutex);
721 /* Only halt host and free memory after both hcds are removed */
722 if (!usb_hcd_is_primary_hcd(hcd)) {
723 mutex_unlock(&xhci->mutex);
729 spin_lock_irq(&xhci->lock);
730 xhci->xhc_state |= XHCI_STATE_HALTED;
731 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
734 spin_unlock_irq(&xhci->lock);
736 xhci_cleanup_msix(xhci);
738 /* Deleting Compliance Mode Recovery Timer */
739 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
740 (!(xhci_all_ports_seen_u0(xhci)))) {
741 del_timer_sync(&xhci->comp_mode_recovery_timer);
742 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
743 "%s: compliance mode recovery timer deleted",
747 if (xhci->quirks & XHCI_AMD_PLL_FIX)
750 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
751 "// Disabling event ring interrupts");
752 temp = readl(&xhci->op_regs->status);
753 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
754 temp = readl(&xhci->ir_set->irq_pending);
755 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
757 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
758 xhci_mem_cleanup(xhci);
759 xhci_debugfs_exit(xhci);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
761 "xhci_stop completed - status = %x",
762 readl(&xhci->op_regs->status));
763 mutex_unlock(&xhci->mutex);
767 * Shutdown HC (not bus-specific)
769 * This is called when the machine is rebooting or halting. We assume that the
770 * machine will be powered off, and the HC's internal state will be reset.
771 * Don't bother to free memory.
773 * This will only ever be called with the main usb_hcd (the USB3 roothub).
775 static void xhci_shutdown(struct usb_hcd *hcd)
777 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
779 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
780 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
782 spin_lock_irq(&xhci->lock);
784 /* Workaround for spurious wakeups at shutdown with HSW */
785 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
787 spin_unlock_irq(&xhci->lock);
789 xhci_cleanup_msix(xhci);
791 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
792 "xhci_shutdown completed - status = %x",
793 readl(&xhci->op_regs->status));
795 /* Yet another workaround for spurious wakeups at shutdown with HSW */
796 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
797 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
801 static void xhci_save_registers(struct xhci_hcd *xhci)
803 xhci->s3.command = readl(&xhci->op_regs->command);
804 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
805 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
806 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
807 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
808 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
809 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
810 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
811 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
814 static void xhci_restore_registers(struct xhci_hcd *xhci)
816 writel(xhci->s3.command, &xhci->op_regs->command);
817 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
818 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
819 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
820 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
821 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
822 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
823 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
824 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
827 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
831 /* step 2: initialize command ring buffer */
832 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
833 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
834 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
835 xhci->cmd_ring->dequeue) &
836 (u64) ~CMD_RING_RSVD_BITS) |
837 xhci->cmd_ring->cycle_state;
838 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
839 "// Setting command ring address to 0x%llx",
840 (long unsigned long) val_64);
841 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
845 * The whole command ring must be cleared to zero when we suspend the host.
847 * The host doesn't save the command ring pointer in the suspend well, so we
848 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
849 * aligned, because of the reserved bits in the command ring dequeue pointer
850 * register. Therefore, we can't just set the dequeue pointer back in the
851 * middle of the ring (TRBs are 16-byte aligned).
853 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
855 struct xhci_ring *ring;
856 struct xhci_segment *seg;
858 ring = xhci->cmd_ring;
862 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
863 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
864 cpu_to_le32(~TRB_CYCLE);
866 } while (seg != ring->deq_seg);
868 /* Reset the software enqueue and dequeue pointers */
869 ring->deq_seg = ring->first_seg;
870 ring->dequeue = ring->first_seg->trbs;
871 ring->enq_seg = ring->deq_seg;
872 ring->enqueue = ring->dequeue;
874 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
876 * Ring is now zeroed, so the HW should look for change of ownership
877 * when the cycle bit is set to 1.
879 ring->cycle_state = 1;
882 * Reset the hardware dequeue pointer.
883 * Yes, this will need to be re-written after resume, but we're paranoid
884 * and want to make sure the hardware doesn't access bogus memory
885 * because, say, the BIOS or an SMI started the host without changing
886 * the command ring pointers.
888 xhci_set_cmd_ring_deq(xhci);
891 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
893 struct xhci_port **ports;
898 spin_lock_irqsave(&xhci->lock, flags);
900 /* disable usb3 ports Wake bits */
901 port_index = xhci->usb3_rhub.num_ports;
902 ports = xhci->usb3_rhub.ports;
903 while (port_index--) {
904 t1 = readl(ports[port_index]->addr);
905 t1 = xhci_port_state_to_neutral(t1);
906 t2 = t1 & ~PORT_WAKE_BITS;
908 writel(t2, ports[port_index]->addr);
911 /* disable usb2 ports Wake bits */
912 port_index = xhci->usb2_rhub.num_ports;
913 ports = xhci->usb2_rhub.ports;
914 while (port_index--) {
915 t1 = readl(ports[port_index]->addr);
916 t1 = xhci_port_state_to_neutral(t1);
917 t2 = t1 & ~PORT_WAKE_BITS;
919 writel(t2, ports[port_index]->addr);
922 spin_unlock_irqrestore(&xhci->lock, flags);
925 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
927 struct xhci_port **ports;
932 status = readl(&xhci->op_regs->status);
933 if (status & STS_EINT)
936 * Checking STS_EINT is not enough as there is a lag between a change
937 * bit being set and the Port Status Change Event that it generated
938 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
941 port_index = xhci->usb2_rhub.num_ports;
942 ports = xhci->usb2_rhub.ports;
943 while (port_index--) {
944 portsc = readl(ports[port_index]->addr);
945 if (portsc & PORT_CHANGE_MASK ||
946 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
949 port_index = xhci->usb3_rhub.num_ports;
950 ports = xhci->usb3_rhub.ports;
951 while (port_index--) {
952 portsc = readl(ports[port_index]->addr);
953 if (portsc & PORT_CHANGE_MASK ||
954 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
961 * Stop HC (not bus-specific)
963 * This is called when the machine transition into S3/S4 mode.
966 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
969 unsigned int delay = XHCI_MAX_HALT_USEC;
970 struct usb_hcd *hcd = xhci_to_hcd(xhci);
977 if (hcd->state != HC_STATE_SUSPENDED ||
978 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
981 xhci_dbc_suspend(xhci);
983 /* Clear root port wake on bits if wakeup not allowed. */
985 xhci_disable_port_wake_on_bits(xhci);
987 /* Don't poll the roothubs on bus suspend. */
988 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
989 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
990 del_timer_sync(&hcd->rh_timer);
991 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
992 del_timer_sync(&xhci->shared_hcd->rh_timer);
994 if (xhci->quirks & XHCI_SUSPEND_DELAY)
995 usleep_range(1000, 1500);
997 spin_lock_irq(&xhci->lock);
998 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
999 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1000 /* step 1: stop endpoint */
1001 /* skipped assuming that port suspend has done */
1003 /* step 2: clear Run/Stop bit */
1004 command = readl(&xhci->op_regs->command);
1005 command &= ~CMD_RUN;
1006 writel(command, &xhci->op_regs->command);
1008 /* Some chips from Fresco Logic need an extraordinary delay */
1009 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1011 if (xhci_handshake(&xhci->op_regs->status,
1012 STS_HALT, STS_HALT, delay)) {
1013 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1014 spin_unlock_irq(&xhci->lock);
1017 xhci_clear_command_ring(xhci);
1019 /* step 3: save registers */
1020 xhci_save_registers(xhci);
1022 /* step 4: set CSS flag */
1023 command = readl(&xhci->op_regs->command);
1025 writel(command, &xhci->op_regs->command);
1026 xhci->broken_suspend = 0;
1027 if (xhci_handshake(&xhci->op_regs->status,
1028 STS_SAVE, 0, 10 * 1000)) {
1030 * AMD SNPS xHC 3.0 occasionally does not clear the
1031 * SSS bit of USBSTS and when driver tries to poll
1032 * to see if the xHC clears BIT(8) which never happens
1033 * and driver assumes that controller is not responding
1034 * and times out. To workaround this, its good to check
1035 * if SRE and HCE bits are not set (as per xhci
1036 * Section 5.4.2) and bypass the timeout.
1038 res = readl(&xhci->op_regs->status);
1039 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1040 (((res & STS_SRE) == 0) &&
1041 ((res & STS_HCE) == 0))) {
1042 xhci->broken_suspend = 1;
1044 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1045 spin_unlock_irq(&xhci->lock);
1049 spin_unlock_irq(&xhci->lock);
1052 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1053 * is about to be suspended.
1055 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1056 (!(xhci_all_ports_seen_u0(xhci)))) {
1057 del_timer_sync(&xhci->comp_mode_recovery_timer);
1058 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1059 "%s: compliance mode recovery timer deleted",
1063 /* step 5: remove core well power */
1064 /* synchronize irq when using MSI-X */
1065 xhci_msix_sync_irqs(xhci);
1069 EXPORT_SYMBOL_GPL(xhci_suspend);
1072 * start xHC (not bus-specific)
1074 * This is called when the machine transition from S3/S4 mode.
1077 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1079 u32 command, temp = 0;
1080 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1081 struct usb_hcd *secondary_hcd;
1083 bool comp_timer_running = false;
1088 /* Wait a bit if either of the roothubs need to settle from the
1089 * transition into bus suspend.
1092 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1093 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1096 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1097 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1099 spin_lock_irq(&xhci->lock);
1100 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1104 /* step 1: restore register */
1105 xhci_restore_registers(xhci);
1106 /* step 2: initialize command ring buffer */
1107 xhci_set_cmd_ring_deq(xhci);
1108 /* step 3: restore state and start state*/
1109 /* step 3: set CRS flag */
1110 command = readl(&xhci->op_regs->command);
1112 writel(command, &xhci->op_regs->command);
1114 * Some controllers take up to 55+ ms to complete the controller
1115 * restore so setting the timeout to 100ms. Xhci specification
1116 * doesn't mention any timeout value.
1118 if (xhci_handshake(&xhci->op_regs->status,
1119 STS_RESTORE, 0, 100 * 1000)) {
1120 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1121 spin_unlock_irq(&xhci->lock);
1124 temp = readl(&xhci->op_regs->status);
1127 /* If restore operation fails, re-initialize the HC during resume */
1128 if ((temp & STS_SRE) || hibernated) {
1130 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1131 !(xhci_all_ports_seen_u0(xhci))) {
1132 del_timer_sync(&xhci->comp_mode_recovery_timer);
1133 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1134 "Compliance Mode Recovery Timer deleted!");
1137 /* Let the USB core know _both_ roothubs lost power. */
1138 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1139 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1141 xhci_dbg(xhci, "Stop HCD\n");
1143 xhci_zero_64b_regs(xhci);
1145 spin_unlock_irq(&xhci->lock);
1146 xhci_cleanup_msix(xhci);
1148 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1149 temp = readl(&xhci->op_regs->status);
1150 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1151 temp = readl(&xhci->ir_set->irq_pending);
1152 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1154 xhci_dbg(xhci, "cleaning up memory\n");
1155 xhci_mem_cleanup(xhci);
1156 xhci_debugfs_exit(xhci);
1157 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1158 readl(&xhci->op_regs->status));
1160 /* USB core calls the PCI reinit and start functions twice:
1161 * first with the primary HCD, and then with the secondary HCD.
1162 * If we don't do the same, the host will never be started.
1164 if (!usb_hcd_is_primary_hcd(hcd))
1165 secondary_hcd = hcd;
1167 secondary_hcd = xhci->shared_hcd;
1169 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1170 retval = xhci_init(hcd->primary_hcd);
1173 comp_timer_running = true;
1175 xhci_dbg(xhci, "Start the primary HCD\n");
1176 retval = xhci_run(hcd->primary_hcd);
1178 xhci_dbg(xhci, "Start the secondary HCD\n");
1179 retval = xhci_run(secondary_hcd);
1181 hcd->state = HC_STATE_SUSPENDED;
1182 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1186 /* step 4: set Run/Stop bit */
1187 command = readl(&xhci->op_regs->command);
1189 writel(command, &xhci->op_regs->command);
1190 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1193 /* step 5: walk topology and initialize portsc,
1194 * portpmsc and portli
1196 /* this is done in bus_resume */
1198 /* step 6: restart each of the previously
1199 * Running endpoints by ringing their doorbells
1202 spin_unlock_irq(&xhci->lock);
1204 xhci_dbc_resume(xhci);
1208 /* Resume root hubs only when have pending events. */
1209 if (xhci_pending_portevent(xhci)) {
1210 usb_hcd_resume_root_hub(xhci->shared_hcd);
1211 usb_hcd_resume_root_hub(hcd);
1216 * If system is subject to the Quirk, Compliance Mode Timer needs to
1217 * be re-initialized Always after a system resume. Ports are subject
1218 * to suffer the Compliance Mode issue again. It doesn't matter if
1219 * ports have entered previously to U0 before system's suspension.
1221 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1222 compliance_mode_recovery_timer_init(xhci);
1224 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1225 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1227 /* Re-enable port polling. */
1228 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1229 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1230 usb_hcd_poll_rh_status(xhci->shared_hcd);
1231 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1232 usb_hcd_poll_rh_status(hcd);
1236 EXPORT_SYMBOL_GPL(xhci_resume);
1237 #endif /* CONFIG_PM */
1239 /*-------------------------------------------------------------------------*/
1242 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1243 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1244 * value to right shift 1 for the bitmask.
1246 * Index = (epnum * 2) + direction - 1,
1247 * where direction = 0 for OUT, 1 for IN.
1248 * For control endpoints, the IN index is used (OUT index is unused), so
1249 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1251 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1254 if (usb_endpoint_xfer_control(desc))
1255 index = (unsigned int) (usb_endpoint_num(desc)*2);
1257 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1258 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1262 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1263 * address from the XHCI endpoint index.
1265 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1267 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1268 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1269 return direction | number;
1272 /* Find the flag for this endpoint (for use in the control context). Use the
1273 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1276 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1278 return 1 << (xhci_get_endpoint_index(desc) + 1);
1281 /* Find the flag for this endpoint (for use in the control context). Use the
1282 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1285 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1287 return 1 << (ep_index + 1);
1290 /* Compute the last valid endpoint context index. Basically, this is the
1291 * endpoint index plus one. For slot contexts with more than valid endpoint,
1292 * we find the most significant bit set in the added contexts flags.
1293 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1294 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1296 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1298 return fls(added_ctxs) - 1;
1301 /* Returns 1 if the arguments are OK;
1302 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1304 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1305 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1307 struct xhci_hcd *xhci;
1308 struct xhci_virt_device *virt_dev;
1310 if (!hcd || (check_ep && !ep) || !udev) {
1311 pr_debug("xHCI %s called with invalid args\n", func);
1314 if (!udev->parent) {
1315 pr_debug("xHCI %s called for root hub\n", func);
1319 xhci = hcd_to_xhci(hcd);
1320 if (check_virt_dev) {
1321 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1322 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1327 virt_dev = xhci->devs[udev->slot_id];
1328 if (virt_dev->udev != udev) {
1329 xhci_dbg(xhci, "xHCI %s called with udev and "
1330 "virt_dev does not match\n", func);
1335 if (xhci->xhc_state & XHCI_STATE_HALTED)
1341 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1342 struct usb_device *udev, struct xhci_command *command,
1343 bool ctx_change, bool must_succeed);
1346 * Full speed devices may have a max packet size greater than 8 bytes, but the
1347 * USB core doesn't know that until it reads the first 8 bytes of the
1348 * descriptor. If the usb_device's max packet size changes after that point,
1349 * we need to issue an evaluate context command and wait on it.
1351 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1352 unsigned int ep_index, struct urb *urb)
1354 struct xhci_container_ctx *out_ctx;
1355 struct xhci_input_control_ctx *ctrl_ctx;
1356 struct xhci_ep_ctx *ep_ctx;
1357 struct xhci_command *command;
1358 int max_packet_size;
1359 int hw_max_packet_size;
1362 out_ctx = xhci->devs[slot_id]->out_ctx;
1363 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1364 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1365 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1366 if (hw_max_packet_size != max_packet_size) {
1367 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1368 "Max Packet Size for ep 0 changed.");
1369 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1370 "Max packet size in usb_device = %d",
1372 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1373 "Max packet size in xHCI HW = %d",
1374 hw_max_packet_size);
1375 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1376 "Issuing evaluate context command.");
1378 /* Set up the input context flags for the command */
1379 /* FIXME: This won't work if a non-default control endpoint
1380 * changes max packet sizes.
1383 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1387 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1388 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1390 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1393 goto command_cleanup;
1395 /* Set up the modified control endpoint 0 */
1396 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1397 xhci->devs[slot_id]->out_ctx, ep_index);
1399 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1400 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1401 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1403 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1404 ctrl_ctx->drop_flags = 0;
1406 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1409 /* Clean up the input context for later use by bandwidth
1412 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1414 kfree(command->completion);
1421 * non-error returns are a promise to giveback() the urb later
1422 * we drop ownership so next owner (or urb unlink) can get it
1424 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1426 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1427 unsigned long flags;
1429 unsigned int slot_id, ep_index;
1430 unsigned int *ep_state;
1431 struct urb_priv *urb_priv;
1434 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1435 true, true, __func__) <= 0)
1438 slot_id = urb->dev->slot_id;
1439 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1440 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1442 if (!HCD_HW_ACCESSIBLE(hcd)) {
1443 if (!in_interrupt())
1444 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1448 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1449 num_tds = urb->number_of_packets;
1450 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1451 urb->transfer_buffer_length > 0 &&
1452 urb->transfer_flags & URB_ZERO_PACKET &&
1453 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1458 urb_priv = kzalloc(sizeof(struct urb_priv) +
1459 num_tds * sizeof(struct xhci_td), mem_flags);
1463 urb_priv->num_tds = num_tds;
1464 urb_priv->num_tds_done = 0;
1465 urb->hcpriv = urb_priv;
1467 trace_xhci_urb_enqueue(urb);
1469 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1470 /* Check to see if the max packet size for the default control
1471 * endpoint changed during FS device enumeration
1473 if (urb->dev->speed == USB_SPEED_FULL) {
1474 ret = xhci_check_maxpacket(xhci, slot_id,
1477 xhci_urb_free_priv(urb_priv);
1484 spin_lock_irqsave(&xhci->lock, flags);
1486 if (xhci->xhc_state & XHCI_STATE_DYING) {
1487 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1488 urb->ep->desc.bEndpointAddress, urb);
1492 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1493 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1498 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1499 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1504 switch (usb_endpoint_type(&urb->ep->desc)) {
1506 case USB_ENDPOINT_XFER_CONTROL:
1507 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1510 case USB_ENDPOINT_XFER_BULK:
1511 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1514 case USB_ENDPOINT_XFER_INT:
1515 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1518 case USB_ENDPOINT_XFER_ISOC:
1519 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1525 xhci_urb_free_priv(urb_priv);
1528 spin_unlock_irqrestore(&xhci->lock, flags);
1533 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1534 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1535 * should pick up where it left off in the TD, unless a Set Transfer Ring
1536 * Dequeue Pointer is issued.
1538 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1539 * the ring. Since the ring is a contiguous structure, they can't be physically
1540 * removed. Instead, there are two options:
1542 * 1) If the HC is in the middle of processing the URB to be canceled, we
1543 * simply move the ring's dequeue pointer past those TRBs using the Set
1544 * Transfer Ring Dequeue Pointer command. This will be the common case,
1545 * when drivers timeout on the last submitted URB and attempt to cancel.
1547 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1548 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1549 * HC will need to invalidate the any TRBs it has cached after the stop
1550 * endpoint command, as noted in the xHCI 0.95 errata.
1552 * 3) The TD may have completed by the time the Stop Endpoint Command
1553 * completes, so software needs to handle that case too.
1555 * This function should protect against the TD enqueueing code ringing the
1556 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1557 * It also needs to account for multiple cancellations on happening at the same
1558 * time for the same endpoint.
1560 * Note that this function can be called in any context, or so says
1561 * usb_hcd_unlink_urb()
1563 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1565 unsigned long flags;
1568 struct xhci_hcd *xhci;
1569 struct urb_priv *urb_priv;
1571 unsigned int ep_index;
1572 struct xhci_ring *ep_ring;
1573 struct xhci_virt_ep *ep;
1574 struct xhci_command *command;
1575 struct xhci_virt_device *vdev;
1577 xhci = hcd_to_xhci(hcd);
1578 spin_lock_irqsave(&xhci->lock, flags);
1580 trace_xhci_urb_dequeue(urb);
1582 /* Make sure the URB hasn't completed or been unlinked already */
1583 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1587 /* give back URB now if we can't queue it for cancel */
1588 vdev = xhci->devs[urb->dev->slot_id];
1589 urb_priv = urb->hcpriv;
1590 if (!vdev || !urb_priv)
1593 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1594 ep = &vdev->eps[ep_index];
1595 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1596 if (!ep || !ep_ring)
1599 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1600 temp = readl(&xhci->op_regs->status);
1601 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1607 * check ring is not re-allocated since URB was enqueued. If it is, then
1608 * make sure none of the ring related pointers in this URB private data
1609 * are touched, such as td_list, otherwise we overwrite freed data
1611 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1612 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1613 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1614 td = &urb_priv->td[i];
1615 if (!list_empty(&td->cancelled_td_list))
1616 list_del_init(&td->cancelled_td_list);
1621 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1622 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1623 "HC halted, freeing TD manually.");
1624 for (i = urb_priv->num_tds_done;
1625 i < urb_priv->num_tds;
1627 td = &urb_priv->td[i];
1628 if (!list_empty(&td->td_list))
1629 list_del_init(&td->td_list);
1630 if (!list_empty(&td->cancelled_td_list))
1631 list_del_init(&td->cancelled_td_list);
1636 i = urb_priv->num_tds_done;
1637 if (i < urb_priv->num_tds)
1638 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1639 "Cancel URB %p, dev %s, ep 0x%x, "
1640 "starting at offset 0x%llx",
1641 urb, urb->dev->devpath,
1642 urb->ep->desc.bEndpointAddress,
1643 (unsigned long long) xhci_trb_virt_to_dma(
1644 urb_priv->td[i].start_seg,
1645 urb_priv->td[i].first_trb));
1647 for (; i < urb_priv->num_tds; i++) {
1648 td = &urb_priv->td[i];
1649 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1652 /* Queue a stop endpoint command, but only if this is
1653 * the first cancellation to be handled.
1655 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1656 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1661 ep->ep_state |= EP_STOP_CMD_PENDING;
1662 ep->stop_cmd_timer.expires = jiffies +
1663 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1664 add_timer(&ep->stop_cmd_timer);
1665 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1667 xhci_ring_cmd_db(xhci);
1670 spin_unlock_irqrestore(&xhci->lock, flags);
1675 xhci_urb_free_priv(urb_priv);
1676 usb_hcd_unlink_urb_from_ep(hcd, urb);
1677 spin_unlock_irqrestore(&xhci->lock, flags);
1678 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1682 /* Drop an endpoint from a new bandwidth configuration for this device.
1683 * Only one call to this function is allowed per endpoint before
1684 * check_bandwidth() or reset_bandwidth() must be called.
1685 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1686 * add the endpoint to the schedule with possibly new parameters denoted by a
1687 * different endpoint descriptor in usb_host_endpoint.
1688 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1691 * The USB core will not allow URBs to be queued to an endpoint that is being
1692 * disabled, so there's no need for mutual exclusion to protect
1693 * the xhci->devs[slot_id] structure.
1695 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1696 struct usb_host_endpoint *ep)
1698 struct xhci_hcd *xhci;
1699 struct xhci_container_ctx *in_ctx, *out_ctx;
1700 struct xhci_input_control_ctx *ctrl_ctx;
1701 unsigned int ep_index;
1702 struct xhci_ep_ctx *ep_ctx;
1704 u32 new_add_flags, new_drop_flags;
1707 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1710 xhci = hcd_to_xhci(hcd);
1711 if (xhci->xhc_state & XHCI_STATE_DYING)
1714 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1715 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1716 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1717 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1718 __func__, drop_flag);
1722 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1723 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1724 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1726 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1731 ep_index = xhci_get_endpoint_index(&ep->desc);
1732 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1733 /* If the HC already knows the endpoint is disabled,
1734 * or the HCD has noted it is disabled, ignore this request
1736 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1737 le32_to_cpu(ctrl_ctx->drop_flags) &
1738 xhci_get_endpoint_flag(&ep->desc)) {
1739 /* Do not warn when called after a usb_device_reset */
1740 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1741 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1746 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1747 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1749 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1750 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1752 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1754 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1756 if (xhci->quirks & XHCI_MTK_HOST)
1757 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1759 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1760 (unsigned int) ep->desc.bEndpointAddress,
1762 (unsigned int) new_drop_flags,
1763 (unsigned int) new_add_flags);
1767 /* Add an endpoint to a new possible bandwidth configuration for this device.
1768 * Only one call to this function is allowed per endpoint before
1769 * check_bandwidth() or reset_bandwidth() must be called.
1770 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1771 * add the endpoint to the schedule with possibly new parameters denoted by a
1772 * different endpoint descriptor in usb_host_endpoint.
1773 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1776 * The USB core will not allow URBs to be queued to an endpoint until the
1777 * configuration or alt setting is installed in the device, so there's no need
1778 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1780 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1781 struct usb_host_endpoint *ep)
1783 struct xhci_hcd *xhci;
1784 struct xhci_container_ctx *in_ctx;
1785 unsigned int ep_index;
1786 struct xhci_input_control_ctx *ctrl_ctx;
1788 u32 new_add_flags, new_drop_flags;
1789 struct xhci_virt_device *virt_dev;
1792 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1794 /* So we won't queue a reset ep command for a root hub */
1798 xhci = hcd_to_xhci(hcd);
1799 if (xhci->xhc_state & XHCI_STATE_DYING)
1802 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1803 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1804 /* FIXME when we have to issue an evaluate endpoint command to
1805 * deal with ep0 max packet size changing once we get the
1808 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1809 __func__, added_ctxs);
1813 virt_dev = xhci->devs[udev->slot_id];
1814 in_ctx = virt_dev->in_ctx;
1815 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1817 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1822 ep_index = xhci_get_endpoint_index(&ep->desc);
1823 /* If this endpoint is already in use, and the upper layers are trying
1824 * to add it again without dropping it, reject the addition.
1826 if (virt_dev->eps[ep_index].ring &&
1827 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1828 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1829 "without dropping it.\n",
1830 (unsigned int) ep->desc.bEndpointAddress);
1834 /* If the HCD has already noted the endpoint is enabled,
1835 * ignore this request.
1837 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1838 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1844 * Configuration and alternate setting changes must be done in
1845 * process context, not interrupt context (or so documenation
1846 * for usb_set_interface() and usb_set_configuration() claim).
1848 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1849 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1850 __func__, ep->desc.bEndpointAddress);
1854 if (xhci->quirks & XHCI_MTK_HOST) {
1855 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1857 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1858 virt_dev->eps[ep_index].new_ring = NULL;
1863 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1864 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1866 /* If xhci_endpoint_disable() was called for this endpoint, but the
1867 * xHC hasn't been notified yet through the check_bandwidth() call,
1868 * this re-adds a new state for the endpoint from the new endpoint
1869 * descriptors. We must drop and re-add this endpoint, so we leave the
1872 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1874 /* Store the usb_device pointer for later use */
1877 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1879 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1880 (unsigned int) ep->desc.bEndpointAddress,
1882 (unsigned int) new_drop_flags,
1883 (unsigned int) new_add_flags);
1887 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1889 struct xhci_input_control_ctx *ctrl_ctx;
1890 struct xhci_ep_ctx *ep_ctx;
1891 struct xhci_slot_ctx *slot_ctx;
1894 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1896 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1901 /* When a device's add flag and drop flag are zero, any subsequent
1902 * configure endpoint command will leave that endpoint's state
1903 * untouched. Make sure we don't leave any old state in the input
1904 * endpoint contexts.
1906 ctrl_ctx->drop_flags = 0;
1907 ctrl_ctx->add_flags = 0;
1908 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1909 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1910 /* Endpoint 0 is always valid */
1911 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1912 for (i = 1; i < 31; i++) {
1913 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1914 ep_ctx->ep_info = 0;
1915 ep_ctx->ep_info2 = 0;
1917 ep_ctx->tx_info = 0;
1921 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1922 struct usb_device *udev, u32 *cmd_status)
1926 switch (*cmd_status) {
1927 case COMP_COMMAND_ABORTED:
1928 case COMP_COMMAND_RING_STOPPED:
1929 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1932 case COMP_RESOURCE_ERROR:
1933 dev_warn(&udev->dev,
1934 "Not enough host controller resources for new device state.\n");
1936 /* FIXME: can we allocate more resources for the HC? */
1938 case COMP_BANDWIDTH_ERROR:
1939 case COMP_SECONDARY_BANDWIDTH_ERROR:
1940 dev_warn(&udev->dev,
1941 "Not enough bandwidth for new device state.\n");
1943 /* FIXME: can we go back to the old state? */
1945 case COMP_TRB_ERROR:
1946 /* the HCD set up something wrong */
1947 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1949 "and endpoint is not disabled.\n");
1952 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1953 dev_warn(&udev->dev,
1954 "ERROR: Incompatible device for endpoint configure command.\n");
1958 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1959 "Successful Endpoint Configure command");
1963 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1971 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1972 struct usb_device *udev, u32 *cmd_status)
1976 switch (*cmd_status) {
1977 case COMP_COMMAND_ABORTED:
1978 case COMP_COMMAND_RING_STOPPED:
1979 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1982 case COMP_PARAMETER_ERROR:
1983 dev_warn(&udev->dev,
1984 "WARN: xHCI driver setup invalid evaluate context command.\n");
1987 case COMP_SLOT_NOT_ENABLED_ERROR:
1988 dev_warn(&udev->dev,
1989 "WARN: slot not enabled for evaluate context command.\n");
1992 case COMP_CONTEXT_STATE_ERROR:
1993 dev_warn(&udev->dev,
1994 "WARN: invalid context state for evaluate context command.\n");
1997 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1998 dev_warn(&udev->dev,
1999 "ERROR: Incompatible device for evaluate context command.\n");
2002 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2003 /* Max Exit Latency too large error */
2004 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2008 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2009 "Successful evaluate context command");
2013 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2021 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2022 struct xhci_input_control_ctx *ctrl_ctx)
2024 u32 valid_add_flags;
2025 u32 valid_drop_flags;
2027 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2028 * (bit 1). The default control endpoint is added during the Address
2029 * Device command and is never removed until the slot is disabled.
2031 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2032 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2034 /* Use hweight32 to count the number of ones in the add flags, or
2035 * number of endpoints added. Don't count endpoints that are changed
2036 * (both added and dropped).
2038 return hweight32(valid_add_flags) -
2039 hweight32(valid_add_flags & valid_drop_flags);
2042 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2043 struct xhci_input_control_ctx *ctrl_ctx)
2045 u32 valid_add_flags;
2046 u32 valid_drop_flags;
2048 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2049 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2051 return hweight32(valid_drop_flags) -
2052 hweight32(valid_add_flags & valid_drop_flags);
2056 * We need to reserve the new number of endpoints before the configure endpoint
2057 * command completes. We can't subtract the dropped endpoints from the number
2058 * of active endpoints until the command completes because we can oversubscribe
2059 * the host in this case:
2061 * - the first configure endpoint command drops more endpoints than it adds
2062 * - a second configure endpoint command that adds more endpoints is queued
2063 * - the first configure endpoint command fails, so the config is unchanged
2064 * - the second command may succeed, even though there isn't enough resources
2066 * Must be called with xhci->lock held.
2068 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2069 struct xhci_input_control_ctx *ctrl_ctx)
2073 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2074 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2075 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2076 "Not enough ep ctxs: "
2077 "%u active, need to add %u, limit is %u.",
2078 xhci->num_active_eps, added_eps,
2079 xhci->limit_active_eps);
2082 xhci->num_active_eps += added_eps;
2083 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2084 "Adding %u ep ctxs, %u now active.", added_eps,
2085 xhci->num_active_eps);
2090 * The configure endpoint was failed by the xHC for some other reason, so we
2091 * need to revert the resources that failed configuration would have used.
2093 * Must be called with xhci->lock held.
2095 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2096 struct xhci_input_control_ctx *ctrl_ctx)
2100 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2101 xhci->num_active_eps -= num_failed_eps;
2102 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2103 "Removing %u failed ep ctxs, %u now active.",
2105 xhci->num_active_eps);
2109 * Now that the command has completed, clean up the active endpoint count by
2110 * subtracting out the endpoints that were dropped (but not changed).
2112 * Must be called with xhci->lock held.
2114 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2115 struct xhci_input_control_ctx *ctrl_ctx)
2117 u32 num_dropped_eps;
2119 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2120 xhci->num_active_eps -= num_dropped_eps;
2121 if (num_dropped_eps)
2122 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2123 "Removing %u dropped ep ctxs, %u now active.",
2125 xhci->num_active_eps);
2128 static unsigned int xhci_get_block_size(struct usb_device *udev)
2130 switch (udev->speed) {
2132 case USB_SPEED_FULL:
2134 case USB_SPEED_HIGH:
2136 case USB_SPEED_SUPER:
2137 case USB_SPEED_SUPER_PLUS:
2139 case USB_SPEED_UNKNOWN:
2140 case USB_SPEED_WIRELESS:
2142 /* Should never happen */
2148 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2150 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2152 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2157 /* If we are changing a LS/FS device under a HS hub,
2158 * make sure (if we are activating a new TT) that the HS bus has enough
2159 * bandwidth for this new TT.
2161 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2162 struct xhci_virt_device *virt_dev,
2165 struct xhci_interval_bw_table *bw_table;
2166 struct xhci_tt_bw_info *tt_info;
2168 /* Find the bandwidth table for the root port this TT is attached to. */
2169 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2170 tt_info = virt_dev->tt_info;
2171 /* If this TT already had active endpoints, the bandwidth for this TT
2172 * has already been added. Removing all periodic endpoints (and thus
2173 * making the TT enactive) will only decrease the bandwidth used.
2177 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2178 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2182 /* Not sure why we would have no new active endpoints...
2184 * Maybe because of an Evaluate Context change for a hub update or a
2185 * control endpoint 0 max packet size change?
2186 * FIXME: skip the bandwidth calculation in that case.
2191 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2192 struct xhci_virt_device *virt_dev)
2194 unsigned int bw_reserved;
2196 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2197 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2200 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2201 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2208 * This algorithm is a very conservative estimate of the worst-case scheduling
2209 * scenario for any one interval. The hardware dynamically schedules the
2210 * packets, so we can't tell which microframe could be the limiting factor in
2211 * the bandwidth scheduling. This only takes into account periodic endpoints.
2213 * Obviously, we can't solve an NP complete problem to find the minimum worst
2214 * case scenario. Instead, we come up with an estimate that is no less than
2215 * the worst case bandwidth used for any one microframe, but may be an
2218 * We walk the requirements for each endpoint by interval, starting with the
2219 * smallest interval, and place packets in the schedule where there is only one
2220 * possible way to schedule packets for that interval. In order to simplify
2221 * this algorithm, we record the largest max packet size for each interval, and
2222 * assume all packets will be that size.
2224 * For interval 0, we obviously must schedule all packets for each interval.
2225 * The bandwidth for interval 0 is just the amount of data to be transmitted
2226 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2227 * the number of packets).
2229 * For interval 1, we have two possible microframes to schedule those packets
2230 * in. For this algorithm, if we can schedule the same number of packets for
2231 * each possible scheduling opportunity (each microframe), we will do so. The
2232 * remaining number of packets will be saved to be transmitted in the gaps in
2233 * the next interval's scheduling sequence.
2235 * As we move those remaining packets to be scheduled with interval 2 packets,
2236 * we have to double the number of remaining packets to transmit. This is
2237 * because the intervals are actually powers of 2, and we would be transmitting
2238 * the previous interval's packets twice in this interval. We also have to be
2239 * sure that when we look at the largest max packet size for this interval, we
2240 * also look at the largest max packet size for the remaining packets and take
2241 * the greater of the two.
2243 * The algorithm continues to evenly distribute packets in each scheduling
2244 * opportunity, and push the remaining packets out, until we get to the last
2245 * interval. Then those packets and their associated overhead are just added
2246 * to the bandwidth used.
2248 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2249 struct xhci_virt_device *virt_dev,
2252 unsigned int bw_reserved;
2253 unsigned int max_bandwidth;
2254 unsigned int bw_used;
2255 unsigned int block_size;
2256 struct xhci_interval_bw_table *bw_table;
2257 unsigned int packet_size = 0;
2258 unsigned int overhead = 0;
2259 unsigned int packets_transmitted = 0;
2260 unsigned int packets_remaining = 0;
2263 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2264 return xhci_check_ss_bw(xhci, virt_dev);
2266 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2267 max_bandwidth = HS_BW_LIMIT;
2268 /* Convert percent of bus BW reserved to blocks reserved */
2269 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2271 max_bandwidth = FS_BW_LIMIT;
2272 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2275 bw_table = virt_dev->bw_table;
2276 /* We need to translate the max packet size and max ESIT payloads into
2277 * the units the hardware uses.
2279 block_size = xhci_get_block_size(virt_dev->udev);
2281 /* If we are manipulating a LS/FS device under a HS hub, double check
2282 * that the HS bus has enough bandwidth if we are activing a new TT.
2284 if (virt_dev->tt_info) {
2285 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2286 "Recalculating BW for rootport %u",
2287 virt_dev->real_port);
2288 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2289 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2290 "newly activated TT.\n");
2293 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2294 "Recalculating BW for TT slot %u port %u",
2295 virt_dev->tt_info->slot_id,
2296 virt_dev->tt_info->ttport);
2298 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2299 "Recalculating BW for rootport %u",
2300 virt_dev->real_port);
2303 /* Add in how much bandwidth will be used for interval zero, or the
2304 * rounded max ESIT payload + number of packets * largest overhead.
2306 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2307 bw_table->interval_bw[0].num_packets *
2308 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2310 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2311 unsigned int bw_added;
2312 unsigned int largest_mps;
2313 unsigned int interval_overhead;
2316 * How many packets could we transmit in this interval?
2317 * If packets didn't fit in the previous interval, we will need
2318 * to transmit that many packets twice within this interval.
2320 packets_remaining = 2 * packets_remaining +
2321 bw_table->interval_bw[i].num_packets;
2323 /* Find the largest max packet size of this or the previous
2326 if (list_empty(&bw_table->interval_bw[i].endpoints))
2329 struct xhci_virt_ep *virt_ep;
2330 struct list_head *ep_entry;
2332 ep_entry = bw_table->interval_bw[i].endpoints.next;
2333 virt_ep = list_entry(ep_entry,
2334 struct xhci_virt_ep, bw_endpoint_list);
2335 /* Convert to blocks, rounding up */
2336 largest_mps = DIV_ROUND_UP(
2337 virt_ep->bw_info.max_packet_size,
2340 if (largest_mps > packet_size)
2341 packet_size = largest_mps;
2343 /* Use the larger overhead of this or the previous interval. */
2344 interval_overhead = xhci_get_largest_overhead(
2345 &bw_table->interval_bw[i]);
2346 if (interval_overhead > overhead)
2347 overhead = interval_overhead;
2349 /* How many packets can we evenly distribute across
2350 * (1 << (i + 1)) possible scheduling opportunities?
2352 packets_transmitted = packets_remaining >> (i + 1);
2354 /* Add in the bandwidth used for those scheduled packets */
2355 bw_added = packets_transmitted * (overhead + packet_size);
2357 /* How many packets do we have remaining to transmit? */
2358 packets_remaining = packets_remaining % (1 << (i + 1));
2360 /* What largest max packet size should those packets have? */
2361 /* If we've transmitted all packets, don't carry over the
2362 * largest packet size.
2364 if (packets_remaining == 0) {
2367 } else if (packets_transmitted > 0) {
2368 /* Otherwise if we do have remaining packets, and we've
2369 * scheduled some packets in this interval, take the
2370 * largest max packet size from endpoints with this
2373 packet_size = largest_mps;
2374 overhead = interval_overhead;
2376 /* Otherwise carry over packet_size and overhead from the last
2377 * time we had a remainder.
2379 bw_used += bw_added;
2380 if (bw_used > max_bandwidth) {
2381 xhci_warn(xhci, "Not enough bandwidth. "
2382 "Proposed: %u, Max: %u\n",
2383 bw_used, max_bandwidth);
2388 * Ok, we know we have some packets left over after even-handedly
2389 * scheduling interval 15. We don't know which microframes they will
2390 * fit into, so we over-schedule and say they will be scheduled every
2393 if (packets_remaining > 0)
2394 bw_used += overhead + packet_size;
2396 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2397 unsigned int port_index = virt_dev->real_port - 1;
2399 /* OK, we're manipulating a HS device attached to a
2400 * root port bandwidth domain. Include the number of active TTs
2401 * in the bandwidth used.
2403 bw_used += TT_HS_OVERHEAD *
2404 xhci->rh_bw[port_index].num_active_tts;
2407 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2408 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2409 "Available: %u " "percent",
2410 bw_used, max_bandwidth, bw_reserved,
2411 (max_bandwidth - bw_used - bw_reserved) * 100 /
2414 bw_used += bw_reserved;
2415 if (bw_used > max_bandwidth) {
2416 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2417 bw_used, max_bandwidth);
2421 bw_table->bw_used = bw_used;
2425 static bool xhci_is_async_ep(unsigned int ep_type)
2427 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2428 ep_type != ISOC_IN_EP &&
2429 ep_type != INT_IN_EP);
2432 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2434 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2437 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2439 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2441 if (ep_bw->ep_interval == 0)
2442 return SS_OVERHEAD_BURST +
2443 (ep_bw->mult * ep_bw->num_packets *
2444 (SS_OVERHEAD + mps));
2445 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2446 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2447 1 << ep_bw->ep_interval);
2451 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2452 struct xhci_bw_info *ep_bw,
2453 struct xhci_interval_bw_table *bw_table,
2454 struct usb_device *udev,
2455 struct xhci_virt_ep *virt_ep,
2456 struct xhci_tt_bw_info *tt_info)
2458 struct xhci_interval_bw *interval_bw;
2459 int normalized_interval;
2461 if (xhci_is_async_ep(ep_bw->type))
2464 if (udev->speed >= USB_SPEED_SUPER) {
2465 if (xhci_is_sync_in_ep(ep_bw->type))
2466 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2467 xhci_get_ss_bw_consumed(ep_bw);
2469 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2470 xhci_get_ss_bw_consumed(ep_bw);
2474 /* SuperSpeed endpoints never get added to intervals in the table, so
2475 * this check is only valid for HS/FS/LS devices.
2477 if (list_empty(&virt_ep->bw_endpoint_list))
2479 /* For LS/FS devices, we need to translate the interval expressed in
2480 * microframes to frames.
2482 if (udev->speed == USB_SPEED_HIGH)
2483 normalized_interval = ep_bw->ep_interval;
2485 normalized_interval = ep_bw->ep_interval - 3;
2487 if (normalized_interval == 0)
2488 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2489 interval_bw = &bw_table->interval_bw[normalized_interval];
2490 interval_bw->num_packets -= ep_bw->num_packets;
2491 switch (udev->speed) {
2493 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2495 case USB_SPEED_FULL:
2496 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2498 case USB_SPEED_HIGH:
2499 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2501 case USB_SPEED_SUPER:
2502 case USB_SPEED_SUPER_PLUS:
2503 case USB_SPEED_UNKNOWN:
2504 case USB_SPEED_WIRELESS:
2505 /* Should never happen because only LS/FS/HS endpoints will get
2506 * added to the endpoint list.
2511 tt_info->active_eps -= 1;
2512 list_del_init(&virt_ep->bw_endpoint_list);
2515 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2516 struct xhci_bw_info *ep_bw,
2517 struct xhci_interval_bw_table *bw_table,
2518 struct usb_device *udev,
2519 struct xhci_virt_ep *virt_ep,
2520 struct xhci_tt_bw_info *tt_info)
2522 struct xhci_interval_bw *interval_bw;
2523 struct xhci_virt_ep *smaller_ep;
2524 int normalized_interval;
2526 if (xhci_is_async_ep(ep_bw->type))
2529 if (udev->speed == USB_SPEED_SUPER) {
2530 if (xhci_is_sync_in_ep(ep_bw->type))
2531 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2532 xhci_get_ss_bw_consumed(ep_bw);
2534 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2535 xhci_get_ss_bw_consumed(ep_bw);
2539 /* For LS/FS devices, we need to translate the interval expressed in
2540 * microframes to frames.
2542 if (udev->speed == USB_SPEED_HIGH)
2543 normalized_interval = ep_bw->ep_interval;
2545 normalized_interval = ep_bw->ep_interval - 3;
2547 if (normalized_interval == 0)
2548 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2549 interval_bw = &bw_table->interval_bw[normalized_interval];
2550 interval_bw->num_packets += ep_bw->num_packets;
2551 switch (udev->speed) {
2553 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2555 case USB_SPEED_FULL:
2556 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2558 case USB_SPEED_HIGH:
2559 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2561 case USB_SPEED_SUPER:
2562 case USB_SPEED_SUPER_PLUS:
2563 case USB_SPEED_UNKNOWN:
2564 case USB_SPEED_WIRELESS:
2565 /* Should never happen because only LS/FS/HS endpoints will get
2566 * added to the endpoint list.
2572 tt_info->active_eps += 1;
2573 /* Insert the endpoint into the list, largest max packet size first. */
2574 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2576 if (ep_bw->max_packet_size >=
2577 smaller_ep->bw_info.max_packet_size) {
2578 /* Add the new ep before the smaller endpoint */
2579 list_add_tail(&virt_ep->bw_endpoint_list,
2580 &smaller_ep->bw_endpoint_list);
2584 /* Add the new endpoint at the end of the list. */
2585 list_add_tail(&virt_ep->bw_endpoint_list,
2586 &interval_bw->endpoints);
2589 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2590 struct xhci_virt_device *virt_dev,
2593 struct xhci_root_port_bw_info *rh_bw_info;
2594 if (!virt_dev->tt_info)
2597 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2598 if (old_active_eps == 0 &&
2599 virt_dev->tt_info->active_eps != 0) {
2600 rh_bw_info->num_active_tts += 1;
2601 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2602 } else if (old_active_eps != 0 &&
2603 virt_dev->tt_info->active_eps == 0) {
2604 rh_bw_info->num_active_tts -= 1;
2605 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2609 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2610 struct xhci_virt_device *virt_dev,
2611 struct xhci_container_ctx *in_ctx)
2613 struct xhci_bw_info ep_bw_info[31];
2615 struct xhci_input_control_ctx *ctrl_ctx;
2616 int old_active_eps = 0;
2618 if (virt_dev->tt_info)
2619 old_active_eps = virt_dev->tt_info->active_eps;
2621 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2623 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2628 for (i = 0; i < 31; i++) {
2629 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2632 /* Make a copy of the BW info in case we need to revert this */
2633 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2634 sizeof(ep_bw_info[i]));
2635 /* Drop the endpoint from the interval table if the endpoint is
2636 * being dropped or changed.
2638 if (EP_IS_DROPPED(ctrl_ctx, i))
2639 xhci_drop_ep_from_interval_table(xhci,
2640 &virt_dev->eps[i].bw_info,
2646 /* Overwrite the information stored in the endpoints' bw_info */
2647 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2648 for (i = 0; i < 31; i++) {
2649 /* Add any changed or added endpoints to the interval table */
2650 if (EP_IS_ADDED(ctrl_ctx, i))
2651 xhci_add_ep_to_interval_table(xhci,
2652 &virt_dev->eps[i].bw_info,
2659 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2660 /* Ok, this fits in the bandwidth we have.
2661 * Update the number of active TTs.
2663 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2667 /* We don't have enough bandwidth for this, revert the stored info. */
2668 for (i = 0; i < 31; i++) {
2669 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2672 /* Drop the new copies of any added or changed endpoints from
2673 * the interval table.
2675 if (EP_IS_ADDED(ctrl_ctx, i)) {
2676 xhci_drop_ep_from_interval_table(xhci,
2677 &virt_dev->eps[i].bw_info,
2683 /* Revert the endpoint back to its old information */
2684 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2685 sizeof(ep_bw_info[i]));
2686 /* Add any changed or dropped endpoints back into the table */
2687 if (EP_IS_DROPPED(ctrl_ctx, i))
2688 xhci_add_ep_to_interval_table(xhci,
2689 &virt_dev->eps[i].bw_info,
2699 /* Issue a configure endpoint command or evaluate context command
2700 * and wait for it to finish.
2702 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2703 struct usb_device *udev,
2704 struct xhci_command *command,
2705 bool ctx_change, bool must_succeed)
2708 unsigned long flags;
2709 struct xhci_input_control_ctx *ctrl_ctx;
2710 struct xhci_virt_device *virt_dev;
2711 struct xhci_slot_ctx *slot_ctx;
2716 spin_lock_irqsave(&xhci->lock, flags);
2718 if (xhci->xhc_state & XHCI_STATE_DYING) {
2719 spin_unlock_irqrestore(&xhci->lock, flags);
2723 virt_dev = xhci->devs[udev->slot_id];
2725 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2727 spin_unlock_irqrestore(&xhci->lock, flags);
2728 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2733 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2734 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2735 spin_unlock_irqrestore(&xhci->lock, flags);
2736 xhci_warn(xhci, "Not enough host resources, "
2737 "active endpoint contexts = %u\n",
2738 xhci->num_active_eps);
2741 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2742 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2743 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2744 xhci_free_host_resources(xhci, ctrl_ctx);
2745 spin_unlock_irqrestore(&xhci->lock, flags);
2746 xhci_warn(xhci, "Not enough bandwidth\n");
2750 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2751 trace_xhci_configure_endpoint(slot_ctx);
2754 ret = xhci_queue_configure_endpoint(xhci, command,
2755 command->in_ctx->dma,
2756 udev->slot_id, must_succeed);
2758 ret = xhci_queue_evaluate_context(xhci, command,
2759 command->in_ctx->dma,
2760 udev->slot_id, must_succeed);
2762 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2763 xhci_free_host_resources(xhci, ctrl_ctx);
2764 spin_unlock_irqrestore(&xhci->lock, flags);
2765 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2766 "FIXME allocate a new ring segment");
2769 xhci_ring_cmd_db(xhci);
2770 spin_unlock_irqrestore(&xhci->lock, flags);
2772 /* Wait for the configure endpoint command to complete */
2773 wait_for_completion(command->completion);
2776 ret = xhci_configure_endpoint_result(xhci, udev,
2779 ret = xhci_evaluate_context_result(xhci, udev,
2782 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2783 spin_lock_irqsave(&xhci->lock, flags);
2784 /* If the command failed, remove the reserved resources.
2785 * Otherwise, clean up the estimate to include dropped eps.
2788 xhci_free_host_resources(xhci, ctrl_ctx);
2790 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2791 spin_unlock_irqrestore(&xhci->lock, flags);
2796 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2797 struct xhci_virt_device *vdev, int i)
2799 struct xhci_virt_ep *ep = &vdev->eps[i];
2801 if (ep->ep_state & EP_HAS_STREAMS) {
2802 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2803 xhci_get_endpoint_address(i));
2804 xhci_free_stream_info(xhci, ep->stream_info);
2805 ep->stream_info = NULL;
2806 ep->ep_state &= ~EP_HAS_STREAMS;
2810 /* Called after one or more calls to xhci_add_endpoint() or
2811 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2812 * to call xhci_reset_bandwidth().
2814 * Since we are in the middle of changing either configuration or
2815 * installing a new alt setting, the USB core won't allow URBs to be
2816 * enqueued for any endpoint on the old config or interface. Nothing
2817 * else should be touching the xhci->devs[slot_id] structure, so we
2818 * don't need to take the xhci->lock for manipulating that.
2820 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2824 struct xhci_hcd *xhci;
2825 struct xhci_virt_device *virt_dev;
2826 struct xhci_input_control_ctx *ctrl_ctx;
2827 struct xhci_slot_ctx *slot_ctx;
2828 struct xhci_command *command;
2830 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2833 xhci = hcd_to_xhci(hcd);
2834 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2835 (xhci->xhc_state & XHCI_STATE_REMOVING))
2838 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2839 virt_dev = xhci->devs[udev->slot_id];
2841 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2845 command->in_ctx = virt_dev->in_ctx;
2847 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2848 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2850 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2853 goto command_cleanup;
2855 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2856 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2857 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2859 /* Don't issue the command if there's no endpoints to update. */
2860 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2861 ctrl_ctx->drop_flags == 0) {
2863 goto command_cleanup;
2865 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2866 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2867 for (i = 31; i >= 1; i--) {
2868 __le32 le32 = cpu_to_le32(BIT(i));
2870 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2871 || (ctrl_ctx->add_flags & le32) || i == 1) {
2872 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2873 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2878 ret = xhci_configure_endpoint(xhci, udev, command,
2881 /* Callee should call reset_bandwidth() */
2882 goto command_cleanup;
2884 /* Free any rings that were dropped, but not changed. */
2885 for (i = 1; i < 31; i++) {
2886 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2887 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2888 xhci_free_endpoint_ring(xhci, virt_dev, i);
2889 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2892 xhci_zero_in_ctx(xhci, virt_dev);
2894 * Install any rings for completely new endpoints or changed endpoints,
2895 * and free any old rings from changed endpoints.
2897 for (i = 1; i < 31; i++) {
2898 if (!virt_dev->eps[i].new_ring)
2900 /* Only free the old ring if it exists.
2901 * It may not if this is the first add of an endpoint.
2903 if (virt_dev->eps[i].ring) {
2904 xhci_free_endpoint_ring(xhci, virt_dev, i);
2906 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2907 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2908 virt_dev->eps[i].new_ring = NULL;
2911 kfree(command->completion);
2917 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2919 struct xhci_hcd *xhci;
2920 struct xhci_virt_device *virt_dev;
2923 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2926 xhci = hcd_to_xhci(hcd);
2928 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2929 virt_dev = xhci->devs[udev->slot_id];
2930 /* Free any rings allocated for added endpoints */
2931 for (i = 0; i < 31; i++) {
2932 if (virt_dev->eps[i].new_ring) {
2933 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2934 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2935 virt_dev->eps[i].new_ring = NULL;
2938 xhci_zero_in_ctx(xhci, virt_dev);
2941 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2942 struct xhci_container_ctx *in_ctx,
2943 struct xhci_container_ctx *out_ctx,
2944 struct xhci_input_control_ctx *ctrl_ctx,
2945 u32 add_flags, u32 drop_flags)
2947 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2948 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2949 xhci_slot_copy(xhci, in_ctx, out_ctx);
2950 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2953 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2954 unsigned int slot_id, unsigned int ep_index,
2955 struct xhci_dequeue_state *deq_state)
2957 struct xhci_input_control_ctx *ctrl_ctx;
2958 struct xhci_container_ctx *in_ctx;
2959 struct xhci_ep_ctx *ep_ctx;
2963 in_ctx = xhci->devs[slot_id]->in_ctx;
2964 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2966 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2971 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2972 xhci->devs[slot_id]->out_ctx, ep_index);
2973 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2974 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2975 deq_state->new_deq_ptr);
2977 xhci_warn(xhci, "WARN Cannot submit config ep after "
2978 "reset ep command\n");
2979 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2980 deq_state->new_deq_seg,
2981 deq_state->new_deq_ptr);
2984 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2986 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2987 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2988 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2989 added_ctxs, added_ctxs);
2992 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2993 unsigned int stream_id, struct xhci_td *td)
2995 struct xhci_dequeue_state deq_state;
2996 struct usb_device *udev = td->urb->dev;
2998 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2999 "Cleaning up stalled endpoint ring");
3000 /* We need to move the HW's dequeue pointer past this TD,
3001 * or it will attempt to resend it on the next doorbell ring.
3003 xhci_find_new_dequeue_state(xhci, udev->slot_id,
3004 ep_index, stream_id, td, &deq_state);
3006 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3009 /* HW with the reset endpoint quirk will use the saved dequeue state to
3010 * issue a configure endpoint command later.
3012 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3013 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3014 "Queueing new dequeue state");
3015 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
3016 ep_index, &deq_state);
3018 /* Better hope no one uses the input context between now and the
3019 * reset endpoint completion!
3020 * XXX: No idea how this hardware will react when stream rings
3023 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3024 "Setting up input context for "
3025 "configure endpoint command");
3026 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3027 ep_index, &deq_state);
3032 * Called after usb core issues a clear halt control message.
3033 * The host side of the halt should already be cleared by a reset endpoint
3034 * command issued when the STALL event was received.
3036 * The reset endpoint command may only be issued to endpoints in the halted
3037 * state. For software that wishes to reset the data toggle or sequence number
3038 * of an endpoint that isn't in the halted state this function will issue a
3039 * configure endpoint command with the Drop and Add bits set for the target
3040 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3043 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3044 struct usb_host_endpoint *host_ep)
3046 struct xhci_hcd *xhci;
3047 struct usb_device *udev;
3048 struct xhci_virt_device *vdev;
3049 struct xhci_virt_ep *ep;
3050 struct xhci_input_control_ctx *ctrl_ctx;
3051 struct xhci_command *stop_cmd, *cfg_cmd;
3052 unsigned int ep_index;
3053 unsigned long flags;
3056 xhci = hcd_to_xhci(hcd);
3057 if (!host_ep->hcpriv)
3059 udev = (struct usb_device *) host_ep->hcpriv;
3060 vdev = xhci->devs[udev->slot_id];
3061 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3062 ep = &vdev->eps[ep_index];
3064 /* Bail out if toggle is already being cleared by a endpoint reset */
3065 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3066 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3069 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3070 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3071 usb_endpoint_xfer_isoc(&host_ep->desc))
3074 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3076 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3079 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3083 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3087 spin_lock_irqsave(&xhci->lock, flags);
3089 /* block queuing new trbs and ringing ep doorbell */
3090 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3093 * Make sure endpoint ring is empty before resetting the toggle/seq.
3094 * Driver is required to synchronously cancel all transfer request.
3095 * Stop the endpoint to force xHC to update the output context
3098 if (!list_empty(&ep->ring->td_list)) {
3099 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3100 spin_unlock_irqrestore(&xhci->lock, flags);
3101 xhci_free_command(xhci, cfg_cmd);
3104 xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
3105 xhci_ring_cmd_db(xhci);
3106 spin_unlock_irqrestore(&xhci->lock, flags);
3108 wait_for_completion(stop_cmd->completion);
3110 spin_lock_irqsave(&xhci->lock, flags);
3112 /* config ep command clears toggle if add and drop ep flags are set */
3113 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3114 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3115 ctrl_ctx, ep_flag, ep_flag);
3116 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3118 xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3119 udev->slot_id, false);
3120 xhci_ring_cmd_db(xhci);
3121 spin_unlock_irqrestore(&xhci->lock, flags);
3123 wait_for_completion(cfg_cmd->completion);
3125 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3126 xhci_free_command(xhci, cfg_cmd);
3128 xhci_free_command(xhci, stop_cmd);
3131 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3132 struct usb_device *udev, struct usb_host_endpoint *ep,
3133 unsigned int slot_id)
3136 unsigned int ep_index;
3137 unsigned int ep_state;
3141 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3144 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3145 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3146 " descriptor for ep 0x%x does not support streams\n",
3147 ep->desc.bEndpointAddress);
3151 ep_index = xhci_get_endpoint_index(&ep->desc);
3152 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3153 if (ep_state & EP_HAS_STREAMS ||
3154 ep_state & EP_GETTING_STREAMS) {
3155 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3156 "already has streams set up.\n",
3157 ep->desc.bEndpointAddress);
3158 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3159 "dynamic stream context array reallocation.\n");
3162 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3163 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3164 "endpoint 0x%x; URBs are pending.\n",
3165 ep->desc.bEndpointAddress);
3171 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3172 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3174 unsigned int max_streams;
3176 /* The stream context array size must be a power of two */
3177 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3179 * Find out how many primary stream array entries the host controller
3180 * supports. Later we may use secondary stream arrays (similar to 2nd
3181 * level page entries), but that's an optional feature for xHCI host
3182 * controllers. xHCs must support at least 4 stream IDs.
3184 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3185 if (*num_stream_ctxs > max_streams) {
3186 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3188 *num_stream_ctxs = max_streams;
3189 *num_streams = max_streams;
3193 /* Returns an error code if one of the endpoint already has streams.
3194 * This does not change any data structures, it only checks and gathers
3197 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3198 struct usb_device *udev,
3199 struct usb_host_endpoint **eps, unsigned int num_eps,
3200 unsigned int *num_streams, u32 *changed_ep_bitmask)
3202 unsigned int max_streams;
3203 unsigned int endpoint_flag;
3207 for (i = 0; i < num_eps; i++) {
3208 ret = xhci_check_streams_endpoint(xhci, udev,
3209 eps[i], udev->slot_id);
3213 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3214 if (max_streams < (*num_streams - 1)) {
3215 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3216 eps[i]->desc.bEndpointAddress,
3218 *num_streams = max_streams+1;
3221 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3222 if (*changed_ep_bitmask & endpoint_flag)
3224 *changed_ep_bitmask |= endpoint_flag;
3229 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3230 struct usb_device *udev,
3231 struct usb_host_endpoint **eps, unsigned int num_eps)
3233 u32 changed_ep_bitmask = 0;
3234 unsigned int slot_id;
3235 unsigned int ep_index;
3236 unsigned int ep_state;
3239 slot_id = udev->slot_id;
3240 if (!xhci->devs[slot_id])
3243 for (i = 0; i < num_eps; i++) {
3244 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3245 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3246 /* Are streams already being freed for the endpoint? */
3247 if (ep_state & EP_GETTING_NO_STREAMS) {
3248 xhci_warn(xhci, "WARN Can't disable streams for "
3250 "streams are being disabled already\n",
3251 eps[i]->desc.bEndpointAddress);
3254 /* Are there actually any streams to free? */
3255 if (!(ep_state & EP_HAS_STREAMS) &&
3256 !(ep_state & EP_GETTING_STREAMS)) {
3257 xhci_warn(xhci, "WARN Can't disable streams for "
3259 "streams are already disabled!\n",
3260 eps[i]->desc.bEndpointAddress);
3261 xhci_warn(xhci, "WARN xhci_free_streams() called "
3262 "with non-streams endpoint\n");
3265 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3267 return changed_ep_bitmask;
3271 * The USB device drivers use this function (through the HCD interface in USB
3272 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3273 * coordinate mass storage command queueing across multiple endpoints (basically
3274 * a stream ID == a task ID).
3276 * Setting up streams involves allocating the same size stream context array
3277 * for each endpoint and issuing a configure endpoint command for all endpoints.
3279 * Don't allow the call to succeed if one endpoint only supports one stream
3280 * (which means it doesn't support streams at all).
3282 * Drivers may get less stream IDs than they asked for, if the host controller
3283 * hardware or endpoints claim they can't support the number of requested
3286 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3287 struct usb_host_endpoint **eps, unsigned int num_eps,
3288 unsigned int num_streams, gfp_t mem_flags)
3291 struct xhci_hcd *xhci;
3292 struct xhci_virt_device *vdev;
3293 struct xhci_command *config_cmd;
3294 struct xhci_input_control_ctx *ctrl_ctx;
3295 unsigned int ep_index;
3296 unsigned int num_stream_ctxs;
3297 unsigned int max_packet;
3298 unsigned long flags;
3299 u32 changed_ep_bitmask = 0;
3304 /* Add one to the number of streams requested to account for
3305 * stream 0 that is reserved for xHCI usage.
3308 xhci = hcd_to_xhci(hcd);
3309 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3312 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3313 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3314 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3315 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3319 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3323 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3325 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3327 xhci_free_command(xhci, config_cmd);
3331 /* Check to make sure all endpoints are not already configured for
3332 * streams. While we're at it, find the maximum number of streams that
3333 * all the endpoints will support and check for duplicate endpoints.
3335 spin_lock_irqsave(&xhci->lock, flags);
3336 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3337 num_eps, &num_streams, &changed_ep_bitmask);
3339 xhci_free_command(xhci, config_cmd);
3340 spin_unlock_irqrestore(&xhci->lock, flags);
3343 if (num_streams <= 1) {
3344 xhci_warn(xhci, "WARN: endpoints can't handle "
3345 "more than one stream.\n");
3346 xhci_free_command(xhci, config_cmd);
3347 spin_unlock_irqrestore(&xhci->lock, flags);
3350 vdev = xhci->devs[udev->slot_id];
3351 /* Mark each endpoint as being in transition, so
3352 * xhci_urb_enqueue() will reject all URBs.
3354 for (i = 0; i < num_eps; i++) {
3355 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3356 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3358 spin_unlock_irqrestore(&xhci->lock, flags);
3360 /* Setup internal data structures and allocate HW data structures for
3361 * streams (but don't install the HW structures in the input context
3362 * until we're sure all memory allocation succeeded).
3364 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3365 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3366 num_stream_ctxs, num_streams);
3368 for (i = 0; i < num_eps; i++) {
3369 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3370 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3371 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3374 max_packet, mem_flags);
3375 if (!vdev->eps[ep_index].stream_info)
3377 /* Set maxPstreams in endpoint context and update deq ptr to
3378 * point to stream context array. FIXME
3382 /* Set up the input context for a configure endpoint command. */
3383 for (i = 0; i < num_eps; i++) {
3384 struct xhci_ep_ctx *ep_ctx;
3386 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3387 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3389 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3390 vdev->out_ctx, ep_index);
3391 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3392 vdev->eps[ep_index].stream_info);
3394 /* Tell the HW to drop its old copy of the endpoint context info
3395 * and add the updated copy from the input context.
3397 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3398 vdev->out_ctx, ctrl_ctx,
3399 changed_ep_bitmask, changed_ep_bitmask);
3401 /* Issue and wait for the configure endpoint command */
3402 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3405 /* xHC rejected the configure endpoint command for some reason, so we
3406 * leave the old ring intact and free our internal streams data
3412 spin_lock_irqsave(&xhci->lock, flags);
3413 for (i = 0; i < num_eps; i++) {
3414 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3415 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3416 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3417 udev->slot_id, ep_index);
3418 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3420 xhci_free_command(xhci, config_cmd);
3421 spin_unlock_irqrestore(&xhci->lock, flags);
3423 /* Subtract 1 for stream 0, which drivers can't use */
3424 return num_streams - 1;
3427 /* If it didn't work, free the streams! */
3428 for (i = 0; i < num_eps; i++) {
3429 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3430 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3431 vdev->eps[ep_index].stream_info = NULL;
3432 /* FIXME Unset maxPstreams in endpoint context and
3433 * update deq ptr to point to normal string ring.
3435 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3436 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3437 xhci_endpoint_zero(xhci, vdev, eps[i]);
3439 xhci_free_command(xhci, config_cmd);
3443 /* Transition the endpoint from using streams to being a "normal" endpoint
3446 * Modify the endpoint context state, submit a configure endpoint command,
3447 * and free all endpoint rings for streams if that completes successfully.
3449 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3450 struct usb_host_endpoint **eps, unsigned int num_eps,
3454 struct xhci_hcd *xhci;
3455 struct xhci_virt_device *vdev;
3456 struct xhci_command *command;
3457 struct xhci_input_control_ctx *ctrl_ctx;
3458 unsigned int ep_index;
3459 unsigned long flags;
3460 u32 changed_ep_bitmask;
3462 xhci = hcd_to_xhci(hcd);
3463 vdev = xhci->devs[udev->slot_id];
3465 /* Set up a configure endpoint command to remove the streams rings */
3466 spin_lock_irqsave(&xhci->lock, flags);
3467 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3468 udev, eps, num_eps);
3469 if (changed_ep_bitmask == 0) {
3470 spin_unlock_irqrestore(&xhci->lock, flags);
3474 /* Use the xhci_command structure from the first endpoint. We may have
3475 * allocated too many, but the driver may call xhci_free_streams() for
3476 * each endpoint it grouped into one call to xhci_alloc_streams().
3478 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3479 command = vdev->eps[ep_index].stream_info->free_streams_command;
3480 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3482 spin_unlock_irqrestore(&xhci->lock, flags);
3483 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3488 for (i = 0; i < num_eps; i++) {
3489 struct xhci_ep_ctx *ep_ctx;
3491 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3492 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3493 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3494 EP_GETTING_NO_STREAMS;
3496 xhci_endpoint_copy(xhci, command->in_ctx,
3497 vdev->out_ctx, ep_index);
3498 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3499 &vdev->eps[ep_index]);
3501 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3502 vdev->out_ctx, ctrl_ctx,
3503 changed_ep_bitmask, changed_ep_bitmask);
3504 spin_unlock_irqrestore(&xhci->lock, flags);
3506 /* Issue and wait for the configure endpoint command,
3507 * which must succeed.
3509 ret = xhci_configure_endpoint(xhci, udev, command,
3512 /* xHC rejected the configure endpoint command for some reason, so we
3513 * leave the streams rings intact.
3518 spin_lock_irqsave(&xhci->lock, flags);
3519 for (i = 0; i < num_eps; i++) {
3520 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3521 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3522 vdev->eps[ep_index].stream_info = NULL;
3523 /* FIXME Unset maxPstreams in endpoint context and
3524 * update deq ptr to point to normal string ring.
3526 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3527 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3529 spin_unlock_irqrestore(&xhci->lock, flags);
3535 * Deletes endpoint resources for endpoints that were active before a Reset
3536 * Device command, or a Disable Slot command. The Reset Device command leaves
3537 * the control endpoint intact, whereas the Disable Slot command deletes it.
3539 * Must be called with xhci->lock held.
3541 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3542 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3545 unsigned int num_dropped_eps = 0;
3546 unsigned int drop_flags = 0;
3548 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3549 if (virt_dev->eps[i].ring) {
3550 drop_flags |= 1 << i;
3554 xhci->num_active_eps -= num_dropped_eps;
3555 if (num_dropped_eps)
3556 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3557 "Dropped %u ep ctxs, flags = 0x%x, "
3559 num_dropped_eps, drop_flags,
3560 xhci->num_active_eps);
3564 * This submits a Reset Device Command, which will set the device state to 0,
3565 * set the device address to 0, and disable all the endpoints except the default
3566 * control endpoint. The USB core should come back and call
3567 * xhci_address_device(), and then re-set up the configuration. If this is
3568 * called because of a usb_reset_and_verify_device(), then the old alternate
3569 * settings will be re-installed through the normal bandwidth allocation
3572 * Wait for the Reset Device command to finish. Remove all structures
3573 * associated with the endpoints that were disabled. Clear the input device
3574 * structure? Reset the control endpoint 0 max packet size?
3576 * If the virt_dev to be reset does not exist or does not match the udev,
3577 * it means the device is lost, possibly due to the xHC restore error and
3578 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3579 * re-allocate the device.
3581 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3582 struct usb_device *udev)
3585 unsigned long flags;
3586 struct xhci_hcd *xhci;
3587 unsigned int slot_id;
3588 struct xhci_virt_device *virt_dev;
3589 struct xhci_command *reset_device_cmd;
3590 struct xhci_slot_ctx *slot_ctx;
3591 int old_active_eps = 0;
3593 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3596 xhci = hcd_to_xhci(hcd);
3597 slot_id = udev->slot_id;
3598 virt_dev = xhci->devs[slot_id];
3600 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3601 "not exist. Re-allocate the device\n", slot_id);
3602 ret = xhci_alloc_dev(hcd, udev);
3609 if (virt_dev->tt_info)
3610 old_active_eps = virt_dev->tt_info->active_eps;
3612 if (virt_dev->udev != udev) {
3613 /* If the virt_dev and the udev does not match, this virt_dev
3614 * may belong to another udev.
3615 * Re-allocate the device.
3617 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3618 "not match the udev. Re-allocate the device\n",
3620 ret = xhci_alloc_dev(hcd, udev);
3627 /* If device is not setup, there is no point in resetting it */
3628 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3629 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3630 SLOT_STATE_DISABLED)
3633 trace_xhci_discover_or_reset_device(slot_ctx);
3635 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3636 /* Allocate the command structure that holds the struct completion.
3637 * Assume we're in process context, since the normal device reset
3638 * process has to wait for the device anyway. Storage devices are
3639 * reset as part of error handling, so use GFP_NOIO instead of
3642 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3643 if (!reset_device_cmd) {
3644 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3648 /* Attempt to submit the Reset Device command to the command ring */
3649 spin_lock_irqsave(&xhci->lock, flags);
3651 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3653 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3654 spin_unlock_irqrestore(&xhci->lock, flags);
3655 goto command_cleanup;
3657 xhci_ring_cmd_db(xhci);
3658 spin_unlock_irqrestore(&xhci->lock, flags);
3660 /* Wait for the Reset Device command to finish */
3661 wait_for_completion(reset_device_cmd->completion);
3663 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3664 * unless we tried to reset a slot ID that wasn't enabled,
3665 * or the device wasn't in the addressed or configured state.
3667 ret = reset_device_cmd->status;
3669 case COMP_COMMAND_ABORTED:
3670 case COMP_COMMAND_RING_STOPPED:
3671 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3673 goto command_cleanup;
3674 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3675 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3676 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3678 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3679 xhci_dbg(xhci, "Not freeing device rings.\n");
3680 /* Don't treat this as an error. May change my mind later. */
3682 goto command_cleanup;
3684 xhci_dbg(xhci, "Successful reset device command.\n");
3687 if (xhci_is_vendor_info_code(xhci, ret))
3689 xhci_warn(xhci, "Unknown completion code %u for "
3690 "reset device command.\n", ret);
3692 goto command_cleanup;
3695 /* Free up host controller endpoint resources */
3696 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3697 spin_lock_irqsave(&xhci->lock, flags);
3698 /* Don't delete the default control endpoint resources */
3699 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3700 spin_unlock_irqrestore(&xhci->lock, flags);
3703 /* Everything but endpoint 0 is disabled, so free the rings. */
3704 for (i = 1; i < 31; i++) {
3705 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3707 if (ep->ep_state & EP_HAS_STREAMS) {
3708 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3709 xhci_get_endpoint_address(i));
3710 xhci_free_stream_info(xhci, ep->stream_info);
3711 ep->stream_info = NULL;
3712 ep->ep_state &= ~EP_HAS_STREAMS;
3716 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3717 xhci_free_endpoint_ring(xhci, virt_dev, i);
3719 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3720 xhci_drop_ep_from_interval_table(xhci,
3721 &virt_dev->eps[i].bw_info,
3726 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3728 /* If necessary, update the number of active TTs on this root port */
3729 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3733 xhci_free_command(xhci, reset_device_cmd);
3738 * At this point, the struct usb_device is about to go away, the device has
3739 * disconnected, and all traffic has been stopped and the endpoints have been
3740 * disabled. Free any HC data structures associated with that device.
3742 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3745 struct xhci_virt_device *virt_dev;
3746 struct xhci_slot_ctx *slot_ctx;
3749 #ifndef CONFIG_USB_DEFAULT_PERSIST
3751 * We called pm_runtime_get_noresume when the device was attached.
3752 * Decrement the counter here to allow controller to runtime suspend
3753 * if no devices remain.
3755 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3756 pm_runtime_put_noidle(hcd->self.controller);
3759 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3760 /* If the host is halted due to driver unload, we still need to free the
3763 if (ret <= 0 && ret != -ENODEV)
3766 virt_dev = xhci->devs[udev->slot_id];
3767 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3768 trace_xhci_free_dev(slot_ctx);
3770 /* Stop any wayward timer functions (which may grab the lock) */
3771 for (i = 0; i < 31; i++) {
3772 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3773 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3775 xhci_debugfs_remove_slot(xhci, udev->slot_id);
3776 virt_dev->udev = NULL;
3777 ret = xhci_disable_slot(xhci, udev->slot_id);
3779 xhci_free_virt_device(xhci, udev->slot_id);
3782 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3784 struct xhci_command *command;
3785 unsigned long flags;
3789 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3793 spin_lock_irqsave(&xhci->lock, flags);
3794 /* Don't disable the slot if the host controller is dead. */
3795 state = readl(&xhci->op_regs->status);
3796 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3797 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3798 spin_unlock_irqrestore(&xhci->lock, flags);
3803 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3806 spin_unlock_irqrestore(&xhci->lock, flags);
3810 xhci_ring_cmd_db(xhci);
3811 spin_unlock_irqrestore(&xhci->lock, flags);
3816 * Checks if we have enough host controller resources for the default control
3819 * Must be called with xhci->lock held.
3821 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3823 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3824 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3825 "Not enough ep ctxs: "
3826 "%u active, need to add 1, limit is %u.",
3827 xhci->num_active_eps, xhci->limit_active_eps);
3830 xhci->num_active_eps += 1;
3831 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3832 "Adding 1 ep ctx, %u now active.",
3833 xhci->num_active_eps);
3839 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3840 * timed out, or allocating memory failed. Returns 1 on success.
3842 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3844 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3845 struct xhci_virt_device *vdev;
3846 struct xhci_slot_ctx *slot_ctx;
3847 unsigned long flags;
3849 struct xhci_command *command;
3851 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3855 spin_lock_irqsave(&xhci->lock, flags);
3856 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3858 spin_unlock_irqrestore(&xhci->lock, flags);
3859 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3860 xhci_free_command(xhci, command);
3863 xhci_ring_cmd_db(xhci);
3864 spin_unlock_irqrestore(&xhci->lock, flags);
3866 wait_for_completion(command->completion);
3867 slot_id = command->slot_id;
3869 if (!slot_id || command->status != COMP_SUCCESS) {
3870 xhci_err(xhci, "Error while assigning device slot ID\n");
3871 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3873 readl(&xhci->cap_regs->hcs_params1)));
3874 xhci_free_command(xhci, command);
3878 xhci_free_command(xhci, command);
3880 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3881 spin_lock_irqsave(&xhci->lock, flags);
3882 ret = xhci_reserve_host_control_ep_resources(xhci);
3884 spin_unlock_irqrestore(&xhci->lock, flags);
3885 xhci_warn(xhci, "Not enough host resources, "
3886 "active endpoint contexts = %u\n",
3887 xhci->num_active_eps);
3890 spin_unlock_irqrestore(&xhci->lock, flags);
3892 /* Use GFP_NOIO, since this function can be called from
3893 * xhci_discover_or_reset_device(), which may be called as part of
3894 * mass storage driver error handling.
3896 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3897 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3900 vdev = xhci->devs[slot_id];
3901 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3902 trace_xhci_alloc_dev(slot_ctx);
3904 udev->slot_id = slot_id;
3906 xhci_debugfs_create_slot(xhci, slot_id);
3908 #ifndef CONFIG_USB_DEFAULT_PERSIST
3910 * If resetting upon resume, we can't put the controller into runtime
3911 * suspend if there is a device attached.
3913 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3914 pm_runtime_get_noresume(hcd->self.controller);
3917 /* Is this a LS or FS device under a HS hub? */
3918 /* Hub or peripherial? */
3922 ret = xhci_disable_slot(xhci, udev->slot_id);
3924 xhci_free_virt_device(xhci, udev->slot_id);
3930 * Issue an Address Device command and optionally send a corresponding
3931 * SetAddress request to the device.
3933 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3934 enum xhci_setup_dev setup)
3936 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3937 unsigned long flags;
3938 struct xhci_virt_device *virt_dev;
3940 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3941 struct xhci_slot_ctx *slot_ctx;
3942 struct xhci_input_control_ctx *ctrl_ctx;
3944 struct xhci_command *command = NULL;
3946 mutex_lock(&xhci->mutex);
3948 if (xhci->xhc_state) { /* dying, removing or halted */
3953 if (!udev->slot_id) {
3954 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3955 "Bad Slot ID %d", udev->slot_id);
3960 virt_dev = xhci->devs[udev->slot_id];
3962 if (WARN_ON(!virt_dev)) {
3964 * In plug/unplug torture test with an NEC controller,
3965 * a zero-dereference was observed once due to virt_dev = 0.
3966 * Print useful debug rather than crash if it is observed again!
3968 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3973 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3974 trace_xhci_setup_device_slot(slot_ctx);
3976 if (setup == SETUP_CONTEXT_ONLY) {
3977 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3978 SLOT_STATE_DEFAULT) {
3979 xhci_dbg(xhci, "Slot already in default state\n");
3984 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3990 command->in_ctx = virt_dev->in_ctx;
3992 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3993 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3995 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4001 * If this is the first Set Address since device plug-in or
4002 * virt_device realloaction after a resume with an xHCI power loss,
4003 * then set up the slot context.
4005 if (!slot_ctx->dev_info)
4006 xhci_setup_addressable_virt_dev(xhci, udev);
4007 /* Otherwise, update the control endpoint ring enqueue pointer. */
4009 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4010 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4011 ctrl_ctx->drop_flags = 0;
4013 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4014 le32_to_cpu(slot_ctx->dev_info) >> 27);
4016 spin_lock_irqsave(&xhci->lock, flags);
4017 trace_xhci_setup_device(virt_dev);
4018 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4019 udev->slot_id, setup);
4021 spin_unlock_irqrestore(&xhci->lock, flags);
4022 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4023 "FIXME: allocate a command ring segment");
4026 xhci_ring_cmd_db(xhci);
4027 spin_unlock_irqrestore(&xhci->lock, flags);
4029 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4030 wait_for_completion(command->completion);
4032 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4033 * the SetAddress() "recovery interval" required by USB and aborting the
4034 * command on a timeout.
4036 switch (command->status) {
4037 case COMP_COMMAND_ABORTED:
4038 case COMP_COMMAND_RING_STOPPED:
4039 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4042 case COMP_CONTEXT_STATE_ERROR:
4043 case COMP_SLOT_NOT_ENABLED_ERROR:
4044 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4045 act, udev->slot_id);
4048 case COMP_USB_TRANSACTION_ERROR:
4049 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4051 mutex_unlock(&xhci->mutex);
4052 ret = xhci_disable_slot(xhci, udev->slot_id);
4054 xhci_alloc_dev(hcd, udev);
4055 kfree(command->completion);
4058 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4059 dev_warn(&udev->dev,
4060 "ERROR: Incompatible device for setup %s command\n", act);
4064 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4065 "Successful setup %s command", act);
4069 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4070 act, command->status);
4071 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4077 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4078 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4079 "Op regs DCBAA ptr = %#016llx", temp_64);
4080 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4081 "Slot ID %d dcbaa entry @%p = %#016llx",
4083 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4084 (unsigned long long)
4085 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4086 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4087 "Output Context DMA address = %#08llx",
4088 (unsigned long long)virt_dev->out_ctx->dma);
4089 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4090 le32_to_cpu(slot_ctx->dev_info) >> 27);
4092 * USB core uses address 1 for the roothubs, so we add one to the
4093 * address given back to us by the HC.
4095 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4096 le32_to_cpu(slot_ctx->dev_info) >> 27);
4097 /* Zero the input context control for later use */
4098 ctrl_ctx->add_flags = 0;
4099 ctrl_ctx->drop_flags = 0;
4101 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4102 "Internal device address = %d",
4103 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4105 mutex_unlock(&xhci->mutex);
4107 kfree(command->completion);
4113 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4115 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4118 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4120 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4124 * Transfer the port index into real index in the HW port status
4125 * registers. Caculate offset between the port's PORTSC register
4126 * and port status base. Divide the number of per port register
4127 * to get the real index. The raw port number bases 1.
4129 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4131 struct xhci_hub *rhub;
4133 rhub = xhci_get_rhub(hcd);
4134 return rhub->ports[port1 - 1]->hw_portnum + 1;
4138 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4139 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4141 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4142 struct usb_device *udev, u16 max_exit_latency)
4144 struct xhci_virt_device *virt_dev;
4145 struct xhci_command *command;
4146 struct xhci_input_control_ctx *ctrl_ctx;
4147 struct xhci_slot_ctx *slot_ctx;
4148 unsigned long flags;
4151 spin_lock_irqsave(&xhci->lock, flags);
4153 virt_dev = xhci->devs[udev->slot_id];
4156 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4157 * xHC was re-initialized. Exit latency will be set later after
4158 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4161 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4162 spin_unlock_irqrestore(&xhci->lock, flags);
4166 /* Attempt to issue an Evaluate Context command to change the MEL. */
4167 command = xhci->lpm_command;
4168 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4170 spin_unlock_irqrestore(&xhci->lock, flags);
4171 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4176 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4177 spin_unlock_irqrestore(&xhci->lock, flags);
4179 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4180 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4181 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4182 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4183 slot_ctx->dev_state = 0;
4185 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4186 "Set up evaluate context for LPM MEL change.");
4188 /* Issue and wait for the evaluate context command. */
4189 ret = xhci_configure_endpoint(xhci, udev, command,
4193 spin_lock_irqsave(&xhci->lock, flags);
4194 virt_dev->current_mel = max_exit_latency;
4195 spin_unlock_irqrestore(&xhci->lock, flags);
4202 /* BESL to HIRD Encoding array for USB2 LPM */
4203 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4204 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4206 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4207 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4208 struct usb_device *udev)
4210 int u2del, besl, besl_host;
4211 int besl_device = 0;
4214 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4215 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4217 if (field & USB_BESL_SUPPORT) {
4218 for (besl_host = 0; besl_host < 16; besl_host++) {
4219 if (xhci_besl_encoding[besl_host] >= u2del)
4222 /* Use baseline BESL value as default */
4223 if (field & USB_BESL_BASELINE_VALID)
4224 besl_device = USB_GET_BESL_BASELINE(field);
4225 else if (field & USB_BESL_DEEP_VALID)
4226 besl_device = USB_GET_BESL_DEEP(field);
4231 besl_host = (u2del - 51) / 75 + 1;
4234 besl = besl_host + besl_device;
4241 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4242 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4249 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4251 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4252 l1 = udev->l1_params.timeout / 256;
4254 /* device has preferred BESLD */
4255 if (field & USB_BESL_DEEP_VALID) {
4256 besld = USB_GET_BESL_DEEP(field);
4260 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4263 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4264 struct usb_device *udev, int enable)
4266 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4267 struct xhci_port **ports;
4268 __le32 __iomem *pm_addr, *hlpm_addr;
4269 u32 pm_val, hlpm_val, field;
4270 unsigned int port_num;
4271 unsigned long flags;
4272 int hird, exit_latency;
4275 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4279 if (!udev->parent || udev->parent->parent ||
4280 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4283 if (udev->usb2_hw_lpm_capable != 1)
4286 spin_lock_irqsave(&xhci->lock, flags);
4288 ports = xhci->usb2_rhub.ports;
4289 port_num = udev->portnum - 1;
4290 pm_addr = ports[port_num]->addr + PORTPMSC;
4291 pm_val = readl(pm_addr);
4292 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4293 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4295 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4296 enable ? "enable" : "disable", port_num + 1);
4298 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4299 /* Host supports BESL timeout instead of HIRD */
4300 if (udev->usb2_hw_lpm_besl_capable) {
4301 /* if device doesn't have a preferred BESL value use a
4302 * default one which works with mixed HIRD and BESL
4303 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4305 if ((field & USB_BESL_SUPPORT) &&
4306 (field & USB_BESL_BASELINE_VALID))
4307 hird = USB_GET_BESL_BASELINE(field);
4309 hird = udev->l1_params.besl;
4311 exit_latency = xhci_besl_encoding[hird];
4312 spin_unlock_irqrestore(&xhci->lock, flags);
4314 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4315 * input context for link powermanagement evaluate
4316 * context commands. It is protected by hcd->bandwidth
4317 * mutex and is shared by all devices. We need to set
4318 * the max ext latency in USB 2 BESL LPM as well, so
4319 * use the same mutex and xhci_change_max_exit_latency()
4321 mutex_lock(hcd->bandwidth_mutex);
4322 ret = xhci_change_max_exit_latency(xhci, udev,
4324 mutex_unlock(hcd->bandwidth_mutex);
4328 spin_lock_irqsave(&xhci->lock, flags);
4330 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4331 writel(hlpm_val, hlpm_addr);
4335 hird = xhci_calculate_hird_besl(xhci, udev);
4338 pm_val &= ~PORT_HIRD_MASK;
4339 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4340 writel(pm_val, pm_addr);
4341 pm_val = readl(pm_addr);
4343 writel(pm_val, pm_addr);
4347 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4348 writel(pm_val, pm_addr);
4351 if (udev->usb2_hw_lpm_besl_capable) {
4352 spin_unlock_irqrestore(&xhci->lock, flags);
4353 mutex_lock(hcd->bandwidth_mutex);
4354 xhci_change_max_exit_latency(xhci, udev, 0);
4355 mutex_unlock(hcd->bandwidth_mutex);
4360 spin_unlock_irqrestore(&xhci->lock, flags);
4364 /* check if a usb2 port supports a given extened capability protocol
4365 * only USB2 ports extended protocol capability values are cached.
4366 * Return 1 if capability is supported
4368 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4369 unsigned capability)
4371 u32 port_offset, port_count;
4374 for (i = 0; i < xhci->num_ext_caps; i++) {
4375 if (xhci->ext_caps[i] & capability) {
4376 /* port offsets starts at 1 */
4377 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4378 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4379 if (port >= port_offset &&
4380 port < port_offset + port_count)
4387 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4389 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4390 int portnum = udev->portnum - 1;
4392 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4395 /* we only support lpm for non-hub device connected to root hub yet */
4396 if (!udev->parent || udev->parent->parent ||
4397 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4400 if (xhci->hw_lpm_support == 1 &&
4401 xhci_check_usb2_port_capability(
4402 xhci, portnum, XHCI_HLC)) {
4403 udev->usb2_hw_lpm_capable = 1;
4404 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4405 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4406 if (xhci_check_usb2_port_capability(xhci, portnum,
4408 udev->usb2_hw_lpm_besl_capable = 1;
4414 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4416 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4417 static unsigned long long xhci_service_interval_to_ns(
4418 struct usb_endpoint_descriptor *desc)
4420 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4423 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4424 enum usb3_link_state state)
4426 unsigned long long sel;
4427 unsigned long long pel;
4428 unsigned int max_sel_pel;
4433 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4434 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4435 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4436 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4440 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4441 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4442 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4446 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4448 return USB3_LPM_DISABLED;
4451 if (sel <= max_sel_pel && pel <= max_sel_pel)
4452 return USB3_LPM_DEVICE_INITIATED;
4454 if (sel > max_sel_pel)
4455 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4456 "due to long SEL %llu ms\n",
4459 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4460 "due to long PEL %llu ms\n",
4462 return USB3_LPM_DISABLED;
4465 /* The U1 timeout should be the maximum of the following values:
4466 * - For control endpoints, U1 system exit latency (SEL) * 3
4467 * - For bulk endpoints, U1 SEL * 5
4468 * - For interrupt endpoints:
4469 * - Notification EPs, U1 SEL * 3
4470 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4471 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4473 static unsigned long long xhci_calculate_intel_u1_timeout(
4474 struct usb_device *udev,
4475 struct usb_endpoint_descriptor *desc)
4477 unsigned long long timeout_ns;
4481 ep_type = usb_endpoint_type(desc);
4483 case USB_ENDPOINT_XFER_CONTROL:
4484 timeout_ns = udev->u1_params.sel * 3;
4486 case USB_ENDPOINT_XFER_BULK:
4487 timeout_ns = udev->u1_params.sel * 5;
4489 case USB_ENDPOINT_XFER_INT:
4490 intr_type = usb_endpoint_interrupt_type(desc);
4491 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4492 timeout_ns = udev->u1_params.sel * 3;
4495 /* Otherwise the calculation is the same as isoc eps */
4497 case USB_ENDPOINT_XFER_ISOC:
4498 timeout_ns = xhci_service_interval_to_ns(desc);
4499 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4500 if (timeout_ns < udev->u1_params.sel * 2)
4501 timeout_ns = udev->u1_params.sel * 2;
4510 /* Returns the hub-encoded U1 timeout value. */
4511 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4512 struct usb_device *udev,
4513 struct usb_endpoint_descriptor *desc)
4515 unsigned long long timeout_ns;
4517 /* Prevent U1 if service interval is shorter than U1 exit latency */
4518 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4519 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4520 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4521 return USB3_LPM_DISABLED;
4525 if (xhci->quirks & XHCI_INTEL_HOST)
4526 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4528 timeout_ns = udev->u1_params.sel;
4530 /* The U1 timeout is encoded in 1us intervals.
4531 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4533 if (timeout_ns == USB3_LPM_DISABLED)
4536 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4538 /* If the necessary timeout value is bigger than what we can set in the
4539 * USB 3.0 hub, we have to disable hub-initiated U1.
4541 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4543 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4544 "due to long timeout %llu ms\n", timeout_ns);
4545 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4548 /* The U2 timeout should be the maximum of:
4549 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4550 * - largest bInterval of any active periodic endpoint (to avoid going
4551 * into lower power link states between intervals).
4552 * - the U2 Exit Latency of the device
4554 static unsigned long long xhci_calculate_intel_u2_timeout(
4555 struct usb_device *udev,
4556 struct usb_endpoint_descriptor *desc)
4558 unsigned long long timeout_ns;
4559 unsigned long long u2_del_ns;
4561 timeout_ns = 10 * 1000 * 1000;
4563 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4564 (xhci_service_interval_to_ns(desc) > timeout_ns))
4565 timeout_ns = xhci_service_interval_to_ns(desc);
4567 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4568 if (u2_del_ns > timeout_ns)
4569 timeout_ns = u2_del_ns;
4574 /* Returns the hub-encoded U2 timeout value. */
4575 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4576 struct usb_device *udev,
4577 struct usb_endpoint_descriptor *desc)
4579 unsigned long long timeout_ns;
4581 /* Prevent U2 if service interval is shorter than U2 exit latency */
4582 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4583 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4584 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4585 return USB3_LPM_DISABLED;
4589 if (xhci->quirks & XHCI_INTEL_HOST)
4590 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4592 timeout_ns = udev->u2_params.sel;
4594 /* The U2 timeout is encoded in 256us intervals */
4595 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4596 /* If the necessary timeout value is bigger than what we can set in the
4597 * USB 3.0 hub, we have to disable hub-initiated U2.
4599 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4601 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4602 "due to long timeout %llu ms\n", timeout_ns);
4603 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4606 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4607 struct usb_device *udev,
4608 struct usb_endpoint_descriptor *desc,
4609 enum usb3_link_state state,
4612 if (state == USB3_LPM_U1)
4613 return xhci_calculate_u1_timeout(xhci, udev, desc);
4614 else if (state == USB3_LPM_U2)
4615 return xhci_calculate_u2_timeout(xhci, udev, desc);
4617 return USB3_LPM_DISABLED;
4620 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4621 struct usb_device *udev,
4622 struct usb_endpoint_descriptor *desc,
4623 enum usb3_link_state state,
4628 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4629 desc, state, timeout);
4631 /* If we found we can't enable hub-initiated LPM, or
4632 * the U1 or U2 exit latency was too high to allow
4633 * device-initiated LPM as well, just stop searching.
4635 if (alt_timeout == USB3_LPM_DISABLED ||
4636 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4637 *timeout = alt_timeout;
4640 if (alt_timeout > *timeout)
4641 *timeout = alt_timeout;
4645 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4646 struct usb_device *udev,
4647 struct usb_host_interface *alt,
4648 enum usb3_link_state state,
4653 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4654 if (xhci_update_timeout_for_endpoint(xhci, udev,
4655 &alt->endpoint[j].desc, state, timeout))
4662 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4663 enum usb3_link_state state)
4665 struct usb_device *parent;
4666 unsigned int num_hubs;
4668 if (state == USB3_LPM_U2)
4671 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4672 for (parent = udev->parent, num_hubs = 0; parent->parent;
4673 parent = parent->parent)
4679 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4680 " below second-tier hub.\n");
4681 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4682 "to decrease power consumption.\n");
4686 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4687 struct usb_device *udev,
4688 enum usb3_link_state state)
4690 if (xhci->quirks & XHCI_INTEL_HOST)
4691 return xhci_check_intel_tier_policy(udev, state);
4696 /* Returns the U1 or U2 timeout that should be enabled.
4697 * If the tier check or timeout setting functions return with a non-zero exit
4698 * code, that means the timeout value has been finalized and we shouldn't look
4699 * at any more endpoints.
4701 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4702 struct usb_device *udev, enum usb3_link_state state)
4704 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4705 struct usb_host_config *config;
4708 u16 timeout = USB3_LPM_DISABLED;
4710 if (state == USB3_LPM_U1)
4712 else if (state == USB3_LPM_U2)
4715 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4720 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4723 /* Gather some information about the currently installed configuration
4724 * and alternate interface settings.
4726 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4730 config = udev->actconfig;
4734 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4735 struct usb_driver *driver;
4736 struct usb_interface *intf = config->interface[i];
4741 /* Check if any currently bound drivers want hub-initiated LPM
4744 if (intf->dev.driver) {
4745 driver = to_usb_driver(intf->dev.driver);
4746 if (driver && driver->disable_hub_initiated_lpm) {
4747 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4748 "at request of driver %s\n",
4749 state_name, driver->name);
4750 return xhci_get_timeout_no_hub_lpm(udev, state);
4754 /* Not sure how this could happen... */
4755 if (!intf->cur_altsetting)
4758 if (xhci_update_timeout_for_interface(xhci, udev,
4759 intf->cur_altsetting,
4766 static int calculate_max_exit_latency(struct usb_device *udev,
4767 enum usb3_link_state state_changed,
4768 u16 hub_encoded_timeout)
4770 unsigned long long u1_mel_us = 0;
4771 unsigned long long u2_mel_us = 0;
4772 unsigned long long mel_us = 0;
4778 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4779 hub_encoded_timeout == USB3_LPM_DISABLED);
4780 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4781 hub_encoded_timeout == USB3_LPM_DISABLED);
4783 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4784 hub_encoded_timeout != USB3_LPM_DISABLED);
4785 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4786 hub_encoded_timeout != USB3_LPM_DISABLED);
4788 /* If U1 was already enabled and we're not disabling it,
4789 * or we're going to enable U1, account for the U1 max exit latency.
4791 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4793 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4794 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4796 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4798 if (u1_mel_us > u2_mel_us)
4802 /* xHCI host controller max exit latency field is only 16 bits wide. */
4803 if (mel_us > MAX_EXIT) {
4804 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4805 "is too big.\n", mel_us);
4811 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4812 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4813 struct usb_device *udev, enum usb3_link_state state)
4815 struct xhci_hcd *xhci;
4816 u16 hub_encoded_timeout;
4820 xhci = hcd_to_xhci(hcd);
4821 /* The LPM timeout values are pretty host-controller specific, so don't
4822 * enable hub-initiated timeouts unless the vendor has provided
4823 * information about their timeout algorithm.
4825 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4826 !xhci->devs[udev->slot_id])
4827 return USB3_LPM_DISABLED;
4829 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4830 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4832 /* Max Exit Latency is too big, disable LPM. */
4833 hub_encoded_timeout = USB3_LPM_DISABLED;
4837 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4840 return hub_encoded_timeout;
4843 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4844 struct usb_device *udev, enum usb3_link_state state)
4846 struct xhci_hcd *xhci;
4849 xhci = hcd_to_xhci(hcd);
4850 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4851 !xhci->devs[udev->slot_id])
4854 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4855 return xhci_change_max_exit_latency(xhci, udev, mel);
4857 #else /* CONFIG_PM */
4859 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4860 struct usb_device *udev, int enable)
4865 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4870 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4871 struct usb_device *udev, enum usb3_link_state state)
4873 return USB3_LPM_DISABLED;
4876 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4877 struct usb_device *udev, enum usb3_link_state state)
4881 #endif /* CONFIG_PM */
4883 /*-------------------------------------------------------------------------*/
4885 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4886 * internal data structures for the device.
4888 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4889 struct usb_tt *tt, gfp_t mem_flags)
4891 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4892 struct xhci_virt_device *vdev;
4893 struct xhci_command *config_cmd;
4894 struct xhci_input_control_ctx *ctrl_ctx;
4895 struct xhci_slot_ctx *slot_ctx;
4896 unsigned long flags;
4897 unsigned think_time;
4900 /* Ignore root hubs */
4904 vdev = xhci->devs[hdev->slot_id];
4906 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4910 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
4914 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4916 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4918 xhci_free_command(xhci, config_cmd);
4922 spin_lock_irqsave(&xhci->lock, flags);
4923 if (hdev->speed == USB_SPEED_HIGH &&
4924 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4925 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4926 xhci_free_command(xhci, config_cmd);
4927 spin_unlock_irqrestore(&xhci->lock, flags);
4931 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4932 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4933 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4934 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4936 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4937 * but it may be already set to 1 when setup an xHCI virtual
4938 * device, so clear it anyway.
4941 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4942 else if (hdev->speed == USB_SPEED_FULL)
4943 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4945 if (xhci->hci_version > 0x95) {
4946 xhci_dbg(xhci, "xHCI version %x needs hub "
4947 "TT think time and number of ports\n",
4948 (unsigned int) xhci->hci_version);
4949 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4950 /* Set TT think time - convert from ns to FS bit times.
4951 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4952 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4954 * xHCI 1.0: this field shall be 0 if the device is not a
4957 think_time = tt->think_time;
4958 if (think_time != 0)
4959 think_time = (think_time / 666) - 1;
4960 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4961 slot_ctx->tt_info |=
4962 cpu_to_le32(TT_THINK_TIME(think_time));
4964 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4965 "TT think time or number of ports\n",
4966 (unsigned int) xhci->hci_version);
4968 slot_ctx->dev_state = 0;
4969 spin_unlock_irqrestore(&xhci->lock, flags);
4971 xhci_dbg(xhci, "Set up %s for hub device.\n",
4972 (xhci->hci_version > 0x95) ?
4973 "configure endpoint" : "evaluate context");
4975 /* Issue and wait for the configure endpoint or
4976 * evaluate context command.
4978 if (xhci->hci_version > 0x95)
4979 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4982 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4985 xhci_free_command(xhci, config_cmd);
4989 static int xhci_get_frame(struct usb_hcd *hcd)
4991 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4992 /* EHCI mods by the periodic size. Why? */
4993 return readl(&xhci->run_regs->microframe_index) >> 3;
4996 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4998 struct xhci_hcd *xhci;
5000 * TODO: Check with DWC3 clients for sysdev according to
5003 struct device *dev = hcd->self.sysdev;
5004 unsigned int minor_rev;
5007 /* Accept arbitrarily long scatter-gather lists */
5008 hcd->self.sg_tablesize = ~0;
5010 /* support to build packet from discontinuous buffers */
5011 hcd->self.no_sg_constraint = 1;
5013 /* XHCI controllers don't stop the ep queue on short packets :| */
5014 hcd->self.no_stop_on_short = 1;
5016 xhci = hcd_to_xhci(hcd);
5018 if (usb_hcd_is_primary_hcd(hcd)) {
5019 xhci->main_hcd = hcd;
5020 xhci->usb2_rhub.hcd = hcd;
5021 /* Mark the first roothub as being USB 2.0.
5022 * The xHCI driver will register the USB 3.0 roothub.
5024 hcd->speed = HCD_USB2;
5025 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5027 * USB 2.0 roothub under xHCI has an integrated TT,
5028 * (rate matching hub) as opposed to having an OHCI/UHCI
5029 * companion controller.
5034 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
5035 * minor revision instead of sbrn
5037 minor_rev = xhci->usb3_rhub.min_rev;
5039 hcd->speed = HCD_USB31;
5040 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5042 xhci_info(xhci, "Host supports USB 3.%x %s SuperSpeed\n",
5044 minor_rev ? "Enhanced" : "");
5046 xhci->usb3_rhub.hcd = hcd;
5047 /* xHCI private pointer was set in xhci_pci_probe for the second
5048 * registered roothub.
5053 mutex_init(&xhci->mutex);
5054 xhci->cap_regs = hcd->regs;
5055 xhci->op_regs = hcd->regs +
5056 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5057 xhci->run_regs = hcd->regs +
5058 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5059 /* Cache read-only capability registers */
5060 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5061 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5062 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5063 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5064 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5065 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5066 if (xhci->hci_version > 0x100)
5067 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5069 xhci->quirks |= quirks;
5071 get_quirks(dev, xhci);
5073 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5074 * success event after a short transfer. This quirk will ignore such
5077 if (xhci->hci_version > 0x96)
5078 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5080 /* Make sure the HC is halted. */
5081 retval = xhci_halt(xhci);
5085 xhci_zero_64b_regs(xhci);
5087 xhci_dbg(xhci, "Resetting HCD\n");
5088 /* Reset the internal HC memory state and registers. */
5089 retval = xhci_reset(xhci);
5092 xhci_dbg(xhci, "Reset complete\n");
5095 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5096 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5097 * address memory pointers actually. So, this driver clears the AC64
5098 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5099 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5101 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5102 xhci->hcc_params &= ~BIT(0);
5104 /* Set dma_mask and coherent_dma_mask to 64-bits,
5105 * if xHC supports 64-bit addressing */
5106 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5107 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5108 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5109 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5112 * This is to avoid error in cases where a 32-bit USB
5113 * controller is used on a 64-bit capable system.
5115 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5118 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5119 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5122 xhci_dbg(xhci, "Calling HCD init\n");
5123 /* Initialize HCD and host controller data structures. */
5124 retval = xhci_init(hcd);
5127 xhci_dbg(xhci, "Called HCD init\n");
5129 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5130 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5134 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5136 static const struct hc_driver xhci_hc_driver = {
5137 .description = "xhci-hcd",
5138 .product_desc = "xHCI Host Controller",
5139 .hcd_priv_size = sizeof(struct xhci_hcd),
5142 * generic hardware linkage
5145 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5148 * basic lifecycle operations
5150 .reset = NULL, /* set in xhci_init_driver() */
5153 .shutdown = xhci_shutdown,
5156 * managing i/o requests and associated device resources
5158 .urb_enqueue = xhci_urb_enqueue,
5159 .urb_dequeue = xhci_urb_dequeue,
5160 .alloc_dev = xhci_alloc_dev,
5161 .free_dev = xhci_free_dev,
5162 .alloc_streams = xhci_alloc_streams,
5163 .free_streams = xhci_free_streams,
5164 .add_endpoint = xhci_add_endpoint,
5165 .drop_endpoint = xhci_drop_endpoint,
5166 .endpoint_reset = xhci_endpoint_reset,
5167 .check_bandwidth = xhci_check_bandwidth,
5168 .reset_bandwidth = xhci_reset_bandwidth,
5169 .address_device = xhci_address_device,
5170 .enable_device = xhci_enable_device,
5171 .update_hub_device = xhci_update_hub_device,
5172 .reset_device = xhci_discover_or_reset_device,
5175 * scheduling support
5177 .get_frame_number = xhci_get_frame,
5182 .hub_control = xhci_hub_control,
5183 .hub_status_data = xhci_hub_status_data,
5184 .bus_suspend = xhci_bus_suspend,
5185 .bus_resume = xhci_bus_resume,
5186 .get_resuming_ports = xhci_get_resuming_ports,
5189 * call back when device connected and addressed
5191 .update_device = xhci_update_device,
5192 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5193 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5194 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5195 .find_raw_port_number = xhci_find_raw_port_number,
5198 void xhci_init_driver(struct hc_driver *drv,
5199 const struct xhci_driver_overrides *over)
5203 /* Copy the generic table to drv then apply the overrides */
5204 *drv = xhci_hc_driver;
5207 drv->hcd_priv_size += over->extra_priv_size;
5209 drv->reset = over->reset;
5211 drv->start = over->start;
5214 EXPORT_SYMBOL_GPL(xhci_init_driver);
5216 MODULE_DESCRIPTION(DRIVER_DESC);
5217 MODULE_AUTHOR(DRIVER_AUTHOR);
5218 MODULE_LICENSE("GPL");
5220 static int __init xhci_hcd_init(void)
5223 * Check the compiler generated sizes of structures that must be laid
5224 * out in specific ways for hardware access.
5226 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5227 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5228 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5229 /* xhci_device_control has eight fields, and also
5230 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5232 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5233 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5234 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5235 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5236 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5237 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5238 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5243 xhci_debugfs_create_root();
5249 * If an init function is provided, an exit function must also be provided
5250 * to allow module unload.
5252 static void __exit xhci_hcd_fini(void)
5254 xhci_debugfs_remove_root();
5257 module_init(xhci_hcd_init);
5258 module_exit(xhci_hcd_fini);