drivers/usb/host/xhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVIDIA Tegra xHCI host controller driver
   4  *
   5  * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
   6  * Copyright (C) 2014 Google, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/firmware.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/phy/tegra/xusb.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/usb/ch9.h>
  23 #include <linux/pm.h>
  24 #include <linux/pm_domain.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/reset.h>
  28 #include <linux/slab.h>
  29 #include <linux/usb/otg.h>
  30 #include <linux/usb/phy.h>
  31 #include <linux/usb/role.h>
  32 #include <soc/tegra/pmc.h>
  33
  34 #include "xhci.h"
  35
  36 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
  37 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
  38
  39 /* FPCI CFG registers */
  40 #define XUSB_CFG_1                              0x004
  41 #define  XUSB_IO_SPACE_EN                       BIT(0)
  42 #define  XUSB_MEM_SPACE_EN                      BIT(1)
  43 #define  XUSB_BUS_MASTER_EN                     BIT(2)
  44 #define XUSB_CFG_4                              0x010
  45 #define  XUSB_BASE_ADDR_SHIFT                   15
  46 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
  47 #define XUSB_CFG_7                              0x01c
  48 #define  XUSB_BASE2_ADDR_SHIFT                  16
  49 #define  XUSB_BASE2_ADDR_MASK                   0xffff
  50 #define XUSB_CFG_16                             0x040
  51 #define XUSB_CFG_24                             0x060
  52 #define XUSB_CFG_AXI_CFG                        0x0f8
  53 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
  54 #define XUSB_CFG_ARU_CONTEXT                    0x43c
  55 #define XUSB_CFG_ARU_CONTEXT_HS_PLS             0x478
  56 #define XUSB_CFG_ARU_CONTEXT_FS_PLS             0x47c
  57 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED         0x480
  58 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP            0x484
  59 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
  60
  61 /* FPCI mailbox registers */
  62 /* XUSB_CFG_ARU_MBOX_CMD */
  63 #define  MBOX_DEST_FALC                         BIT(27)
  64 #define  MBOX_DEST_PME                          BIT(28)
  65 #define  MBOX_DEST_SMI                          BIT(29)
  66 #define  MBOX_DEST_XHCI                         BIT(30)
  67 #define  MBOX_INT_EN                            BIT(31)
  68 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
  69 #define  CMD_DATA_SHIFT                         0
  70 #define  CMD_DATA_MASK                          0xffffff
  71 #define  CMD_TYPE_SHIFT                         24
  72 #define  CMD_TYPE_MASK                          0xff
  73 /* XUSB_CFG_ARU_MBOX_OWNER */
  74 #define  MBOX_OWNER_NONE                        0
  75 #define  MBOX_OWNER_FW                          1
  76 #define  MBOX_OWNER_SW                          2
  77 #define XUSB_CFG_ARU_SMI_INTR                   0x428
  78 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
  79 #define  MBOX_SMI_INTR_EN                       BIT(3)
  80
  81 /* BAR2 registers */
  82 #define XUSB_BAR2_ARU_MBOX_CMD                  0x004
  83 #define XUSB_BAR2_ARU_MBOX_DATA_IN              0x008
  84 #define XUSB_BAR2_ARU_MBOX_DATA_OUT             0x00c
  85 #define XUSB_BAR2_ARU_MBOX_OWNER                0x010
  86 #define XUSB_BAR2_ARU_SMI_INTR                  0x014
  87 #define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0  0x01c
  88 #define XUSB_BAR2_ARU_IFRDMA_CFG0               0x0e0
  89 #define XUSB_BAR2_ARU_IFRDMA_CFG1               0x0e4
  90 #define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD     0x0e8
  91 #define XUSB_BAR2_ARU_C11_CSBRANGE              0x9c
  92 #define XUSB_BAR2_ARU_FW_SCRATCH                0x1000
  93 #define XUSB_BAR2_CSB_BASE_ADDR                 0x2000
  94
  95 /* IPFS registers */
  96 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0             0x0c0
  97 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0         0x0c4
  98 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0        0x0c8
  99 #define IPFS_XUSB_HOST_MSI_VEC0_0               0x100
 100 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0            0x140
 101 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
 102 #define  IPFS_EN_FPCI                           BIT(0)
 103 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0       0x184
 104 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
 105 #define  IPFS_IP_INT_MASK                       BIT(16)
 106 #define IPFS_XUSB_HOST_INTR_ENABLE_0            0x198
 107 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0           0x19c
 108 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
 109 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0         0x1dc
 110
 111 #define CSB_PAGE_SELECT_MASK                    0x7fffff
 112 #define CSB_PAGE_SELECT_SHIFT                   9
 113 #define CSB_PAGE_OFFSET_MASK                    0x1ff
 114 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
 115                                  CSB_PAGE_SELECT_MASK)
 116 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
 117
 118 /* Falcon CSB registers */
 119 #define XUSB_FALC_CPUCTL                        0x100
 120 #define  CPUCTL_STARTCPU                        BIT(1)
 121 #define  CPUCTL_STATE_HALTED                    BIT(4)
 122 #define  CPUCTL_STATE_STOPPED                   BIT(5)
 123 #define XUSB_FALC_BOOTVEC                       0x104
 124 #define XUSB_FALC_DMACTL                        0x10c
 125 #define XUSB_FALC_IMFILLRNG1                    0x154
 126 #define  IMFILLRNG1_TAG_MASK                    0xffff
 127 #define  IMFILLRNG1_TAG_LO_SHIFT                0
 128 #define  IMFILLRNG1_TAG_HI_SHIFT                16
 129 #define XUSB_FALC_IMFILLCTL                     0x158
 130
 131 /* CSB ARU registers */
 132 #define XUSB_CSB_ARU_SCRATCH0                   0x100100
 133
 134 /* MP CSB registers */
 135 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
 136 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
 137 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
 138 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
 139 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
 140 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
 141 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
 142 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
 143 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
 144 #define  L2IMEMOP_ACTION_SHIFT                  24
 145 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
 146 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
 147 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT        0x101a18
 148 #define  L2IMEMOP_RESULT_VLD                    BIT(31)
 149 #define XUSB_CSB_MP_APMAP                       0x10181c
 150 #define  APMAP_BOOTPATH                         BIT(31)
 151
 152 #define IMEM_BLOCK_SIZE                         256
 153
 154 #define FW_IOCTL_TYPE_SHIFT                     24
 155 #define FW_IOCTL_CFGTBL_READ            17
 156
 157 struct tegra_xusb_fw_header {
 158         __le32 boot_loadaddr_in_imem;
 159         __le32 boot_codedfi_offset;
 160         __le32 boot_codetag;
 161         __le32 boot_codesize;
 162         __le32 phys_memaddr;
 163         __le16 reqphys_memsize;
 164         __le16 alloc_phys_memsize;
 165         __le32 rodata_img_offset;
 166         __le32 rodata_section_start;
 167         __le32 rodata_section_end;
 168         __le32 main_fnaddr;
 169         __le32 fwimg_cksum;
 170         __le32 fwimg_created_time;
 171         __le32 imem_resident_start;
 172         __le32 imem_resident_end;
 173         __le32 idirect_start;
 174         __le32 idirect_end;
 175         __le32 l2_imem_start;
 176         __le32 l2_imem_end;
 177         __le32 version_id;
 178         u8 init_ddirect;
 179         u8 reserved[3];
 180         __le32 phys_addr_log_buffer;
 181         __le32 total_log_entries;
 182         __le32 dequeue_ptr;
 183         __le32 dummy_var[2];
 184         __le32 fwimg_len;
 185         u8 magic[8];
 186         __le32 ss_low_power_entry_timeout;
 187         u8 num_hsic_port;
 188         u8 padding[139]; /* Pad to 256 bytes */
 189 };
 190
 191 struct tegra_xusb_phy_type {
 192         const char *name;
 193         unsigned int num;
 194 };
 195
 196 struct tegra_xusb_mbox_regs {
 197         u16 cmd;
 198         u16 data_in;
 199         u16 data_out;
 200         u16 owner;
 201         u16 smi_intr;
 202 };
 203
 204 struct tegra_xusb_context_soc {
 205         struct {
 206                 const unsigned int *offsets;
 207                 unsigned int num_offsets;
 208         } ipfs;
 209
 210         struct {
 211                 const unsigned int *offsets;
 212                 unsigned int num_offsets;
 213         } fpci;
 214 };
 215
 216 struct tegra_xusb;
 217 struct tegra_xusb_soc_ops {
 218         u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, unsigned int offset);
 219         void (*mbox_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset);
 220         u32 (*csb_reg_readl)(struct tegra_xusb *tegra, unsigned int offset);
 221         void (*csb_reg_writel)(struct tegra_xusb *tegra, u32 value, unsigned int offset);
 222 };
 223
 224 struct tegra_xusb_soc {
 225         const char *firmware;
 226         const char * const *supply_names;
 227         unsigned int num_supplies;
 228         const struct tegra_xusb_phy_type *phy_types;
 229         unsigned int num_types;
 230         const struct tegra_xusb_context_soc *context;
 231
 232         struct {
 233                 struct {
 234                         unsigned int offset;
 235                         unsigned int count;
 236                 } usb2, ulpi, hsic, usb3;
 237         } ports;
 238
 239         struct tegra_xusb_mbox_regs mbox;
 240         const struct tegra_xusb_soc_ops *ops;
 241
 242         bool scale_ss_clock;
 243         bool has_ipfs;
 244         bool lpm_support;
 245         bool otg_reset_sspi;
 246
 247         bool has_bar2;
 248 };
 249
 250 struct tegra_xusb_context {
 251         u32 *ipfs;
 252         u32 *fpci;
 253 };
 254
 255 struct tegra_xusb {
 256         struct device *dev;
 257         void __iomem *regs;
 258         struct usb_hcd *hcd;
 259
 260         struct mutex lock;
 261
 262         int xhci_irq;
 263         int mbox_irq;
 264         int padctl_irq;
 265
 266         void __iomem *ipfs_base;
 267         void __iomem *fpci_base;
 268         void __iomem *bar2_base;
 269         struct resource *bar2;
 270
 271         const struct tegra_xusb_soc *soc;
 272
 273         struct regulator_bulk_data *supplies;
 274
 275         struct tegra_xusb_padctl *padctl;
 276
 277         struct clk *host_clk;
 278         struct clk *falcon_clk;
 279         struct clk *ss_clk;
 280         struct clk *ss_src_clk;
 281         struct clk *hs_src_clk;
 282         struct clk *fs_src_clk;
 283         struct clk *pll_u_480m;
 284         struct clk *clk_m;
 285         struct clk *pll_e;
 286
 287         struct reset_control *host_rst;
 288         struct reset_control *ss_rst;
 289
 290         struct device *genpd_dev_host;
 291         struct device *genpd_dev_ss;
 292         bool use_genpd;
 293
 294         struct phy **phys;
 295         unsigned int num_phys;
 296
 297         struct usb_phy **usbphy;
 298         unsigned int num_usb_phys;
 299         int otg_usb2_port;
 300         int otg_usb3_port;
 301         bool host_mode;
 302         struct notifier_block id_nb;
 303         struct work_struct id_work;
 304
 305         /* Firmware loading related */
 306         struct {
 307                 size_t size;
 308                 void *virt;
 309                 dma_addr_t phys;
 310         } fw;
 311
 312         bool suspended;
 313         struct tegra_xusb_context context;
 314         u8 lp0_utmi_pad_mask;
 315 };
 316
 317 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
 318
 319 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
 320 {
 321         return readl(tegra->fpci_base + offset);
 322 }
 323
 324 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
 325                                unsigned int offset)
 326 {
 327         writel(value, tegra->fpci_base + offset);
 328 }
 329
 330 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
 331 {
 332         return readl(tegra->ipfs_base + offset);
 333 }
 334
 335 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
 336                                unsigned int offset)
 337 {
 338         writel(value, tegra->ipfs_base + offset);
 339 }
 340
 341 static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset)
 342 {
 343         return readl(tegra->bar2_base + offset);
 344 }
 345
 346 static inline void bar2_writel(struct tegra_xusb *tegra, u32 value,
 347                                unsigned int offset)
 348 {
 349         writel(value, tegra->bar2_base + offset);
 350 }
 351
 352 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 353 {
 354         const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
 355
 356         return ops->csb_reg_readl(tegra, offset);
 357 }
 358
 359 static void csb_writel(struct tegra_xusb *tegra, u32 value,
 360                        unsigned int offset)
 361 {
 362         const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
 363
 364         ops->csb_reg_writel(tegra, value, offset);
 365 }
 366
 367 static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 368 {
 369         u32 page = CSB_PAGE_SELECT(offset);
 370         u32 ofs = CSB_PAGE_OFFSET(offset);
 371
 372         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 373
 374         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
 375 }
 376
 377 static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value,
 378                             unsigned int offset)
 379 {
 380         u32 page = CSB_PAGE_SELECT(offset);
 381         u32 ofs = CSB_PAGE_OFFSET(offset);
 382
 383         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 384         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
 385 }
 386
 387 static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 388 {
 389         u32 page = CSB_PAGE_SELECT(offset);
 390         u32 ofs = CSB_PAGE_OFFSET(offset);
 391
 392         bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE);
 393
 394         return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs);
 395 }
 396
 397 static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value,
 398                             unsigned int offset)
 399 {
 400         u32 page = CSB_PAGE_SELECT(offset);
 401         u32 ofs = CSB_PAGE_OFFSET(offset);
 402
 403         bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE);
 404         bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs);
 405 }
 406
 407 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
 408                                  unsigned long rate)
 409 {
 410         unsigned long new_parent_rate, old_parent_rate;
 411         struct clk *clk = tegra->ss_src_clk;
 412         unsigned int div;
 413         int err;
 414
 415         if (clk_get_rate(clk) == rate)
 416                 return 0;
 417
 418         switch (rate) {
 419         case TEGRA_XHCI_SS_HIGH_SPEED:
 420                 /*
 421                  * Reparent to PLLU_480M. Set divider first to avoid
 422                  * overclocking.
 423                  */
 424                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
 425                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
 426                 div = new_parent_rate / rate;
 427
 428                 err = clk_set_rate(clk, old_parent_rate / div);
 429                 if (err)
 430                         return err;
 431
 432                 err = clk_set_parent(clk, tegra->pll_u_480m);
 433                 if (err)
 434                         return err;
 435
 436                 /*
 437                  * The rate should already be correct, but set it again just
 438                  * to be sure.
 439                  */
 440                 err = clk_set_rate(clk, rate);
 441                 if (err)
 442                         return err;
 443
 444                 break;
 445
 446         case TEGRA_XHCI_SS_LOW_SPEED:
 447                 /* Reparent to CLK_M */
 448                 err = clk_set_parent(clk, tegra->clk_m);
 449                 if (err)
 450                         return err;
 451
 452                 err = clk_set_rate(clk, rate);
 453                 if (err)
 454                         return err;
 455
 456                 break;
 457
 458         default:
 459                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
 460                 return -EINVAL;
 461         }
 462
 463         if (clk_get_rate(clk) != rate) {
 464                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
 465                 return -EINVAL;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static unsigned long extract_field(u32 value, unsigned int start,
 472                                    unsigned int count)
 473 {
 474         return (value >> start) & ((1 << count) - 1);
 475 }
 476
 477 /* Command requests from the firmware */
 478 enum tegra_xusb_mbox_cmd {
 479         MBOX_CMD_MSG_ENABLED = 1,
 480         MBOX_CMD_INC_FALC_CLOCK,
 481         MBOX_CMD_DEC_FALC_CLOCK,
 482         MBOX_CMD_INC_SSPI_CLOCK,
 483         MBOX_CMD_DEC_SSPI_CLOCK,
 484         MBOX_CMD_SET_BW, /* no ACK/NAK required */
 485         MBOX_CMD_SET_SS_PWR_GATING,
 486         MBOX_CMD_SET_SS_PWR_UNGATING,
 487         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 488         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 489         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
 490         MBOX_CMD_START_HSIC_IDLE,
 491         MBOX_CMD_STOP_HSIC_IDLE,
 492         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 493         MBOX_CMD_HSIC_PRETEND_CONNECT,
 494         MBOX_CMD_RESET_SSPI,
 495         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 496         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 497
 498         MBOX_CMD_MAX,
 499
 500         /* Response message to above commands */
 501         MBOX_CMD_ACK = 128,
 502         MBOX_CMD_NAK
 503 };
 504
 505 struct tegra_xusb_mbox_msg {
 506         u32 cmd;
 507         u32 data;
 508 };
 509
 510 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
 511 {
 512         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
 513                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
 514 }
 515 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
 516                                           u32 value)
 517 {
 518         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
 519         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
 520 }
 521
 522 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
 523 {
 524         switch (cmd) {
 525         case MBOX_CMD_SET_BW:
 526         case MBOX_CMD_ACK:
 527         case MBOX_CMD_NAK:
 528                 return false;
 529
 530         default:
 531                 return true;
 532         }
 533 }
 534
 535 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
 536                                 const struct tegra_xusb_mbox_msg *msg)
 537 {
 538         const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
 539         bool wait_for_idle = false;
 540         u32 value;
 541
 542         /*
 543          * Acquire the mailbox. The firmware still owns the mailbox for
 544          * ACK/NAK messages.
 545          */
 546         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
 547                 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
 548                 if (value != MBOX_OWNER_NONE) {
 549                         dev_err(tegra->dev, "mailbox is busy\n");
 550                         return -EBUSY;
 551                 }
 552
 553                 ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
 554
 555                 value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
 556                 if (value != MBOX_OWNER_SW) {
 557                         dev_err(tegra->dev, "failed to acquire mailbox\n");
 558                         return -EBUSY;
 559                 }
 560
 561                 wait_for_idle = true;
 562         }
 563
 564         value = tegra_xusb_mbox_pack(msg);
 565         ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in);
 566
 567         value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd);
 568         value |= MBOX_INT_EN | MBOX_DEST_FALC;
 569         ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd);
 570
 571         if (wait_for_idle) {
 572                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
 573
 574                 while (time_before(jiffies, timeout)) {
 575                         value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
 576                         if (value == MBOX_OWNER_NONE)
 577                                 break;
 578
 579                         usleep_range(10, 20);
 580                 }
 581
 582                 if (time_after(jiffies, timeout))
 583                         value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner);
 584
 585                 if (value != MBOX_OWNER_NONE)
 586                         return -ETIMEDOUT;
 587         }
 588
 589         return 0;
 590 }
 591
 592 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
 593 {
 594         struct tegra_xusb *tegra = data;
 595         const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
 596         u32 value;
 597
 598         /* clear mailbox interrupts */
 599         value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr);
 600         ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr);
 601
 602         if (value & MBOX_SMI_INTR_FW_HANG)
 603                 dev_err(tegra->dev, "controller firmware hang\n");
 604
 605         return IRQ_WAKE_THREAD;
 606 }
 607
 608 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 609                                    const struct tegra_xusb_mbox_msg *msg)
 610 {
 611         struct tegra_xusb_padctl *padctl = tegra->padctl;
 612         const struct tegra_xusb_soc *soc = tegra->soc;
 613         struct device *dev = tegra->dev;
 614         struct tegra_xusb_mbox_msg rsp;
 615         unsigned long mask;
 616         unsigned int port;
 617         bool idle, enable;
 618         int err = 0;
 619
 620         memset(&rsp, 0, sizeof(rsp));
 621
 622         switch (msg->cmd) {
 623         case MBOX_CMD_INC_FALC_CLOCK:
 624         case MBOX_CMD_DEC_FALC_CLOCK:
 625                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
 626                 if (rsp.data != msg->data)
 627                         rsp.cmd = MBOX_CMD_NAK;
 628                 else
 629                         rsp.cmd = MBOX_CMD_ACK;
 630
 631                 break;
 632
 633         case MBOX_CMD_INC_SSPI_CLOCK:
 634         case MBOX_CMD_DEC_SSPI_CLOCK:
 635                 if (tegra->soc->scale_ss_clock) {
 636                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
 637                         if (err < 0)
 638                                 rsp.cmd = MBOX_CMD_NAK;
 639                         else
 640                                 rsp.cmd = MBOX_CMD_ACK;
 641
 642                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
 643                 } else {
 644                         rsp.cmd = MBOX_CMD_ACK;
 645                         rsp.data = msg->data;
 646                 }
 647
 648                 break;
 649
 650         case MBOX_CMD_SET_BW:
 651                 /*
 652                  * TODO: Request bandwidth once EMC scaling is supported.
 653                  * Ignore for now since ACK/NAK is not required for SET_BW
 654                  * messages.
 655                  */
 656                 break;
 657
 658         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
 659                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
 660                 if (err < 0) {
 661                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
 662                                 msg->data, err);
 663                         rsp.cmd = MBOX_CMD_NAK;
 664                 } else {
 665                         rsp.cmd = MBOX_CMD_ACK;
 666                 }
 667
 668                 rsp.data = msg->data;
 669                 break;
 670
 671         case MBOX_CMD_START_HSIC_IDLE:
 672         case MBOX_CMD_STOP_HSIC_IDLE:
 673                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
 674                         idle = false;
 675                 else
 676                         idle = true;
 677
 678                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
 679                                      soc->ports.hsic.count);
 680
 681                 for_each_set_bit(port, &mask, 32) {
 682                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
 683                                                               idle);
 684                         if (err < 0)
 685                                 break;
 686                 }
 687
 688                 if (err < 0) {
 689                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
 690                                 idle ? "idle" : "busy", err);
 691                         rsp.cmd = MBOX_CMD_NAK;
 692                 } else {
 693                         rsp.cmd = MBOX_CMD_ACK;
 694                 }
 695
 696                 rsp.data = msg->data;
 697                 break;
 698
 699         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
 700         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
 701                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
 702                         enable = false;
 703                 else
 704                         enable = true;
 705
 706                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
 707                                      soc->ports.usb3.count);
 708
 709                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
 710                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
 711                                                                      port,
 712                                                                      enable);
 713                         if (err < 0)
 714                                 break;
 715
 716                         /*
 717                          * wait 500us for LFPS detector to be disabled before
 718                          * sending ACK
 719                          */
 720                         if (!enable)
 721                                 usleep_range(500, 1000);
 722                 }
 723
 724                 if (err < 0) {
 725                         dev_err(dev,
 726                                 "failed to %s LFPS detection on USB3#%u: %d\n",
 727                                 enable ? "enable" : "disable", port, err);
 728                         rsp.cmd = MBOX_CMD_NAK;
 729                 } else {
 730                         rsp.cmd = MBOX_CMD_ACK;
 731                 }
 732
 733                 rsp.data = msg->data;
 734                 break;
 735
 736         default:
 737                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
 738                 break;
 739         }
 740
 741         if (rsp.cmd) {
 742                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
 743
 744                 err = tegra_xusb_mbox_send(tegra, &rsp);
 745                 if (err < 0)
 746                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
 747         }
 748 }
 749
 750 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
 751 {
 752         struct tegra_xusb *tegra = data;
 753         const struct tegra_xusb_soc_ops *ops = tegra->soc->ops;
 754         struct tegra_xusb_mbox_msg msg;
 755         u32 value;
 756
 757         mutex_lock(&tegra->lock);
 758
 759         if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
 760                 goto out;
 761
 762         value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out);
 763         tegra_xusb_mbox_unpack(&msg, value);
 764
 765         value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd);
 766         value &= ~MBOX_DEST_SMI;
 767         ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd);
 768
 769         /* clear mailbox owner if no ACK/NAK is required */
 770         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
 771                 ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
 772
 773         tegra_xusb_mbox_handle(tegra, &msg);
 774
 775 out:
 776         mutex_unlock(&tegra->lock);
 777         return IRQ_HANDLED;
 778 }
 779
 780 static void tegra_xusb_config(struct tegra_xusb *tegra)
 781 {
 782         u32 regs = tegra->hcd->rsrc_start;
 783         u32 value;
 784
 785         if (tegra->soc->has_ipfs) {
 786                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
 787                 value |= IPFS_EN_FPCI;
 788                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
 789
 790                 usleep_range(10, 20);
 791         }
 792
 793         /* Program BAR0 space */
 794         value = fpci_readl(tegra, XUSB_CFG_4);
 795         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 796         value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 797         fpci_writel(tegra, value, XUSB_CFG_4);
 798
 799         /* Program BAR2 space */
 800         if (tegra->bar2) {
 801                 value = fpci_readl(tegra, XUSB_CFG_7);
 802                 value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT);
 803                 value |= tegra->bar2->start &
 804                         (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT);
 805                 fpci_writel(tegra, value, XUSB_CFG_7);
 806         }
 807
 808         usleep_range(100, 200);
 809
 810         /* Enable bus master */
 811         value = fpci_readl(tegra, XUSB_CFG_1);
 812         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
 813         fpci_writel(tegra, value, XUSB_CFG_1);
 814
 815         if (tegra->soc->has_ipfs) {
 816                 /* Enable interrupt assertion */
 817                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
 818                 value |= IPFS_IP_INT_MASK;
 819                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
 820
 821                 /* Set hysteresis */
 822                 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
 823         }
 824 }
 825
 826 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
 827 {
 828         int err;
 829
 830         err = clk_prepare_enable(tegra->pll_e);
 831         if (err < 0)
 832                 return err;
 833
 834         err = clk_prepare_enable(tegra->host_clk);
 835         if (err < 0)
 836                 goto disable_plle;
 837
 838         err = clk_prepare_enable(tegra->ss_clk);
 839         if (err < 0)
 840                 goto disable_host;
 841
 842         err = clk_prepare_enable(tegra->falcon_clk);
 843         if (err < 0)
 844                 goto disable_ss;
 845
 846         err = clk_prepare_enable(tegra->fs_src_clk);
 847         if (err < 0)
 848                 goto disable_falc;
 849
 850         err = clk_prepare_enable(tegra->hs_src_clk);
 851         if (err < 0)
 852                 goto disable_fs_src;
 853
 854         if (tegra->soc->scale_ss_clock) {
 855                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
 856                 if (err < 0)
 857                         goto disable_hs_src;
 858         }
 859
 860         return 0;
 861
 862 disable_hs_src:
 863         clk_disable_unprepare(tegra->hs_src_clk);
 864 disable_fs_src:
 865         clk_disable_unprepare(tegra->fs_src_clk);
 866 disable_falc:
 867         clk_disable_unprepare(tegra->falcon_clk);
 868 disable_ss:
 869         clk_disable_unprepare(tegra->ss_clk);
 870 disable_host:
 871         clk_disable_unprepare(tegra->host_clk);
 872 disable_plle:
 873         clk_disable_unprepare(tegra->pll_e);
 874         return err;
 875 }
 876
 877 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
 878 {
 879         clk_disable_unprepare(tegra->pll_e);
 880         clk_disable_unprepare(tegra->host_clk);
 881         clk_disable_unprepare(tegra->ss_clk);
 882         clk_disable_unprepare(tegra->falcon_clk);
 883         clk_disable_unprepare(tegra->fs_src_clk);
 884         clk_disable_unprepare(tegra->hs_src_clk);
 885 }
 886
 887 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
 888 {
 889         unsigned int i;
 890         int err;
 891
 892         for (i = 0; i < tegra->num_phys; i++) {
 893                 err = phy_init(tegra->phys[i]);
 894                 if (err)
 895                         goto disable_phy;
 896
 897                 err = phy_power_on(tegra->phys[i]);
 898                 if (err) {
 899                         phy_exit(tegra->phys[i]);
 900                         goto disable_phy;
 901                 }
 902         }
 903
 904         return 0;
 905
 906 disable_phy:
 907         while (i--) {
 908                 phy_power_off(tegra->phys[i]);
 909                 phy_exit(tegra->phys[i]);
 910         }
 911
 912         return err;
 913 }
 914
 915 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
 916 {
 917         unsigned int i;
 918
 919         for (i = 0; i < tegra->num_phys; i++) {
 920                 phy_power_off(tegra->phys[i]);
 921                 phy_exit(tegra->phys[i]);
 922         }
 923 }
 924
 925 #ifdef CONFIG_PM_SLEEP
 926 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
 927 {
 928         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
 929
 930         tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
 931                                            sizeof(u32), GFP_KERNEL);
 932         if (!tegra->context.ipfs)
 933                 return -ENOMEM;
 934
 935         tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
 936                                            sizeof(u32), GFP_KERNEL);
 937         if (!tegra->context.fpci)
 938                 return -ENOMEM;
 939
 940         return 0;
 941 }
 942 #else
 943 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
 944 {
 945         return 0;
 946 }
 947 #endif
 948
 949 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
 950 {
 951         struct tegra_xusb_fw_header *header;
 952         const struct firmware *fw;
 953         int err;
 954
 955         err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
 956         if (err < 0) {
 957                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
 958                 return err;
 959         }
 960
 961         /* Load Falcon controller with its firmware. */
 962         header = (struct tegra_xusb_fw_header *)fw->data;
 963         tegra->fw.size = le32_to_cpu(header->fwimg_len);
 964
 965         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
 966                                             &tegra->fw.phys, GFP_KERNEL);
 967         if (!tegra->fw.virt) {
 968                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
 969                 release_firmware(fw);
 970                 return -ENOMEM;
 971         }
 972
 973         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 974         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
 975         release_firmware(fw);
 976
 977         return 0;
 978 }
 979
 980 static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra)
 981 {
 982         struct xhci_cap_regs __iomem *cap_regs;
 983         struct xhci_op_regs __iomem *op_regs;
 984         int ret;
 985         u32 value;
 986
 987         cap_regs = tegra->regs;
 988         op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase));
 989
 990         ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000);
 991
 992         if (ret)
 993                 dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n",
 994                         csb_readl(tegra, XUSB_FALC_CPUCTL));
 995
 996         return ret;
 997 }
 998
 999 static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra)
1000 {
1001         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
1002         struct tegra_xusb_fw_header *header;
1003         struct device *dev = tegra->dev;
1004         time64_t timestamp;
1005         u64 address;
1006         u32 value;
1007         int err;
1008
1009         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
1010
1011         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1012                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
1013                          csb_readl(tegra, XUSB_FALC_CPUCTL));
1014                 return 0;
1015         }
1016
1017         /* Program the size of DFI into ILOAD_ATTR. */
1018         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
1019
1020         /*
1021          * Boot code of the firmware reads the ILOAD_BASE registers
1022          * to get to the start of the DFI in system memory.
1023          */
1024         address = tegra->fw.phys + sizeof(*header);
1025         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
1026         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
1027
1028         /* Set BOOTPATH to 1 in APMAP. */
1029         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
1030
1031         /* Invalidate L2IMEM. */
1032         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
1033
1034         /*
1035          * Initiate fetch of bootcode from system memory into L2IMEM.
1036          * Program bootcode location and size in system memory.
1037          */
1038         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
1039                                        IMEM_BLOCK_SIZE);
1040         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
1041                                         IMEM_BLOCK_SIZE);
1042         code_blocks = code_tag_blocks + code_size_blocks;
1043
1044         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
1045                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
1046                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
1047                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
1048         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
1049
1050         /* Trigger L2IMEM load operation. */
1051         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
1052                    XUSB_CSB_MP_L2IMEMOP_TRIG);
1053
1054         /* Setup Falcon auto-fill. */
1055         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
1056
1057         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
1058                         IMFILLRNG1_TAG_LO_SHIFT) |
1059                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
1060                         IMFILLRNG1_TAG_HI_SHIFT);
1061         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
1062
1063         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
1064
1065         /* wait for RESULT_VLD to get set */
1066 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
1067         err = readx_poll_timeout(tegra_csb_readl,
1068                                  XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
1069                                  value & L2IMEMOP_RESULT_VLD, 100, 10000);
1070         if (err < 0) {
1071                 dev_err(dev, "DMA controller not ready %#010x\n", value);
1072                 return err;
1073         }
1074 #undef tegra_csb_readl
1075
1076         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
1077                    XUSB_FALC_BOOTVEC);
1078
1079         /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
1080         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
1081
1082         if (tegra_xusb_wait_for_falcon(tegra))
1083                 return -EIO;
1084
1085         timestamp = le32_to_cpu(header->fwimg_created_time);
1086
1087         dev_info(dev, "Firmware timestamp: %ptTs UTC\n", &timestamp);
1088
1089         return 0;
1090 }
1091
1092 static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset)
1093 {
1094         /*
1095          * We only accept reading the firmware config table
1096          * The offset should not exceed the fw header structure
1097          */
1098         if (offset >= sizeof(struct tegra_xusb_fw_header))
1099                 return 0;
1100
1101         bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset,
1102                     XUSB_BAR2_ARU_FW_SCRATCH);
1103         return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0);
1104 }
1105
1106 static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra)
1107 {
1108         time64_t timestamp;
1109
1110         if (tegra_xusb_wait_for_falcon(tegra))
1111                 return -EIO;
1112
1113 #define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32)))
1114         timestamp = tegra_xusb_read_firmware_header(tegra, offsetof_32(struct tegra_xusb_fw_header,
1115                                                                        fwimg_created_time) << 2);
1116
1117         dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", &timestamp);
1118
1119         return 0;
1120 }
1121
1122 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
1123 {
1124         if (!tegra->soc->firmware)
1125                 return tegra_xusb_init_ifr_firmware(tegra);
1126         else
1127                 return tegra_xusb_load_firmware_rom(tegra);
1128 }
1129
1130 static void tegra_xusb_powerdomain_remove(struct device *dev,
1131                                           struct tegra_xusb *tegra)
1132 {
1133         if (!tegra->use_genpd)
1134                 return;
1135
1136         if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1137                 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1138         if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1139                 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1140 }
1141
1142 static int tegra_xusb_powerdomain_init(struct device *dev,
1143                                        struct tegra_xusb *tegra)
1144 {
1145         int err;
1146
1147         tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1148         if (IS_ERR_OR_NULL(tegra->genpd_dev_host)) {
1149                 err = PTR_ERR(tegra->genpd_dev_host) ? : -ENODATA;
1150                 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1151                 return err;
1152         }
1153
1154         tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1155         if (IS_ERR_OR_NULL(tegra->genpd_dev_ss)) {
1156                 err = PTR_ERR(tegra->genpd_dev_ss) ? : -ENODATA;
1157                 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1158                 return err;
1159         }
1160
1161         tegra->use_genpd = true;
1162
1163         return 0;
1164 }
1165
1166 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1167 {
1168         struct device *dev = tegra->dev;
1169         int rc;
1170
1171         if (tegra->use_genpd) {
1172                 rc = pm_runtime_resume_and_get(tegra->genpd_dev_ss);
1173                 if (rc < 0) {
1174                         dev_err(dev, "failed to enable XUSB SS partition\n");
1175                         return rc;
1176                 }
1177
1178                 rc = pm_runtime_resume_and_get(tegra->genpd_dev_host);
1179                 if (rc < 0) {
1180                         dev_err(dev, "failed to enable XUSB Host partition\n");
1181                         pm_runtime_put_sync(tegra->genpd_dev_ss);
1182                         return rc;
1183                 }
1184         } else {
1185                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1186                                                         tegra->ss_clk,
1187                                                         tegra->ss_rst);
1188                 if (rc < 0) {
1189                         dev_err(dev, "failed to enable XUSB SS partition\n");
1190                         return rc;
1191                 }
1192
1193                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1194                                                         tegra->host_clk,
1195                                                         tegra->host_rst);
1196                 if (rc < 0) {
1197                         dev_err(dev, "failed to enable XUSB Host partition\n");
1198                         tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1199                         return rc;
1200                 }
1201         }
1202
1203         return 0;
1204 }
1205
1206 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1207 {
1208         struct device *dev = tegra->dev;
1209         int rc;
1210
1211         if (tegra->use_genpd) {
1212                 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1213                 if (rc < 0) {
1214                         dev_err(dev, "failed to disable XUSB Host partition\n");
1215                         return rc;
1216                 }
1217
1218                 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1219                 if (rc < 0) {
1220                         dev_err(dev, "failed to disable XUSB SS partition\n");
1221                         pm_runtime_get_sync(tegra->genpd_dev_host);
1222                         return rc;
1223                 }
1224         } else {
1225                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1226                 if (rc < 0) {
1227                         dev_err(dev, "failed to disable XUSB Host partition\n");
1228                         return rc;
1229                 }
1230
1231                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1232                 if (rc < 0) {
1233                         dev_err(dev, "failed to disable XUSB SS partition\n");
1234                         tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1235                                                           tegra->host_clk,
1236                                                           tegra->host_rst);
1237                         return rc;
1238                 }
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1245 {
1246         struct tegra_xusb_mbox_msg msg;
1247         int err;
1248
1249         /* Enable firmware messages from controller. */
1250         msg.cmd = MBOX_CMD_MSG_ENABLED;
1251         msg.data = 0;
1252
1253         err = tegra_xusb_mbox_send(tegra, &msg);
1254         if (err < 0)
1255                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1256
1257         return err;
1258 }
1259
1260 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
1261 {
1262         struct tegra_xusb *tegra = data;
1263
1264         mutex_lock(&tegra->lock);
1265
1266         if (tegra->suspended) {
1267                 mutex_unlock(&tegra->lock);
1268                 return IRQ_HANDLED;
1269         }
1270
1271         mutex_unlock(&tegra->lock);
1272
1273         pm_runtime_resume(tegra->dev);
1274
1275         return IRQ_HANDLED;
1276 }
1277
1278 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1279 {
1280         int err;
1281
1282         mutex_lock(&tegra->lock);
1283         err = __tegra_xusb_enable_firmware_messages(tegra);
1284         mutex_unlock(&tegra->lock);
1285
1286         return err;
1287 }
1288
1289 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1290                                                  bool set)
1291 {
1292         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1293         struct usb_hcd *hcd = main ?  xhci->main_hcd : xhci->shared_hcd;
1294         unsigned int wait = (!main && !set) ? 1000 : 10;
1295         u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1296         u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1297         u32 status;
1298         u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1299         u32 status_val = set ? stat_power : 0;
1300
1301         dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1302                 set ? "set" : "clear", main ? "HS" : "SS");
1303
1304         hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1305                                  NULL, 0);
1306
1307         do {
1308                 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1309                                         (char *) &status, sizeof(status));
1310                 if (status_val == (status & stat_power))
1311                         break;
1312
1313                 if (!main && !set)
1314                         usleep_range(600, 700);
1315                 else
1316                         usleep_range(10, 20);
1317         } while (--wait > 0);
1318
1319         if (status_val != (status & stat_power))
1320                 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1321                                                 set ? "set" : "clear",
1322                                                 main ? "HS" : "SS", status);
1323 }
1324
1325 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1326                                                                 int port)
1327 {
1328         unsigned int i, phy_count = 0;
1329
1330         for (i = 0; i < tegra->soc->num_types; i++) {
1331                 if (!strncmp(tegra->soc->phy_types[i].name, name,
1332                                                             strlen(name)))
1333                         return tegra->phys[phy_count+port];
1334
1335                 phy_count += tegra->soc->phy_types[i].num;
1336         }
1337
1338         return NULL;
1339 }
1340
1341 static void tegra_xhci_id_work(struct work_struct *work)
1342 {
1343         struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1344                                                 id_work);
1345         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1346         struct tegra_xusb_mbox_msg msg;
1347         struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1348                                                     tegra->otg_usb2_port);
1349         u32 status;
1350         int ret;
1351
1352         dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
1353
1354         mutex_lock(&tegra->lock);
1355
1356         if (tegra->host_mode)
1357                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1358         else
1359                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1360
1361         mutex_unlock(&tegra->lock);
1362
1363         if (tegra->host_mode) {
1364                 /* switch to host mode */
1365                 if (tegra->otg_usb3_port >= 0) {
1366                         if (tegra->soc->otg_reset_sspi) {
1367                                 /* set PP=0 */
1368                                 tegra_xhci_hc_driver.hub_control(
1369                                         xhci->shared_hcd, GetPortStatus,
1370                                         0, tegra->otg_usb3_port+1,
1371                                         (char *) &status, sizeof(status));
1372                                 if (status & USB_SS_PORT_STAT_POWER)
1373                                         tegra_xhci_set_port_power(tegra, false,
1374                                                                   false);
1375
1376                                 /* reset OTG port SSPI */
1377                                 msg.cmd = MBOX_CMD_RESET_SSPI;
1378                                 msg.data = tegra->otg_usb3_port+1;
1379
1380                                 ret = tegra_xusb_mbox_send(tegra, &msg);
1381                                 if (ret < 0) {
1382                                         dev_info(tegra->dev,
1383                                                 "failed to RESET_SSPI %d\n",
1384                                                 ret);
1385                                 }
1386                         }
1387
1388                         tegra_xhci_set_port_power(tegra, false, true);
1389                 }
1390
1391                 tegra_xhci_set_port_power(tegra, true, true);
1392
1393         } else {
1394                 if (tegra->otg_usb3_port >= 0)
1395                         tegra_xhci_set_port_power(tegra, false, false);
1396
1397                 tegra_xhci_set_port_power(tegra, true, false);
1398         }
1399 }
1400
1401 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
1402 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1403 {
1404         return (tegra->usbphy[index] != NULL);
1405 }
1406
1407 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1408 {
1409         struct tegra_xusb_padctl *padctl = tegra->padctl;
1410         unsigned int i;
1411         int port;
1412
1413         for (i = 0; i < tegra->num_usb_phys; i++) {
1414                 if (is_usb2_otg_phy(tegra, i)) {
1415                         port = tegra_xusb_padctl_get_usb3_companion(padctl, i);
1416                         if ((port >= 0) && (index == (unsigned int)port))
1417                                 return true;
1418                 }
1419         }
1420
1421         return false;
1422 }
1423
1424 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index)
1425 {
1426         if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
1427                 return true;
1428
1429         if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
1430                 if (is_usb2_otg_phy(tegra, index))
1431                         return ((index == tegra->otg_usb2_port) && tegra->host_mode);
1432                 else
1433                         return true;
1434         }
1435
1436         if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
1437                 if (is_usb3_otg_phy(tegra, index))
1438                         return ((index == tegra->otg_usb3_port) && tegra->host_mode);
1439                 else
1440                         return true;
1441         }
1442
1443         return false;
1444 }
1445 #endif
1446
1447 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1448                                               struct usb_phy *usbphy)
1449 {
1450         unsigned int i;
1451
1452         for (i = 0; i < tegra->num_usb_phys; i++) {
1453                 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1454                         return i;
1455         }
1456
1457         return -1;
1458 }
1459
1460 static int tegra_xhci_id_notify(struct notifier_block *nb,
1461                                          unsigned long action, void *data)
1462 {
1463         struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1464                                                     id_nb);
1465         struct usb_phy *usbphy = (struct usb_phy *)data;
1466
1467         dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1468
1469         if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1470                 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1471                 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1472                         tegra->host_mode);
1473                 return NOTIFY_OK;
1474         }
1475
1476         tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1477         tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
1478                                                         tegra->padctl,
1479                                                         tegra->otg_usb2_port);
1480
1481         tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1482
1483         schedule_work(&tegra->id_work);
1484
1485         return NOTIFY_OK;
1486 }
1487
1488 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1489 {
1490         unsigned int i;
1491
1492         tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1493                                    sizeof(*tegra->usbphy), GFP_KERNEL);
1494         if (!tegra->usbphy)
1495                 return -ENOMEM;
1496
1497         INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1498         tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1499         tegra->otg_usb2_port = -EINVAL;
1500         tegra->otg_usb3_port = -EINVAL;
1501
1502         for (i = 0; i < tegra->num_usb_phys; i++) {
1503                 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1504
1505                 if (!phy)
1506                         continue;
1507
1508                 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1509                                                         phy->dev.of_node,
1510                                                         &tegra->id_nb);
1511                 if (!IS_ERR(tegra->usbphy[i])) {
1512                         dev_dbg(tegra->dev, "usbphy-%d registered", i);
1513                         otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1514                 } else {
1515                         /*
1516                          * usb-phy is optional, continue if its not available.
1517                          */
1518                         tegra->usbphy[i] = NULL;
1519                 }
1520         }
1521
1522         return 0;
1523 }
1524
1525 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1526 {
1527         unsigned int i;
1528
1529         cancel_work_sync(&tegra->id_work);
1530
1531         for (i = 0; i < tegra->num_usb_phys; i++)
1532                 if (tegra->usbphy[i])
1533                         otg_set_host(tegra->usbphy[i]->otg, NULL);
1534 }
1535
1536 static int tegra_xusb_probe(struct platform_device *pdev)
1537 {
1538         struct of_phandle_args args;
1539         struct tegra_xusb *tegra;
1540         struct device_node *np;
1541         struct resource *regs;
1542         struct xhci_hcd *xhci;
1543         unsigned int i, j, k;
1544         struct phy *phy;
1545         int err;
1546
1547         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1548
1549         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1550         if (!tegra)
1551                 return -ENOMEM;
1552
1553         tegra->soc = of_device_get_match_data(&pdev->dev);
1554         mutex_init(&tegra->lock);
1555         tegra->dev = &pdev->dev;
1556
1557         err = tegra_xusb_init_context(tegra);
1558         if (err < 0)
1559                 return err;
1560
1561         tegra->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
1562         if (IS_ERR(tegra->regs))
1563                 return PTR_ERR(tegra->regs);
1564
1565         tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1566         if (IS_ERR(tegra->fpci_base))
1567                 return PTR_ERR(tegra->fpci_base);
1568
1569         if (tegra->soc->has_ipfs) {
1570                 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1571                 if (IS_ERR(tegra->ipfs_base))
1572                         return PTR_ERR(tegra->ipfs_base);
1573         } else if (tegra->soc->has_bar2) {
1574                 tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2);
1575                 if (IS_ERR(tegra->bar2_base))
1576                         return PTR_ERR(tegra->bar2_base);
1577         }
1578
1579         tegra->xhci_irq = platform_get_irq(pdev, 0);
1580         if (tegra->xhci_irq < 0)
1581                 return tegra->xhci_irq;
1582
1583         tegra->mbox_irq = platform_get_irq(pdev, 1);
1584         if (tegra->mbox_irq < 0)
1585                 return tegra->mbox_irq;
1586
1587         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1588         if (IS_ERR(tegra->padctl))
1589                 return PTR_ERR(tegra->padctl);
1590
1591         np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
1592         if (!np) {
1593                 err = -ENODEV;
1594                 goto put_padctl;
1595         }
1596
1597         /* Older device-trees don't have padctrl interrupt */
1598         err = of_irq_parse_one(np, 0, &args);
1599         if (!err) {
1600                 tegra->padctl_irq = of_irq_get(np, 0);
1601                 if (tegra->padctl_irq <= 0) {
1602                         err = (tegra->padctl_irq == 0) ? -ENODEV : tegra->padctl_irq;
1603                         goto put_padctl;
1604                 }
1605         } else {
1606                 dev_dbg(&pdev->dev,
1607                         "%pOF is missing an interrupt, disabling PM support\n", np);
1608         }
1609
1610         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1611         if (IS_ERR(tegra->host_clk)) {
1612                 err = PTR_ERR(tegra->host_clk);
1613                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1614                 goto put_padctl;
1615         }
1616
1617         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1618         if (IS_ERR(tegra->falcon_clk)) {
1619                 err = PTR_ERR(tegra->falcon_clk);
1620                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1621                 goto put_padctl;
1622         }
1623
1624         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1625         if (IS_ERR(tegra->ss_clk)) {
1626                 err = PTR_ERR(tegra->ss_clk);
1627                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1628                 goto put_padctl;
1629         }
1630
1631         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1632         if (IS_ERR(tegra->ss_src_clk)) {
1633                 err = PTR_ERR(tegra->ss_src_clk);
1634                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1635                 goto put_padctl;
1636         }
1637
1638         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1639         if (IS_ERR(tegra->hs_src_clk)) {
1640                 err = PTR_ERR(tegra->hs_src_clk);
1641                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1642                 goto put_padctl;
1643         }
1644
1645         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1646         if (IS_ERR(tegra->fs_src_clk)) {
1647                 err = PTR_ERR(tegra->fs_src_clk);
1648                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1649                 goto put_padctl;
1650         }
1651
1652         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1653         if (IS_ERR(tegra->pll_u_480m)) {
1654                 err = PTR_ERR(tegra->pll_u_480m);
1655                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1656                 goto put_padctl;
1657         }
1658
1659         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1660         if (IS_ERR(tegra->clk_m)) {
1661                 err = PTR_ERR(tegra->clk_m);
1662                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1663                 goto put_padctl;
1664         }
1665
1666         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1667         if (IS_ERR(tegra->pll_e)) {
1668                 err = PTR_ERR(tegra->pll_e);
1669                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1670                 goto put_padctl;
1671         }
1672
1673         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1674                 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1675                                                          "xusb_host");
1676                 if (IS_ERR(tegra->host_rst)) {
1677                         err = PTR_ERR(tegra->host_rst);
1678                         dev_err(&pdev->dev,
1679                                 "failed to get xusb_host reset: %d\n", err);
1680                         goto put_padctl;
1681                 }
1682
1683                 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1684                 if (IS_ERR(tegra->ss_rst)) {
1685                         err = PTR_ERR(tegra->ss_rst);
1686                         dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1687                                 err);
1688                         goto put_padctl;
1689                 }
1690         } else {
1691                 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1692                 if (err)
1693                         goto put_powerdomains;
1694         }
1695
1696         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1697                                        sizeof(*tegra->supplies), GFP_KERNEL);
1698         if (!tegra->supplies) {
1699                 err = -ENOMEM;
1700                 goto put_powerdomains;
1701         }
1702
1703         regulator_bulk_set_supply_names(tegra->supplies,
1704                                         tegra->soc->supply_names,
1705                                         tegra->soc->num_supplies);
1706
1707         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1708                                       tegra->supplies);
1709         if (err) {
1710                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1711                 goto put_powerdomains;
1712         }
1713
1714         for (i = 0; i < tegra->soc->num_types; i++) {
1715                 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1716                         tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1717                 tegra->num_phys += tegra->soc->phy_types[i].num;
1718         }
1719
1720         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1721                                    sizeof(*tegra->phys), GFP_KERNEL);
1722         if (!tegra->phys) {
1723                 err = -ENOMEM;
1724                 goto put_powerdomains;
1725         }
1726
1727         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1728                 char prop[8];
1729
1730                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1731                         snprintf(prop, sizeof(prop), "%s-%d",
1732                                  tegra->soc->phy_types[i].name, j);
1733
1734                         phy = devm_phy_optional_get(&pdev->dev, prop);
1735                         if (IS_ERR(phy)) {
1736                                 dev_err(&pdev->dev,
1737                                         "failed to get PHY %s: %ld\n", prop,
1738                                         PTR_ERR(phy));
1739                                 err = PTR_ERR(phy);
1740                                 goto put_powerdomains;
1741                         }
1742
1743                         tegra->phys[k++] = phy;
1744                 }
1745         }
1746
1747         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1748                                     dev_name(&pdev->dev));
1749         if (!tegra->hcd) {
1750                 err = -ENOMEM;
1751                 goto put_powerdomains;
1752         }
1753
1754         tegra->hcd->skip_phy_initialization = 1;
1755         tegra->hcd->regs = tegra->regs;
1756         tegra->hcd->rsrc_start = regs->start;
1757         tegra->hcd->rsrc_len = resource_size(regs);
1758
1759         /*
1760          * This must happen after usb_create_hcd(), because usb_create_hcd()
1761          * will overwrite the drvdata of the device with the hcd it creates.
1762          */
1763         platform_set_drvdata(pdev, tegra);
1764
1765         err = tegra_xusb_clk_enable(tegra);
1766         if (err) {
1767                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1768                 goto put_hcd;
1769         }
1770
1771         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1772         if (err) {
1773                 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1774                 goto disable_clk;
1775         }
1776
1777         err = tegra_xusb_phy_enable(tegra);
1778         if (err < 0) {
1779                 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1780                 goto disable_regulator;
1781         }
1782
1783         /*
1784          * The XUSB Falcon microcontroller can only address 40 bits, so set
1785          * the DMA mask accordingly.
1786          */
1787         err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1788         if (err < 0) {
1789                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1790                 goto disable_phy;
1791         }
1792
1793         if (tegra->soc->firmware) {
1794                 err = tegra_xusb_request_firmware(tegra);
1795                 if (err < 0) {
1796                         dev_err(&pdev->dev,
1797                                 "failed to request firmware: %d\n", err);
1798                         goto disable_phy;
1799                 }
1800         }
1801
1802         err = tegra_xusb_unpowergate_partitions(tegra);
1803         if (err)
1804                 goto free_firmware;
1805
1806         tegra_xusb_config(tegra);
1807
1808         err = tegra_xusb_load_firmware(tegra);
1809         if (err < 0) {
1810                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1811                 goto powergate;
1812         }
1813
1814         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1815         if (err < 0) {
1816                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1817                 goto powergate;
1818         }
1819
1820         device_wakeup_enable(tegra->hcd->self.controller);
1821
1822         xhci = hcd_to_xhci(tegra->hcd);
1823
1824         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1825                                                  &pdev->dev,
1826                                                  dev_name(&pdev->dev),
1827                                                  tegra->hcd);
1828         if (!xhci->shared_hcd) {
1829                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1830                 err = -ENOMEM;
1831                 goto remove_usb2;
1832         }
1833
1834         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1835         if (err < 0) {
1836                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1837                 goto put_usb3;
1838         }
1839
1840         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1841                                         tegra_xusb_mbox_irq,
1842                                         tegra_xusb_mbox_thread, 0,
1843                                         dev_name(&pdev->dev), tegra);
1844         if (err < 0) {
1845                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1846                 goto remove_usb3;
1847         }
1848
1849         if (tegra->padctl_irq) {
1850                 err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq,
1851                                                 NULL, tegra_xusb_padctl_irq,
1852                                                 IRQF_ONESHOT, dev_name(&pdev->dev),
1853                                                 tegra);
1854                 if (err < 0) {
1855                         dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
1856                         goto remove_usb3;
1857                 }
1858         }
1859
1860         err = tegra_xusb_enable_firmware_messages(tegra);
1861         if (err < 0) {
1862                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1863                 goto remove_usb3;
1864         }
1865
1866         err = tegra_xusb_init_usb_phy(tegra);
1867         if (err < 0) {
1868                 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1869                 goto remove_usb3;
1870         }
1871
1872         /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
1873         device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
1874         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
1875
1876         pm_runtime_use_autosuspend(tegra->dev);
1877         pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
1878         pm_runtime_mark_last_busy(tegra->dev);
1879         pm_runtime_set_active(tegra->dev);
1880
1881         if (tegra->padctl_irq) {
1882                 device_init_wakeup(tegra->dev, true);
1883                 pm_runtime_enable(tegra->dev);
1884         }
1885
1886         return 0;
1887
1888 remove_usb3:
1889         usb_remove_hcd(xhci->shared_hcd);
1890 put_usb3:
1891         usb_put_hcd(xhci->shared_hcd);
1892 remove_usb2:
1893         usb_remove_hcd(tegra->hcd);
1894 powergate:
1895         tegra_xusb_powergate_partitions(tegra);
1896 free_firmware:
1897         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1898                           tegra->fw.phys);
1899 disable_phy:
1900         tegra_xusb_phy_disable(tegra);
1901 disable_regulator:
1902         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1903 disable_clk:
1904         tegra_xusb_clk_disable(tegra);
1905 put_hcd:
1906         usb_put_hcd(tegra->hcd);
1907 put_powerdomains:
1908         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1909 put_padctl:
1910         of_node_put(np);
1911         tegra_xusb_padctl_put(tegra->padctl);
1912         return err;
1913 }
1914
1915 static int tegra_xusb_remove(struct platform_device *pdev)
1916 {
1917         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1918         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1919
1920         tegra_xusb_deinit_usb_phy(tegra);
1921
1922         pm_runtime_get_sync(&pdev->dev);
1923         usb_remove_hcd(xhci->shared_hcd);
1924         usb_put_hcd(xhci->shared_hcd);
1925         xhci->shared_hcd = NULL;
1926         usb_remove_hcd(tegra->hcd);
1927         usb_put_hcd(tegra->hcd);
1928
1929         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1930                           tegra->fw.phys);
1931
1932         if (tegra->padctl_irq)
1933                 pm_runtime_disable(&pdev->dev);
1934
1935         pm_runtime_put(&pdev->dev);
1936
1937         tegra_xusb_powergate_partitions(tegra);
1938
1939         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1940
1941         tegra_xusb_phy_disable(tegra);
1942         tegra_xusb_clk_disable(tegra);
1943         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1944         tegra_xusb_padctl_put(tegra->padctl);
1945
1946         return 0;
1947 }
1948
1949 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1950 {
1951         struct device *dev = hub->hcd->self.controller;
1952         bool status = true;
1953         unsigned int i;
1954         u32 value;
1955
1956         for (i = 0; i < hub->num_ports; i++) {
1957                 value = readl(hub->ports[i]->addr);
1958                 if ((value & PORT_PE) == 0)
1959                         continue;
1960
1961                 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1962                         dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1963                                  hub->hcd->self.busnum, i + 1, value);
1964                         status = false;
1965                 }
1966         }
1967
1968         return status;
1969 }
1970
1971 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1972 {
1973         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1974         struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state;
1975         unsigned long flags;
1976         int err = 0;
1977
1978         if (bus_state->bus_suspended) {
1979                 /* xusb_hub_suspend() has just directed one or more USB2 port(s)
1980                  * to U3 state, it takes 3ms to enter U3.
1981                  */
1982                 usleep_range(3000, 4000);
1983         }
1984
1985         spin_lock_irqsave(&xhci->lock, flags);
1986
1987         if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1988             !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1989                 err = -EBUSY;
1990
1991         spin_unlock_irqrestore(&xhci->lock, flags);
1992
1993         return err;
1994 }
1995
1996 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1997 {
1998         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1999         struct tegra_xusb_context *ctx = &tegra->context;
2000         unsigned int i;
2001
2002         if (soc->ipfs.num_offsets > 0) {
2003                 for (i = 0; i < soc->ipfs.num_offsets; i++)
2004                         ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
2005         }
2006
2007         if (soc->fpci.num_offsets > 0) {
2008                 for (i = 0; i < soc->fpci.num_offsets; i++)
2009                         ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
2010         }
2011 }
2012
2013 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
2014 {
2015         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
2016         struct tegra_xusb_context *ctx = &tegra->context;
2017         unsigned int i;
2018
2019         if (soc->fpci.num_offsets > 0) {
2020                 for (i = 0; i < soc->fpci.num_offsets; i++)
2021                         fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
2022         }
2023
2024         if (soc->ipfs.num_offsets > 0) {
2025                 for (i = 0; i < soc->ipfs.num_offsets; i++)
2026                         ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
2027         }
2028 }
2029
2030 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
2031 {
2032         if (DEV_LOWSPEED(portsc))
2033                 return USB_SPEED_LOW;
2034
2035         if (DEV_HIGHSPEED(portsc))
2036                 return USB_SPEED_HIGH;
2037
2038         if (DEV_FULLSPEED(portsc))
2039                 return USB_SPEED_FULL;
2040
2041         if (DEV_SUPERSPEED_ANY(portsc))
2042                 return USB_SPEED_SUPER;
2043
2044         return USB_SPEED_UNKNOWN;
2045 }
2046
2047 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
2048 {
2049         struct tegra_xusb_padctl *padctl = tegra->padctl;
2050         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2051         enum usb_device_speed speed;
2052         struct phy *phy;
2053         unsigned int index, offset;
2054         unsigned int i, j, k;
2055         struct xhci_hub *rhub;
2056         u32 portsc;
2057
2058         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
2059                 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
2060                         rhub = &xhci->usb3_rhub;
2061                 else
2062                         rhub = &xhci->usb2_rhub;
2063
2064                 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
2065                         offset = tegra->soc->ports.usb2.count;
2066                 else
2067                         offset = 0;
2068
2069                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
2070                         phy = tegra->phys[k++];
2071
2072                         if (!phy)
2073                                 continue;
2074
2075                         index = j + offset;
2076
2077                         if (index >= rhub->num_ports)
2078                                 continue;
2079
2080                         if (!is_host_mode_phy(tegra, i, j))
2081                                 continue;
2082
2083                         portsc = readl(rhub->ports[index]->addr);
2084                         speed = tegra_xhci_portsc_to_speed(tegra, portsc);
2085                         tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed);
2086                         tegra_xusb_padctl_enable_phy_wake(padctl, phy);
2087                 }
2088         }
2089 }
2090
2091 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
2092 {
2093         struct tegra_xusb_padctl *padctl = tegra->padctl;
2094         unsigned int i;
2095
2096         for (i = 0; i < tegra->num_usb_phys; i++) {
2097                 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
2098
2099                 if (!phy)
2100                         continue;
2101
2102                 if (tegra_xusb_padctl_remote_wake_detected(padctl, phy))
2103                         tegra_phy_xusb_utmi_pad_power_on(phy);
2104         }
2105
2106         for (i = 0; i < tegra->num_phys; i++) {
2107                 if (!tegra->phys[i])
2108                         continue;
2109
2110                 if (tegra_xusb_padctl_remote_wake_detected(padctl, tegra->phys[i]))
2111                         dev_dbg(tegra->dev, "%pOF remote wake detected\n",
2112                                 tegra->phys[i]->dev.of_node);
2113
2114                 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
2115         }
2116 }
2117
2118 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
2119 {
2120         struct tegra_xusb_padctl *padctl = tegra->padctl;
2121         unsigned int i;
2122
2123         for (i = 0; i < tegra->num_phys; i++) {
2124                 if (!tegra->phys[i])
2125                         continue;
2126
2127                 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
2128         }
2129 }
2130
2131 static void tegra_xhci_program_utmi_power_lp0_exit(struct tegra_xusb *tegra)
2132 {
2133         unsigned int i, index_to_usb2;
2134         struct phy *phy;
2135
2136         for (i = 0; i < tegra->soc->num_types; i++) {
2137                 if (strcmp(tegra->soc->phy_types[i].name, "usb2") == 0)
2138                         index_to_usb2 = i;
2139         }
2140
2141         for (i = 0; i < tegra->num_usb_phys; i++) {
2142                 if (!is_host_mode_phy(tegra, index_to_usb2, i))
2143                         continue;
2144
2145                 phy = tegra_xusb_get_phy(tegra, "usb2", i);
2146                 if (tegra->lp0_utmi_pad_mask & BIT(i))
2147                         tegra_phy_xusb_utmi_pad_power_on(phy);
2148                 else
2149                         tegra_phy_xusb_utmi_pad_power_down(phy);
2150         }
2151 }
2152
2153 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime)
2154 {
2155         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2156         struct device *dev = tegra->dev;
2157         bool wakeup = runtime ? true : device_may_wakeup(dev);
2158         unsigned int i;
2159         int err;
2160         u32 usbcmd;
2161         u32 portsc;
2162
2163         dev_dbg(dev, "entering ELPG\n");
2164
2165         usbcmd = readl(&xhci->op_regs->command);
2166         usbcmd &= ~CMD_EIE;
2167         writel(usbcmd, &xhci->op_regs->command);
2168
2169         err = tegra_xusb_check_ports(tegra);
2170         if (err < 0) {
2171                 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
2172                 goto out;
2173         }
2174
2175         for (i = 0; i < tegra->num_usb_phys; i++) {
2176                 if (!xhci->usb2_rhub.ports[i])
2177                         continue;
2178                 portsc = readl(xhci->usb2_rhub.ports[i]->addr);
2179                 tegra->lp0_utmi_pad_mask &= ~BIT(i);
2180                 if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS))
2181                         tegra->lp0_utmi_pad_mask |= BIT(i);
2182         }
2183
2184         err = xhci_suspend(xhci, wakeup);
2185         if (err < 0) {
2186                 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
2187                 goto out;
2188         }
2189
2190         tegra_xusb_save_context(tegra);
2191
2192         if (wakeup)
2193                 tegra_xhci_enable_phy_sleepwalk_wake(tegra);
2194
2195         tegra_xusb_powergate_partitions(tegra);
2196
2197         for (i = 0; i < tegra->num_phys; i++) {
2198                 if (!tegra->phys[i])
2199                         continue;
2200
2201                 phy_power_off(tegra->phys[i]);
2202                 if (!wakeup)
2203                         phy_exit(tegra->phys[i]);
2204         }
2205
2206         tegra_xusb_clk_disable(tegra);
2207
2208 out:
2209         if (!err)
2210                 dev_dbg(tegra->dev, "entering ELPG done\n");
2211         else {
2212                 usbcmd = readl(&xhci->op_regs->command);
2213                 usbcmd |= CMD_EIE;
2214                 writel(usbcmd, &xhci->op_regs->command);
2215
2216                 dev_dbg(tegra->dev, "entering ELPG failed\n");
2217                 pm_runtime_mark_last_busy(tegra->dev);
2218         }
2219
2220         return err;
2221 }
2222
2223 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime)
2224 {
2225         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2226         struct device *dev = tegra->dev;
2227         bool wakeup = runtime ? true : device_may_wakeup(dev);
2228         unsigned int i;
2229         u32 usbcmd;
2230         int err;
2231
2232         dev_dbg(dev, "exiting ELPG\n");
2233         pm_runtime_mark_last_busy(tegra->dev);
2234
2235         err = tegra_xusb_clk_enable(tegra);
2236         if (err < 0) {
2237                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
2238                 goto out;
2239         }
2240
2241         err = tegra_xusb_unpowergate_partitions(tegra);
2242         if (err)
2243                 goto disable_clks;
2244
2245         if (wakeup)
2246                 tegra_xhci_disable_phy_wake(tegra);
2247
2248         for (i = 0; i < tegra->num_phys; i++) {
2249                 if (!tegra->phys[i])
2250                         continue;
2251
2252                 if (!wakeup)
2253                         phy_init(tegra->phys[i]);
2254
2255                 phy_power_on(tegra->phys[i]);
2256         }
2257         if (tegra->suspended)
2258                 tegra_xhci_program_utmi_power_lp0_exit(tegra);
2259
2260         tegra_xusb_config(tegra);
2261         tegra_xusb_restore_context(tegra);
2262
2263         err = tegra_xusb_load_firmware(tegra);
2264         if (err < 0) {
2265                 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
2266                 goto disable_phy;
2267         }
2268
2269         err = __tegra_xusb_enable_firmware_messages(tegra);
2270         if (err < 0) {
2271                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
2272                 goto disable_phy;
2273         }
2274
2275         if (wakeup)
2276                 tegra_xhci_disable_phy_sleepwalk(tegra);
2277
2278         err = xhci_resume(xhci, 0);
2279         if (err < 0) {
2280                 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
2281                 goto disable_phy;
2282         }
2283
2284         usbcmd = readl(&xhci->op_regs->command);
2285         usbcmd |= CMD_EIE;
2286         writel(usbcmd, &xhci->op_regs->command);
2287
2288         goto out;
2289
2290 disable_phy:
2291         for (i = 0; i < tegra->num_phys; i++) {
2292                 if (!tegra->phys[i])
2293                         continue;
2294
2295                 phy_power_off(tegra->phys[i]);
2296                 if (!wakeup)
2297                         phy_exit(tegra->phys[i]);
2298         }
2299         tegra_xusb_powergate_partitions(tegra);
2300 disable_clks:
2301         tegra_xusb_clk_disable(tegra);
2302 out:
2303         if (!err)
2304                 dev_dbg(dev, "exiting ELPG done\n");
2305         else
2306                 dev_dbg(dev, "exiting ELPG failed\n");
2307
2308         return err;
2309 }
2310
2311 static __maybe_unused int tegra_xusb_suspend(struct device *dev)
2312 {
2313         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2314         int err;
2315
2316         synchronize_irq(tegra->mbox_irq);
2317
2318         mutex_lock(&tegra->lock);
2319
2320         if (pm_runtime_suspended(dev)) {
2321                 err = tegra_xusb_exit_elpg(tegra, true);
2322                 if (err < 0)
2323                         goto out;
2324         }
2325
2326         err = tegra_xusb_enter_elpg(tegra, false);
2327         if (err < 0) {
2328                 if (pm_runtime_suspended(dev)) {
2329                         pm_runtime_disable(dev);
2330                         pm_runtime_set_active(dev);
2331                         pm_runtime_enable(dev);
2332                 }
2333
2334                 goto out;
2335         }
2336
2337 out:
2338         if (!err) {
2339                 tegra->suspended = true;
2340                 pm_runtime_disable(dev);
2341
2342                 if (device_may_wakeup(dev)) {
2343                         if (enable_irq_wake(tegra->padctl_irq))
2344                                 dev_err(dev, "failed to enable padctl wakes\n");
2345                 }
2346         }
2347
2348         mutex_unlock(&tegra->lock);
2349
2350         return err;
2351 }
2352
2353 static __maybe_unused int tegra_xusb_resume(struct device *dev)
2354 {
2355         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2356         int err;
2357
2358         mutex_lock(&tegra->lock);
2359
2360         if (!tegra->suspended) {
2361                 mutex_unlock(&tegra->lock);
2362                 return 0;
2363         }
2364
2365         err = tegra_xusb_exit_elpg(tegra, false);
2366         if (err < 0) {
2367                 mutex_unlock(&tegra->lock);
2368                 return err;
2369         }
2370
2371         if (device_may_wakeup(dev)) {
2372                 if (disable_irq_wake(tegra->padctl_irq))
2373                         dev_err(dev, "failed to disable padctl wakes\n");
2374         }
2375         tegra->suspended = false;
2376         mutex_unlock(&tegra->lock);
2377
2378         pm_runtime_set_active(dev);
2379         pm_runtime_enable(dev);
2380
2381         return 0;
2382 }
2383
2384 static __maybe_unused int tegra_xusb_runtime_suspend(struct device *dev)
2385 {
2386         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2387         int ret;
2388
2389         synchronize_irq(tegra->mbox_irq);
2390         mutex_lock(&tegra->lock);
2391         ret = tegra_xusb_enter_elpg(tegra, true);
2392         mutex_unlock(&tegra->lock);
2393
2394         return ret;
2395 }
2396
2397 static __maybe_unused int tegra_xusb_runtime_resume(struct device *dev)
2398 {
2399         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2400         int err;
2401
2402         mutex_lock(&tegra->lock);
2403         err = tegra_xusb_exit_elpg(tegra, true);
2404         mutex_unlock(&tegra->lock);
2405
2406         return err;
2407 }
2408
2409 static const struct dev_pm_ops tegra_xusb_pm_ops = {
2410         SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
2411                            tegra_xusb_runtime_resume, NULL)
2412         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
2413 };
2414
2415 static const char * const tegra124_supply_names[] = {
2416         "avddio-pex",
2417         "dvddio-pex",
2418         "avdd-usb",
2419         "hvdd-usb-ss",
2420 };
2421
2422 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
2423         { .name = "usb3", .num = 2, },
2424         { .name = "usb2", .num = 3, },
2425         { .name = "hsic", .num = 2, },
2426 };
2427
2428 static const unsigned int tegra124_xusb_context_ipfs[] = {
2429         IPFS_XUSB_HOST_MSI_BAR_SZ_0,
2430         IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
2431         IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
2432         IPFS_XUSB_HOST_MSI_VEC0_0,
2433         IPFS_XUSB_HOST_MSI_EN_VEC0_0,
2434         IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
2435         IPFS_XUSB_HOST_INTR_MASK_0,
2436         IPFS_XUSB_HOST_INTR_ENABLE_0,
2437         IPFS_XUSB_HOST_UFPCI_CONFIG_0,
2438         IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
2439         IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
2440 };
2441
2442 static const unsigned int tegra124_xusb_context_fpci[] = {
2443         XUSB_CFG_ARU_CONTEXT_HS_PLS,
2444         XUSB_CFG_ARU_CONTEXT_FS_PLS,
2445         XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
2446         XUSB_CFG_ARU_CONTEXT_HSFS_PP,
2447         XUSB_CFG_ARU_CONTEXT,
2448         XUSB_CFG_AXI_CFG,
2449         XUSB_CFG_24,
2450         XUSB_CFG_16,
2451 };
2452
2453 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
2454         .ipfs = {
2455                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
2456                 .offsets = tegra124_xusb_context_ipfs,
2457         },
2458         .fpci = {
2459                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2460                 .offsets = tegra124_xusb_context_fpci,
2461         },
2462 };
2463
2464 static const struct tegra_xusb_soc_ops tegra124_ops = {
2465         .mbox_reg_readl = &fpci_readl,
2466         .mbox_reg_writel = &fpci_writel,
2467         .csb_reg_readl = &fpci_csb_readl,
2468         .csb_reg_writel = &fpci_csb_writel,
2469 };
2470
2471 static const struct tegra_xusb_soc tegra124_soc = {
2472         .firmware = "nvidia/tegra124/xusb.bin",
2473         .supply_names = tegra124_supply_names,
2474         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
2475         .phy_types = tegra124_phy_types,
2476         .num_types = ARRAY_SIZE(tegra124_phy_types),
2477         .context = &tegra124_xusb_context,
2478         .ports = {
2479                 .usb2 = { .offset = 4, .count = 4, },
2480                 .hsic = { .offset = 6, .count = 2, },
2481                 .usb3 = { .offset = 0, .count = 2, },
2482         },
2483         .scale_ss_clock = true,
2484         .has_ipfs = true,
2485         .otg_reset_sspi = false,
2486         .ops = &tegra124_ops,
2487         .mbox = {
2488                 .cmd = 0xe4,
2489                 .data_in = 0xe8,
2490                 .data_out = 0xec,
2491                 .owner = 0xf0,
2492                 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2493         },
2494 };
2495 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
2496
2497 static const char * const tegra210_supply_names[] = {
2498         "dvddio-pex",
2499         "hvddio-pex",
2500         "avdd-usb",
2501 };
2502
2503 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
2504         { .name = "usb3", .num = 4, },
2505         { .name = "usb2", .num = 4, },
2506         { .name = "hsic", .num = 1, },
2507 };
2508
2509 static const struct tegra_xusb_soc tegra210_soc = {
2510         .firmware = "nvidia/tegra210/xusb.bin",
2511         .supply_names = tegra210_supply_names,
2512         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
2513         .phy_types = tegra210_phy_types,
2514         .num_types = ARRAY_SIZE(tegra210_phy_types),
2515         .context = &tegra124_xusb_context,
2516         .ports = {
2517                 .usb2 = { .offset = 4, .count = 4, },
2518                 .hsic = { .offset = 8, .count = 1, },
2519                 .usb3 = { .offset = 0, .count = 4, },
2520         },
2521         .scale_ss_clock = false,
2522         .has_ipfs = true,
2523         .otg_reset_sspi = true,
2524         .ops = &tegra124_ops,
2525         .mbox = {
2526                 .cmd = 0xe4,
2527                 .data_in = 0xe8,
2528                 .data_out = 0xec,
2529                 .owner = 0xf0,
2530                 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2531         },
2532 };
2533 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
2534
2535 static const char * const tegra186_supply_names[] = {
2536 };
2537 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
2538
2539 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2540         { .name = "usb3", .num = 3, },
2541         { .name = "usb2", .num = 3, },
2542         { .name = "hsic", .num = 1, },
2543 };
2544
2545 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
2546         .fpci = {
2547                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2548                 .offsets = tegra124_xusb_context_fpci,
2549         },
2550 };
2551
2552 static const struct tegra_xusb_soc tegra186_soc = {
2553         .firmware = "nvidia/tegra186/xusb.bin",
2554         .supply_names = tegra186_supply_names,
2555         .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2556         .phy_types = tegra186_phy_types,
2557         .num_types = ARRAY_SIZE(tegra186_phy_types),
2558         .context = &tegra186_xusb_context,
2559         .ports = {
2560                 .usb3 = { .offset = 0, .count = 3, },
2561                 .usb2 = { .offset = 3, .count = 3, },
2562                 .hsic = { .offset = 6, .count = 1, },
2563         },
2564         .scale_ss_clock = false,
2565         .has_ipfs = false,
2566         .otg_reset_sspi = false,
2567         .ops = &tegra124_ops,
2568         .mbox = {
2569                 .cmd = 0xe4,
2570                 .data_in = 0xe8,
2571                 .data_out = 0xec,
2572                 .owner = 0xf0,
2573                 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2574         },
2575         .lpm_support = true,
2576 };
2577
2578 static const char * const tegra194_supply_names[] = {
2579 };
2580
2581 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2582         { .name = "usb3", .num = 4, },
2583         { .name = "usb2", .num = 4, },
2584 };
2585
2586 static const struct tegra_xusb_soc tegra194_soc = {
2587         .firmware = "nvidia/tegra194/xusb.bin",
2588         .supply_names = tegra194_supply_names,
2589         .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2590         .phy_types = tegra194_phy_types,
2591         .num_types = ARRAY_SIZE(tegra194_phy_types),
2592         .context = &tegra186_xusb_context,
2593         .ports = {
2594                 .usb3 = { .offset = 0, .count = 4, },
2595                 .usb2 = { .offset = 4, .count = 4, },
2596         },
2597         .scale_ss_clock = false,
2598         .has_ipfs = false,
2599         .otg_reset_sspi = false,
2600         .ops = &tegra124_ops,
2601         .mbox = {
2602                 .cmd = 0x68,
2603                 .data_in = 0x6c,
2604                 .data_out = 0x70,
2605                 .owner = 0x74,
2606                 .smi_intr = XUSB_CFG_ARU_SMI_INTR,
2607         },
2608         .lpm_support = true,
2609 };
2610 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2611
2612 static const struct tegra_xusb_soc_ops tegra234_ops = {
2613         .mbox_reg_readl = &bar2_readl,
2614         .mbox_reg_writel = &bar2_writel,
2615         .csb_reg_readl = &bar2_csb_readl,
2616         .csb_reg_writel = &bar2_csb_writel,
2617 };
2618
2619 static const struct tegra_xusb_soc tegra234_soc = {
2620         .supply_names = tegra194_supply_names,
2621         .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2622         .phy_types = tegra194_phy_types,
2623         .num_types = ARRAY_SIZE(tegra194_phy_types),
2624         .context = &tegra186_xusb_context,
2625         .ports = {
2626                 .usb3 = { .offset = 0, .count = 4, },
2627                 .usb2 = { .offset = 4, .count = 4, },
2628         },
2629         .scale_ss_clock = false,
2630         .has_ipfs = false,
2631         .otg_reset_sspi = false,
2632         .ops = &tegra234_ops,
2633         .mbox = {
2634                 .cmd = XUSB_BAR2_ARU_MBOX_CMD,
2635                 .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN,
2636                 .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT,
2637                 .owner = XUSB_BAR2_ARU_MBOX_OWNER,
2638                 .smi_intr = XUSB_BAR2_ARU_SMI_INTR,
2639         },
2640         .lpm_support = true,
2641         .has_bar2 = true,
2642 };
2643
2644 static const struct of_device_id tegra_xusb_of_match[] = {
2645         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2646         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2647         { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2648         { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2649         { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc },
2650         { },
2651 };
2652 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2653
2654 static struct platform_driver tegra_xusb_driver = {
2655         .probe = tegra_xusb_probe,
2656         .remove = tegra_xusb_remove,
2657         .driver = {
2658                 .name = "tegra-xusb",
2659                 .pm = &tegra_xusb_pm_ops,
2660                 .of_match_table = tegra_xusb_of_match,
2661         },
2662 };
2663
2664 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2665 {
2666         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2667
2668         xhci->quirks |= XHCI_PLAT;
2669         if (tegra && tegra->soc->lpm_support)
2670                 xhci->quirks |= XHCI_LPM_SUPPORT;
2671 }
2672
2673 static int tegra_xhci_setup(struct usb_hcd *hcd)
2674 {
2675         return xhci_gen_setup(hcd, tegra_xhci_quirks);
2676 }
2677
2678 static int tegra_xhci_hub_control(struct usb_hcd *hcd, u16 type_req, u16 value, u16 index,
2679                                   char *buf, u16 length)
2680 {
2681         struct tegra_xusb *tegra = dev_get_drvdata(hcd->self.controller);
2682         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2683         struct xhci_hub *rhub;
2684         struct xhci_bus_state *bus_state;
2685         int port = (index & 0xff) - 1;
2686         unsigned int i;
2687         struct xhci_port **ports;
2688         u32 portsc;
2689         int ret;
2690         struct phy *phy;
2691
2692         rhub = &xhci->usb2_rhub;
2693         bus_state = &rhub->bus_state;
2694         if (bus_state->resuming_ports && hcd->speed == HCD_USB2) {
2695                 ports = rhub->ports;
2696                 i = rhub->num_ports;
2697                 while (i--) {
2698                         if (!test_bit(i, &bus_state->resuming_ports))
2699                                 continue;
2700                         portsc = readl(ports[i]->addr);
2701                         if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2702                                 tegra_phy_xusb_utmi_pad_power_on(
2703                                         tegra_xusb_get_phy(tegra, "usb2", (int) i));
2704                 }
2705         }
2706
2707         if (hcd->speed == HCD_USB2) {
2708                 phy = tegra_xusb_get_phy(tegra, "usb2", port);
2709                 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_SUSPEND)) {
2710                         if (!index || index > rhub->num_ports)
2711                                 return -EPIPE;
2712                         tegra_phy_xusb_utmi_pad_power_on(phy);
2713                 }
2714                 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_RESET)) {
2715                         if (!index || index > rhub->num_ports)
2716                                 return -EPIPE;
2717                         ports = rhub->ports;
2718                         portsc = readl(ports[port]->addr);
2719                         if (portsc & PORT_CONNECT)
2720                                 tegra_phy_xusb_utmi_pad_power_on(phy);
2721                 }
2722         }
2723
2724         ret = xhci_hub_control(hcd, type_req, value, index, buf, length);
2725         if (ret < 0)
2726                 return ret;
2727
2728         if (hcd->speed == HCD_USB2) {
2729                 /* Use phy where we set previously */
2730                 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_SUSPEND))
2731                         /* We don't suspend the PAD while HNP role swap happens on the OTG port */
2732                         if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable))
2733                                 tegra_phy_xusb_utmi_pad_power_down(phy);
2734
2735                 if ((type_req == ClearPortFeature) && (value == USB_PORT_FEAT_C_CONNECTION)) {
2736                         ports = rhub->ports;
2737                         portsc = readl(ports[port]->addr);
2738                         if (!(portsc & PORT_CONNECT)) {
2739                                 /* We don't suspend the PAD while HNP role swap happens on the OTG
2740                                  * port
2741                                  */
2742                                 if (!((hcd->self.otg_port == (port + 1)) && hcd->self.b_hnp_enable))
2743                                         tegra_phy_xusb_utmi_pad_power_down(phy);
2744                         }
2745                 }
2746                 if ((type_req == SetPortFeature) && (value == USB_PORT_FEAT_TEST))
2747                         tegra_phy_xusb_utmi_pad_power_on(phy);
2748         }
2749
2750         return ret;
2751 }
2752
2753 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2754         .reset = tegra_xhci_setup,
2755         .hub_control = tegra_xhci_hub_control,
2756 };
2757
2758 static int __init tegra_xusb_init(void)
2759 {
2760         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2761
2762         return platform_driver_register(&tegra_xusb_driver);
2763 }
2764 module_init(tegra_xusb_init);
2765
2766 static void __exit tegra_xusb_exit(void)
2767 {
2768         platform_driver_unregister(&tegra_xusb_driver);
2769 }
2770 module_exit(tegra_xusb_exit);
2771
2772 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2773 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2774 MODULE_LICENSE("GPL v2");