2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset > TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
302 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
305 xhci_err(xhci, "Stopped the command ring failed, "
306 "maybe the host is dead\n");
307 xhci->xhc_state |= XHCI_STATE_DYING;
316 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
317 unsigned int slot_id,
318 unsigned int ep_index,
319 unsigned int stream_id)
321 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
322 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
323 unsigned int ep_state = ep->ep_state;
325 /* Don't ring the doorbell for this endpoint if there are pending
326 * cancellations because we don't want to interrupt processing.
327 * We don't want to restart any stream rings if there's a set dequeue
328 * pointer command pending because the device can choose to start any
329 * stream once the endpoint is on the HW schedule.
330 * FIXME - check all the stream rings for pending cancellations.
332 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
333 (ep_state & EP_HALTED))
335 writel(DB_VALUE(ep_index, stream_id), db_addr);
336 /* The CPU has better things to do at this point than wait for a
337 * write-posting flush. It'll get there soon enough.
341 /* Ring the doorbell for any rings with pending URBs */
342 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
343 unsigned int slot_id,
344 unsigned int ep_index)
346 unsigned int stream_id;
347 struct xhci_virt_ep *ep;
349 ep = &xhci->devs[slot_id]->eps[ep_index];
351 /* A ring has pending URBs if its TD list is not empty */
352 if (!(ep->ep_state & EP_HAS_STREAMS)) {
353 if (ep->ring && !(list_empty(&ep->ring->td_list)))
354 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
358 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
360 struct xhci_stream_info *stream_info = ep->stream_info;
361 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
362 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
367 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
368 unsigned int slot_id, unsigned int ep_index,
369 unsigned int stream_id)
371 struct xhci_virt_ep *ep;
373 ep = &xhci->devs[slot_id]->eps[ep_index];
374 /* Common case: no streams */
375 if (!(ep->ep_state & EP_HAS_STREAMS))
378 if (stream_id == 0) {
380 "WARN: Slot ID %u, ep index %u has streams, "
381 "but URB has no stream ID.\n",
386 if (stream_id < ep->stream_info->num_streams)
387 return ep->stream_info->stream_rings[stream_id];
390 "WARN: Slot ID %u, ep index %u has "
391 "stream IDs 1 to %u allocated, "
392 "but stream ID %u is requested.\n",
394 ep->stream_info->num_streams - 1,
399 /* Get the right ring for the given URB.
400 * If the endpoint supports streams, boundary check the URB's stream ID.
401 * If the endpoint doesn't support streams, return the singular endpoint ring.
403 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
406 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
407 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
411 * Move the xHC's endpoint ring dequeue pointer past cur_td.
412 * Record the new state of the xHC's endpoint ring dequeue segment,
413 * dequeue pointer, and new consumer cycle state in state.
414 * Update our internal representation of the ring's dequeue pointer.
416 * We do this in three jumps:
417 * - First we update our new ring state to be the same as when the xHC stopped.
418 * - Then we traverse the ring to find the segment that contains
419 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
420 * any link TRBs with the toggle cycle bit set.
421 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
422 * if we've moved it past a link TRB with the toggle cycle bit set.
424 * Some of the uses of xhci_generic_trb are grotty, but if they're done
425 * with correct __le32 accesses they should work fine. Only users of this are
428 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
429 unsigned int slot_id, unsigned int ep_index,
430 unsigned int stream_id, struct xhci_td *cur_td,
431 struct xhci_dequeue_state *state)
433 struct xhci_virt_device *dev = xhci->devs[slot_id];
434 struct xhci_virt_ep *ep = &dev->eps[ep_index];
435 struct xhci_ring *ep_ring;
436 struct xhci_segment *new_seg;
437 union xhci_trb *new_deq;
440 bool cycle_found = false;
441 bool td_last_trb_found = false;
443 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
444 ep_index, stream_id);
446 xhci_warn(xhci, "WARN can't find new dequeue state "
447 "for invalid stream ID %u.\n",
452 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
453 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
454 "Finding endpoint context");
455 /* 4.6.9 the css flag is written to the stream context for streams */
456 if (ep->ep_state & EP_HAS_STREAMS) {
457 struct xhci_stream_ctx *ctx =
458 &ep->stream_info->stream_ctx_array[stream_id];
459 hw_dequeue = le64_to_cpu(ctx->stream_ring);
461 struct xhci_ep_ctx *ep_ctx
462 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
463 hw_dequeue = le64_to_cpu(ep_ctx->deq);
466 new_seg = ep_ring->deq_seg;
467 new_deq = ep_ring->dequeue;
468 state->new_cycle_state = hw_dequeue & 0x1;
471 * We want to find the pointer, segment and cycle state of the new trb
472 * (the one after current TD's last_trb). We know the cycle state at
473 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
477 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
478 == (dma_addr_t)(hw_dequeue & ~0xf)) {
480 if (td_last_trb_found)
483 if (new_deq == cur_td->last_trb)
484 td_last_trb_found = true;
487 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
488 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
489 state->new_cycle_state ^= 0x1;
491 next_trb(xhci, ep_ring, &new_seg, &new_deq);
493 /* Search wrapped around, bail out */
494 if (new_deq == ep->ring->dequeue) {
495 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
496 state->new_deq_seg = NULL;
497 state->new_deq_ptr = NULL;
501 } while (!cycle_found || !td_last_trb_found);
503 state->new_deq_seg = new_seg;
504 state->new_deq_ptr = new_deq;
506 /* Don't update the ring cycle state for the producer (us). */
507 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
508 "Cycle state = 0x%x", state->new_cycle_state);
510 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
511 "New dequeue segment = %p (virtual)",
513 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
514 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
515 "New dequeue pointer = 0x%llx (DMA)",
516 (unsigned long long) addr);
519 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
520 * (The last TRB actually points to the ring enqueue pointer, which is not part
521 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
523 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
524 struct xhci_td *cur_td, bool flip_cycle)
526 struct xhci_segment *cur_seg;
527 union xhci_trb *cur_trb;
529 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
531 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
532 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
533 /* Unchain any chained Link TRBs, but
534 * leave the pointers intact.
536 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
537 /* Flip the cycle bit (link TRBs can't be the first
541 cur_trb->generic.field[3] ^=
542 cpu_to_le32(TRB_CYCLE);
543 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
544 "Cancel (unchain) link TRB");
545 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
546 "Address = %p (0x%llx dma); "
547 "in seg %p (0x%llx dma)",
549 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
551 (unsigned long long)cur_seg->dma);
553 cur_trb->generic.field[0] = 0;
554 cur_trb->generic.field[1] = 0;
555 cur_trb->generic.field[2] = 0;
556 /* Preserve only the cycle bit of this TRB */
557 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
558 /* Flip the cycle bit except on the first or last TRB */
559 if (flip_cycle && cur_trb != cur_td->first_trb &&
560 cur_trb != cur_td->last_trb)
561 cur_trb->generic.field[3] ^=
562 cpu_to_le32(TRB_CYCLE);
563 cur_trb->generic.field[3] |= cpu_to_le32(
564 TRB_TYPE(TRB_TR_NOOP));
565 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
566 "TRB to noop at offset 0x%llx",
568 xhci_trb_virt_to_dma(cur_seg, cur_trb));
570 if (cur_trb == cur_td->last_trb)
575 static int queue_set_tr_deq(struct xhci_hcd *xhci,
576 struct xhci_command *cmd, int slot_id,
577 unsigned int ep_index, unsigned int stream_id,
578 struct xhci_segment *deq_seg,
579 union xhci_trb *deq_ptr, u32 cycle_state);
581 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
582 struct xhci_command *cmd,
583 unsigned int slot_id, unsigned int ep_index,
584 unsigned int stream_id,
585 struct xhci_dequeue_state *deq_state)
587 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
589 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
590 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
591 "new deq ptr = %p (0x%llx dma), new cycle = %u",
592 deq_state->new_deq_seg,
593 (unsigned long long)deq_state->new_deq_seg->dma,
594 deq_state->new_deq_ptr,
595 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
596 deq_state->new_cycle_state);
597 queue_set_tr_deq(xhci, cmd, slot_id, ep_index, stream_id,
598 deq_state->new_deq_seg,
599 deq_state->new_deq_ptr,
600 (u32) deq_state->new_cycle_state);
601 /* Stop the TD queueing code from ringing the doorbell until
602 * this command completes. The HC won't set the dequeue pointer
603 * if the ring is running, and ringing the doorbell starts the
606 ep->ep_state |= SET_DEQ_PENDING;
609 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
610 struct xhci_virt_ep *ep)
612 ep->ep_state &= ~EP_HALT_PENDING;
613 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
614 * timer is running on another CPU, we don't decrement stop_cmds_pending
615 * (since we didn't successfully stop the watchdog timer).
617 if (del_timer(&ep->stop_cmd_timer))
618 ep->stop_cmds_pending--;
621 /* Must be called with xhci->lock held in interrupt context */
622 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
623 struct xhci_td *cur_td, int status)
627 struct urb_priv *urb_priv;
630 urb_priv = urb->hcpriv;
632 hcd = bus_to_hcd(urb->dev->bus);
634 /* Only giveback urb when this is the last td in urb */
635 if (urb_priv->td_cnt == urb_priv->length) {
636 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
637 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
638 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
639 if (xhci->quirks & XHCI_AMD_PLL_FIX)
640 usb_amd_quirk_pll_enable();
643 usb_hcd_unlink_urb_from_ep(hcd, urb);
645 spin_unlock(&xhci->lock);
646 usb_hcd_giveback_urb(hcd, urb, status);
647 xhci_urb_free_priv(xhci, urb_priv);
648 spin_lock(&xhci->lock);
653 * When we get a command completion for a Stop Endpoint Command, we need to
654 * unlink any cancelled TDs from the ring. There are two ways to do that:
656 * 1. If the HW was in the middle of processing the TD that needs to be
657 * cancelled, then we must move the ring's dequeue pointer past the last TRB
658 * in the TD with a Set Dequeue Pointer Command.
659 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
660 * bit cleared) so that the HW will skip over them.
662 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
663 union xhci_trb *trb, struct xhci_event_cmd *event)
665 unsigned int ep_index;
666 struct xhci_ring *ep_ring;
667 struct xhci_virt_ep *ep;
668 struct list_head *entry;
669 struct xhci_td *cur_td = NULL;
670 struct xhci_td *last_unlinked_td;
672 struct xhci_dequeue_state deq_state;
674 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
675 if (!xhci->devs[slot_id])
676 xhci_warn(xhci, "Stop endpoint command "
677 "completion for disabled slot %u\n",
682 memset(&deq_state, 0, sizeof(deq_state));
683 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
684 ep = &xhci->devs[slot_id]->eps[ep_index];
686 if (list_empty(&ep->cancelled_td_list)) {
687 xhci_stop_watchdog_timer_in_irq(xhci, ep);
688 ep->stopped_td = NULL;
689 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
693 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
694 * We have the xHCI lock, so nothing can modify this list until we drop
695 * it. We're also in the event handler, so we can't get re-interrupted
696 * if another Stop Endpoint command completes
698 list_for_each(entry, &ep->cancelled_td_list) {
699 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
700 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
701 "Removing canceled TD starting at 0x%llx (dma).",
702 (unsigned long long)xhci_trb_virt_to_dma(
703 cur_td->start_seg, cur_td->first_trb));
704 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
706 /* This shouldn't happen unless a driver is mucking
707 * with the stream ID after submission. This will
708 * leave the TD on the hardware ring, and the hardware
709 * will try to execute it, and may access a buffer
710 * that has already been freed. In the best case, the
711 * hardware will execute it, and the event handler will
712 * ignore the completion event for that TD, since it was
713 * removed from the td_list for that endpoint. In
714 * short, don't muck with the stream ID after
717 xhci_warn(xhci, "WARN Cancelled URB %p "
718 "has invalid stream ID %u.\n",
720 cur_td->urb->stream_id);
721 goto remove_finished_td;
724 * If we stopped on the TD we need to cancel, then we have to
725 * move the xHC endpoint ring dequeue pointer past this TD.
727 if (cur_td == ep->stopped_td)
728 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
729 cur_td->urb->stream_id,
732 td_to_noop(xhci, ep_ring, cur_td, false);
735 * The event handler won't see a completion for this TD anymore,
736 * so remove it from the endpoint ring's TD list. Keep it in
737 * the cancelled TD list for URB completion later.
739 list_del_init(&cur_td->td_list);
741 last_unlinked_td = cur_td;
742 xhci_stop_watchdog_timer_in_irq(xhci, ep);
744 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
745 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
746 struct xhci_command *command;
747 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
748 xhci_queue_new_dequeue_state(xhci, command,
750 ep->stopped_td->urb->stream_id,
752 xhci_ring_cmd_db(xhci);
754 /* Otherwise ring the doorbell(s) to restart queued transfers */
755 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
758 /* Clear stopped_td if endpoint is not halted */
759 if (!(ep->ep_state & EP_HALTED))
760 ep->stopped_td = NULL;
763 * Drop the lock and complete the URBs in the cancelled TD list.
764 * New TDs to be cancelled might be added to the end of the list before
765 * we can complete all the URBs for the TDs we already unlinked.
766 * So stop when we've completed the URB for the last TD we unlinked.
769 cur_td = list_entry(ep->cancelled_td_list.next,
770 struct xhci_td, cancelled_td_list);
771 list_del_init(&cur_td->cancelled_td_list);
773 /* Clean up the cancelled URB */
774 /* Doesn't matter what we pass for status, since the core will
775 * just overwrite it (because the URB has been unlinked).
777 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
779 /* Stop processing the cancelled list if the watchdog timer is
782 if (xhci->xhc_state & XHCI_STATE_DYING)
784 } while (cur_td != last_unlinked_td);
786 /* Return to the event handler with xhci->lock re-acquired */
789 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
791 struct xhci_td *cur_td;
793 while (!list_empty(&ring->td_list)) {
794 cur_td = list_first_entry(&ring->td_list,
795 struct xhci_td, td_list);
796 list_del_init(&cur_td->td_list);
797 if (!list_empty(&cur_td->cancelled_td_list))
798 list_del_init(&cur_td->cancelled_td_list);
799 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
803 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
804 int slot_id, int ep_index)
806 struct xhci_td *cur_td;
807 struct xhci_virt_ep *ep;
808 struct xhci_ring *ring;
810 ep = &xhci->devs[slot_id]->eps[ep_index];
811 if ((ep->ep_state & EP_HAS_STREAMS) ||
812 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
815 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
817 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
818 "Killing URBs for slot ID %u, ep index %u, stream %u",
819 slot_id, ep_index, stream_id + 1);
820 xhci_kill_ring_urbs(xhci,
821 ep->stream_info->stream_rings[stream_id]);
827 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
828 "Killing URBs for slot ID %u, ep index %u",
830 xhci_kill_ring_urbs(xhci, ring);
832 while (!list_empty(&ep->cancelled_td_list)) {
833 cur_td = list_first_entry(&ep->cancelled_td_list,
834 struct xhci_td, cancelled_td_list);
835 list_del_init(&cur_td->cancelled_td_list);
836 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
840 /* Watchdog timer function for when a stop endpoint command fails to complete.
841 * In this case, we assume the host controller is broken or dying or dead. The
842 * host may still be completing some other events, so we have to be careful to
843 * let the event ring handler and the URB dequeueing/enqueueing functions know
844 * through xhci->state.
846 * The timer may also fire if the host takes a very long time to respond to the
847 * command, and the stop endpoint command completion handler cannot delete the
848 * timer before the timer function is called. Another endpoint cancellation may
849 * sneak in before the timer function can grab the lock, and that may queue
850 * another stop endpoint command and add the timer back. So we cannot use a
851 * simple flag to say whether there is a pending stop endpoint command for a
852 * particular endpoint.
854 * Instead we use a combination of that flag and a counter for the number of
855 * pending stop endpoint commands. If the timer is the tail end of the last
856 * stop endpoint command, and the endpoint's command is still pending, we assume
859 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
861 struct xhci_hcd *xhci;
862 struct xhci_virt_ep *ep;
866 ep = (struct xhci_virt_ep *) arg;
869 spin_lock_irqsave(&xhci->lock, flags);
871 ep->stop_cmds_pending--;
872 if (xhci->xhc_state & XHCI_STATE_DYING) {
873 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
874 "Stop EP timer ran, but another timer marked "
875 "xHCI as DYING, exiting.");
876 spin_unlock_irqrestore(&xhci->lock, flags);
879 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
880 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
881 "Stop EP timer ran, but no command pending, "
883 spin_unlock_irqrestore(&xhci->lock, flags);
887 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
888 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
889 /* Oops, HC is dead or dying or at least not responding to the stop
892 xhci->xhc_state |= XHCI_STATE_DYING;
893 /* Disable interrupts from the host controller and start halting it */
895 spin_unlock_irqrestore(&xhci->lock, flags);
897 ret = xhci_halt(xhci);
899 spin_lock_irqsave(&xhci->lock, flags);
901 /* This is bad; the host is not responding to commands and it's
902 * not allowing itself to be halted. At least interrupts are
903 * disabled. If we call usb_hc_died(), it will attempt to
904 * disconnect all device drivers under this host. Those
905 * disconnect() methods will wait for all URBs to be unlinked,
906 * so we must complete them.
908 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
909 xhci_warn(xhci, "Completing active URBs anyway.\n");
910 /* We could turn all TDs on the rings to no-ops. This won't
911 * help if the host has cached part of the ring, and is slow if
912 * we want to preserve the cycle bit. Skip it and hope the host
913 * doesn't touch the memory.
916 for (i = 0; i < MAX_HC_SLOTS; i++) {
919 for (j = 0; j < 31; j++)
920 xhci_kill_endpoint_urbs(xhci, i, j);
922 spin_unlock_irqrestore(&xhci->lock, flags);
923 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
924 "Calling usb_hc_died()");
925 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
926 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
927 "xHCI host controller is dead.");
931 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
932 struct xhci_virt_device *dev,
933 struct xhci_ring *ep_ring,
934 unsigned int ep_index)
936 union xhci_trb *dequeue_temp;
937 int num_trbs_free_temp;
940 num_trbs_free_temp = ep_ring->num_trbs_free;
941 dequeue_temp = ep_ring->dequeue;
943 /* If we get two back-to-back stalls, and the first stalled transfer
944 * ends just before a link TRB, the dequeue pointer will be left on
945 * the link TRB by the code in the while loop. So we have to update
946 * the dequeue pointer one segment further, or we'll jump off
947 * the segment into la-la-land.
949 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
950 ep_ring->deq_seg = ep_ring->deq_seg->next;
951 ep_ring->dequeue = ep_ring->deq_seg->trbs;
954 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
955 /* We have more usable TRBs */
956 ep_ring->num_trbs_free++;
958 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
960 if (ep_ring->dequeue ==
961 dev->eps[ep_index].queued_deq_ptr)
963 ep_ring->deq_seg = ep_ring->deq_seg->next;
964 ep_ring->dequeue = ep_ring->deq_seg->trbs;
966 if (ep_ring->dequeue == dequeue_temp) {
973 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
974 ep_ring->num_trbs_free = num_trbs_free_temp;
979 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
980 * we need to clear the set deq pending flag in the endpoint ring state, so that
981 * the TD queueing code can ring the doorbell again. We also need to ring the
982 * endpoint doorbell to restart the ring, but only if there aren't more
983 * cancellations pending.
985 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
986 union xhci_trb *trb, u32 cmd_comp_code)
988 unsigned int ep_index;
989 unsigned int stream_id;
990 struct xhci_ring *ep_ring;
991 struct xhci_virt_device *dev;
992 struct xhci_virt_ep *ep;
993 struct xhci_ep_ctx *ep_ctx;
994 struct xhci_slot_ctx *slot_ctx;
996 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
997 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
998 dev = xhci->devs[slot_id];
999 ep = &dev->eps[ep_index];
1001 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1003 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1005 /* XXX: Harmless??? */
1006 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1010 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1011 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1013 if (cmd_comp_code != COMP_SUCCESS) {
1014 unsigned int ep_state;
1015 unsigned int slot_state;
1017 switch (cmd_comp_code) {
1019 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1021 case COMP_CTX_STATE:
1022 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1023 ep_state = le32_to_cpu(ep_ctx->ep_info);
1024 ep_state &= EP_STATE_MASK;
1025 slot_state = le32_to_cpu(slot_ctx->dev_state);
1026 slot_state = GET_SLOT_STATE(slot_state);
1027 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1028 "Slot state = %u, EP state = %u",
1029 slot_state, ep_state);
1032 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1036 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1040 /* OK what do we do now? The endpoint state is hosed, and we
1041 * should never get to this point if the synchronization between
1042 * queueing, and endpoint state are correct. This might happen
1043 * if the device gets disconnected after we've finished
1044 * cancelling URBs, which might not be an error...
1048 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1049 if (ep->ep_state & EP_HAS_STREAMS) {
1050 struct xhci_stream_ctx *ctx =
1051 &ep->stream_info->stream_ctx_array[stream_id];
1052 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1054 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1056 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1057 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1058 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1059 ep->queued_deq_ptr) == deq) {
1060 /* Update the ring's dequeue segment and dequeue pointer
1061 * to reflect the new position.
1063 update_ring_for_set_deq_completion(xhci, dev,
1066 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1067 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1068 ep->queued_deq_seg, ep->queued_deq_ptr);
1072 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1073 dev->eps[ep_index].queued_deq_seg = NULL;
1074 dev->eps[ep_index].queued_deq_ptr = NULL;
1075 /* Restart any rings with pending URBs */
1076 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1079 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1080 union xhci_trb *trb, u32 cmd_comp_code)
1082 unsigned int ep_index;
1084 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1085 /* This command will only fail if the endpoint wasn't halted,
1086 * but we don't care.
1088 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1089 "Ignoring reset ep completion code of %u", cmd_comp_code);
1091 /* HW with the reset endpoint quirk needs to have a configure endpoint
1092 * command complete before the endpoint can be used. Queue that here
1093 * because the HW can't handle two commands being queued in a row.
1095 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1096 struct xhci_command *command;
1097 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1099 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1102 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1103 "Queueing configure endpoint command");
1104 xhci_queue_configure_endpoint(xhci, command,
1105 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1107 xhci_ring_cmd_db(xhci);
1109 /* Clear our internal halted state and restart the ring(s) */
1110 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1111 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1115 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1118 if (cmd_comp_code == COMP_SUCCESS)
1119 xhci->slot_id = slot_id;
1124 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1126 struct xhci_virt_device *virt_dev;
1128 virt_dev = xhci->devs[slot_id];
1131 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1132 /* Delete default control endpoint resources */
1133 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1134 xhci_free_virt_device(xhci, slot_id);
1137 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1138 struct xhci_event_cmd *event, u32 cmd_comp_code)
1140 struct xhci_virt_device *virt_dev;
1141 struct xhci_input_control_ctx *ctrl_ctx;
1142 unsigned int ep_index;
1143 unsigned int ep_state;
1144 u32 add_flags, drop_flags;
1147 * Configure endpoint commands can come from the USB core
1148 * configuration or alt setting changes, or because the HW
1149 * needed an extra configure endpoint command after a reset
1150 * endpoint command or streams were being configured.
1151 * If the command was for a halted endpoint, the xHCI driver
1152 * is not waiting on the configure endpoint command.
1154 virt_dev = xhci->devs[slot_id];
1155 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1157 xhci_warn(xhci, "Could not get input context, bad type.\n");
1161 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1162 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1163 /* Input ctx add_flags are the endpoint index plus one */
1164 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1166 /* A usb_set_interface() call directly after clearing a halted
1167 * condition may race on this quirky hardware. Not worth
1168 * worrying about, since this is prototype hardware. Not sure
1169 * if this will work for streams, but streams support was
1170 * untested on this prototype.
1172 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1173 ep_index != (unsigned int) -1 &&
1174 add_flags - SLOT_FLAG == drop_flags) {
1175 ep_state = virt_dev->eps[ep_index].ep_state;
1176 if (!(ep_state & EP_HALTED))
1178 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1179 "Completed config ep cmd - "
1180 "last ep index = %d, state = %d",
1181 ep_index, ep_state);
1182 /* Clear internal halted state and restart ring(s) */
1183 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1184 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1190 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1191 struct xhci_event_cmd *event)
1193 xhci_dbg(xhci, "Completed reset device command.\n");
1194 if (!xhci->devs[slot_id])
1195 xhci_warn(xhci, "Reset device command completion "
1196 "for disabled slot %u\n", slot_id);
1199 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1200 struct xhci_event_cmd *event)
1202 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1203 xhci->error_bitmask |= 1 << 6;
1206 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1207 "NEC firmware version %2x.%02x",
1208 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1209 NEC_FW_MINOR(le32_to_cpu(event->status)));
1212 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1214 list_del(&cmd->cmd_list);
1216 if (cmd->completion) {
1217 cmd->status = status;
1218 complete(cmd->completion);
1224 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1226 struct xhci_command *cur_cmd, *tmp_cmd;
1227 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1228 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1232 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1233 * If there are other commands waiting then restart the ring and kick the timer.
1234 * This must be called with command ring stopped and xhci->lock held.
1236 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1237 struct xhci_command *cur_cmd)
1239 struct xhci_command *i_cmd, *tmp_cmd;
1242 /* Turn all aborted commands in list to no-ops, then restart */
1243 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1246 if (i_cmd->status != COMP_CMD_ABORT)
1249 i_cmd->status = COMP_CMD_STOP;
1251 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1252 i_cmd->command_trb);
1253 /* get cycle state from the original cmd trb */
1254 cycle_state = le32_to_cpu(
1255 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1256 /* modify the command trb to no-op command */
1257 i_cmd->command_trb->generic.field[0] = 0;
1258 i_cmd->command_trb->generic.field[1] = 0;
1259 i_cmd->command_trb->generic.field[2] = 0;
1260 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1261 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1264 * caller waiting for completion is called when command
1265 * completion event is received for these no-op commands
1269 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1271 /* ring command ring doorbell to restart the command ring */
1272 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1273 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1274 xhci->current_cmd = cur_cmd;
1275 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1276 xhci_ring_cmd_db(xhci);
1282 void xhci_handle_command_timeout(unsigned long data)
1284 struct xhci_hcd *xhci;
1286 unsigned long flags;
1288 struct xhci_command *cur_cmd = NULL;
1289 xhci = (struct xhci_hcd *) data;
1291 /* mark this command to be cancelled */
1292 spin_lock_irqsave(&xhci->lock, flags);
1293 if (xhci->current_cmd) {
1294 cur_cmd = xhci->current_cmd;
1295 cur_cmd->status = COMP_CMD_ABORT;
1299 /* Make sure command ring is running before aborting it */
1300 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1301 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1302 (hw_ring_state & CMD_RING_RUNNING)) {
1304 spin_unlock_irqrestore(&xhci->lock, flags);
1305 xhci_dbg(xhci, "Command timeout\n");
1306 ret = xhci_abort_cmd_ring(xhci);
1307 if (unlikely(ret == -ESHUTDOWN)) {
1308 xhci_err(xhci, "Abort command ring failed\n");
1309 xhci_cleanup_command_queue(xhci);
1310 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1311 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1315 /* command timeout on stopped ring, ring can't be aborted */
1316 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1317 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1318 spin_unlock_irqrestore(&xhci->lock, flags);
1322 static void handle_cmd_completion(struct xhci_hcd *xhci,
1323 struct xhci_event_cmd *event)
1325 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1327 dma_addr_t cmd_dequeue_dma;
1329 union xhci_trb *cmd_trb;
1330 struct xhci_command *cmd;
1333 cmd_dma = le64_to_cpu(event->cmd_trb);
1334 cmd_trb = xhci->cmd_ring->dequeue;
1335 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1337 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1338 if (cmd_dequeue_dma == 0) {
1339 xhci->error_bitmask |= 1 << 4;
1342 /* Does the DMA address match our internal dequeue pointer address? */
1343 if (cmd_dma != (u64) cmd_dequeue_dma) {
1344 xhci->error_bitmask |= 1 << 5;
1348 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1350 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1352 "Command completion event does not match command\n");
1356 del_timer(&xhci->cmd_timer);
1358 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1360 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1362 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1363 if (cmd_comp_code == COMP_CMD_STOP) {
1364 xhci_handle_stopped_cmd_ring(xhci, cmd);
1368 * Host aborted the command ring, check if the current command was
1369 * supposed to be aborted, otherwise continue normally.
1370 * The command ring is stopped now, but the xHC will issue a Command
1371 * Ring Stopped event which will cause us to restart it.
1373 if (cmd_comp_code == COMP_CMD_ABORT) {
1374 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1375 if (cmd->status == COMP_CMD_ABORT)
1379 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1381 case TRB_ENABLE_SLOT:
1382 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1384 case TRB_DISABLE_SLOT:
1385 xhci_handle_cmd_disable_slot(xhci, slot_id);
1388 if (!cmd->completion)
1389 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1392 case TRB_EVAL_CONTEXT:
1397 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1398 le32_to_cpu(cmd_trb->generic.field[3])));
1399 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1402 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1403 le32_to_cpu(cmd_trb->generic.field[3])));
1404 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1407 /* Is this an aborted command turned to NO-OP? */
1408 if (cmd->status == COMP_CMD_STOP)
1409 cmd_comp_code = COMP_CMD_STOP;
1412 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1413 le32_to_cpu(cmd_trb->generic.field[3])));
1414 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1417 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1418 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1420 slot_id = TRB_TO_SLOT_ID(
1421 le32_to_cpu(cmd_trb->generic.field[3]));
1422 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1424 case TRB_NEC_GET_FW:
1425 xhci_handle_cmd_nec_get_fw(xhci, event);
1428 /* Skip over unknown commands on the event ring */
1429 xhci->error_bitmask |= 1 << 6;
1433 /* restart timer if this wasn't the last command */
1434 if (cmd->cmd_list.next != &xhci->cmd_list) {
1435 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1436 struct xhci_command, cmd_list);
1437 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1441 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1443 inc_deq(xhci, xhci->cmd_ring);
1446 static void handle_vendor_event(struct xhci_hcd *xhci,
1447 union xhci_trb *event)
1451 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1452 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1453 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1454 handle_cmd_completion(xhci, &event->event_cmd);
1457 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1458 * port registers -- USB 3.0 and USB 2.0).
1460 * Returns a zero-based port number, which is suitable for indexing into each of
1461 * the split roothubs' port arrays and bus state arrays.
1462 * Add one to it in order to call xhci_find_slot_id_by_port.
1464 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1465 struct xhci_hcd *xhci, u32 port_id)
1468 unsigned int num_similar_speed_ports = 0;
1470 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1471 * and usb2_ports are 0-based indexes. Count the number of similar
1472 * speed ports, up to 1 port before this port.
1474 for (i = 0; i < (port_id - 1); i++) {
1475 u8 port_speed = xhci->port_array[i];
1478 * Skip ports that don't have known speeds, or have duplicate
1479 * Extended Capabilities port speed entries.
1481 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1485 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1486 * 1.1 ports are under the USB 2.0 hub. If the port speed
1487 * matches the device speed, it's a similar speed port.
1489 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1490 num_similar_speed_ports++;
1492 return num_similar_speed_ports;
1495 static void handle_device_notification(struct xhci_hcd *xhci,
1496 union xhci_trb *event)
1499 struct usb_device *udev;
1501 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1502 if (!xhci->devs[slot_id]) {
1503 xhci_warn(xhci, "Device Notification event for "
1504 "unused slot %u\n", slot_id);
1508 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1510 udev = xhci->devs[slot_id]->udev;
1511 if (udev && udev->parent)
1512 usb_wakeup_notification(udev->parent, udev->portnum);
1515 static void handle_port_status(struct xhci_hcd *xhci,
1516 union xhci_trb *event)
1518 struct usb_hcd *hcd;
1523 unsigned int faked_port_index;
1525 struct xhci_bus_state *bus_state;
1526 __le32 __iomem **port_array;
1527 bool bogus_port_status = false;
1529 /* Port status change events always have a successful completion code */
1530 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1531 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1532 xhci->error_bitmask |= 1 << 8;
1534 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1535 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1537 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1538 if ((port_id <= 0) || (port_id > max_ports)) {
1539 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1540 inc_deq(xhci, xhci->event_ring);
1544 /* Figure out which usb_hcd this port is attached to:
1545 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1547 major_revision = xhci->port_array[port_id - 1];
1549 /* Find the right roothub. */
1550 hcd = xhci_to_hcd(xhci);
1551 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1552 hcd = xhci->shared_hcd;
1554 if (major_revision == 0) {
1555 xhci_warn(xhci, "Event for port %u not in "
1556 "Extended Capabilities, ignoring.\n",
1558 bogus_port_status = true;
1561 if (major_revision == DUPLICATE_ENTRY) {
1562 xhci_warn(xhci, "Event for port %u duplicated in"
1563 "Extended Capabilities, ignoring.\n",
1565 bogus_port_status = true;
1570 * Hardware port IDs reported by a Port Status Change Event include USB
1571 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1572 * resume event, but we first need to translate the hardware port ID
1573 * into the index into the ports on the correct split roothub, and the
1574 * correct bus_state structure.
1576 bus_state = &xhci->bus_state[hcd_index(hcd)];
1577 if (hcd->speed == HCD_USB3)
1578 port_array = xhci->usb3_ports;
1580 port_array = xhci->usb2_ports;
1581 /* Find the faked port hub number */
1582 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1585 temp = readl(port_array[faked_port_index]);
1586 if (hcd->state == HC_STATE_SUSPENDED) {
1587 xhci_dbg(xhci, "resume root hub\n");
1588 usb_hcd_resume_root_hub(hcd);
1591 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1592 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1594 temp1 = readl(&xhci->op_regs->command);
1595 if (!(temp1 & CMD_RUN)) {
1596 xhci_warn(xhci, "xHC is not running.\n");
1600 if (DEV_SUPERSPEED(temp)) {
1601 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1602 /* Set a flag to say the port signaled remote wakeup,
1603 * so we can tell the difference between the end of
1604 * device and host initiated resume.
1606 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1607 xhci_test_and_clear_bit(xhci, port_array,
1608 faked_port_index, PORT_PLC);
1609 xhci_set_link_state(xhci, port_array, faked_port_index,
1611 /* Need to wait until the next link state change
1612 * indicates the device is actually in U0.
1614 bogus_port_status = true;
1617 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1618 bus_state->resume_done[faked_port_index] = jiffies +
1619 msecs_to_jiffies(20);
1620 set_bit(faked_port_index, &bus_state->resuming_ports);
1621 mod_timer(&hcd->rh_timer,
1622 bus_state->resume_done[faked_port_index]);
1623 /* Do the rest in GetPortStatus */
1627 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1628 DEV_SUPERSPEED(temp)) {
1629 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1630 /* We've just brought the device into U0 through either the
1631 * Resume state after a device remote wakeup, or through the
1632 * U3Exit state after a host-initiated resume. If it's a device
1633 * initiated remote wake, don't pass up the link state change,
1634 * so the roothub behavior is consistent with external
1635 * USB 3.0 hub behavior.
1637 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1638 faked_port_index + 1);
1639 if (slot_id && xhci->devs[slot_id])
1640 xhci_ring_device(xhci, slot_id);
1641 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1642 bus_state->port_remote_wakeup &=
1643 ~(1 << faked_port_index);
1644 xhci_test_and_clear_bit(xhci, port_array,
1645 faked_port_index, PORT_PLC);
1646 usb_wakeup_notification(hcd->self.root_hub,
1647 faked_port_index + 1);
1648 bogus_port_status = true;
1654 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1655 * RExit to a disconnect state). If so, let the the driver know it's
1656 * out of the RExit state.
1658 if (!DEV_SUPERSPEED(temp) &&
1659 test_and_clear_bit(faked_port_index,
1660 &bus_state->rexit_ports)) {
1661 complete(&bus_state->rexit_done[faked_port_index]);
1662 bogus_port_status = true;
1666 if (hcd->speed != HCD_USB3)
1667 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1671 /* Update event ring dequeue pointer before dropping the lock */
1672 inc_deq(xhci, xhci->event_ring);
1674 /* Don't make the USB core poll the roothub if we got a bad port status
1675 * change event. Besides, at that point we can't tell which roothub
1676 * (USB 2.0 or USB 3.0) to kick.
1678 if (bogus_port_status)
1682 * xHCI port-status-change events occur when the "or" of all the
1683 * status-change bits in the portsc register changes from 0 to 1.
1684 * New status changes won't cause an event if any other change
1685 * bits are still set. When an event occurs, switch over to
1686 * polling to avoid losing status changes.
1688 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1689 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1690 spin_unlock(&xhci->lock);
1691 /* Pass this up to the core */
1692 usb_hcd_poll_rh_status(hcd);
1693 spin_lock(&xhci->lock);
1697 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1698 * at end_trb, which may be in another segment. If the suspect DMA address is a
1699 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1702 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1703 union xhci_trb *start_trb,
1704 union xhci_trb *end_trb,
1705 dma_addr_t suspect_dma)
1707 dma_addr_t start_dma;
1708 dma_addr_t end_seg_dma;
1709 dma_addr_t end_trb_dma;
1710 struct xhci_segment *cur_seg;
1712 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1713 cur_seg = start_seg;
1718 /* We may get an event for a Link TRB in the middle of a TD */
1719 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1720 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1721 /* If the end TRB isn't in this segment, this is set to 0 */
1722 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1724 if (end_trb_dma > 0) {
1725 /* The end TRB is in this segment, so suspect should be here */
1726 if (start_dma <= end_trb_dma) {
1727 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1730 /* Case for one segment with
1731 * a TD wrapped around to the top
1733 if ((suspect_dma >= start_dma &&
1734 suspect_dma <= end_seg_dma) ||
1735 (suspect_dma >= cur_seg->dma &&
1736 suspect_dma <= end_trb_dma))
1741 /* Might still be somewhere in this segment */
1742 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1745 cur_seg = cur_seg->next;
1746 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1747 } while (cur_seg != start_seg);
1752 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1753 unsigned int slot_id, unsigned int ep_index,
1754 unsigned int stream_id,
1755 struct xhci_td *td, union xhci_trb *event_trb)
1757 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1758 struct xhci_command *command;
1759 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1763 ep->ep_state |= EP_HALTED;
1764 ep->stopped_td = td;
1765 ep->stopped_stream = stream_id;
1767 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1768 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1770 ep->stopped_td = NULL;
1771 ep->stopped_stream = 0;
1773 xhci_ring_cmd_db(xhci);
1776 /* Check if an error has halted the endpoint ring. The class driver will
1777 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1778 * However, a babble and other errors also halt the endpoint ring, and the class
1779 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1780 * Ring Dequeue Pointer command manually.
1782 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1783 struct xhci_ep_ctx *ep_ctx,
1784 unsigned int trb_comp_code)
1786 /* TRB completion codes that may require a manual halt cleanup */
1787 if (trb_comp_code == COMP_TX_ERR ||
1788 trb_comp_code == COMP_BABBLE ||
1789 trb_comp_code == COMP_SPLIT_ERR)
1790 /* The 0.96 spec says a babbling control endpoint
1791 * is not halted. The 0.96 spec says it is. Some HW
1792 * claims to be 0.95 compliant, but it halts the control
1793 * endpoint anyway. Check if a babble halted the
1796 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1797 cpu_to_le32(EP_STATE_HALTED))
1803 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1805 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1806 /* Vendor defined "informational" completion code,
1807 * treat as not-an-error.
1809 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1811 xhci_dbg(xhci, "Treating code as success.\n");
1818 * Finish the td processing, remove the td from td list;
1819 * Return 1 if the urb can be given back.
1821 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1822 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1823 struct xhci_virt_ep *ep, int *status, bool skip)
1825 struct xhci_virt_device *xdev;
1826 struct xhci_ring *ep_ring;
1827 unsigned int slot_id;
1829 struct urb *urb = NULL;
1830 struct xhci_ep_ctx *ep_ctx;
1832 struct urb_priv *urb_priv;
1835 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1836 xdev = xhci->devs[slot_id];
1837 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1838 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1839 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1840 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1845 if (trb_comp_code == COMP_STOP_INVAL ||
1846 trb_comp_code == COMP_STOP) {
1847 /* The Endpoint Stop Command completion will take care of any
1848 * stopped TDs. A stopped TD may be restarted, so don't update
1849 * the ring dequeue pointer or take this TD off any lists yet.
1851 ep->stopped_td = td;
1854 if (trb_comp_code == COMP_STALL) {
1855 /* The transfer is completed from the driver's
1856 * perspective, but we need to issue a set dequeue
1857 * command for this stalled endpoint to move the dequeue
1858 * pointer past the TD. We can't do that here because
1859 * the halt condition must be cleared first. Let the
1860 * USB class driver clear the stall later.
1862 ep->stopped_td = td;
1863 ep->stopped_stream = ep_ring->stream_id;
1864 } else if (xhci_requires_manual_halt_cleanup(xhci,
1865 ep_ctx, trb_comp_code)) {
1866 /* Other types of errors halt the endpoint, but the
1867 * class driver doesn't call usb_reset_endpoint() unless
1868 * the error is -EPIPE. Clear the halted status in the
1869 * xHCI hardware manually.
1871 xhci_cleanup_halted_endpoint(xhci,
1872 slot_id, ep_index, ep_ring->stream_id,
1875 /* Update ring dequeue pointer */
1876 while (ep_ring->dequeue != td->last_trb)
1877 inc_deq(xhci, ep_ring);
1878 inc_deq(xhci, ep_ring);
1882 /* Clean up the endpoint's TD list */
1884 urb_priv = urb->hcpriv;
1886 /* Do one last check of the actual transfer length.
1887 * If the host controller said we transferred more data than
1888 * the buffer length, urb->actual_length will be a very big
1889 * number (since it's unsigned). Play it safe and say we didn't
1890 * transfer anything.
1892 if (urb->actual_length > urb->transfer_buffer_length) {
1893 xhci_warn(xhci, "URB transfer length is wrong, "
1894 "xHC issue? req. len = %u, "
1896 urb->transfer_buffer_length,
1897 urb->actual_length);
1898 urb->actual_length = 0;
1899 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1900 *status = -EREMOTEIO;
1904 list_del_init(&td->td_list);
1905 /* Was this TD slated to be cancelled but completed anyway? */
1906 if (!list_empty(&td->cancelled_td_list))
1907 list_del_init(&td->cancelled_td_list);
1910 /* Giveback the urb when all the tds are completed */
1911 if (urb_priv->td_cnt == urb_priv->length) {
1913 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1914 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1915 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1917 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1918 usb_amd_quirk_pll_enable();
1928 * Process control tds, update urb status and actual_length.
1930 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1931 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1932 struct xhci_virt_ep *ep, int *status)
1934 struct xhci_virt_device *xdev;
1935 struct xhci_ring *ep_ring;
1936 unsigned int slot_id;
1938 struct xhci_ep_ctx *ep_ctx;
1941 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1942 xdev = xhci->devs[slot_id];
1943 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1944 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1945 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1946 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1948 switch (trb_comp_code) {
1950 if (event_trb == ep_ring->dequeue) {
1951 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1952 "without IOC set??\n");
1953 *status = -ESHUTDOWN;
1954 } else if (event_trb != td->last_trb) {
1955 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1956 "without IOC set??\n");
1957 *status = -ESHUTDOWN;
1963 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1964 *status = -EREMOTEIO;
1968 case COMP_STOP_INVAL:
1970 return finish_td(xhci, td, event_trb, event, ep, status, false);
1972 if (!xhci_requires_manual_halt_cleanup(xhci,
1973 ep_ctx, trb_comp_code))
1975 xhci_dbg(xhci, "TRB error code %u, "
1976 "halted endpoint index = %u\n",
1977 trb_comp_code, ep_index);
1978 /* else fall through */
1980 /* Did we transfer part of the data (middle) phase? */
1981 if (event_trb != ep_ring->dequeue &&
1982 event_trb != td->last_trb)
1983 td->urb->actual_length =
1984 td->urb->transfer_buffer_length -
1985 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1987 td->urb->actual_length = 0;
1989 xhci_cleanup_halted_endpoint(xhci,
1990 slot_id, ep_index, 0, td, event_trb);
1991 return finish_td(xhci, td, event_trb, event, ep, status, true);
1994 * Did we transfer any data, despite the errors that might have
1995 * happened? I.e. did we get past the setup stage?
1997 if (event_trb != ep_ring->dequeue) {
1998 /* The event was for the status stage */
1999 if (event_trb == td->last_trb) {
2000 if (td->urb->actual_length != 0) {
2001 /* Don't overwrite a previously set error code
2003 if ((*status == -EINPROGRESS || *status == 0) &&
2004 (td->urb->transfer_flags
2005 & URB_SHORT_NOT_OK))
2006 /* Did we already see a short data
2008 *status = -EREMOTEIO;
2010 td->urb->actual_length =
2011 td->urb->transfer_buffer_length;
2014 /* Maybe the event was for the data stage? */
2015 td->urb->actual_length =
2016 td->urb->transfer_buffer_length -
2017 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2018 xhci_dbg(xhci, "Waiting for status "
2024 return finish_td(xhci, td, event_trb, event, ep, status, false);
2028 * Process isochronous tds, update urb packet status and actual_length.
2030 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2031 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2032 struct xhci_virt_ep *ep, int *status)
2034 struct xhci_ring *ep_ring;
2035 struct urb_priv *urb_priv;
2038 union xhci_trb *cur_trb;
2039 struct xhci_segment *cur_seg;
2040 struct usb_iso_packet_descriptor *frame;
2042 bool skip_td = false;
2044 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2045 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2046 urb_priv = td->urb->hcpriv;
2047 idx = urb_priv->td_cnt;
2048 frame = &td->urb->iso_frame_desc[idx];
2050 /* handle completion code */
2051 switch (trb_comp_code) {
2053 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2057 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2058 trb_comp_code = COMP_SHORT_TX;
2060 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2064 frame->status = -ECOMM;
2067 case COMP_BUFF_OVER:
2069 frame->status = -EOVERFLOW;
2075 frame->status = -EPROTO;
2079 case COMP_STOP_INVAL:
2086 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2087 frame->actual_length = frame->length;
2088 td->urb->actual_length += frame->length;
2090 for (cur_trb = ep_ring->dequeue,
2091 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2092 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2093 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2094 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2095 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2097 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2098 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2100 if (trb_comp_code != COMP_STOP_INVAL) {
2101 frame->actual_length = len;
2102 td->urb->actual_length += len;
2106 return finish_td(xhci, td, event_trb, event, ep, status, false);
2109 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2110 struct xhci_transfer_event *event,
2111 struct xhci_virt_ep *ep, int *status)
2113 struct xhci_ring *ep_ring;
2114 struct urb_priv *urb_priv;
2115 struct usb_iso_packet_descriptor *frame;
2118 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2119 urb_priv = td->urb->hcpriv;
2120 idx = urb_priv->td_cnt;
2121 frame = &td->urb->iso_frame_desc[idx];
2123 /* The transfer is partly done. */
2124 frame->status = -EXDEV;
2126 /* calc actual length */
2127 frame->actual_length = 0;
2129 /* Update ring dequeue pointer */
2130 while (ep_ring->dequeue != td->last_trb)
2131 inc_deq(xhci, ep_ring);
2132 inc_deq(xhci, ep_ring);
2134 return finish_td(xhci, td, NULL, event, ep, status, true);
2138 * Process bulk and interrupt tds, update urb status and actual_length.
2140 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2141 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2142 struct xhci_virt_ep *ep, int *status)
2144 struct xhci_ring *ep_ring;
2145 union xhci_trb *cur_trb;
2146 struct xhci_segment *cur_seg;
2149 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2150 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2152 switch (trb_comp_code) {
2154 /* Double check that the HW transferred everything. */
2155 if (event_trb != td->last_trb ||
2156 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2157 xhci_warn(xhci, "WARN Successful completion "
2159 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2160 *status = -EREMOTEIO;
2163 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2164 trb_comp_code = COMP_SHORT_TX;
2170 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2171 *status = -EREMOTEIO;
2176 /* Others already handled above */
2179 if (trb_comp_code == COMP_SHORT_TX)
2180 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2181 "%d bytes untransferred\n",
2182 td->urb->ep->desc.bEndpointAddress,
2183 td->urb->transfer_buffer_length,
2184 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2185 /* Fast path - was this the last TRB in the TD for this URB? */
2186 if (event_trb == td->last_trb) {
2187 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2188 td->urb->actual_length =
2189 td->urb->transfer_buffer_length -
2190 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2191 if (td->urb->transfer_buffer_length <
2192 td->urb->actual_length) {
2193 xhci_warn(xhci, "HC gave bad length "
2194 "of %d bytes left\n",
2195 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2196 td->urb->actual_length = 0;
2197 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2198 *status = -EREMOTEIO;
2202 /* Don't overwrite a previously set error code */
2203 if (*status == -EINPROGRESS) {
2204 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2205 *status = -EREMOTEIO;
2210 td->urb->actual_length =
2211 td->urb->transfer_buffer_length;
2212 /* Ignore a short packet completion if the
2213 * untransferred length was zero.
2215 if (*status == -EREMOTEIO)
2219 /* Slow path - walk the list, starting from the dequeue
2220 * pointer, to get the actual length transferred.
2222 td->urb->actual_length = 0;
2223 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2224 cur_trb != event_trb;
2225 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2226 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2227 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2228 td->urb->actual_length +=
2229 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2231 /* If the ring didn't stop on a Link or No-op TRB, add
2232 * in the actual bytes transferred from the Normal TRB
2234 if (trb_comp_code != COMP_STOP_INVAL)
2235 td->urb->actual_length +=
2236 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2237 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2240 return finish_td(xhci, td, event_trb, event, ep, status, false);
2244 * If this function returns an error condition, it means it got a Transfer
2245 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2246 * At this point, the host controller is probably hosed and should be reset.
2248 static int handle_tx_event(struct xhci_hcd *xhci,
2249 struct xhci_transfer_event *event)
2250 __releases(&xhci->lock)
2251 __acquires(&xhci->lock)
2253 struct xhci_virt_device *xdev;
2254 struct xhci_virt_ep *ep;
2255 struct xhci_ring *ep_ring;
2256 unsigned int slot_id;
2258 struct xhci_td *td = NULL;
2259 dma_addr_t event_dma;
2260 struct xhci_segment *event_seg;
2261 union xhci_trb *event_trb;
2262 struct urb *urb = NULL;
2263 int status = -EINPROGRESS;
2264 struct urb_priv *urb_priv;
2265 struct xhci_ep_ctx *ep_ctx;
2266 struct list_head *tmp;
2271 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2272 xdev = xhci->devs[slot_id];
2274 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2275 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2276 (unsigned long long) xhci_trb_virt_to_dma(
2277 xhci->event_ring->deq_seg,
2278 xhci->event_ring->dequeue),
2279 lower_32_bits(le64_to_cpu(event->buffer)),
2280 upper_32_bits(le64_to_cpu(event->buffer)),
2281 le32_to_cpu(event->transfer_len),
2282 le32_to_cpu(event->flags));
2283 xhci_dbg(xhci, "Event ring:\n");
2284 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2288 /* Endpoint ID is 1 based, our index is zero based */
2289 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2290 ep = &xdev->eps[ep_index];
2291 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2292 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2294 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2295 EP_STATE_DISABLED) {
2296 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2297 "or incorrect stream ring\n");
2298 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2299 (unsigned long long) xhci_trb_virt_to_dma(
2300 xhci->event_ring->deq_seg,
2301 xhci->event_ring->dequeue),
2302 lower_32_bits(le64_to_cpu(event->buffer)),
2303 upper_32_bits(le64_to_cpu(event->buffer)),
2304 le32_to_cpu(event->transfer_len),
2305 le32_to_cpu(event->flags));
2306 xhci_dbg(xhci, "Event ring:\n");
2307 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2311 /* Count current td numbers if ep->skip is set */
2313 list_for_each(tmp, &ep_ring->td_list)
2317 event_dma = le64_to_cpu(event->buffer);
2318 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2319 /* Look for common error cases */
2320 switch (trb_comp_code) {
2321 /* Skip codes that require special handling depending on
2325 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2327 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2328 trb_comp_code = COMP_SHORT_TX;
2330 xhci_warn_ratelimited(xhci,
2331 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2335 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2337 case COMP_STOP_INVAL:
2338 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2341 xhci_dbg(xhci, "Stalled endpoint\n");
2342 ep->ep_state |= EP_HALTED;
2346 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2349 case COMP_SPLIT_ERR:
2351 xhci_dbg(xhci, "Transfer error on endpoint\n");
2355 xhci_dbg(xhci, "Babble error on endpoint\n");
2356 status = -EOVERFLOW;
2359 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2363 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2365 case COMP_BUFF_OVER:
2366 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2370 * When the Isoch ring is empty, the xHC will generate
2371 * a Ring Overrun Event for IN Isoch endpoint or Ring
2372 * Underrun Event for OUT Isoch endpoint.
2374 xhci_dbg(xhci, "underrun event on endpoint\n");
2375 if (!list_empty(&ep_ring->td_list))
2376 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2377 "still with TDs queued?\n",
2378 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2382 xhci_dbg(xhci, "overrun event on endpoint\n");
2383 if (!list_empty(&ep_ring->td_list))
2384 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2385 "still with TDs queued?\n",
2386 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2390 xhci_warn(xhci, "WARN: detect an incompatible device");
2393 case COMP_MISSED_INT:
2395 * When encounter missed service error, one or more isoc tds
2396 * may be missed by xHC.
2397 * Set skip flag of the ep_ring; Complete the missed tds as
2398 * short transfer when process the ep_ring next time.
2401 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2404 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2408 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2414 /* This TRB should be in the TD at the head of this ring's
2417 if (list_empty(&ep_ring->td_list)) {
2419 * A stopped endpoint may generate an extra completion
2420 * event if the device was suspended. Don't print
2423 if (!(trb_comp_code == COMP_STOP ||
2424 trb_comp_code == COMP_STOP_INVAL)) {
2425 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2426 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2428 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2429 (le32_to_cpu(event->flags) &
2430 TRB_TYPE_BITMASK)>>10);
2431 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2435 xhci_dbg(xhci, "td_list is empty while skip "
2436 "flag set. Clear skip flag.\n");
2442 /* We've skipped all the TDs on the ep ring when ep->skip set */
2443 if (ep->skip && td_num == 0) {
2445 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2446 "Clear skip flag.\n");
2451 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2455 /* Is this a TRB in the currently executing TD? */
2456 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2457 td->last_trb, event_dma);
2460 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2461 * is not in the current TD pointed by ep_ring->dequeue because
2462 * that the hardware dequeue pointer still at the previous TRB
2463 * of the current TD. The previous TRB maybe a Link TD or the
2464 * last TRB of the previous TD. The command completion handle
2465 * will take care the rest.
2467 if (!event_seg && (trb_comp_code == COMP_STOP ||
2468 trb_comp_code == COMP_STOP_INVAL)) {
2475 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2476 /* Some host controllers give a spurious
2477 * successful event after a short transfer.
2480 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2481 ep_ring->last_td_was_short) {
2482 ep_ring->last_td_was_short = false;
2486 /* HC is busted, give up! */
2488 "ERROR Transfer event TRB DMA ptr not "
2489 "part of current TD\n");
2493 ret = skip_isoc_td(xhci, td, event, ep, &status);
2496 if (trb_comp_code == COMP_SHORT_TX)
2497 ep_ring->last_td_was_short = true;
2499 ep_ring->last_td_was_short = false;
2502 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2506 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2507 sizeof(*event_trb)];
2509 * No-op TRB should not trigger interrupts.
2510 * If event_trb is a no-op TRB, it means the
2511 * corresponding TD has been cancelled. Just ignore
2514 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2516 "event_trb is a no-op TRB. Skip it\n");
2520 /* Now update the urb's actual_length and give back to
2523 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2524 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2526 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2527 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2530 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2535 * Do not update event ring dequeue pointer if ep->skip is set.
2536 * Will roll back to continue process missed tds.
2538 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2539 inc_deq(xhci, xhci->event_ring);
2544 urb_priv = urb->hcpriv;
2545 /* Leave the TD around for the reset endpoint function
2546 * to use(but only if it's not a control endpoint,
2547 * since we already queued the Set TR dequeue pointer
2548 * command for stalled control endpoints).
2550 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2551 (trb_comp_code != COMP_STALL &&
2552 trb_comp_code != COMP_BABBLE))
2553 xhci_urb_free_priv(xhci, urb_priv);
2557 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2558 if ((urb->actual_length != urb->transfer_buffer_length &&
2559 (urb->transfer_flags &
2560 URB_SHORT_NOT_OK)) ||
2562 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2563 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2564 "expected = %d, status = %d\n",
2565 urb, urb->actual_length,
2566 urb->transfer_buffer_length,
2568 spin_unlock(&xhci->lock);
2569 /* EHCI, UHCI, and OHCI always unconditionally set the
2570 * urb->status of an isochronous endpoint to 0.
2572 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2574 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2575 spin_lock(&xhci->lock);
2579 * If ep->skip is set, it means there are missed tds on the
2580 * endpoint ring need to take care of.
2581 * Process them as short transfer until reach the td pointed by
2584 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2590 * This function handles all OS-owned events on the event ring. It may drop
2591 * xhci->lock between event processing (e.g. to pass up port status changes).
2592 * Returns >0 for "possibly more events to process" (caller should call again),
2593 * otherwise 0 if done. In future, <0 returns should indicate error code.
2595 static int xhci_handle_event(struct xhci_hcd *xhci)
2597 union xhci_trb *event;
2598 int update_ptrs = 1;
2601 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2602 xhci->error_bitmask |= 1 << 1;
2606 event = xhci->event_ring->dequeue;
2607 /* Does the HC or OS own the TRB? */
2608 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2609 xhci->event_ring->cycle_state) {
2610 xhci->error_bitmask |= 1 << 2;
2615 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2616 * speculative reads of the event's flags/data below.
2619 /* FIXME: Handle more event types. */
2620 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2621 case TRB_TYPE(TRB_COMPLETION):
2622 handle_cmd_completion(xhci, &event->event_cmd);
2624 case TRB_TYPE(TRB_PORT_STATUS):
2625 handle_port_status(xhci, event);
2628 case TRB_TYPE(TRB_TRANSFER):
2629 ret = handle_tx_event(xhci, &event->trans_event);
2631 xhci->error_bitmask |= 1 << 9;
2635 case TRB_TYPE(TRB_DEV_NOTE):
2636 handle_device_notification(xhci, event);
2639 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2641 handle_vendor_event(xhci, event);
2643 xhci->error_bitmask |= 1 << 3;
2645 /* Any of the above functions may drop and re-acquire the lock, so check
2646 * to make sure a watchdog timer didn't mark the host as non-responsive.
2648 if (xhci->xhc_state & XHCI_STATE_DYING) {
2649 xhci_dbg(xhci, "xHCI host dying, returning from "
2650 "event handler.\n");
2655 /* Update SW event ring dequeue pointer */
2656 inc_deq(xhci, xhci->event_ring);
2658 /* Are there more items on the event ring? Caller will call us again to
2665 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2666 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2667 * indicators of an event TRB error, but we check the status *first* to be safe.
2669 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2671 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2674 union xhci_trb *event_ring_deq;
2677 spin_lock(&xhci->lock);
2678 /* Check if the xHC generated the interrupt, or the irq is shared */
2679 status = readl(&xhci->op_regs->status);
2680 if (status == 0xffffffff)
2683 if (!(status & STS_EINT)) {
2684 spin_unlock(&xhci->lock);
2687 if (status & STS_FATAL) {
2688 xhci_warn(xhci, "WARNING: Host System Error\n");
2691 spin_unlock(&xhci->lock);
2696 * Clear the op reg interrupt status first,
2697 * so we can receive interrupts from other MSI-X interrupters.
2698 * Write 1 to clear the interrupt status.
2701 writel(status, &xhci->op_regs->status);
2702 /* FIXME when MSI-X is supported and there are multiple vectors */
2703 /* Clear the MSI-X event interrupt status */
2707 /* Acknowledge the PCI interrupt */
2708 irq_pending = readl(&xhci->ir_set->irq_pending);
2709 irq_pending |= IMAN_IP;
2710 writel(irq_pending, &xhci->ir_set->irq_pending);
2713 if (xhci->xhc_state & XHCI_STATE_DYING) {
2714 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2715 "Shouldn't IRQs be disabled?\n");
2716 /* Clear the event handler busy flag (RW1C);
2717 * the event ring should be empty.
2719 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2720 xhci_write_64(xhci, temp_64 | ERST_EHB,
2721 &xhci->ir_set->erst_dequeue);
2722 spin_unlock(&xhci->lock);
2727 event_ring_deq = xhci->event_ring->dequeue;
2728 /* FIXME this should be a delayed service routine
2729 * that clears the EHB.
2731 while (xhci_handle_event(xhci) > 0) {}
2733 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2734 /* If necessary, update the HW's version of the event ring deq ptr. */
2735 if (event_ring_deq != xhci->event_ring->dequeue) {
2736 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2737 xhci->event_ring->dequeue);
2739 xhci_warn(xhci, "WARN something wrong with SW event "
2740 "ring dequeue ptr.\n");
2741 /* Update HC event ring dequeue pointer */
2742 temp_64 &= ERST_PTR_MASK;
2743 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2746 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2747 temp_64 |= ERST_EHB;
2748 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2750 spin_unlock(&xhci->lock);
2755 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2757 return xhci_irq(hcd);
2760 /**** Endpoint Ring Operations ****/
2763 * Generic function for queueing a TRB on a ring.
2764 * The caller must have checked to make sure there's room on the ring.
2766 * @more_trbs_coming: Will you enqueue more TRBs before calling
2767 * prepare_transfer()?
2769 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2770 bool more_trbs_coming,
2771 u32 field1, u32 field2, u32 field3, u32 field4)
2773 struct xhci_generic_trb *trb;
2775 trb = &ring->enqueue->generic;
2776 trb->field[0] = cpu_to_le32(field1);
2777 trb->field[1] = cpu_to_le32(field2);
2778 trb->field[2] = cpu_to_le32(field3);
2779 trb->field[3] = cpu_to_le32(field4);
2780 inc_enq(xhci, ring, more_trbs_coming);
2784 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2785 * FIXME allocate segments if the ring is full.
2787 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2788 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2790 unsigned int num_trbs_needed;
2792 /* Make sure the endpoint has been added to xHC schedule */
2794 case EP_STATE_DISABLED:
2796 * USB core changed config/interfaces without notifying us,
2797 * or hardware is reporting the wrong state.
2799 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2801 case EP_STATE_ERROR:
2802 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2803 /* FIXME event handling code for error needs to clear it */
2804 /* XXX not sure if this should be -ENOENT or not */
2806 case EP_STATE_HALTED:
2807 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2808 case EP_STATE_STOPPED:
2809 case EP_STATE_RUNNING:
2812 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2814 * FIXME issue Configure Endpoint command to try to get the HC
2815 * back into a known state.
2821 if (room_on_ring(xhci, ep_ring, num_trbs))
2824 if (ep_ring == xhci->cmd_ring) {
2825 xhci_err(xhci, "Do not support expand command ring\n");
2829 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2830 "ERROR no room on ep ring, try ring expansion");
2831 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2832 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2834 xhci_err(xhci, "Ring expansion failed\n");
2839 if (enqueue_is_link_trb(ep_ring)) {
2840 struct xhci_ring *ring = ep_ring;
2841 union xhci_trb *next;
2843 next = ring->enqueue;
2845 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2846 /* If we're not dealing with 0.95 hardware or isoc rings
2847 * on AMD 0.96 host, clear the chain bit.
2849 if (!xhci_link_trb_quirk(xhci) &&
2850 !(ring->type == TYPE_ISOC &&
2851 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2852 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2854 next->link.control |= cpu_to_le32(TRB_CHAIN);
2857 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2859 /* Toggle the cycle bit after the last ring segment. */
2860 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2861 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2863 ring->enq_seg = ring->enq_seg->next;
2864 ring->enqueue = ring->enq_seg->trbs;
2865 next = ring->enqueue;
2872 static int prepare_transfer(struct xhci_hcd *xhci,
2873 struct xhci_virt_device *xdev,
2874 unsigned int ep_index,
2875 unsigned int stream_id,
2876 unsigned int num_trbs,
2878 unsigned int td_index,
2882 struct urb_priv *urb_priv;
2884 struct xhci_ring *ep_ring;
2885 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2887 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2889 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2894 ret = prepare_ring(xhci, ep_ring,
2895 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2896 num_trbs, mem_flags);
2900 urb_priv = urb->hcpriv;
2901 td = urb_priv->td[td_index];
2903 INIT_LIST_HEAD(&td->td_list);
2904 INIT_LIST_HEAD(&td->cancelled_td_list);
2906 if (td_index == 0) {
2907 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2913 /* Add this TD to the tail of the endpoint ring's TD list */
2914 list_add_tail(&td->td_list, &ep_ring->td_list);
2915 td->start_seg = ep_ring->enq_seg;
2916 td->first_trb = ep_ring->enqueue;
2918 urb_priv->td[td_index] = td;
2923 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2925 int num_sgs, num_trbs, running_total, temp, i;
2926 struct scatterlist *sg;
2929 num_sgs = urb->num_mapped_sgs;
2930 temp = urb->transfer_buffer_length;
2933 for_each_sg(urb->sg, sg, num_sgs, i) {
2934 unsigned int len = sg_dma_len(sg);
2936 /* Scatter gather list entries may cross 64KB boundaries */
2937 running_total = TRB_MAX_BUFF_SIZE -
2938 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2939 running_total &= TRB_MAX_BUFF_SIZE - 1;
2940 if (running_total != 0)
2943 /* How many more 64KB chunks to transfer, how many more TRBs? */
2944 while (running_total < sg_dma_len(sg) && running_total < temp) {
2946 running_total += TRB_MAX_BUFF_SIZE;
2948 len = min_t(int, len, temp);
2956 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2959 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2960 "TRBs, %d left\n", __func__,
2961 urb->ep->desc.bEndpointAddress, num_trbs);
2962 if (running_total != urb->transfer_buffer_length)
2963 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2964 "queued %#x (%d), asked for %#x (%d)\n",
2966 urb->ep->desc.bEndpointAddress,
2967 running_total, running_total,
2968 urb->transfer_buffer_length,
2969 urb->transfer_buffer_length);
2972 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2973 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2974 struct xhci_generic_trb *start_trb)
2977 * Pass all the TRBs to the hardware at once and make sure this write
2982 start_trb->field[3] |= cpu_to_le32(start_cycle);
2984 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2985 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2989 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2990 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2991 * (comprised of sg list entries) can take several service intervals to
2994 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2995 struct urb *urb, int slot_id, unsigned int ep_index)
2997 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2998 xhci->devs[slot_id]->out_ctx, ep_index);
3002 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3003 ep_interval = urb->interval;
3004 /* Convert to microframes */
3005 if (urb->dev->speed == USB_SPEED_LOW ||
3006 urb->dev->speed == USB_SPEED_FULL)
3008 /* FIXME change this to a warning and a suggestion to use the new API
3009 * to set the polling interval (once the API is added).
3011 if (xhci_interval != ep_interval) {
3012 dev_dbg_ratelimited(&urb->dev->dev,
3013 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3014 ep_interval, ep_interval == 1 ? "" : "s",
3015 xhci_interval, xhci_interval == 1 ? "" : "s");
3016 urb->interval = xhci_interval;
3017 /* Convert back to frames for LS/FS devices */
3018 if (urb->dev->speed == USB_SPEED_LOW ||
3019 urb->dev->speed == USB_SPEED_FULL)
3022 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3026 * The TD size is the number of bytes remaining in the TD (including this TRB),
3027 * right shifted by 10.
3028 * It must fit in bits 21:17, so it can't be bigger than 31.
3030 static u32 xhci_td_remainder(unsigned int remainder)
3032 u32 max = (1 << (21 - 17 + 1)) - 1;
3034 if ((remainder >> 10) >= max)
3037 return (remainder >> 10) << 17;
3041 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3042 * packets remaining in the TD (*not* including this TRB).
3044 * Total TD packet count = total_packet_count =
3045 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3047 * Packets transferred up to and including this TRB = packets_transferred =
3048 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3050 * TD size = total_packet_count - packets_transferred
3052 * It must fit in bits 21:17, so it can't be bigger than 31.
3053 * The last TRB in a TD must have the TD size set to zero.
3055 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3056 unsigned int total_packet_count, struct urb *urb,
3057 unsigned int num_trbs_left)
3059 int packets_transferred;
3061 /* One TRB with a zero-length data packet. */
3062 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3065 /* All the TRB queueing functions don't count the current TRB in
3068 packets_transferred = (running_total + trb_buff_len) /
3069 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3071 if ((total_packet_count - packets_transferred) > 31)
3073 return (total_packet_count - packets_transferred) << 17;
3076 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3077 struct urb *urb, int slot_id, unsigned int ep_index)
3079 struct xhci_ring *ep_ring;
3080 unsigned int num_trbs;
3081 struct urb_priv *urb_priv;
3083 struct scatterlist *sg;
3085 int trb_buff_len, this_sg_len, running_total;
3086 unsigned int total_packet_count;
3089 bool more_trbs_coming;
3091 struct xhci_generic_trb *start_trb;
3094 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3098 num_trbs = count_sg_trbs_needed(xhci, urb);
3099 num_sgs = urb->num_mapped_sgs;
3100 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3101 usb_endpoint_maxp(&urb->ep->desc));
3103 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3104 ep_index, urb->stream_id,
3105 num_trbs, urb, 0, mem_flags);
3106 if (trb_buff_len < 0)
3107 return trb_buff_len;
3109 urb_priv = urb->hcpriv;
3110 td = urb_priv->td[0];
3113 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3114 * until we've finished creating all the other TRBs. The ring's cycle
3115 * state may change as we enqueue the other TRBs, so save it too.
3117 start_trb = &ep_ring->enqueue->generic;
3118 start_cycle = ep_ring->cycle_state;
3122 * How much data is in the first TRB?
3124 * There are three forces at work for TRB buffer pointers and lengths:
3125 * 1. We don't want to walk off the end of this sg-list entry buffer.
3126 * 2. The transfer length that the driver requested may be smaller than
3127 * the amount of memory allocated for this scatter-gather list.
3128 * 3. TRBs buffers can't cross 64KB boundaries.
3131 addr = (u64) sg_dma_address(sg);
3132 this_sg_len = sg_dma_len(sg);
3133 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3134 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3135 if (trb_buff_len > urb->transfer_buffer_length)
3136 trb_buff_len = urb->transfer_buffer_length;
3139 /* Queue the first TRB, even if it's zero-length */
3142 u32 length_field = 0;
3145 /* Don't change the cycle bit of the first TRB until later */
3148 if (start_cycle == 0)
3151 field |= ep_ring->cycle_state;
3153 /* Chain all the TRBs together; clear the chain bit in the last
3154 * TRB to indicate it's the last TRB in the chain.
3159 /* FIXME - add check for ZERO_PACKET flag before this */
3160 td->last_trb = ep_ring->enqueue;
3164 /* Only set interrupt on short packet for IN endpoints */
3165 if (usb_urb_dir_in(urb))
3168 if (TRB_MAX_BUFF_SIZE -
3169 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3170 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3171 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3172 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3173 (unsigned int) addr + trb_buff_len);
3176 /* Set the TRB length, TD size, and interrupter fields. */
3177 if (xhci->hci_version < 0x100) {
3178 remainder = xhci_td_remainder(
3179 urb->transfer_buffer_length -
3182 remainder = xhci_v1_0_td_remainder(running_total,
3183 trb_buff_len, total_packet_count, urb,
3186 length_field = TRB_LEN(trb_buff_len) |
3191 more_trbs_coming = true;
3193 more_trbs_coming = false;
3194 queue_trb(xhci, ep_ring, more_trbs_coming,
3195 lower_32_bits(addr),
3196 upper_32_bits(addr),
3198 field | TRB_TYPE(TRB_NORMAL));
3200 running_total += trb_buff_len;
3202 /* Calculate length for next transfer --
3203 * Are we done queueing all the TRBs for this sg entry?
3205 this_sg_len -= trb_buff_len;
3206 if (this_sg_len == 0) {
3211 addr = (u64) sg_dma_address(sg);
3212 this_sg_len = sg_dma_len(sg);
3214 addr += trb_buff_len;
3217 trb_buff_len = TRB_MAX_BUFF_SIZE -
3218 (addr & (TRB_MAX_BUFF_SIZE - 1));
3219 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3220 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3222 urb->transfer_buffer_length - running_total;
3223 } while (running_total < urb->transfer_buffer_length);
3225 check_trb_math(urb, num_trbs, running_total);
3226 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3227 start_cycle, start_trb);
3231 /* This is very similar to what ehci-q.c qtd_fill() does */
3232 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3233 struct urb *urb, int slot_id, unsigned int ep_index)
3235 struct xhci_ring *ep_ring;
3236 struct urb_priv *urb_priv;
3239 struct xhci_generic_trb *start_trb;
3241 bool more_trbs_coming;
3243 u32 field, length_field;
3245 int running_total, trb_buff_len, ret;
3246 unsigned int total_packet_count;
3250 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3252 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3257 /* How much data is (potentially) left before the 64KB boundary? */
3258 running_total = TRB_MAX_BUFF_SIZE -
3259 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3260 running_total &= TRB_MAX_BUFF_SIZE - 1;
3262 /* If there's some data on this 64KB chunk, or we have to send a
3263 * zero-length transfer, we need at least one TRB
3265 if (running_total != 0 || urb->transfer_buffer_length == 0)
3267 /* How many more 64KB chunks to transfer, how many more TRBs? */
3268 while (running_total < urb->transfer_buffer_length) {
3270 running_total += TRB_MAX_BUFF_SIZE;
3272 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3274 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3275 ep_index, urb->stream_id,
3276 num_trbs, urb, 0, mem_flags);
3280 urb_priv = urb->hcpriv;
3281 td = urb_priv->td[0];
3284 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3285 * until we've finished creating all the other TRBs. The ring's cycle
3286 * state may change as we enqueue the other TRBs, so save it too.
3288 start_trb = &ep_ring->enqueue->generic;
3289 start_cycle = ep_ring->cycle_state;
3292 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3293 usb_endpoint_maxp(&urb->ep->desc));
3294 /* How much data is in the first TRB? */
3295 addr = (u64) urb->transfer_dma;
3296 trb_buff_len = TRB_MAX_BUFF_SIZE -
3297 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3298 if (trb_buff_len > urb->transfer_buffer_length)
3299 trb_buff_len = urb->transfer_buffer_length;
3303 /* Queue the first TRB, even if it's zero-length */
3308 /* Don't change the cycle bit of the first TRB until later */
3311 if (start_cycle == 0)
3314 field |= ep_ring->cycle_state;
3316 /* Chain all the TRBs together; clear the chain bit in the last
3317 * TRB to indicate it's the last TRB in the chain.
3322 /* FIXME - add check for ZERO_PACKET flag before this */
3323 td->last_trb = ep_ring->enqueue;
3327 /* Only set interrupt on short packet for IN endpoints */
3328 if (usb_urb_dir_in(urb))
3331 /* Set the TRB length, TD size, and interrupter fields. */
3332 if (xhci->hci_version < 0x100) {
3333 remainder = xhci_td_remainder(
3334 urb->transfer_buffer_length -
3337 remainder = xhci_v1_0_td_remainder(running_total,
3338 trb_buff_len, total_packet_count, urb,
3341 length_field = TRB_LEN(trb_buff_len) |
3346 more_trbs_coming = true;
3348 more_trbs_coming = false;
3349 queue_trb(xhci, ep_ring, more_trbs_coming,
3350 lower_32_bits(addr),
3351 upper_32_bits(addr),
3353 field | TRB_TYPE(TRB_NORMAL));
3355 running_total += trb_buff_len;
3357 /* Calculate length for next transfer */
3358 addr += trb_buff_len;
3359 trb_buff_len = urb->transfer_buffer_length - running_total;
3360 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3361 trb_buff_len = TRB_MAX_BUFF_SIZE;
3362 } while (running_total < urb->transfer_buffer_length);
3364 check_trb_math(urb, num_trbs, running_total);
3365 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3366 start_cycle, start_trb);
3370 /* Caller must have locked xhci->lock */
3371 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3372 struct urb *urb, int slot_id, unsigned int ep_index)
3374 struct xhci_ring *ep_ring;
3377 struct usb_ctrlrequest *setup;
3378 struct xhci_generic_trb *start_trb;
3380 u32 field, length_field;
3381 struct urb_priv *urb_priv;
3384 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3389 * Need to copy setup packet into setup TRB, so we can't use the setup
3392 if (!urb->setup_packet)
3395 /* 1 TRB for setup, 1 for status */
3398 * Don't need to check if we need additional event data and normal TRBs,
3399 * since data in control transfers will never get bigger than 16MB
3400 * XXX: can we get a buffer that crosses 64KB boundaries?
3402 if (urb->transfer_buffer_length > 0)
3404 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3405 ep_index, urb->stream_id,
3406 num_trbs, urb, 0, mem_flags);
3410 urb_priv = urb->hcpriv;
3411 td = urb_priv->td[0];
3414 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3415 * until we've finished creating all the other TRBs. The ring's cycle
3416 * state may change as we enqueue the other TRBs, so save it too.
3418 start_trb = &ep_ring->enqueue->generic;
3419 start_cycle = ep_ring->cycle_state;
3421 /* Queue setup TRB - see section 6.4.1.2.1 */
3422 /* FIXME better way to translate setup_packet into two u32 fields? */
3423 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3425 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3426 if (start_cycle == 0)
3429 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3430 if (xhci->hci_version == 0x100) {
3431 if (urb->transfer_buffer_length > 0) {
3432 if (setup->bRequestType & USB_DIR_IN)
3433 field |= TRB_TX_TYPE(TRB_DATA_IN);
3435 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3439 queue_trb(xhci, ep_ring, true,
3440 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3441 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3442 TRB_LEN(8) | TRB_INTR_TARGET(0),
3443 /* Immediate data in pointer */
3446 /* If there's data, queue data TRBs */
3447 /* Only set interrupt on short packet for IN endpoints */
3448 if (usb_urb_dir_in(urb))
3449 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3451 field = TRB_TYPE(TRB_DATA);
3453 length_field = TRB_LEN(urb->transfer_buffer_length) |
3454 xhci_td_remainder(urb->transfer_buffer_length) |
3456 if (urb->transfer_buffer_length > 0) {
3457 if (setup->bRequestType & USB_DIR_IN)
3458 field |= TRB_DIR_IN;
3459 queue_trb(xhci, ep_ring, true,
3460 lower_32_bits(urb->transfer_dma),
3461 upper_32_bits(urb->transfer_dma),
3463 field | ep_ring->cycle_state);
3466 /* Save the DMA address of the last TRB in the TD */
3467 td->last_trb = ep_ring->enqueue;
3469 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3470 /* If the device sent data, the status stage is an OUT transfer */
3471 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3475 queue_trb(xhci, ep_ring, false,
3479 /* Event on completion */
3480 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3482 giveback_first_trb(xhci, slot_id, ep_index, 0,
3483 start_cycle, start_trb);
3487 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3488 struct urb *urb, int i)
3493 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3494 td_len = urb->iso_frame_desc[i].length;
3496 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3505 * The transfer burst count field of the isochronous TRB defines the number of
3506 * bursts that are required to move all packets in this TD. Only SuperSpeed
3507 * devices can burst up to bMaxBurst number of packets per service interval.
3508 * This field is zero based, meaning a value of zero in the field means one
3509 * burst. Basically, for everything but SuperSpeed devices, this field will be
3510 * zero. Only xHCI 1.0 host controllers support this field.
3512 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3513 struct usb_device *udev,
3514 struct urb *urb, unsigned int total_packet_count)
3516 unsigned int max_burst;
3518 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3521 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3522 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3526 * Returns the number of packets in the last "burst" of packets. This field is
3527 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3528 * the last burst packet count is equal to the total number of packets in the
3529 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3530 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3531 * contain 1 to (bMaxBurst + 1) packets.
3533 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3534 struct usb_device *udev,
3535 struct urb *urb, unsigned int total_packet_count)
3537 unsigned int max_burst;
3538 unsigned int residue;
3540 if (xhci->hci_version < 0x100)
3543 switch (udev->speed) {
3544 case USB_SPEED_SUPER:
3545 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3546 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3547 residue = total_packet_count % (max_burst + 1);
3548 /* If residue is zero, the last burst contains (max_burst + 1)
3549 * number of packets, but the TLBPC field is zero-based.
3555 if (total_packet_count == 0)
3557 return total_packet_count - 1;
3561 /* This is for isoc transfer */
3562 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3563 struct urb *urb, int slot_id, unsigned int ep_index)
3565 struct xhci_ring *ep_ring;
3566 struct urb_priv *urb_priv;
3568 int num_tds, trbs_per_td;
3569 struct xhci_generic_trb *start_trb;
3572 u32 field, length_field;
3573 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3574 u64 start_addr, addr;
3576 bool more_trbs_coming;
3578 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3580 num_tds = urb->number_of_packets;
3582 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3586 start_addr = (u64) urb->transfer_dma;
3587 start_trb = &ep_ring->enqueue->generic;
3588 start_cycle = ep_ring->cycle_state;
3590 urb_priv = urb->hcpriv;
3591 /* Queue the first TRB, even if it's zero-length */
3592 for (i = 0; i < num_tds; i++) {
3593 unsigned int total_packet_count;
3594 unsigned int burst_count;
3595 unsigned int residue;
3599 addr = start_addr + urb->iso_frame_desc[i].offset;
3600 td_len = urb->iso_frame_desc[i].length;
3601 td_remain_len = td_len;
3602 total_packet_count = DIV_ROUND_UP(td_len,
3604 usb_endpoint_maxp(&urb->ep->desc)));
3605 /* A zero-length transfer still involves at least one packet. */
3606 if (total_packet_count == 0)
3607 total_packet_count++;
3608 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3609 total_packet_count);
3610 residue = xhci_get_last_burst_packet_count(xhci,
3611 urb->dev, urb, total_packet_count);
3613 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3615 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3616 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3623 td = urb_priv->td[i];
3624 for (j = 0; j < trbs_per_td; j++) {
3629 field = TRB_TBC(burst_count) |
3631 /* Queue the isoc TRB */
3632 field |= TRB_TYPE(TRB_ISOC);
3633 /* Assume URB_ISO_ASAP is set */
3636 if (start_cycle == 0)
3639 field |= ep_ring->cycle_state;
3642 /* Queue other normal TRBs */
3643 field |= TRB_TYPE(TRB_NORMAL);
3644 field |= ep_ring->cycle_state;
3647 /* Only set interrupt on short packet for IN EPs */
3648 if (usb_urb_dir_in(urb))
3651 /* Chain all the TRBs together; clear the chain bit in
3652 * the last TRB to indicate it's the last TRB in the
3655 if (j < trbs_per_td - 1) {
3657 more_trbs_coming = true;
3659 td->last_trb = ep_ring->enqueue;
3661 if (xhci->hci_version == 0x100 &&
3664 /* Set BEI bit except for the last td */
3665 if (i < num_tds - 1)
3668 more_trbs_coming = false;
3671 /* Calculate TRB length */
3672 trb_buff_len = TRB_MAX_BUFF_SIZE -
3673 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3674 if (trb_buff_len > td_remain_len)
3675 trb_buff_len = td_remain_len;
3677 /* Set the TRB length, TD size, & interrupter fields. */
3678 if (xhci->hci_version < 0x100) {
3679 remainder = xhci_td_remainder(
3680 td_len - running_total);
3682 remainder = xhci_v1_0_td_remainder(
3683 running_total, trb_buff_len,
3684 total_packet_count, urb,
3685 (trbs_per_td - j - 1));
3687 length_field = TRB_LEN(trb_buff_len) |
3691 queue_trb(xhci, ep_ring, more_trbs_coming,
3692 lower_32_bits(addr),
3693 upper_32_bits(addr),
3696 running_total += trb_buff_len;
3698 addr += trb_buff_len;
3699 td_remain_len -= trb_buff_len;
3702 /* Check TD length */
3703 if (running_total != td_len) {
3704 xhci_err(xhci, "ISOC TD length unmatch\n");
3710 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3711 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3712 usb_amd_quirk_pll_disable();
3714 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3716 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3717 start_cycle, start_trb);
3720 /* Clean up a partially enqueued isoc transfer. */
3722 for (i--; i >= 0; i--)
3723 list_del_init(&urb_priv->td[i]->td_list);
3725 /* Use the first TD as a temporary variable to turn the TDs we've queued
3726 * into No-ops with a software-owned cycle bit. That way the hardware
3727 * won't accidentally start executing bogus TDs when we partially
3728 * overwrite them. td->first_trb and td->start_seg are already set.
3730 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3731 /* Every TRB except the first & last will have its cycle bit flipped. */
3732 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3734 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3735 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3736 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3737 ep_ring->cycle_state = start_cycle;
3738 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3739 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3744 * Check transfer ring to guarantee there is enough room for the urb.
3745 * Update ISO URB start_frame and interval.
3746 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3747 * update the urb->start_frame by now.
3748 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3750 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3751 struct urb *urb, int slot_id, unsigned int ep_index)
3753 struct xhci_virt_device *xdev;
3754 struct xhci_ring *ep_ring;
3755 struct xhci_ep_ctx *ep_ctx;
3759 int num_tds, num_trbs, i;
3762 xdev = xhci->devs[slot_id];
3763 ep_ring = xdev->eps[ep_index].ring;
3764 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3767 num_tds = urb->number_of_packets;
3768 for (i = 0; i < num_tds; i++)
3769 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3771 /* Check the ring to guarantee there is enough room for the whole urb.
3772 * Do not insert any td of the urb to the ring if the check failed.
3774 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3775 num_trbs, mem_flags);
3779 start_frame = readl(&xhci->run_regs->microframe_index);
3780 start_frame &= 0x3fff;
3782 urb->start_frame = start_frame;
3783 if (urb->dev->speed == USB_SPEED_LOW ||
3784 urb->dev->speed == USB_SPEED_FULL)
3785 urb->start_frame >>= 3;
3787 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3788 ep_interval = urb->interval;
3789 /* Convert to microframes */
3790 if (urb->dev->speed == USB_SPEED_LOW ||
3791 urb->dev->speed == USB_SPEED_FULL)
3793 /* FIXME change this to a warning and a suggestion to use the new API
3794 * to set the polling interval (once the API is added).
3796 if (xhci_interval != ep_interval) {
3797 dev_dbg_ratelimited(&urb->dev->dev,
3798 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3799 ep_interval, ep_interval == 1 ? "" : "s",
3800 xhci_interval, xhci_interval == 1 ? "" : "s");
3801 urb->interval = xhci_interval;
3802 /* Convert back to frames for LS/FS devices */
3803 if (urb->dev->speed == USB_SPEED_LOW ||
3804 urb->dev->speed == USB_SPEED_FULL)
3807 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3809 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3812 /**** Command Ring Operations ****/
3814 /* Generic function for queueing a command TRB on the command ring.
3815 * Check to make sure there's room on the command ring for one command TRB.
3816 * Also check that there's room reserved for commands that must not fail.
3817 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3818 * then only check for the number of reserved spots.
3819 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3820 * because the command event handler may want to resubmit a failed command.
3822 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3823 u32 field1, u32 field2,
3824 u32 field3, u32 field4, bool command_must_succeed)
3826 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3828 if (xhci->xhc_state & XHCI_STATE_DYING)
3831 if (!command_must_succeed)
3834 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3835 reserved_trbs, GFP_ATOMIC);
3837 xhci_err(xhci, "ERR: No room for command on command ring\n");
3838 if (command_must_succeed)
3839 xhci_err(xhci, "ERR: Reserved TRB counting for "
3840 "unfailable commands failed.\n");
3844 cmd->command_trb = xhci->cmd_ring->enqueue;
3845 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3847 /* if there are no other commands queued we start the timeout timer */
3848 if (xhci->cmd_list.next == &cmd->cmd_list &&
3849 !timer_pending(&xhci->cmd_timer)) {
3850 xhci->current_cmd = cmd;
3851 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3854 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3855 field4 | xhci->cmd_ring->cycle_state);
3859 /* Queue a slot enable or disable request on the command ring */
3860 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3861 u32 trb_type, u32 slot_id)
3863 return queue_command(xhci, cmd, 0, 0, 0,
3864 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3867 /* Queue an address device command TRB */
3868 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3869 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3871 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3872 upper_32_bits(in_ctx_ptr), 0,
3873 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3874 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3877 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3878 u32 field1, u32 field2, u32 field3, u32 field4)
3880 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3883 /* Queue a reset device command TRB */
3884 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3887 return queue_command(xhci, cmd, 0, 0, 0,
3888 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3892 /* Queue a configure endpoint command TRB */
3893 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3894 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3895 u32 slot_id, bool command_must_succeed)
3897 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3898 upper_32_bits(in_ctx_ptr), 0,
3899 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3900 command_must_succeed);
3903 /* Queue an evaluate context command TRB */
3904 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3905 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3907 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3908 upper_32_bits(in_ctx_ptr), 0,
3909 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3910 command_must_succeed);
3914 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3915 * activity on an endpoint that is about to be suspended.
3917 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3918 int slot_id, unsigned int ep_index, int suspend)
3920 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3921 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3922 u32 type = TRB_TYPE(TRB_STOP_RING);
3923 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3925 return queue_command(xhci, cmd, 0, 0, 0,
3926 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3929 /* Set Transfer Ring Dequeue Pointer command.
3930 * This should not be used for endpoints that have streams enabled.
3932 static int queue_set_tr_deq(struct xhci_hcd *xhci, struct xhci_command *cmd,
3934 unsigned int ep_index, unsigned int stream_id,
3935 struct xhci_segment *deq_seg,
3936 union xhci_trb *deq_ptr, u32 cycle_state)
3939 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3940 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3941 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3943 u32 type = TRB_TYPE(TRB_SET_DEQ);
3944 struct xhci_virt_ep *ep;
3946 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3948 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3949 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3953 ep = &xhci->devs[slot_id]->eps[ep_index];
3954 if ((ep->ep_state & SET_DEQ_PENDING)) {
3955 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3956 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3959 ep->queued_deq_seg = deq_seg;
3960 ep->queued_deq_ptr = deq_ptr;
3962 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
3963 return queue_command(xhci, cmd,
3964 lower_32_bits(addr) | trb_sct | cycle_state,
3965 upper_32_bits(addr), trb_stream_id,
3966 trb_slot_id | trb_ep_index | type, false);
3969 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3970 int slot_id, unsigned int ep_index)
3972 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3973 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3974 u32 type = TRB_TYPE(TRB_RESET_EP);
3976 return queue_command(xhci, cmd, 0, 0, 0,
3977 trb_slot_id | trb_ep_index | type, false);