2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset > TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
302 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
305 xhci_err(xhci, "Stopped the command ring failed, "
306 "maybe the host is dead\n");
307 xhci->xhc_state |= XHCI_STATE_DYING;
316 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
317 unsigned int slot_id,
318 unsigned int ep_index,
319 unsigned int stream_id)
321 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
322 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
323 unsigned int ep_state = ep->ep_state;
325 /* Don't ring the doorbell for this endpoint if there are pending
326 * cancellations because we don't want to interrupt processing.
327 * We don't want to restart any stream rings if there's a set dequeue
328 * pointer command pending because the device can choose to start any
329 * stream once the endpoint is on the HW schedule.
330 * FIXME - check all the stream rings for pending cancellations.
332 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
333 (ep_state & EP_HALTED))
335 writel(DB_VALUE(ep_index, stream_id), db_addr);
336 /* The CPU has better things to do at this point than wait for a
337 * write-posting flush. It'll get there soon enough.
341 /* Ring the doorbell for any rings with pending URBs */
342 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
343 unsigned int slot_id,
344 unsigned int ep_index)
346 unsigned int stream_id;
347 struct xhci_virt_ep *ep;
349 ep = &xhci->devs[slot_id]->eps[ep_index];
351 /* A ring has pending URBs if its TD list is not empty */
352 if (!(ep->ep_state & EP_HAS_STREAMS)) {
353 if (ep->ring && !(list_empty(&ep->ring->td_list)))
354 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
358 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
360 struct xhci_stream_info *stream_info = ep->stream_info;
361 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
362 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
368 * Find the segment that trb is in. Start searching in start_seg.
369 * If we must move past a segment that has a link TRB with a toggle cycle state
370 * bit set, then we will toggle the value pointed at by cycle_state.
372 static struct xhci_segment *find_trb_seg(
373 struct xhci_segment *start_seg,
374 union xhci_trb *trb, int *cycle_state)
376 struct xhci_segment *cur_seg = start_seg;
377 struct xhci_generic_trb *generic_trb;
379 while (cur_seg->trbs > trb ||
380 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
381 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
382 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
384 cur_seg = cur_seg->next;
385 if (cur_seg == start_seg)
386 /* Looped over the entire list. Oops! */
393 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
394 unsigned int slot_id, unsigned int ep_index,
395 unsigned int stream_id)
397 struct xhci_virt_ep *ep;
399 ep = &xhci->devs[slot_id]->eps[ep_index];
400 /* Common case: no streams */
401 if (!(ep->ep_state & EP_HAS_STREAMS))
404 if (stream_id == 0) {
406 "WARN: Slot ID %u, ep index %u has streams, "
407 "but URB has no stream ID.\n",
412 if (stream_id < ep->stream_info->num_streams)
413 return ep->stream_info->stream_rings[stream_id];
416 "WARN: Slot ID %u, ep index %u has "
417 "stream IDs 1 to %u allocated, "
418 "but stream ID %u is requested.\n",
420 ep->stream_info->num_streams - 1,
425 /* Get the right ring for the given URB.
426 * If the endpoint supports streams, boundary check the URB's stream ID.
427 * If the endpoint doesn't support streams, return the singular endpoint ring.
429 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
432 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
433 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
437 * Move the xHC's endpoint ring dequeue pointer past cur_td.
438 * Record the new state of the xHC's endpoint ring dequeue segment,
439 * dequeue pointer, and new consumer cycle state in state.
440 * Update our internal representation of the ring's dequeue pointer.
442 * We do this in three jumps:
443 * - First we update our new ring state to be the same as when the xHC stopped.
444 * - Then we traverse the ring to find the segment that contains
445 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
446 * any link TRBs with the toggle cycle bit set.
447 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
448 * if we've moved it past a link TRB with the toggle cycle bit set.
450 * Some of the uses of xhci_generic_trb are grotty, but if they're done
451 * with correct __le32 accesses they should work fine. Only users of this are
454 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
455 unsigned int slot_id, unsigned int ep_index,
456 unsigned int stream_id, struct xhci_td *cur_td,
457 struct xhci_dequeue_state *state)
459 struct xhci_virt_device *dev = xhci->devs[slot_id];
460 struct xhci_virt_ep *ep = &dev->eps[ep_index];
461 struct xhci_ring *ep_ring;
462 struct xhci_generic_trb *trb;
466 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
467 ep_index, stream_id);
469 xhci_warn(xhci, "WARN can't find new dequeue state "
470 "for invalid stream ID %u.\n",
475 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
476 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
477 "Finding endpoint context");
478 /* 4.6.9 the css flag is written to the stream context for streams */
479 if (ep->ep_state & EP_HAS_STREAMS) {
480 struct xhci_stream_ctx *ctx =
481 &ep->stream_info->stream_ctx_array[stream_id];
482 hw_dequeue = le64_to_cpu(ctx->stream_ring);
484 struct xhci_ep_ctx *ep_ctx
485 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
486 hw_dequeue = le64_to_cpu(ep_ctx->deq);
489 /* Find virtual address and segment of hardware dequeue pointer */
490 state->new_deq_seg = ep_ring->deq_seg;
491 state->new_deq_ptr = ep_ring->dequeue;
492 while (xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr)
493 != (dma_addr_t)(hw_dequeue & ~0xf)) {
494 next_trb(xhci, ep_ring, &state->new_deq_seg,
495 &state->new_deq_ptr);
496 if (state->new_deq_ptr == ep_ring->dequeue) {
502 * Find cycle state for last_trb, starting at old cycle state of
503 * hw_dequeue. If there is only one segment ring, find_trb_seg() will
504 * return immediately and cannot toggle the cycle state if this search
505 * wraps around, so add one more toggle manually in that case.
507 state->new_cycle_state = hw_dequeue & 0x1;
508 if (ep_ring->first_seg == ep_ring->first_seg->next &&
509 cur_td->last_trb < state->new_deq_ptr)
510 state->new_cycle_state ^= 0x1;
512 state->new_deq_ptr = cur_td->last_trb;
513 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
514 "Finding segment containing last TRB in TD.");
515 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
516 state->new_deq_ptr, &state->new_cycle_state);
517 if (!state->new_deq_seg) {
522 /* Increment to find next TRB after last_trb. Cycle if appropriate. */
523 trb = &state->new_deq_ptr->generic;
524 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
525 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
526 state->new_cycle_state ^= 0x1;
527 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
529 /* Don't update the ring cycle state for the producer (us). */
530 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
531 "Cycle state = 0x%x", state->new_cycle_state);
533 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
534 "New dequeue segment = %p (virtual)",
536 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
537 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
538 "New dequeue pointer = 0x%llx (DMA)",
539 (unsigned long long) addr);
542 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
543 * (The last TRB actually points to the ring enqueue pointer, which is not part
544 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
546 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
547 struct xhci_td *cur_td, bool flip_cycle)
549 struct xhci_segment *cur_seg;
550 union xhci_trb *cur_trb;
552 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
554 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
555 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
556 /* Unchain any chained Link TRBs, but
557 * leave the pointers intact.
559 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
560 /* Flip the cycle bit (link TRBs can't be the first
564 cur_trb->generic.field[3] ^=
565 cpu_to_le32(TRB_CYCLE);
566 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
567 "Cancel (unchain) link TRB");
568 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
569 "Address = %p (0x%llx dma); "
570 "in seg %p (0x%llx dma)",
572 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
574 (unsigned long long)cur_seg->dma);
576 cur_trb->generic.field[0] = 0;
577 cur_trb->generic.field[1] = 0;
578 cur_trb->generic.field[2] = 0;
579 /* Preserve only the cycle bit of this TRB */
580 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
581 /* Flip the cycle bit except on the first or last TRB */
582 if (flip_cycle && cur_trb != cur_td->first_trb &&
583 cur_trb != cur_td->last_trb)
584 cur_trb->generic.field[3] ^=
585 cpu_to_le32(TRB_CYCLE);
586 cur_trb->generic.field[3] |= cpu_to_le32(
587 TRB_TYPE(TRB_TR_NOOP));
588 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
589 "TRB to noop at offset 0x%llx",
591 xhci_trb_virt_to_dma(cur_seg, cur_trb));
593 if (cur_trb == cur_td->last_trb)
598 static int queue_set_tr_deq(struct xhci_hcd *xhci,
599 struct xhci_command *cmd, int slot_id,
600 unsigned int ep_index, unsigned int stream_id,
601 struct xhci_segment *deq_seg,
602 union xhci_trb *deq_ptr, u32 cycle_state);
604 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
605 struct xhci_command *cmd,
606 unsigned int slot_id, unsigned int ep_index,
607 unsigned int stream_id,
608 struct xhci_dequeue_state *deq_state)
610 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
612 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
613 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
614 "new deq ptr = %p (0x%llx dma), new cycle = %u",
615 deq_state->new_deq_seg,
616 (unsigned long long)deq_state->new_deq_seg->dma,
617 deq_state->new_deq_ptr,
618 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
619 deq_state->new_cycle_state);
620 queue_set_tr_deq(xhci, cmd, slot_id, ep_index, stream_id,
621 deq_state->new_deq_seg,
622 deq_state->new_deq_ptr,
623 (u32) deq_state->new_cycle_state);
624 /* Stop the TD queueing code from ringing the doorbell until
625 * this command completes. The HC won't set the dequeue pointer
626 * if the ring is running, and ringing the doorbell starts the
629 ep->ep_state |= SET_DEQ_PENDING;
632 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
633 struct xhci_virt_ep *ep)
635 ep->ep_state &= ~EP_HALT_PENDING;
636 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
637 * timer is running on another CPU, we don't decrement stop_cmds_pending
638 * (since we didn't successfully stop the watchdog timer).
640 if (del_timer(&ep->stop_cmd_timer))
641 ep->stop_cmds_pending--;
644 /* Must be called with xhci->lock held in interrupt context */
645 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
646 struct xhci_td *cur_td, int status)
650 struct urb_priv *urb_priv;
653 urb_priv = urb->hcpriv;
655 hcd = bus_to_hcd(urb->dev->bus);
657 /* Only giveback urb when this is the last td in urb */
658 if (urb_priv->td_cnt == urb_priv->length) {
659 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
660 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
661 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
662 if (xhci->quirks & XHCI_AMD_PLL_FIX)
663 usb_amd_quirk_pll_enable();
666 usb_hcd_unlink_urb_from_ep(hcd, urb);
668 spin_unlock(&xhci->lock);
669 usb_hcd_giveback_urb(hcd, urb, status);
670 xhci_urb_free_priv(xhci, urb_priv);
671 spin_lock(&xhci->lock);
676 * When we get a command completion for a Stop Endpoint Command, we need to
677 * unlink any cancelled TDs from the ring. There are two ways to do that:
679 * 1. If the HW was in the middle of processing the TD that needs to be
680 * cancelled, then we must move the ring's dequeue pointer past the last TRB
681 * in the TD with a Set Dequeue Pointer Command.
682 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
683 * bit cleared) so that the HW will skip over them.
685 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
686 union xhci_trb *trb, struct xhci_event_cmd *event)
688 unsigned int ep_index;
689 struct xhci_ring *ep_ring;
690 struct xhci_virt_ep *ep;
691 struct list_head *entry;
692 struct xhci_td *cur_td = NULL;
693 struct xhci_td *last_unlinked_td;
695 struct xhci_dequeue_state deq_state;
697 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
698 if (!xhci->devs[slot_id])
699 xhci_warn(xhci, "Stop endpoint command "
700 "completion for disabled slot %u\n",
705 memset(&deq_state, 0, sizeof(deq_state));
706 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
707 ep = &xhci->devs[slot_id]->eps[ep_index];
709 if (list_empty(&ep->cancelled_td_list)) {
710 xhci_stop_watchdog_timer_in_irq(xhci, ep);
711 ep->stopped_td = NULL;
712 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
716 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
717 * We have the xHCI lock, so nothing can modify this list until we drop
718 * it. We're also in the event handler, so we can't get re-interrupted
719 * if another Stop Endpoint command completes
721 list_for_each(entry, &ep->cancelled_td_list) {
722 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
723 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
724 "Removing canceled TD starting at 0x%llx (dma).",
725 (unsigned long long)xhci_trb_virt_to_dma(
726 cur_td->start_seg, cur_td->first_trb));
727 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
729 /* This shouldn't happen unless a driver is mucking
730 * with the stream ID after submission. This will
731 * leave the TD on the hardware ring, and the hardware
732 * will try to execute it, and may access a buffer
733 * that has already been freed. In the best case, the
734 * hardware will execute it, and the event handler will
735 * ignore the completion event for that TD, since it was
736 * removed from the td_list for that endpoint. In
737 * short, don't muck with the stream ID after
740 xhci_warn(xhci, "WARN Cancelled URB %p "
741 "has invalid stream ID %u.\n",
743 cur_td->urb->stream_id);
744 goto remove_finished_td;
747 * If we stopped on the TD we need to cancel, then we have to
748 * move the xHC endpoint ring dequeue pointer past this TD.
750 if (cur_td == ep->stopped_td)
751 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
752 cur_td->urb->stream_id,
755 td_to_noop(xhci, ep_ring, cur_td, false);
758 * The event handler won't see a completion for this TD anymore,
759 * so remove it from the endpoint ring's TD list. Keep it in
760 * the cancelled TD list for URB completion later.
762 list_del_init(&cur_td->td_list);
764 last_unlinked_td = cur_td;
765 xhci_stop_watchdog_timer_in_irq(xhci, ep);
767 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
768 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
769 struct xhci_command *command;
770 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
771 xhci_queue_new_dequeue_state(xhci, command,
773 ep->stopped_td->urb->stream_id,
775 xhci_ring_cmd_db(xhci);
777 /* Otherwise ring the doorbell(s) to restart queued transfers */
778 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
781 /* Clear stopped_td if endpoint is not halted */
782 if (!(ep->ep_state & EP_HALTED))
783 ep->stopped_td = NULL;
786 * Drop the lock and complete the URBs in the cancelled TD list.
787 * New TDs to be cancelled might be added to the end of the list before
788 * we can complete all the URBs for the TDs we already unlinked.
789 * So stop when we've completed the URB for the last TD we unlinked.
792 cur_td = list_entry(ep->cancelled_td_list.next,
793 struct xhci_td, cancelled_td_list);
794 list_del_init(&cur_td->cancelled_td_list);
796 /* Clean up the cancelled URB */
797 /* Doesn't matter what we pass for status, since the core will
798 * just overwrite it (because the URB has been unlinked).
800 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
802 /* Stop processing the cancelled list if the watchdog timer is
805 if (xhci->xhc_state & XHCI_STATE_DYING)
807 } while (cur_td != last_unlinked_td);
809 /* Return to the event handler with xhci->lock re-acquired */
812 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
814 struct xhci_td *cur_td;
816 while (!list_empty(&ring->td_list)) {
817 cur_td = list_first_entry(&ring->td_list,
818 struct xhci_td, td_list);
819 list_del_init(&cur_td->td_list);
820 if (!list_empty(&cur_td->cancelled_td_list))
821 list_del_init(&cur_td->cancelled_td_list);
822 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
826 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
827 int slot_id, int ep_index)
829 struct xhci_td *cur_td;
830 struct xhci_virt_ep *ep;
831 struct xhci_ring *ring;
833 ep = &xhci->devs[slot_id]->eps[ep_index];
834 if ((ep->ep_state & EP_HAS_STREAMS) ||
835 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
838 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
840 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
841 "Killing URBs for slot ID %u, ep index %u, stream %u",
842 slot_id, ep_index, stream_id + 1);
843 xhci_kill_ring_urbs(xhci,
844 ep->stream_info->stream_rings[stream_id]);
850 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
851 "Killing URBs for slot ID %u, ep index %u",
853 xhci_kill_ring_urbs(xhci, ring);
855 while (!list_empty(&ep->cancelled_td_list)) {
856 cur_td = list_first_entry(&ep->cancelled_td_list,
857 struct xhci_td, cancelled_td_list);
858 list_del_init(&cur_td->cancelled_td_list);
859 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
863 /* Watchdog timer function for when a stop endpoint command fails to complete.
864 * In this case, we assume the host controller is broken or dying or dead. The
865 * host may still be completing some other events, so we have to be careful to
866 * let the event ring handler and the URB dequeueing/enqueueing functions know
867 * through xhci->state.
869 * The timer may also fire if the host takes a very long time to respond to the
870 * command, and the stop endpoint command completion handler cannot delete the
871 * timer before the timer function is called. Another endpoint cancellation may
872 * sneak in before the timer function can grab the lock, and that may queue
873 * another stop endpoint command and add the timer back. So we cannot use a
874 * simple flag to say whether there is a pending stop endpoint command for a
875 * particular endpoint.
877 * Instead we use a combination of that flag and a counter for the number of
878 * pending stop endpoint commands. If the timer is the tail end of the last
879 * stop endpoint command, and the endpoint's command is still pending, we assume
882 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
884 struct xhci_hcd *xhci;
885 struct xhci_virt_ep *ep;
889 ep = (struct xhci_virt_ep *) arg;
892 spin_lock_irqsave(&xhci->lock, flags);
894 ep->stop_cmds_pending--;
895 if (xhci->xhc_state & XHCI_STATE_DYING) {
896 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
897 "Stop EP timer ran, but another timer marked "
898 "xHCI as DYING, exiting.");
899 spin_unlock_irqrestore(&xhci->lock, flags);
902 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
903 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
904 "Stop EP timer ran, but no command pending, "
906 spin_unlock_irqrestore(&xhci->lock, flags);
910 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
911 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
912 /* Oops, HC is dead or dying or at least not responding to the stop
915 xhci->xhc_state |= XHCI_STATE_DYING;
916 /* Disable interrupts from the host controller and start halting it */
918 spin_unlock_irqrestore(&xhci->lock, flags);
920 ret = xhci_halt(xhci);
922 spin_lock_irqsave(&xhci->lock, flags);
924 /* This is bad; the host is not responding to commands and it's
925 * not allowing itself to be halted. At least interrupts are
926 * disabled. If we call usb_hc_died(), it will attempt to
927 * disconnect all device drivers under this host. Those
928 * disconnect() methods will wait for all URBs to be unlinked,
929 * so we must complete them.
931 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
932 xhci_warn(xhci, "Completing active URBs anyway.\n");
933 /* We could turn all TDs on the rings to no-ops. This won't
934 * help if the host has cached part of the ring, and is slow if
935 * we want to preserve the cycle bit. Skip it and hope the host
936 * doesn't touch the memory.
939 for (i = 0; i < MAX_HC_SLOTS; i++) {
942 for (j = 0; j < 31; j++)
943 xhci_kill_endpoint_urbs(xhci, i, j);
945 spin_unlock_irqrestore(&xhci->lock, flags);
946 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
947 "Calling usb_hc_died()");
948 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
949 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
950 "xHCI host controller is dead.");
954 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
955 struct xhci_virt_device *dev,
956 struct xhci_ring *ep_ring,
957 unsigned int ep_index)
959 union xhci_trb *dequeue_temp;
960 int num_trbs_free_temp;
963 num_trbs_free_temp = ep_ring->num_trbs_free;
964 dequeue_temp = ep_ring->dequeue;
966 /* If we get two back-to-back stalls, and the first stalled transfer
967 * ends just before a link TRB, the dequeue pointer will be left on
968 * the link TRB by the code in the while loop. So we have to update
969 * the dequeue pointer one segment further, or we'll jump off
970 * the segment into la-la-land.
972 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
973 ep_ring->deq_seg = ep_ring->deq_seg->next;
974 ep_ring->dequeue = ep_ring->deq_seg->trbs;
977 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
978 /* We have more usable TRBs */
979 ep_ring->num_trbs_free++;
981 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
983 if (ep_ring->dequeue ==
984 dev->eps[ep_index].queued_deq_ptr)
986 ep_ring->deq_seg = ep_ring->deq_seg->next;
987 ep_ring->dequeue = ep_ring->deq_seg->trbs;
989 if (ep_ring->dequeue == dequeue_temp) {
996 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
997 ep_ring->num_trbs_free = num_trbs_free_temp;
1002 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1003 * we need to clear the set deq pending flag in the endpoint ring state, so that
1004 * the TD queueing code can ring the doorbell again. We also need to ring the
1005 * endpoint doorbell to restart the ring, but only if there aren't more
1006 * cancellations pending.
1008 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1009 union xhci_trb *trb, u32 cmd_comp_code)
1011 unsigned int ep_index;
1012 unsigned int stream_id;
1013 struct xhci_ring *ep_ring;
1014 struct xhci_virt_device *dev;
1015 struct xhci_virt_ep *ep;
1016 struct xhci_ep_ctx *ep_ctx;
1017 struct xhci_slot_ctx *slot_ctx;
1019 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1020 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1021 dev = xhci->devs[slot_id];
1022 ep = &dev->eps[ep_index];
1024 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1026 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1028 /* XXX: Harmless??? */
1029 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1033 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1034 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1036 if (cmd_comp_code != COMP_SUCCESS) {
1037 unsigned int ep_state;
1038 unsigned int slot_state;
1040 switch (cmd_comp_code) {
1042 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1044 case COMP_CTX_STATE:
1045 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1046 ep_state = le32_to_cpu(ep_ctx->ep_info);
1047 ep_state &= EP_STATE_MASK;
1048 slot_state = le32_to_cpu(slot_ctx->dev_state);
1049 slot_state = GET_SLOT_STATE(slot_state);
1050 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1051 "Slot state = %u, EP state = %u",
1052 slot_state, ep_state);
1055 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1059 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1063 /* OK what do we do now? The endpoint state is hosed, and we
1064 * should never get to this point if the synchronization between
1065 * queueing, and endpoint state are correct. This might happen
1066 * if the device gets disconnected after we've finished
1067 * cancelling URBs, which might not be an error...
1071 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1072 if (ep->ep_state & EP_HAS_STREAMS) {
1073 struct xhci_stream_ctx *ctx =
1074 &ep->stream_info->stream_ctx_array[stream_id];
1075 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1077 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1079 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1080 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1081 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1082 ep->queued_deq_ptr) == deq) {
1083 /* Update the ring's dequeue segment and dequeue pointer
1084 * to reflect the new position.
1086 update_ring_for_set_deq_completion(xhci, dev,
1089 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1090 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1091 ep->queued_deq_seg, ep->queued_deq_ptr);
1095 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1096 dev->eps[ep_index].queued_deq_seg = NULL;
1097 dev->eps[ep_index].queued_deq_ptr = NULL;
1098 /* Restart any rings with pending URBs */
1099 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1102 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1103 union xhci_trb *trb, u32 cmd_comp_code)
1105 unsigned int ep_index;
1107 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1108 /* This command will only fail if the endpoint wasn't halted,
1109 * but we don't care.
1111 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1112 "Ignoring reset ep completion code of %u", cmd_comp_code);
1114 /* HW with the reset endpoint quirk needs to have a configure endpoint
1115 * command complete before the endpoint can be used. Queue that here
1116 * because the HW can't handle two commands being queued in a row.
1118 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1119 struct xhci_command *command;
1120 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1121 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1122 "Queueing configure endpoint command");
1123 xhci_queue_configure_endpoint(xhci, command,
1124 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1126 xhci_ring_cmd_db(xhci);
1128 /* Clear our internal halted state and restart the ring(s) */
1129 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1130 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1134 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1137 if (cmd_comp_code == COMP_SUCCESS)
1138 xhci->slot_id = slot_id;
1143 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1145 struct xhci_virt_device *virt_dev;
1147 virt_dev = xhci->devs[slot_id];
1150 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1151 /* Delete default control endpoint resources */
1152 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1153 xhci_free_virt_device(xhci, slot_id);
1156 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1157 struct xhci_event_cmd *event, u32 cmd_comp_code)
1159 struct xhci_virt_device *virt_dev;
1160 struct xhci_input_control_ctx *ctrl_ctx;
1161 unsigned int ep_index;
1162 unsigned int ep_state;
1163 u32 add_flags, drop_flags;
1166 * Configure endpoint commands can come from the USB core
1167 * configuration or alt setting changes, or because the HW
1168 * needed an extra configure endpoint command after a reset
1169 * endpoint command or streams were being configured.
1170 * If the command was for a halted endpoint, the xHCI driver
1171 * is not waiting on the configure endpoint command.
1173 virt_dev = xhci->devs[slot_id];
1174 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1176 xhci_warn(xhci, "Could not get input context, bad type.\n");
1180 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1181 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1182 /* Input ctx add_flags are the endpoint index plus one */
1183 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1185 /* A usb_set_interface() call directly after clearing a halted
1186 * condition may race on this quirky hardware. Not worth
1187 * worrying about, since this is prototype hardware. Not sure
1188 * if this will work for streams, but streams support was
1189 * untested on this prototype.
1191 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1192 ep_index != (unsigned int) -1 &&
1193 add_flags - SLOT_FLAG == drop_flags) {
1194 ep_state = virt_dev->eps[ep_index].ep_state;
1195 if (!(ep_state & EP_HALTED))
1197 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1198 "Completed config ep cmd - "
1199 "last ep index = %d, state = %d",
1200 ep_index, ep_state);
1201 /* Clear internal halted state and restart ring(s) */
1202 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1203 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1209 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1210 struct xhci_event_cmd *event)
1212 xhci_dbg(xhci, "Completed reset device command.\n");
1213 if (!xhci->devs[slot_id])
1214 xhci_warn(xhci, "Reset device command completion "
1215 "for disabled slot %u\n", slot_id);
1218 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1219 struct xhci_event_cmd *event)
1221 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1222 xhci->error_bitmask |= 1 << 6;
1225 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1226 "NEC firmware version %2x.%02x",
1227 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1228 NEC_FW_MINOR(le32_to_cpu(event->status)));
1231 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1233 list_del(&cmd->cmd_list);
1235 if (cmd->completion) {
1236 cmd->status = status;
1237 complete(cmd->completion);
1243 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1245 struct xhci_command *cur_cmd, *tmp_cmd;
1246 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1247 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1251 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1252 * If there are other commands waiting then restart the ring and kick the timer.
1253 * This must be called with command ring stopped and xhci->lock held.
1255 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1256 struct xhci_command *cur_cmd)
1258 struct xhci_command *i_cmd, *tmp_cmd;
1261 /* Turn all aborted commands in list to no-ops, then restart */
1262 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1265 if (i_cmd->status != COMP_CMD_ABORT)
1268 i_cmd->status = COMP_CMD_STOP;
1270 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1271 i_cmd->command_trb);
1272 /* get cycle state from the original cmd trb */
1273 cycle_state = le32_to_cpu(
1274 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1275 /* modify the command trb to no-op command */
1276 i_cmd->command_trb->generic.field[0] = 0;
1277 i_cmd->command_trb->generic.field[1] = 0;
1278 i_cmd->command_trb->generic.field[2] = 0;
1279 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1280 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1283 * caller waiting for completion is called when command
1284 * completion event is received for these no-op commands
1288 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1290 /* ring command ring doorbell to restart the command ring */
1291 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1292 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1293 xhci->current_cmd = cur_cmd;
1294 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1295 xhci_ring_cmd_db(xhci);
1301 void xhci_handle_command_timeout(unsigned long data)
1303 struct xhci_hcd *xhci;
1305 unsigned long flags;
1307 struct xhci_command *cur_cmd = NULL;
1308 xhci = (struct xhci_hcd *) data;
1310 /* mark this command to be cancelled */
1311 spin_lock_irqsave(&xhci->lock, flags);
1312 if (xhci->current_cmd) {
1313 cur_cmd = xhci->current_cmd;
1314 cur_cmd->status = COMP_CMD_ABORT;
1318 /* Make sure command ring is running before aborting it */
1319 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1320 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1321 (hw_ring_state & CMD_RING_RUNNING)) {
1323 spin_unlock_irqrestore(&xhci->lock, flags);
1324 xhci_dbg(xhci, "Command timeout\n");
1325 ret = xhci_abort_cmd_ring(xhci);
1326 if (unlikely(ret == -ESHUTDOWN)) {
1327 xhci_err(xhci, "Abort command ring failed\n");
1328 xhci_cleanup_command_queue(xhci);
1329 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1330 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1334 /* command timeout on stopped ring, ring can't be aborted */
1335 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1336 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1337 spin_unlock_irqrestore(&xhci->lock, flags);
1341 static void handle_cmd_completion(struct xhci_hcd *xhci,
1342 struct xhci_event_cmd *event)
1344 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1346 dma_addr_t cmd_dequeue_dma;
1348 union xhci_trb *cmd_trb;
1349 struct xhci_command *cmd;
1352 cmd_dma = le64_to_cpu(event->cmd_trb);
1353 cmd_trb = xhci->cmd_ring->dequeue;
1354 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1356 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1357 if (cmd_dequeue_dma == 0) {
1358 xhci->error_bitmask |= 1 << 4;
1361 /* Does the DMA address match our internal dequeue pointer address? */
1362 if (cmd_dma != (u64) cmd_dequeue_dma) {
1363 xhci->error_bitmask |= 1 << 5;
1367 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1369 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1371 "Command completion event does not match command\n");
1375 del_timer(&xhci->cmd_timer);
1377 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1379 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1381 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1382 if (cmd_comp_code == COMP_CMD_STOP) {
1383 xhci_handle_stopped_cmd_ring(xhci, cmd);
1387 * Host aborted the command ring, check if the current command was
1388 * supposed to be aborted, otherwise continue normally.
1389 * The command ring is stopped now, but the xHC will issue a Command
1390 * Ring Stopped event which will cause us to restart it.
1392 if (cmd_comp_code == COMP_CMD_ABORT) {
1393 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1394 if (cmd->status == COMP_CMD_ABORT)
1398 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1400 case TRB_ENABLE_SLOT:
1401 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1403 case TRB_DISABLE_SLOT:
1404 xhci_handle_cmd_disable_slot(xhci, slot_id);
1407 if (!cmd->completion)
1408 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1411 case TRB_EVAL_CONTEXT:
1416 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1417 le32_to_cpu(cmd_trb->generic.field[3])));
1418 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1421 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1422 le32_to_cpu(cmd_trb->generic.field[3])));
1423 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1426 /* Is this an aborted command turned to NO-OP? */
1427 if (cmd->status == COMP_CMD_STOP)
1428 cmd_comp_code = COMP_CMD_STOP;
1431 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1432 le32_to_cpu(cmd_trb->generic.field[3])));
1433 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1436 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1437 le32_to_cpu(cmd_trb->generic.field[3])));
1438 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1440 case TRB_NEC_GET_FW:
1441 xhci_handle_cmd_nec_get_fw(xhci, event);
1444 /* Skip over unknown commands on the event ring */
1445 xhci->error_bitmask |= 1 << 6;
1449 /* restart timer if this wasn't the last command */
1450 if (cmd->cmd_list.next != &xhci->cmd_list) {
1451 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1452 struct xhci_command, cmd_list);
1453 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1457 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1459 inc_deq(xhci, xhci->cmd_ring);
1462 static void handle_vendor_event(struct xhci_hcd *xhci,
1463 union xhci_trb *event)
1467 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1468 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1469 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1470 handle_cmd_completion(xhci, &event->event_cmd);
1473 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1474 * port registers -- USB 3.0 and USB 2.0).
1476 * Returns a zero-based port number, which is suitable for indexing into each of
1477 * the split roothubs' port arrays and bus state arrays.
1478 * Add one to it in order to call xhci_find_slot_id_by_port.
1480 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1481 struct xhci_hcd *xhci, u32 port_id)
1484 unsigned int num_similar_speed_ports = 0;
1486 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1487 * and usb2_ports are 0-based indexes. Count the number of similar
1488 * speed ports, up to 1 port before this port.
1490 for (i = 0; i < (port_id - 1); i++) {
1491 u8 port_speed = xhci->port_array[i];
1494 * Skip ports that don't have known speeds, or have duplicate
1495 * Extended Capabilities port speed entries.
1497 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1501 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1502 * 1.1 ports are under the USB 2.0 hub. If the port speed
1503 * matches the device speed, it's a similar speed port.
1505 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1506 num_similar_speed_ports++;
1508 return num_similar_speed_ports;
1511 static void handle_device_notification(struct xhci_hcd *xhci,
1512 union xhci_trb *event)
1515 struct usb_device *udev;
1517 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1518 if (!xhci->devs[slot_id]) {
1519 xhci_warn(xhci, "Device Notification event for "
1520 "unused slot %u\n", slot_id);
1524 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1526 udev = xhci->devs[slot_id]->udev;
1527 if (udev && udev->parent)
1528 usb_wakeup_notification(udev->parent, udev->portnum);
1531 static void handle_port_status(struct xhci_hcd *xhci,
1532 union xhci_trb *event)
1534 struct usb_hcd *hcd;
1539 unsigned int faked_port_index;
1541 struct xhci_bus_state *bus_state;
1542 __le32 __iomem **port_array;
1543 bool bogus_port_status = false;
1545 /* Port status change events always have a successful completion code */
1546 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1547 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1548 xhci->error_bitmask |= 1 << 8;
1550 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1551 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1553 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1554 if ((port_id <= 0) || (port_id > max_ports)) {
1555 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1556 inc_deq(xhci, xhci->event_ring);
1560 /* Figure out which usb_hcd this port is attached to:
1561 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1563 major_revision = xhci->port_array[port_id - 1];
1565 /* Find the right roothub. */
1566 hcd = xhci_to_hcd(xhci);
1567 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1568 hcd = xhci->shared_hcd;
1570 if (major_revision == 0) {
1571 xhci_warn(xhci, "Event for port %u not in "
1572 "Extended Capabilities, ignoring.\n",
1574 bogus_port_status = true;
1577 if (major_revision == DUPLICATE_ENTRY) {
1578 xhci_warn(xhci, "Event for port %u duplicated in"
1579 "Extended Capabilities, ignoring.\n",
1581 bogus_port_status = true;
1586 * Hardware port IDs reported by a Port Status Change Event include USB
1587 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1588 * resume event, but we first need to translate the hardware port ID
1589 * into the index into the ports on the correct split roothub, and the
1590 * correct bus_state structure.
1592 bus_state = &xhci->bus_state[hcd_index(hcd)];
1593 if (hcd->speed == HCD_USB3)
1594 port_array = xhci->usb3_ports;
1596 port_array = xhci->usb2_ports;
1597 /* Find the faked port hub number */
1598 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1601 temp = readl(port_array[faked_port_index]);
1602 if (hcd->state == HC_STATE_SUSPENDED) {
1603 xhci_dbg(xhci, "resume root hub\n");
1604 usb_hcd_resume_root_hub(hcd);
1607 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1608 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1610 temp1 = readl(&xhci->op_regs->command);
1611 if (!(temp1 & CMD_RUN)) {
1612 xhci_warn(xhci, "xHC is not running.\n");
1616 if (DEV_SUPERSPEED(temp)) {
1617 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1618 /* Set a flag to say the port signaled remote wakeup,
1619 * so we can tell the difference between the end of
1620 * device and host initiated resume.
1622 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1623 xhci_test_and_clear_bit(xhci, port_array,
1624 faked_port_index, PORT_PLC);
1625 xhci_set_link_state(xhci, port_array, faked_port_index,
1627 /* Need to wait until the next link state change
1628 * indicates the device is actually in U0.
1630 bogus_port_status = true;
1633 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1634 bus_state->resume_done[faked_port_index] = jiffies +
1635 msecs_to_jiffies(20);
1636 set_bit(faked_port_index, &bus_state->resuming_ports);
1637 mod_timer(&hcd->rh_timer,
1638 bus_state->resume_done[faked_port_index]);
1639 /* Do the rest in GetPortStatus */
1643 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1644 DEV_SUPERSPEED(temp)) {
1645 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1646 /* We've just brought the device into U0 through either the
1647 * Resume state after a device remote wakeup, or through the
1648 * U3Exit state after a host-initiated resume. If it's a device
1649 * initiated remote wake, don't pass up the link state change,
1650 * so the roothub behavior is consistent with external
1651 * USB 3.0 hub behavior.
1653 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1654 faked_port_index + 1);
1655 if (slot_id && xhci->devs[slot_id])
1656 xhci_ring_device(xhci, slot_id);
1657 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1658 bus_state->port_remote_wakeup &=
1659 ~(1 << faked_port_index);
1660 xhci_test_and_clear_bit(xhci, port_array,
1661 faked_port_index, PORT_PLC);
1662 usb_wakeup_notification(hcd->self.root_hub,
1663 faked_port_index + 1);
1664 bogus_port_status = true;
1670 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1671 * RExit to a disconnect state). If so, let the the driver know it's
1672 * out of the RExit state.
1674 if (!DEV_SUPERSPEED(temp) &&
1675 test_and_clear_bit(faked_port_index,
1676 &bus_state->rexit_ports)) {
1677 complete(&bus_state->rexit_done[faked_port_index]);
1678 bogus_port_status = true;
1682 if (hcd->speed != HCD_USB3)
1683 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1687 /* Update event ring dequeue pointer before dropping the lock */
1688 inc_deq(xhci, xhci->event_ring);
1690 /* Don't make the USB core poll the roothub if we got a bad port status
1691 * change event. Besides, at that point we can't tell which roothub
1692 * (USB 2.0 or USB 3.0) to kick.
1694 if (bogus_port_status)
1698 * xHCI port-status-change events occur when the "or" of all the
1699 * status-change bits in the portsc register changes from 0 to 1.
1700 * New status changes won't cause an event if any other change
1701 * bits are still set. When an event occurs, switch over to
1702 * polling to avoid losing status changes.
1704 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1705 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1706 spin_unlock(&xhci->lock);
1707 /* Pass this up to the core */
1708 usb_hcd_poll_rh_status(hcd);
1709 spin_lock(&xhci->lock);
1713 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1714 * at end_trb, which may be in another segment. If the suspect DMA address is a
1715 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1718 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1719 union xhci_trb *start_trb,
1720 union xhci_trb *end_trb,
1721 dma_addr_t suspect_dma)
1723 dma_addr_t start_dma;
1724 dma_addr_t end_seg_dma;
1725 dma_addr_t end_trb_dma;
1726 struct xhci_segment *cur_seg;
1728 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1729 cur_seg = start_seg;
1734 /* We may get an event for a Link TRB in the middle of a TD */
1735 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1736 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1737 /* If the end TRB isn't in this segment, this is set to 0 */
1738 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1740 if (end_trb_dma > 0) {
1741 /* The end TRB is in this segment, so suspect should be here */
1742 if (start_dma <= end_trb_dma) {
1743 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1746 /* Case for one segment with
1747 * a TD wrapped around to the top
1749 if ((suspect_dma >= start_dma &&
1750 suspect_dma <= end_seg_dma) ||
1751 (suspect_dma >= cur_seg->dma &&
1752 suspect_dma <= end_trb_dma))
1757 /* Might still be somewhere in this segment */
1758 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1761 cur_seg = cur_seg->next;
1762 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1763 } while (cur_seg != start_seg);
1768 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1769 unsigned int slot_id, unsigned int ep_index,
1770 unsigned int stream_id,
1771 struct xhci_td *td, union xhci_trb *event_trb)
1773 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1774 struct xhci_command *command;
1775 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1779 ep->ep_state |= EP_HALTED;
1780 ep->stopped_td = td;
1781 ep->stopped_stream = stream_id;
1783 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1784 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1786 ep->stopped_td = NULL;
1787 ep->stopped_stream = 0;
1789 xhci_ring_cmd_db(xhci);
1792 /* Check if an error has halted the endpoint ring. The class driver will
1793 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1794 * However, a babble and other errors also halt the endpoint ring, and the class
1795 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1796 * Ring Dequeue Pointer command manually.
1798 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1799 struct xhci_ep_ctx *ep_ctx,
1800 unsigned int trb_comp_code)
1802 /* TRB completion codes that may require a manual halt cleanup */
1803 if (trb_comp_code == COMP_TX_ERR ||
1804 trb_comp_code == COMP_BABBLE ||
1805 trb_comp_code == COMP_SPLIT_ERR)
1806 /* The 0.96 spec says a babbling control endpoint
1807 * is not halted. The 0.96 spec says it is. Some HW
1808 * claims to be 0.95 compliant, but it halts the control
1809 * endpoint anyway. Check if a babble halted the
1812 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1813 cpu_to_le32(EP_STATE_HALTED))
1819 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1821 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1822 /* Vendor defined "informational" completion code,
1823 * treat as not-an-error.
1825 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1827 xhci_dbg(xhci, "Treating code as success.\n");
1834 * Finish the td processing, remove the td from td list;
1835 * Return 1 if the urb can be given back.
1837 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1838 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1839 struct xhci_virt_ep *ep, int *status, bool skip)
1841 struct xhci_virt_device *xdev;
1842 struct xhci_ring *ep_ring;
1843 unsigned int slot_id;
1845 struct urb *urb = NULL;
1846 struct xhci_ep_ctx *ep_ctx;
1848 struct urb_priv *urb_priv;
1851 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1852 xdev = xhci->devs[slot_id];
1853 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1854 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1855 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1856 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1861 if (trb_comp_code == COMP_STOP_INVAL ||
1862 trb_comp_code == COMP_STOP) {
1863 /* The Endpoint Stop Command completion will take care of any
1864 * stopped TDs. A stopped TD may be restarted, so don't update
1865 * the ring dequeue pointer or take this TD off any lists yet.
1867 ep->stopped_td = td;
1870 if (trb_comp_code == COMP_STALL) {
1871 /* The transfer is completed from the driver's
1872 * perspective, but we need to issue a set dequeue
1873 * command for this stalled endpoint to move the dequeue
1874 * pointer past the TD. We can't do that here because
1875 * the halt condition must be cleared first. Let the
1876 * USB class driver clear the stall later.
1878 ep->stopped_td = td;
1879 ep->stopped_stream = ep_ring->stream_id;
1880 } else if (xhci_requires_manual_halt_cleanup(xhci,
1881 ep_ctx, trb_comp_code)) {
1882 /* Other types of errors halt the endpoint, but the
1883 * class driver doesn't call usb_reset_endpoint() unless
1884 * the error is -EPIPE. Clear the halted status in the
1885 * xHCI hardware manually.
1887 xhci_cleanup_halted_endpoint(xhci,
1888 slot_id, ep_index, ep_ring->stream_id,
1891 /* Update ring dequeue pointer */
1892 while (ep_ring->dequeue != td->last_trb)
1893 inc_deq(xhci, ep_ring);
1894 inc_deq(xhci, ep_ring);
1898 /* Clean up the endpoint's TD list */
1900 urb_priv = urb->hcpriv;
1902 /* Do one last check of the actual transfer length.
1903 * If the host controller said we transferred more data than
1904 * the buffer length, urb->actual_length will be a very big
1905 * number (since it's unsigned). Play it safe and say we didn't
1906 * transfer anything.
1908 if (urb->actual_length > urb->transfer_buffer_length) {
1909 xhci_warn(xhci, "URB transfer length is wrong, "
1910 "xHC issue? req. len = %u, "
1912 urb->transfer_buffer_length,
1913 urb->actual_length);
1914 urb->actual_length = 0;
1915 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1916 *status = -EREMOTEIO;
1920 list_del_init(&td->td_list);
1921 /* Was this TD slated to be cancelled but completed anyway? */
1922 if (!list_empty(&td->cancelled_td_list))
1923 list_del_init(&td->cancelled_td_list);
1926 /* Giveback the urb when all the tds are completed */
1927 if (urb_priv->td_cnt == urb_priv->length) {
1929 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1930 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1931 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1933 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1934 usb_amd_quirk_pll_enable();
1944 * Process control tds, update urb status and actual_length.
1946 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1947 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1948 struct xhci_virt_ep *ep, int *status)
1950 struct xhci_virt_device *xdev;
1951 struct xhci_ring *ep_ring;
1952 unsigned int slot_id;
1954 struct xhci_ep_ctx *ep_ctx;
1957 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1958 xdev = xhci->devs[slot_id];
1959 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1960 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1961 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1962 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1964 switch (trb_comp_code) {
1966 if (event_trb == ep_ring->dequeue) {
1967 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1968 "without IOC set??\n");
1969 *status = -ESHUTDOWN;
1970 } else if (event_trb != td->last_trb) {
1971 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1972 "without IOC set??\n");
1973 *status = -ESHUTDOWN;
1979 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1980 *status = -EREMOTEIO;
1984 case COMP_STOP_INVAL:
1986 return finish_td(xhci, td, event_trb, event, ep, status, false);
1988 if (!xhci_requires_manual_halt_cleanup(xhci,
1989 ep_ctx, trb_comp_code))
1991 xhci_dbg(xhci, "TRB error code %u, "
1992 "halted endpoint index = %u\n",
1993 trb_comp_code, ep_index);
1994 /* else fall through */
1996 /* Did we transfer part of the data (middle) phase? */
1997 if (event_trb != ep_ring->dequeue &&
1998 event_trb != td->last_trb)
1999 td->urb->actual_length =
2000 td->urb->transfer_buffer_length -
2001 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2003 td->urb->actual_length = 0;
2005 xhci_cleanup_halted_endpoint(xhci,
2006 slot_id, ep_index, 0, td, event_trb);
2007 return finish_td(xhci, td, event_trb, event, ep, status, true);
2010 * Did we transfer any data, despite the errors that might have
2011 * happened? I.e. did we get past the setup stage?
2013 if (event_trb != ep_ring->dequeue) {
2014 /* The event was for the status stage */
2015 if (event_trb == td->last_trb) {
2016 if (td->urb->actual_length != 0) {
2017 /* Don't overwrite a previously set error code
2019 if ((*status == -EINPROGRESS || *status == 0) &&
2020 (td->urb->transfer_flags
2021 & URB_SHORT_NOT_OK))
2022 /* Did we already see a short data
2024 *status = -EREMOTEIO;
2026 td->urb->actual_length =
2027 td->urb->transfer_buffer_length;
2030 /* Maybe the event was for the data stage? */
2031 td->urb->actual_length =
2032 td->urb->transfer_buffer_length -
2033 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2034 xhci_dbg(xhci, "Waiting for status "
2040 return finish_td(xhci, td, event_trb, event, ep, status, false);
2044 * Process isochronous tds, update urb packet status and actual_length.
2046 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2047 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2048 struct xhci_virt_ep *ep, int *status)
2050 struct xhci_ring *ep_ring;
2051 struct urb_priv *urb_priv;
2054 union xhci_trb *cur_trb;
2055 struct xhci_segment *cur_seg;
2056 struct usb_iso_packet_descriptor *frame;
2058 bool skip_td = false;
2060 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2061 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2062 urb_priv = td->urb->hcpriv;
2063 idx = urb_priv->td_cnt;
2064 frame = &td->urb->iso_frame_desc[idx];
2066 /* handle completion code */
2067 switch (trb_comp_code) {
2069 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2073 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2074 trb_comp_code = COMP_SHORT_TX;
2076 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2080 frame->status = -ECOMM;
2083 case COMP_BUFF_OVER:
2085 frame->status = -EOVERFLOW;
2091 frame->status = -EPROTO;
2095 case COMP_STOP_INVAL:
2102 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2103 frame->actual_length = frame->length;
2104 td->urb->actual_length += frame->length;
2106 for (cur_trb = ep_ring->dequeue,
2107 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2108 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2109 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2110 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2111 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2113 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2114 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2116 if (trb_comp_code != COMP_STOP_INVAL) {
2117 frame->actual_length = len;
2118 td->urb->actual_length += len;
2122 return finish_td(xhci, td, event_trb, event, ep, status, false);
2125 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2126 struct xhci_transfer_event *event,
2127 struct xhci_virt_ep *ep, int *status)
2129 struct xhci_ring *ep_ring;
2130 struct urb_priv *urb_priv;
2131 struct usb_iso_packet_descriptor *frame;
2134 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2135 urb_priv = td->urb->hcpriv;
2136 idx = urb_priv->td_cnt;
2137 frame = &td->urb->iso_frame_desc[idx];
2139 /* The transfer is partly done. */
2140 frame->status = -EXDEV;
2142 /* calc actual length */
2143 frame->actual_length = 0;
2145 /* Update ring dequeue pointer */
2146 while (ep_ring->dequeue != td->last_trb)
2147 inc_deq(xhci, ep_ring);
2148 inc_deq(xhci, ep_ring);
2150 return finish_td(xhci, td, NULL, event, ep, status, true);
2154 * Process bulk and interrupt tds, update urb status and actual_length.
2156 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2157 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2158 struct xhci_virt_ep *ep, int *status)
2160 struct xhci_ring *ep_ring;
2161 union xhci_trb *cur_trb;
2162 struct xhci_segment *cur_seg;
2165 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2166 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2168 switch (trb_comp_code) {
2170 /* Double check that the HW transferred everything. */
2171 if (event_trb != td->last_trb ||
2172 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2173 xhci_warn(xhci, "WARN Successful completion "
2175 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2176 *status = -EREMOTEIO;
2179 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2180 trb_comp_code = COMP_SHORT_TX;
2186 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2187 *status = -EREMOTEIO;
2192 /* Others already handled above */
2195 if (trb_comp_code == COMP_SHORT_TX)
2196 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2197 "%d bytes untransferred\n",
2198 td->urb->ep->desc.bEndpointAddress,
2199 td->urb->transfer_buffer_length,
2200 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2201 /* Fast path - was this the last TRB in the TD for this URB? */
2202 if (event_trb == td->last_trb) {
2203 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2204 td->urb->actual_length =
2205 td->urb->transfer_buffer_length -
2206 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2207 if (td->urb->transfer_buffer_length <
2208 td->urb->actual_length) {
2209 xhci_warn(xhci, "HC gave bad length "
2210 "of %d bytes left\n",
2211 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2212 td->urb->actual_length = 0;
2213 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2214 *status = -EREMOTEIO;
2218 /* Don't overwrite a previously set error code */
2219 if (*status == -EINPROGRESS) {
2220 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2221 *status = -EREMOTEIO;
2226 td->urb->actual_length =
2227 td->urb->transfer_buffer_length;
2228 /* Ignore a short packet completion if the
2229 * untransferred length was zero.
2231 if (*status == -EREMOTEIO)
2235 /* Slow path - walk the list, starting from the dequeue
2236 * pointer, to get the actual length transferred.
2238 td->urb->actual_length = 0;
2239 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2240 cur_trb != event_trb;
2241 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2242 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2243 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2244 td->urb->actual_length +=
2245 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2247 /* If the ring didn't stop on a Link or No-op TRB, add
2248 * in the actual bytes transferred from the Normal TRB
2250 if (trb_comp_code != COMP_STOP_INVAL)
2251 td->urb->actual_length +=
2252 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2253 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2256 return finish_td(xhci, td, event_trb, event, ep, status, false);
2260 * If this function returns an error condition, it means it got a Transfer
2261 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2262 * At this point, the host controller is probably hosed and should be reset.
2264 static int handle_tx_event(struct xhci_hcd *xhci,
2265 struct xhci_transfer_event *event)
2266 __releases(&xhci->lock)
2267 __acquires(&xhci->lock)
2269 struct xhci_virt_device *xdev;
2270 struct xhci_virt_ep *ep;
2271 struct xhci_ring *ep_ring;
2272 unsigned int slot_id;
2274 struct xhci_td *td = NULL;
2275 dma_addr_t event_dma;
2276 struct xhci_segment *event_seg;
2277 union xhci_trb *event_trb;
2278 struct urb *urb = NULL;
2279 int status = -EINPROGRESS;
2280 struct urb_priv *urb_priv;
2281 struct xhci_ep_ctx *ep_ctx;
2282 struct list_head *tmp;
2287 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2288 xdev = xhci->devs[slot_id];
2290 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2291 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2292 (unsigned long long) xhci_trb_virt_to_dma(
2293 xhci->event_ring->deq_seg,
2294 xhci->event_ring->dequeue),
2295 lower_32_bits(le64_to_cpu(event->buffer)),
2296 upper_32_bits(le64_to_cpu(event->buffer)),
2297 le32_to_cpu(event->transfer_len),
2298 le32_to_cpu(event->flags));
2299 xhci_dbg(xhci, "Event ring:\n");
2300 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2304 /* Endpoint ID is 1 based, our index is zero based */
2305 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2306 ep = &xdev->eps[ep_index];
2307 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2308 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2310 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2311 EP_STATE_DISABLED) {
2312 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2313 "or incorrect stream ring\n");
2314 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2315 (unsigned long long) xhci_trb_virt_to_dma(
2316 xhci->event_ring->deq_seg,
2317 xhci->event_ring->dequeue),
2318 lower_32_bits(le64_to_cpu(event->buffer)),
2319 upper_32_bits(le64_to_cpu(event->buffer)),
2320 le32_to_cpu(event->transfer_len),
2321 le32_to_cpu(event->flags));
2322 xhci_dbg(xhci, "Event ring:\n");
2323 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2327 /* Count current td numbers if ep->skip is set */
2329 list_for_each(tmp, &ep_ring->td_list)
2333 event_dma = le64_to_cpu(event->buffer);
2334 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2335 /* Look for common error cases */
2336 switch (trb_comp_code) {
2337 /* Skip codes that require special handling depending on
2341 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2343 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2344 trb_comp_code = COMP_SHORT_TX;
2346 xhci_warn_ratelimited(xhci,
2347 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2351 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2353 case COMP_STOP_INVAL:
2354 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2357 xhci_dbg(xhci, "Stalled endpoint\n");
2358 ep->ep_state |= EP_HALTED;
2362 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2365 case COMP_SPLIT_ERR:
2367 xhci_dbg(xhci, "Transfer error on endpoint\n");
2371 xhci_dbg(xhci, "Babble error on endpoint\n");
2372 status = -EOVERFLOW;
2375 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2379 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2381 case COMP_BUFF_OVER:
2382 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2386 * When the Isoch ring is empty, the xHC will generate
2387 * a Ring Overrun Event for IN Isoch endpoint or Ring
2388 * Underrun Event for OUT Isoch endpoint.
2390 xhci_dbg(xhci, "underrun event on endpoint\n");
2391 if (!list_empty(&ep_ring->td_list))
2392 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2393 "still with TDs queued?\n",
2394 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2398 xhci_dbg(xhci, "overrun event on endpoint\n");
2399 if (!list_empty(&ep_ring->td_list))
2400 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2401 "still with TDs queued?\n",
2402 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2406 xhci_warn(xhci, "WARN: detect an incompatible device");
2409 case COMP_MISSED_INT:
2411 * When encounter missed service error, one or more isoc tds
2412 * may be missed by xHC.
2413 * Set skip flag of the ep_ring; Complete the missed tds as
2414 * short transfer when process the ep_ring next time.
2417 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2420 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2424 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2430 /* This TRB should be in the TD at the head of this ring's
2433 if (list_empty(&ep_ring->td_list)) {
2435 * A stopped endpoint may generate an extra completion
2436 * event if the device was suspended. Don't print
2439 if (!(trb_comp_code == COMP_STOP ||
2440 trb_comp_code == COMP_STOP_INVAL)) {
2441 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2442 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2444 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2445 (le32_to_cpu(event->flags) &
2446 TRB_TYPE_BITMASK)>>10);
2447 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2451 xhci_dbg(xhci, "td_list is empty while skip "
2452 "flag set. Clear skip flag.\n");
2458 /* We've skipped all the TDs on the ep ring when ep->skip set */
2459 if (ep->skip && td_num == 0) {
2461 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2462 "Clear skip flag.\n");
2467 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2471 /* Is this a TRB in the currently executing TD? */
2472 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2473 td->last_trb, event_dma);
2476 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2477 * is not in the current TD pointed by ep_ring->dequeue because
2478 * that the hardware dequeue pointer still at the previous TRB
2479 * of the current TD. The previous TRB maybe a Link TD or the
2480 * last TRB of the previous TD. The command completion handle
2481 * will take care the rest.
2483 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2490 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2491 /* Some host controllers give a spurious
2492 * successful event after a short transfer.
2495 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2496 ep_ring->last_td_was_short) {
2497 ep_ring->last_td_was_short = false;
2501 /* HC is busted, give up! */
2503 "ERROR Transfer event TRB DMA ptr not "
2504 "part of current TD\n");
2508 ret = skip_isoc_td(xhci, td, event, ep, &status);
2511 if (trb_comp_code == COMP_SHORT_TX)
2512 ep_ring->last_td_was_short = true;
2514 ep_ring->last_td_was_short = false;
2517 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2521 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2522 sizeof(*event_trb)];
2524 * No-op TRB should not trigger interrupts.
2525 * If event_trb is a no-op TRB, it means the
2526 * corresponding TD has been cancelled. Just ignore
2529 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2531 "event_trb is a no-op TRB. Skip it\n");
2535 /* Now update the urb's actual_length and give back to
2538 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2539 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2541 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2542 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2545 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2550 * Do not update event ring dequeue pointer if ep->skip is set.
2551 * Will roll back to continue process missed tds.
2553 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2554 inc_deq(xhci, xhci->event_ring);
2559 urb_priv = urb->hcpriv;
2560 /* Leave the TD around for the reset endpoint function
2561 * to use(but only if it's not a control endpoint,
2562 * since we already queued the Set TR dequeue pointer
2563 * command for stalled control endpoints).
2565 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2566 (trb_comp_code != COMP_STALL &&
2567 trb_comp_code != COMP_BABBLE))
2568 xhci_urb_free_priv(xhci, urb_priv);
2572 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2573 if ((urb->actual_length != urb->transfer_buffer_length &&
2574 (urb->transfer_flags &
2575 URB_SHORT_NOT_OK)) ||
2577 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2578 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2579 "expected = %d, status = %d\n",
2580 urb, urb->actual_length,
2581 urb->transfer_buffer_length,
2583 spin_unlock(&xhci->lock);
2584 /* EHCI, UHCI, and OHCI always unconditionally set the
2585 * urb->status of an isochronous endpoint to 0.
2587 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2589 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2590 spin_lock(&xhci->lock);
2594 * If ep->skip is set, it means there are missed tds on the
2595 * endpoint ring need to take care of.
2596 * Process them as short transfer until reach the td pointed by
2599 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2605 * This function handles all OS-owned events on the event ring. It may drop
2606 * xhci->lock between event processing (e.g. to pass up port status changes).
2607 * Returns >0 for "possibly more events to process" (caller should call again),
2608 * otherwise 0 if done. In future, <0 returns should indicate error code.
2610 static int xhci_handle_event(struct xhci_hcd *xhci)
2612 union xhci_trb *event;
2613 int update_ptrs = 1;
2616 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2617 xhci->error_bitmask |= 1 << 1;
2621 event = xhci->event_ring->dequeue;
2622 /* Does the HC or OS own the TRB? */
2623 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2624 xhci->event_ring->cycle_state) {
2625 xhci->error_bitmask |= 1 << 2;
2630 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2631 * speculative reads of the event's flags/data below.
2634 /* FIXME: Handle more event types. */
2635 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2636 case TRB_TYPE(TRB_COMPLETION):
2637 handle_cmd_completion(xhci, &event->event_cmd);
2639 case TRB_TYPE(TRB_PORT_STATUS):
2640 handle_port_status(xhci, event);
2643 case TRB_TYPE(TRB_TRANSFER):
2644 ret = handle_tx_event(xhci, &event->trans_event);
2646 xhci->error_bitmask |= 1 << 9;
2650 case TRB_TYPE(TRB_DEV_NOTE):
2651 handle_device_notification(xhci, event);
2654 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2656 handle_vendor_event(xhci, event);
2658 xhci->error_bitmask |= 1 << 3;
2660 /* Any of the above functions may drop and re-acquire the lock, so check
2661 * to make sure a watchdog timer didn't mark the host as non-responsive.
2663 if (xhci->xhc_state & XHCI_STATE_DYING) {
2664 xhci_dbg(xhci, "xHCI host dying, returning from "
2665 "event handler.\n");
2670 /* Update SW event ring dequeue pointer */
2671 inc_deq(xhci, xhci->event_ring);
2673 /* Are there more items on the event ring? Caller will call us again to
2680 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2681 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2682 * indicators of an event TRB error, but we check the status *first* to be safe.
2684 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2686 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2689 union xhci_trb *event_ring_deq;
2692 spin_lock(&xhci->lock);
2693 /* Check if the xHC generated the interrupt, or the irq is shared */
2694 status = readl(&xhci->op_regs->status);
2695 if (status == 0xffffffff)
2698 if (!(status & STS_EINT)) {
2699 spin_unlock(&xhci->lock);
2702 if (status & STS_FATAL) {
2703 xhci_warn(xhci, "WARNING: Host System Error\n");
2706 spin_unlock(&xhci->lock);
2711 * Clear the op reg interrupt status first,
2712 * so we can receive interrupts from other MSI-X interrupters.
2713 * Write 1 to clear the interrupt status.
2716 writel(status, &xhci->op_regs->status);
2717 /* FIXME when MSI-X is supported and there are multiple vectors */
2718 /* Clear the MSI-X event interrupt status */
2722 /* Acknowledge the PCI interrupt */
2723 irq_pending = readl(&xhci->ir_set->irq_pending);
2724 irq_pending |= IMAN_IP;
2725 writel(irq_pending, &xhci->ir_set->irq_pending);
2728 if (xhci->xhc_state & XHCI_STATE_DYING) {
2729 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2730 "Shouldn't IRQs be disabled?\n");
2731 /* Clear the event handler busy flag (RW1C);
2732 * the event ring should be empty.
2734 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2735 xhci_write_64(xhci, temp_64 | ERST_EHB,
2736 &xhci->ir_set->erst_dequeue);
2737 spin_unlock(&xhci->lock);
2742 event_ring_deq = xhci->event_ring->dequeue;
2743 /* FIXME this should be a delayed service routine
2744 * that clears the EHB.
2746 while (xhci_handle_event(xhci) > 0) {}
2748 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2749 /* If necessary, update the HW's version of the event ring deq ptr. */
2750 if (event_ring_deq != xhci->event_ring->dequeue) {
2751 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2752 xhci->event_ring->dequeue);
2754 xhci_warn(xhci, "WARN something wrong with SW event "
2755 "ring dequeue ptr.\n");
2756 /* Update HC event ring dequeue pointer */
2757 temp_64 &= ERST_PTR_MASK;
2758 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2761 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2762 temp_64 |= ERST_EHB;
2763 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2765 spin_unlock(&xhci->lock);
2770 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2772 return xhci_irq(hcd);
2775 /**** Endpoint Ring Operations ****/
2778 * Generic function for queueing a TRB on a ring.
2779 * The caller must have checked to make sure there's room on the ring.
2781 * @more_trbs_coming: Will you enqueue more TRBs before calling
2782 * prepare_transfer()?
2784 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2785 bool more_trbs_coming,
2786 u32 field1, u32 field2, u32 field3, u32 field4)
2788 struct xhci_generic_trb *trb;
2790 trb = &ring->enqueue->generic;
2791 trb->field[0] = cpu_to_le32(field1);
2792 trb->field[1] = cpu_to_le32(field2);
2793 trb->field[2] = cpu_to_le32(field3);
2794 trb->field[3] = cpu_to_le32(field4);
2795 inc_enq(xhci, ring, more_trbs_coming);
2799 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2800 * FIXME allocate segments if the ring is full.
2802 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2803 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2805 unsigned int num_trbs_needed;
2807 /* Make sure the endpoint has been added to xHC schedule */
2809 case EP_STATE_DISABLED:
2811 * USB core changed config/interfaces without notifying us,
2812 * or hardware is reporting the wrong state.
2814 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2816 case EP_STATE_ERROR:
2817 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2818 /* FIXME event handling code for error needs to clear it */
2819 /* XXX not sure if this should be -ENOENT or not */
2821 case EP_STATE_HALTED:
2822 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2823 case EP_STATE_STOPPED:
2824 case EP_STATE_RUNNING:
2827 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2829 * FIXME issue Configure Endpoint command to try to get the HC
2830 * back into a known state.
2836 if (room_on_ring(xhci, ep_ring, num_trbs))
2839 if (ep_ring == xhci->cmd_ring) {
2840 xhci_err(xhci, "Do not support expand command ring\n");
2844 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2845 "ERROR no room on ep ring, try ring expansion");
2846 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2847 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2849 xhci_err(xhci, "Ring expansion failed\n");
2854 if (enqueue_is_link_trb(ep_ring)) {
2855 struct xhci_ring *ring = ep_ring;
2856 union xhci_trb *next;
2858 next = ring->enqueue;
2860 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2861 /* If we're not dealing with 0.95 hardware or isoc rings
2862 * on AMD 0.96 host, clear the chain bit.
2864 if (!xhci_link_trb_quirk(xhci) &&
2865 !(ring->type == TYPE_ISOC &&
2866 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2867 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2869 next->link.control |= cpu_to_le32(TRB_CHAIN);
2872 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2874 /* Toggle the cycle bit after the last ring segment. */
2875 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2876 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2878 ring->enq_seg = ring->enq_seg->next;
2879 ring->enqueue = ring->enq_seg->trbs;
2880 next = ring->enqueue;
2887 static int prepare_transfer(struct xhci_hcd *xhci,
2888 struct xhci_virt_device *xdev,
2889 unsigned int ep_index,
2890 unsigned int stream_id,
2891 unsigned int num_trbs,
2893 unsigned int td_index,
2897 struct urb_priv *urb_priv;
2899 struct xhci_ring *ep_ring;
2900 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2902 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2904 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2909 ret = prepare_ring(xhci, ep_ring,
2910 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2911 num_trbs, mem_flags);
2915 urb_priv = urb->hcpriv;
2916 td = urb_priv->td[td_index];
2918 INIT_LIST_HEAD(&td->td_list);
2919 INIT_LIST_HEAD(&td->cancelled_td_list);
2921 if (td_index == 0) {
2922 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2928 /* Add this TD to the tail of the endpoint ring's TD list */
2929 list_add_tail(&td->td_list, &ep_ring->td_list);
2930 td->start_seg = ep_ring->enq_seg;
2931 td->first_trb = ep_ring->enqueue;
2933 urb_priv->td[td_index] = td;
2938 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2940 int num_sgs, num_trbs, running_total, temp, i;
2941 struct scatterlist *sg;
2944 num_sgs = urb->num_mapped_sgs;
2945 temp = urb->transfer_buffer_length;
2948 for_each_sg(urb->sg, sg, num_sgs, i) {
2949 unsigned int len = sg_dma_len(sg);
2951 /* Scatter gather list entries may cross 64KB boundaries */
2952 running_total = TRB_MAX_BUFF_SIZE -
2953 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2954 running_total &= TRB_MAX_BUFF_SIZE - 1;
2955 if (running_total != 0)
2958 /* How many more 64KB chunks to transfer, how many more TRBs? */
2959 while (running_total < sg_dma_len(sg) && running_total < temp) {
2961 running_total += TRB_MAX_BUFF_SIZE;
2963 len = min_t(int, len, temp);
2971 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2974 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2975 "TRBs, %d left\n", __func__,
2976 urb->ep->desc.bEndpointAddress, num_trbs);
2977 if (running_total != urb->transfer_buffer_length)
2978 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2979 "queued %#x (%d), asked for %#x (%d)\n",
2981 urb->ep->desc.bEndpointAddress,
2982 running_total, running_total,
2983 urb->transfer_buffer_length,
2984 urb->transfer_buffer_length);
2987 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2988 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2989 struct xhci_generic_trb *start_trb)
2992 * Pass all the TRBs to the hardware at once and make sure this write
2997 start_trb->field[3] |= cpu_to_le32(start_cycle);
2999 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3000 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3004 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3005 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3006 * (comprised of sg list entries) can take several service intervals to
3009 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3010 struct urb *urb, int slot_id, unsigned int ep_index)
3012 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3013 xhci->devs[slot_id]->out_ctx, ep_index);
3017 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3018 ep_interval = urb->interval;
3019 /* Convert to microframes */
3020 if (urb->dev->speed == USB_SPEED_LOW ||
3021 urb->dev->speed == USB_SPEED_FULL)
3023 /* FIXME change this to a warning and a suggestion to use the new API
3024 * to set the polling interval (once the API is added).
3026 if (xhci_interval != ep_interval) {
3027 dev_dbg_ratelimited(&urb->dev->dev,
3028 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3029 ep_interval, ep_interval == 1 ? "" : "s",
3030 xhci_interval, xhci_interval == 1 ? "" : "s");
3031 urb->interval = xhci_interval;
3032 /* Convert back to frames for LS/FS devices */
3033 if (urb->dev->speed == USB_SPEED_LOW ||
3034 urb->dev->speed == USB_SPEED_FULL)
3037 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3041 * The TD size is the number of bytes remaining in the TD (including this TRB),
3042 * right shifted by 10.
3043 * It must fit in bits 21:17, so it can't be bigger than 31.
3045 static u32 xhci_td_remainder(unsigned int remainder)
3047 u32 max = (1 << (21 - 17 + 1)) - 1;
3049 if ((remainder >> 10) >= max)
3052 return (remainder >> 10) << 17;
3056 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3057 * packets remaining in the TD (*not* including this TRB).
3059 * Total TD packet count = total_packet_count =
3060 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3062 * Packets transferred up to and including this TRB = packets_transferred =
3063 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3065 * TD size = total_packet_count - packets_transferred
3067 * It must fit in bits 21:17, so it can't be bigger than 31.
3068 * The last TRB in a TD must have the TD size set to zero.
3070 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3071 unsigned int total_packet_count, struct urb *urb,
3072 unsigned int num_trbs_left)
3074 int packets_transferred;
3076 /* One TRB with a zero-length data packet. */
3077 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3080 /* All the TRB queueing functions don't count the current TRB in
3083 packets_transferred = (running_total + trb_buff_len) /
3084 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3086 if ((total_packet_count - packets_transferred) > 31)
3088 return (total_packet_count - packets_transferred) << 17;
3091 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3092 struct urb *urb, int slot_id, unsigned int ep_index)
3094 struct xhci_ring *ep_ring;
3095 unsigned int num_trbs;
3096 struct urb_priv *urb_priv;
3098 struct scatterlist *sg;
3100 int trb_buff_len, this_sg_len, running_total;
3101 unsigned int total_packet_count;
3104 bool more_trbs_coming;
3106 struct xhci_generic_trb *start_trb;
3109 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3113 num_trbs = count_sg_trbs_needed(xhci, urb);
3114 num_sgs = urb->num_mapped_sgs;
3115 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3116 usb_endpoint_maxp(&urb->ep->desc));
3118 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3119 ep_index, urb->stream_id,
3120 num_trbs, urb, 0, mem_flags);
3121 if (trb_buff_len < 0)
3122 return trb_buff_len;
3124 urb_priv = urb->hcpriv;
3125 td = urb_priv->td[0];
3128 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3129 * until we've finished creating all the other TRBs. The ring's cycle
3130 * state may change as we enqueue the other TRBs, so save it too.
3132 start_trb = &ep_ring->enqueue->generic;
3133 start_cycle = ep_ring->cycle_state;
3137 * How much data is in the first TRB?
3139 * There are three forces at work for TRB buffer pointers and lengths:
3140 * 1. We don't want to walk off the end of this sg-list entry buffer.
3141 * 2. The transfer length that the driver requested may be smaller than
3142 * the amount of memory allocated for this scatter-gather list.
3143 * 3. TRBs buffers can't cross 64KB boundaries.
3146 addr = (u64) sg_dma_address(sg);
3147 this_sg_len = sg_dma_len(sg);
3148 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3149 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3150 if (trb_buff_len > urb->transfer_buffer_length)
3151 trb_buff_len = urb->transfer_buffer_length;
3154 /* Queue the first TRB, even if it's zero-length */
3157 u32 length_field = 0;
3160 /* Don't change the cycle bit of the first TRB until later */
3163 if (start_cycle == 0)
3166 field |= ep_ring->cycle_state;
3168 /* Chain all the TRBs together; clear the chain bit in the last
3169 * TRB to indicate it's the last TRB in the chain.
3174 /* FIXME - add check for ZERO_PACKET flag before this */
3175 td->last_trb = ep_ring->enqueue;
3179 /* Only set interrupt on short packet for IN endpoints */
3180 if (usb_urb_dir_in(urb))
3183 if (TRB_MAX_BUFF_SIZE -
3184 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3185 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3186 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3187 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3188 (unsigned int) addr + trb_buff_len);
3191 /* Set the TRB length, TD size, and interrupter fields. */
3192 if (xhci->hci_version < 0x100) {
3193 remainder = xhci_td_remainder(
3194 urb->transfer_buffer_length -
3197 remainder = xhci_v1_0_td_remainder(running_total,
3198 trb_buff_len, total_packet_count, urb,
3201 length_field = TRB_LEN(trb_buff_len) |
3206 more_trbs_coming = true;
3208 more_trbs_coming = false;
3209 queue_trb(xhci, ep_ring, more_trbs_coming,
3210 lower_32_bits(addr),
3211 upper_32_bits(addr),
3213 field | TRB_TYPE(TRB_NORMAL));
3215 running_total += trb_buff_len;
3217 /* Calculate length for next transfer --
3218 * Are we done queueing all the TRBs for this sg entry?
3220 this_sg_len -= trb_buff_len;
3221 if (this_sg_len == 0) {
3226 addr = (u64) sg_dma_address(sg);
3227 this_sg_len = sg_dma_len(sg);
3229 addr += trb_buff_len;
3232 trb_buff_len = TRB_MAX_BUFF_SIZE -
3233 (addr & (TRB_MAX_BUFF_SIZE - 1));
3234 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3235 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3237 urb->transfer_buffer_length - running_total;
3238 } while (running_total < urb->transfer_buffer_length);
3240 check_trb_math(urb, num_trbs, running_total);
3241 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3242 start_cycle, start_trb);
3246 /* This is very similar to what ehci-q.c qtd_fill() does */
3247 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3248 struct urb *urb, int slot_id, unsigned int ep_index)
3250 struct xhci_ring *ep_ring;
3251 struct urb_priv *urb_priv;
3254 struct xhci_generic_trb *start_trb;
3256 bool more_trbs_coming;
3258 u32 field, length_field;
3260 int running_total, trb_buff_len, ret;
3261 unsigned int total_packet_count;
3265 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3267 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3272 /* How much data is (potentially) left before the 64KB boundary? */
3273 running_total = TRB_MAX_BUFF_SIZE -
3274 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3275 running_total &= TRB_MAX_BUFF_SIZE - 1;
3277 /* If there's some data on this 64KB chunk, or we have to send a
3278 * zero-length transfer, we need at least one TRB
3280 if (running_total != 0 || urb->transfer_buffer_length == 0)
3282 /* How many more 64KB chunks to transfer, how many more TRBs? */
3283 while (running_total < urb->transfer_buffer_length) {
3285 running_total += TRB_MAX_BUFF_SIZE;
3287 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3289 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3290 ep_index, urb->stream_id,
3291 num_trbs, urb, 0, mem_flags);
3295 urb_priv = urb->hcpriv;
3296 td = urb_priv->td[0];
3299 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3300 * until we've finished creating all the other TRBs. The ring's cycle
3301 * state may change as we enqueue the other TRBs, so save it too.
3303 start_trb = &ep_ring->enqueue->generic;
3304 start_cycle = ep_ring->cycle_state;
3307 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3308 usb_endpoint_maxp(&urb->ep->desc));
3309 /* How much data is in the first TRB? */
3310 addr = (u64) urb->transfer_dma;
3311 trb_buff_len = TRB_MAX_BUFF_SIZE -
3312 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3313 if (trb_buff_len > urb->transfer_buffer_length)
3314 trb_buff_len = urb->transfer_buffer_length;
3318 /* Queue the first TRB, even if it's zero-length */
3323 /* Don't change the cycle bit of the first TRB until later */
3326 if (start_cycle == 0)
3329 field |= ep_ring->cycle_state;
3331 /* Chain all the TRBs together; clear the chain bit in the last
3332 * TRB to indicate it's the last TRB in the chain.
3337 /* FIXME - add check for ZERO_PACKET flag before this */
3338 td->last_trb = ep_ring->enqueue;
3342 /* Only set interrupt on short packet for IN endpoints */
3343 if (usb_urb_dir_in(urb))
3346 /* Set the TRB length, TD size, and interrupter fields. */
3347 if (xhci->hci_version < 0x100) {
3348 remainder = xhci_td_remainder(
3349 urb->transfer_buffer_length -
3352 remainder = xhci_v1_0_td_remainder(running_total,
3353 trb_buff_len, total_packet_count, urb,
3356 length_field = TRB_LEN(trb_buff_len) |
3361 more_trbs_coming = true;
3363 more_trbs_coming = false;
3364 queue_trb(xhci, ep_ring, more_trbs_coming,
3365 lower_32_bits(addr),
3366 upper_32_bits(addr),
3368 field | TRB_TYPE(TRB_NORMAL));
3370 running_total += trb_buff_len;
3372 /* Calculate length for next transfer */
3373 addr += trb_buff_len;
3374 trb_buff_len = urb->transfer_buffer_length - running_total;
3375 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3376 trb_buff_len = TRB_MAX_BUFF_SIZE;
3377 } while (running_total < urb->transfer_buffer_length);
3379 check_trb_math(urb, num_trbs, running_total);
3380 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3381 start_cycle, start_trb);
3385 /* Caller must have locked xhci->lock */
3386 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3387 struct urb *urb, int slot_id, unsigned int ep_index)
3389 struct xhci_ring *ep_ring;
3392 struct usb_ctrlrequest *setup;
3393 struct xhci_generic_trb *start_trb;
3395 u32 field, length_field;
3396 struct urb_priv *urb_priv;
3399 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3404 * Need to copy setup packet into setup TRB, so we can't use the setup
3407 if (!urb->setup_packet)
3410 /* 1 TRB for setup, 1 for status */
3413 * Don't need to check if we need additional event data and normal TRBs,
3414 * since data in control transfers will never get bigger than 16MB
3415 * XXX: can we get a buffer that crosses 64KB boundaries?
3417 if (urb->transfer_buffer_length > 0)
3419 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3420 ep_index, urb->stream_id,
3421 num_trbs, urb, 0, mem_flags);
3425 urb_priv = urb->hcpriv;
3426 td = urb_priv->td[0];
3429 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3430 * until we've finished creating all the other TRBs. The ring's cycle
3431 * state may change as we enqueue the other TRBs, so save it too.
3433 start_trb = &ep_ring->enqueue->generic;
3434 start_cycle = ep_ring->cycle_state;
3436 /* Queue setup TRB - see section 6.4.1.2.1 */
3437 /* FIXME better way to translate setup_packet into two u32 fields? */
3438 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3440 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3441 if (start_cycle == 0)
3444 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3445 if (xhci->hci_version == 0x100) {
3446 if (urb->transfer_buffer_length > 0) {
3447 if (setup->bRequestType & USB_DIR_IN)
3448 field |= TRB_TX_TYPE(TRB_DATA_IN);
3450 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3454 queue_trb(xhci, ep_ring, true,
3455 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3456 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3457 TRB_LEN(8) | TRB_INTR_TARGET(0),
3458 /* Immediate data in pointer */
3461 /* If there's data, queue data TRBs */
3462 /* Only set interrupt on short packet for IN endpoints */
3463 if (usb_urb_dir_in(urb))
3464 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3466 field = TRB_TYPE(TRB_DATA);
3468 length_field = TRB_LEN(urb->transfer_buffer_length) |
3469 xhci_td_remainder(urb->transfer_buffer_length) |
3471 if (urb->transfer_buffer_length > 0) {
3472 if (setup->bRequestType & USB_DIR_IN)
3473 field |= TRB_DIR_IN;
3474 queue_trb(xhci, ep_ring, true,
3475 lower_32_bits(urb->transfer_dma),
3476 upper_32_bits(urb->transfer_dma),
3478 field | ep_ring->cycle_state);
3481 /* Save the DMA address of the last TRB in the TD */
3482 td->last_trb = ep_ring->enqueue;
3484 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3485 /* If the device sent data, the status stage is an OUT transfer */
3486 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3490 queue_trb(xhci, ep_ring, false,
3494 /* Event on completion */
3495 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3497 giveback_first_trb(xhci, slot_id, ep_index, 0,
3498 start_cycle, start_trb);
3502 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3503 struct urb *urb, int i)
3508 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3509 td_len = urb->iso_frame_desc[i].length;
3511 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3520 * The transfer burst count field of the isochronous TRB defines the number of
3521 * bursts that are required to move all packets in this TD. Only SuperSpeed
3522 * devices can burst up to bMaxBurst number of packets per service interval.
3523 * This field is zero based, meaning a value of zero in the field means one
3524 * burst. Basically, for everything but SuperSpeed devices, this field will be
3525 * zero. Only xHCI 1.0 host controllers support this field.
3527 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3528 struct usb_device *udev,
3529 struct urb *urb, unsigned int total_packet_count)
3531 unsigned int max_burst;
3533 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3536 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3537 return roundup(total_packet_count, max_burst + 1) - 1;
3541 * Returns the number of packets in the last "burst" of packets. This field is
3542 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3543 * the last burst packet count is equal to the total number of packets in the
3544 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3545 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3546 * contain 1 to (bMaxBurst + 1) packets.
3548 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3549 struct usb_device *udev,
3550 struct urb *urb, unsigned int total_packet_count)
3552 unsigned int max_burst;
3553 unsigned int residue;
3555 if (xhci->hci_version < 0x100)
3558 switch (udev->speed) {
3559 case USB_SPEED_SUPER:
3560 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3561 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3562 residue = total_packet_count % (max_burst + 1);
3563 /* If residue is zero, the last burst contains (max_burst + 1)
3564 * number of packets, but the TLBPC field is zero-based.
3570 if (total_packet_count == 0)
3572 return total_packet_count - 1;
3576 /* This is for isoc transfer */
3577 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3578 struct urb *urb, int slot_id, unsigned int ep_index)
3580 struct xhci_ring *ep_ring;
3581 struct urb_priv *urb_priv;
3583 int num_tds, trbs_per_td;
3584 struct xhci_generic_trb *start_trb;
3587 u32 field, length_field;
3588 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3589 u64 start_addr, addr;
3591 bool more_trbs_coming;
3593 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3595 num_tds = urb->number_of_packets;
3597 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3601 start_addr = (u64) urb->transfer_dma;
3602 start_trb = &ep_ring->enqueue->generic;
3603 start_cycle = ep_ring->cycle_state;
3605 urb_priv = urb->hcpriv;
3606 /* Queue the first TRB, even if it's zero-length */
3607 for (i = 0; i < num_tds; i++) {
3608 unsigned int total_packet_count;
3609 unsigned int burst_count;
3610 unsigned int residue;
3614 addr = start_addr + urb->iso_frame_desc[i].offset;
3615 td_len = urb->iso_frame_desc[i].length;
3616 td_remain_len = td_len;
3617 total_packet_count = DIV_ROUND_UP(td_len,
3619 usb_endpoint_maxp(&urb->ep->desc)));
3620 /* A zero-length transfer still involves at least one packet. */
3621 if (total_packet_count == 0)
3622 total_packet_count++;
3623 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3624 total_packet_count);
3625 residue = xhci_get_last_burst_packet_count(xhci,
3626 urb->dev, urb, total_packet_count);
3628 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3630 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3631 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3638 td = urb_priv->td[i];
3639 for (j = 0; j < trbs_per_td; j++) {
3644 field = TRB_TBC(burst_count) |
3646 /* Queue the isoc TRB */
3647 field |= TRB_TYPE(TRB_ISOC);
3648 /* Assume URB_ISO_ASAP is set */
3651 if (start_cycle == 0)
3654 field |= ep_ring->cycle_state;
3657 /* Queue other normal TRBs */
3658 field |= TRB_TYPE(TRB_NORMAL);
3659 field |= ep_ring->cycle_state;
3662 /* Only set interrupt on short packet for IN EPs */
3663 if (usb_urb_dir_in(urb))
3666 /* Chain all the TRBs together; clear the chain bit in
3667 * the last TRB to indicate it's the last TRB in the
3670 if (j < trbs_per_td - 1) {
3672 more_trbs_coming = true;
3674 td->last_trb = ep_ring->enqueue;
3676 if (xhci->hci_version == 0x100 &&
3679 /* Set BEI bit except for the last td */
3680 if (i < num_tds - 1)
3683 more_trbs_coming = false;
3686 /* Calculate TRB length */
3687 trb_buff_len = TRB_MAX_BUFF_SIZE -
3688 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3689 if (trb_buff_len > td_remain_len)
3690 trb_buff_len = td_remain_len;
3692 /* Set the TRB length, TD size, & interrupter fields. */
3693 if (xhci->hci_version < 0x100) {
3694 remainder = xhci_td_remainder(
3695 td_len - running_total);
3697 remainder = xhci_v1_0_td_remainder(
3698 running_total, trb_buff_len,
3699 total_packet_count, urb,
3700 (trbs_per_td - j - 1));
3702 length_field = TRB_LEN(trb_buff_len) |
3706 queue_trb(xhci, ep_ring, more_trbs_coming,
3707 lower_32_bits(addr),
3708 upper_32_bits(addr),
3711 running_total += trb_buff_len;
3713 addr += trb_buff_len;
3714 td_remain_len -= trb_buff_len;
3717 /* Check TD length */
3718 if (running_total != td_len) {
3719 xhci_err(xhci, "ISOC TD length unmatch\n");
3725 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3726 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3727 usb_amd_quirk_pll_disable();
3729 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3731 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3732 start_cycle, start_trb);
3735 /* Clean up a partially enqueued isoc transfer. */
3737 for (i--; i >= 0; i--)
3738 list_del_init(&urb_priv->td[i]->td_list);
3740 /* Use the first TD as a temporary variable to turn the TDs we've queued
3741 * into No-ops with a software-owned cycle bit. That way the hardware
3742 * won't accidentally start executing bogus TDs when we partially
3743 * overwrite them. td->first_trb and td->start_seg are already set.
3745 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3746 /* Every TRB except the first & last will have its cycle bit flipped. */
3747 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3749 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3750 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3751 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3752 ep_ring->cycle_state = start_cycle;
3753 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3754 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3759 * Check transfer ring to guarantee there is enough room for the urb.
3760 * Update ISO URB start_frame and interval.
3761 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3762 * update the urb->start_frame by now.
3763 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3765 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3766 struct urb *urb, int slot_id, unsigned int ep_index)
3768 struct xhci_virt_device *xdev;
3769 struct xhci_ring *ep_ring;
3770 struct xhci_ep_ctx *ep_ctx;
3774 int num_tds, num_trbs, i;
3777 xdev = xhci->devs[slot_id];
3778 ep_ring = xdev->eps[ep_index].ring;
3779 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3782 num_tds = urb->number_of_packets;
3783 for (i = 0; i < num_tds; i++)
3784 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3786 /* Check the ring to guarantee there is enough room for the whole urb.
3787 * Do not insert any td of the urb to the ring if the check failed.
3789 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3790 num_trbs, mem_flags);
3794 start_frame = readl(&xhci->run_regs->microframe_index);
3795 start_frame &= 0x3fff;
3797 urb->start_frame = start_frame;
3798 if (urb->dev->speed == USB_SPEED_LOW ||
3799 urb->dev->speed == USB_SPEED_FULL)
3800 urb->start_frame >>= 3;
3802 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3803 ep_interval = urb->interval;
3804 /* Convert to microframes */
3805 if (urb->dev->speed == USB_SPEED_LOW ||
3806 urb->dev->speed == USB_SPEED_FULL)
3808 /* FIXME change this to a warning and a suggestion to use the new API
3809 * to set the polling interval (once the API is added).
3811 if (xhci_interval != ep_interval) {
3812 dev_dbg_ratelimited(&urb->dev->dev,
3813 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3814 ep_interval, ep_interval == 1 ? "" : "s",
3815 xhci_interval, xhci_interval == 1 ? "" : "s");
3816 urb->interval = xhci_interval;
3817 /* Convert back to frames for LS/FS devices */
3818 if (urb->dev->speed == USB_SPEED_LOW ||
3819 urb->dev->speed == USB_SPEED_FULL)
3822 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3824 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3827 /**** Command Ring Operations ****/
3829 /* Generic function for queueing a command TRB on the command ring.
3830 * Check to make sure there's room on the command ring for one command TRB.
3831 * Also check that there's room reserved for commands that must not fail.
3832 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3833 * then only check for the number of reserved spots.
3834 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3835 * because the command event handler may want to resubmit a failed command.
3837 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3838 u32 field1, u32 field2,
3839 u32 field3, u32 field4, bool command_must_succeed)
3841 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3843 if (xhci->xhc_state & XHCI_STATE_DYING)
3846 if (!command_must_succeed)
3849 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3850 reserved_trbs, GFP_ATOMIC);
3852 xhci_err(xhci, "ERR: No room for command on command ring\n");
3853 if (command_must_succeed)
3854 xhci_err(xhci, "ERR: Reserved TRB counting for "
3855 "unfailable commands failed.\n");
3859 cmd->command_trb = xhci->cmd_ring->enqueue;
3860 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3862 /* if there are no other commands queued we start the timeout timer */
3863 if (xhci->cmd_list.next == &cmd->cmd_list &&
3864 !timer_pending(&xhci->cmd_timer)) {
3865 xhci->current_cmd = cmd;
3866 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3869 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3870 field4 | xhci->cmd_ring->cycle_state);
3874 /* Queue a slot enable or disable request on the command ring */
3875 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3876 u32 trb_type, u32 slot_id)
3878 return queue_command(xhci, cmd, 0, 0, 0,
3879 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3882 /* Queue an address device command TRB */
3883 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3884 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3886 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3887 upper_32_bits(in_ctx_ptr), 0,
3888 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3889 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3892 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3893 u32 field1, u32 field2, u32 field3, u32 field4)
3895 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3898 /* Queue a reset device command TRB */
3899 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3902 return queue_command(xhci, cmd, 0, 0, 0,
3903 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3907 /* Queue a configure endpoint command TRB */
3908 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3909 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3910 u32 slot_id, bool command_must_succeed)
3912 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3913 upper_32_bits(in_ctx_ptr), 0,
3914 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3915 command_must_succeed);
3918 /* Queue an evaluate context command TRB */
3919 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3920 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3922 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3923 upper_32_bits(in_ctx_ptr), 0,
3924 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3925 command_must_succeed);
3929 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3930 * activity on an endpoint that is about to be suspended.
3932 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3933 int slot_id, unsigned int ep_index, int suspend)
3935 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3936 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3937 u32 type = TRB_TYPE(TRB_STOP_RING);
3938 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3940 return queue_command(xhci, cmd, 0, 0, 0,
3941 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3944 /* Set Transfer Ring Dequeue Pointer command.
3945 * This should not be used for endpoints that have streams enabled.
3947 static int queue_set_tr_deq(struct xhci_hcd *xhci, struct xhci_command *cmd,
3949 unsigned int ep_index, unsigned int stream_id,
3950 struct xhci_segment *deq_seg,
3951 union xhci_trb *deq_ptr, u32 cycle_state)
3954 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3955 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3956 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3958 u32 type = TRB_TYPE(TRB_SET_DEQ);
3959 struct xhci_virt_ep *ep;
3961 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3963 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3964 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3968 ep = &xhci->devs[slot_id]->eps[ep_index];
3969 if ((ep->ep_state & SET_DEQ_PENDING)) {
3970 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3971 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3974 ep->queued_deq_seg = deq_seg;
3975 ep->queued_deq_ptr = deq_ptr;
3977 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
3978 return queue_command(xhci, cmd,
3979 lower_32_bits(addr) | trb_sct | cycle_state,
3980 upper_32_bits(addr), trb_stream_id,
3981 trb_slot_id | trb_ep_index | type, false);
3984 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3985 int slot_id, unsigned int ep_index)
3987 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3988 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3989 u32 type = TRB_TYPE(TRB_RESET_EP);
3991 return queue_command(xhci, cmd, 0, 0, 0,
3992 trb_slot_id | trb_ep_index | type, false);