drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                 }
 159                 ring->deq_seg = ring->deq_seg->next;
 160                 ring->dequeue = ring->deq_seg->trbs;
 161                 next = ring->dequeue;
 162         }
 163         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 164 }
 165
 166 /*
 167  * See Cycle bit rules. SW is the consumer for the event ring only.
 168  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 169  *
 170  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 171  * chain bit is set), then set the chain bit in all the following link TRBs.
 172  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 173  * have their chain bit cleared (so that each Link TRB is a separate TD).
 174  *
 175  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 176  * set, but other sections talk about dealing with the chain bit set.  This was
 177  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 178  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 179  *
 180  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 181  *                      prepare_transfer()?
 182  */
 183 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 184                 bool consumer, bool more_trbs_coming, bool isoc)
 185 {
 186         u32 chain;
 187         union xhci_trb *next;
 188         unsigned long long addr;
 189
 190         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 191         next = ++(ring->enqueue);
 192
 193         ring->enq_updates++;
 194         /* Update the dequeue pointer further if that was a link TRB or we're at
 195          * the end of an event ring segment (which doesn't have link TRBS)
 196          */
 197         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 198                 if (!consumer) {
 199                         if (ring != xhci->event_ring) {
 200                                 /*
 201                                  * If the caller doesn't plan on enqueueing more
 202                                  * TDs before ringing the doorbell, then we
 203                                  * don't want to give the link TRB to the
 204                                  * hardware just yet.  We'll give the link TRB
 205                                  * back in prepare_ring() just before we enqueue
 206                                  * the TD at the top of the ring.
 207                                  */
 208                                 if (!chain && !more_trbs_coming)
 209                                         break;
 210
 211                                 /* If we're not dealing with 0.95 hardware or
 212                                  * isoc rings on AMD 0.96 host,
 213                                  * carry over the chain bit of the previous TRB
 214                                  * (which may mean the chain bit is cleared).
 215                                  */
 216                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 217                                                 && !xhci_link_trb_quirk(xhci)) {
 218                                         next->link.control &=
 219                                                 cpu_to_le32(~TRB_CHAIN);
 220                                         next->link.control |=
 221                                                 cpu_to_le32(chain);
 222                                 }
 223                                 /* Give this link TRB to the hardware */
 224                                 wmb();
 225                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 226                         }
 227                         /* Toggle the cycle bit after the last ring segment. */
 228                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 229                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 230                         }
 231                 }
 232                 ring->enq_seg = ring->enq_seg->next;
 233                 ring->enqueue = ring->enq_seg->trbs;
 234                 next = ring->enqueue;
 235         }
 236         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 237 }
 238
 239 /*
 240  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 241  * above.
 242  * FIXME: this would be simpler and faster if we just kept track of the number
 243  * of free TRBs in a ring.
 244  */
 245 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 246                 unsigned int num_trbs)
 247 {
 248         int i;
 249         union xhci_trb *enq = ring->enqueue;
 250         struct xhci_segment *enq_seg = ring->enq_seg;
 251         struct xhci_segment *cur_seg;
 252         unsigned int left_on_ring;
 253
 254         /* If we are currently pointing to a link TRB, advance the
 255          * enqueue pointer before checking for space */
 256         while (last_trb(xhci, ring, enq_seg, enq)) {
 257                 enq_seg = enq_seg->next;
 258                 enq = enq_seg->trbs;
 259         }
 260
 261         /* Check if ring is empty */
 262         if (enq == ring->dequeue) {
 263                 /* Can't use link trbs */
 264                 left_on_ring = TRBS_PER_SEGMENT - 1;
 265                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 266                                 cur_seg = cur_seg->next)
 267                         left_on_ring += TRBS_PER_SEGMENT - 1;
 268
 269                 /* Always need one TRB free in the ring. */
 270                 left_on_ring -= 1;
 271                 if (num_trbs > left_on_ring) {
 272                         xhci_warn(xhci, "Not enough room on ring; "
 273                                         "need %u TRBs, %u TRBs left\n",
 274                                         num_trbs, left_on_ring);
 275                         return 0;
 276                 }
 277                 return 1;
 278         }
 279         /* Make sure there's an extra empty TRB available */
 280         for (i = 0; i <= num_trbs; ++i) {
 281                 if (enq == ring->dequeue)
 282                         return 0;
 283                 enq++;
 284                 while (last_trb(xhci, ring, enq_seg, enq)) {
 285                         enq_seg = enq_seg->next;
 286                         enq = enq_seg->trbs;
 287                 }
 288         }
 289         return 1;
 290 }
 291
 292 /* Ring the host controller doorbell after placing a command on the ring */
 293 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 294 {
 295         xhci_dbg(xhci, "// Ding dong!\n");
 296         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 297         /* Flush PCI posted writes */
 298         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 299 }
 300
 301 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 302                 unsigned int slot_id,
 303                 unsigned int ep_index,
 304                 unsigned int stream_id)
 305 {
 306         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 307         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 308         unsigned int ep_state = ep->ep_state;
 309
 310         /* Don't ring the doorbell for this endpoint if there are pending
 311          * cancellations because we don't want to interrupt processing.
 312          * We don't want to restart any stream rings if there's a set dequeue
 313          * pointer command pending because the device can choose to start any
 314          * stream once the endpoint is on the HW schedule.
 315          * FIXME - check all the stream rings for pending cancellations.
 316          */
 317         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 318             (ep_state & EP_HALTED))
 319                 return;
 320         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 321         /* The CPU has better things to do at this point than wait for a
 322          * write-posting flush.  It'll get there soon enough.
 323          */
 324 }
 325
 326 /* Ring the doorbell for any rings with pending URBs */
 327 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 328                 unsigned int slot_id,
 329                 unsigned int ep_index)
 330 {
 331         unsigned int stream_id;
 332         struct xhci_virt_ep *ep;
 333
 334         ep = &xhci->devs[slot_id]->eps[ep_index];
 335
 336         /* A ring has pending URBs if its TD list is not empty */
 337         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 338                 if (!(list_empty(&ep->ring->td_list)))
 339                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 340                 return;
 341         }
 342
 343         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 344                         stream_id++) {
 345                 struct xhci_stream_info *stream_info = ep->stream_info;
 346                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 347                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 348                                                 stream_id);
 349         }
 350 }
 351
 352 /*
 353  * Find the segment that trb is in.  Start searching in start_seg.
 354  * If we must move past a segment that has a link TRB with a toggle cycle state
 355  * bit set, then we will toggle the value pointed at by cycle_state.
 356  */
 357 static struct xhci_segment *find_trb_seg(
 358                 struct xhci_segment *start_seg,
 359                 union xhci_trb  *trb, int *cycle_state)
 360 {
 361         struct xhci_segment *cur_seg = start_seg;
 362         struct xhci_generic_trb *generic_trb;
 363
 364         while (cur_seg->trbs > trb ||
 365                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 366                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 367                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 368                         *cycle_state ^= 0x1;
 369                 cur_seg = cur_seg->next;
 370                 if (cur_seg == start_seg)
 371                         /* Looped over the entire list.  Oops! */
 372                         return NULL;
 373         }
 374         return cur_seg;
 375 }
 376
 377
 378 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 379                 unsigned int slot_id, unsigned int ep_index,
 380                 unsigned int stream_id)
 381 {
 382         struct xhci_virt_ep *ep;
 383
 384         ep = &xhci->devs[slot_id]->eps[ep_index];
 385         /* Common case: no streams */
 386         if (!(ep->ep_state & EP_HAS_STREAMS))
 387                 return ep->ring;
 388
 389         if (stream_id == 0) {
 390                 xhci_warn(xhci,
 391                                 "WARN: Slot ID %u, ep index %u has streams, "
 392                                 "but URB has no stream ID.\n",
 393                                 slot_id, ep_index);
 394                 return NULL;
 395         }
 396
 397         if (stream_id < ep->stream_info->num_streams)
 398                 return ep->stream_info->stream_rings[stream_id];
 399
 400         xhci_warn(xhci,
 401                         "WARN: Slot ID %u, ep index %u has "
 402                         "stream IDs 1 to %u allocated, "
 403                         "but stream ID %u is requested.\n",
 404                         slot_id, ep_index,
 405                         ep->stream_info->num_streams - 1,
 406                         stream_id);
 407         return NULL;
 408 }
 409
 410 /* Get the right ring for the given URB.
 411  * If the endpoint supports streams, boundary check the URB's stream ID.
 412  * If the endpoint doesn't support streams, return the singular endpoint ring.
 413  */
 414 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 415                 struct urb *urb)
 416 {
 417         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 418                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 419 }
 420
 421 /*
 422  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 423  * Record the new state of the xHC's endpoint ring dequeue segment,
 424  * dequeue pointer, and new consumer cycle state in state.
 425  * Update our internal representation of the ring's dequeue pointer.
 426  *
 427  * We do this in three jumps:
 428  *  - First we update our new ring state to be the same as when the xHC stopped.
 429  *  - Then we traverse the ring to find the segment that contains
 430  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 431  *    any link TRBs with the toggle cycle bit set.
 432  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 433  *    if we've moved it past a link TRB with the toggle cycle bit set.
 434  *
 435  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 436  * with correct __le32 accesses they should work fine.  Only users of this are
 437  * in here.
 438  */
 439 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 440                 unsigned int slot_id, unsigned int ep_index,
 441                 unsigned int stream_id, struct xhci_td *cur_td,
 442                 struct xhci_dequeue_state *state)
 443 {
 444         struct xhci_virt_device *dev = xhci->devs[slot_id];
 445         struct xhci_ring *ep_ring;
 446         struct xhci_generic_trb *trb;
 447         struct xhci_ep_ctx *ep_ctx;
 448         dma_addr_t addr;
 449
 450         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 451                         ep_index, stream_id);
 452         if (!ep_ring) {
 453                 xhci_warn(xhci, "WARN can't find new dequeue state "
 454                                 "for invalid stream ID %u.\n",
 455                                 stream_id);
 456                 return;
 457         }
 458         state->new_cycle_state = 0;
 459         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 460         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 461                         dev->eps[ep_index].stopped_trb,
 462                         &state->new_cycle_state);
 463         if (!state->new_deq_seg) {
 464                 WARN_ON(1);
 465                 return;
 466         }
 467
 468         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 469         xhci_dbg(xhci, "Finding endpoint context\n");
 470         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 471         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 472
 473         state->new_deq_ptr = cur_td->last_trb;
 474         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 475         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 476                         state->new_deq_ptr,
 477                         &state->new_cycle_state);
 478         if (!state->new_deq_seg) {
 479                 WARN_ON(1);
 480                 return;
 481         }
 482
 483         trb = &state->new_deq_ptr->generic;
 484         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 485             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 486                 state->new_cycle_state ^= 0x1;
 487         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 488
 489         /*
 490          * If there is only one segment in a ring, find_trb_seg()'s while loop
 491          * will not run, and it will return before it has a chance to see if it
 492          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 493          * ended just before the link TRB on a one-segment ring, or if the TD
 494          * wrapped around the top of the ring, because it doesn't have the TD in
 495          * question.  Look for the one-segment case where stalled TRB's address
 496          * is greater than the new dequeue pointer address.
 497          */
 498         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 499                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 500                 state->new_cycle_state ^= 0x1;
 501         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 502
 503         /* Don't update the ring cycle state for the producer (us). */
 504         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 505                         state->new_deq_seg);
 506         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 507         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 508                         (unsigned long long) addr);
 509 }
 510
 511 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 512  * (The last TRB actually points to the ring enqueue pointer, which is not part
 513  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 514  */
 515 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 516                 struct xhci_td *cur_td, bool flip_cycle)
 517 {
 518         struct xhci_segment *cur_seg;
 519         union xhci_trb *cur_trb;
 520
 521         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 522                         true;
 523                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 524                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 525                         /* Unchain any chained Link TRBs, but
 526                          * leave the pointers intact.
 527                          */
 528                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 529                         /* Flip the cycle bit (link TRBs can't be the first
 530                          * or last TRB).
 531                          */
 532                         if (flip_cycle)
 533                                 cur_trb->generic.field[3] ^=
 534                                         cpu_to_le32(TRB_CYCLE);
 535                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 536                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 537                                         "in seg %p (0x%llx dma)\n",
 538                                         cur_trb,
 539                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 540                                         cur_seg,
 541                                         (unsigned long long)cur_seg->dma);
 542                 } else {
 543                         cur_trb->generic.field[0] = 0;
 544                         cur_trb->generic.field[1] = 0;
 545                         cur_trb->generic.field[2] = 0;
 546                         /* Preserve only the cycle bit of this TRB */
 547                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 548                         /* Flip the cycle bit except on the first or last TRB */
 549                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 550                                         cur_trb != cur_td->last_trb)
 551                                 cur_trb->generic.field[3] ^=
 552                                         cpu_to_le32(TRB_CYCLE);
 553                         cur_trb->generic.field[3] |= cpu_to_le32(
 554                                 TRB_TYPE(TRB_TR_NOOP));
 555                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 556                                         (unsigned long long)
 557                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 558                 }
 559                 if (cur_trb == cur_td->last_trb)
 560                         break;
 561         }
 562 }
 563
 564 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 565                 unsigned int ep_index, unsigned int stream_id,
 566                 struct xhci_segment *deq_seg,
 567                 union xhci_trb *deq_ptr, u32 cycle_state);
 568
 569 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 570                 unsigned int slot_id, unsigned int ep_index,
 571                 unsigned int stream_id,
 572                 struct xhci_dequeue_state *deq_state)
 573 {
 574         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 575
 576         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 577                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 578                         deq_state->new_deq_seg,
 579                         (unsigned long long)deq_state->new_deq_seg->dma,
 580                         deq_state->new_deq_ptr,
 581                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 582                         deq_state->new_cycle_state);
 583         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 584                         deq_state->new_deq_seg,
 585                         deq_state->new_deq_ptr,
 586                         (u32) deq_state->new_cycle_state);
 587         /* Stop the TD queueing code from ringing the doorbell until
 588          * this command completes.  The HC won't set the dequeue pointer
 589          * if the ring is running, and ringing the doorbell starts the
 590          * ring running.
 591          */
 592         ep->ep_state |= SET_DEQ_PENDING;
 593 }
 594
 595 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 596                 struct xhci_virt_ep *ep)
 597 {
 598         ep->ep_state &= ~EP_HALT_PENDING;
 599         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 600          * timer is running on another CPU, we don't decrement stop_cmds_pending
 601          * (since we didn't successfully stop the watchdog timer).
 602          */
 603         if (del_timer(&ep->stop_cmd_timer))
 604                 ep->stop_cmds_pending--;
 605 }
 606
 607 /* Must be called with xhci->lock held in interrupt context */
 608 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 609                 struct xhci_td *cur_td, int status, char *adjective)
 610 {
 611         struct usb_hcd *hcd;
 612         struct urb      *urb;
 613         struct urb_priv *urb_priv;
 614
 615         urb = cur_td->urb;
 616         urb_priv = urb->hcpriv;
 617         urb_priv->td_cnt++;
 618         hcd = bus_to_hcd(urb->dev->bus);
 619
 620         /* Only giveback urb when this is the last td in urb */
 621         if (urb_priv->td_cnt == urb_priv->length) {
 622                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 623                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 624                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 625                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 626                                         usb_amd_quirk_pll_enable();
 627                         }
 628                 }
 629                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 630
 631                 spin_unlock(&xhci->lock);
 632                 usb_hcd_giveback_urb(hcd, urb, status);
 633                 xhci_urb_free_priv(xhci, urb_priv);
 634                 spin_lock(&xhci->lock);
 635         }
 636 }
 637
 638 /*
 639  * When we get a command completion for a Stop Endpoint Command, we need to
 640  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 641  *
 642  *  1. If the HW was in the middle of processing the TD that needs to be
 643  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 644  *     in the TD with a Set Dequeue Pointer Command.
 645  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 646  *     bit cleared) so that the HW will skip over them.
 647  */
 648 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 649                 union xhci_trb *trb, struct xhci_event_cmd *event)
 650 {
 651         unsigned int slot_id;
 652         unsigned int ep_index;
 653         struct xhci_virt_device *virt_dev;
 654         struct xhci_ring *ep_ring;
 655         struct xhci_virt_ep *ep;
 656         struct list_head *entry;
 657         struct xhci_td *cur_td = NULL;
 658         struct xhci_td *last_unlinked_td;
 659
 660         struct xhci_dequeue_state deq_state;
 661
 662         if (unlikely(TRB_TO_SUSPEND_PORT(
 663                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 664                 slot_id = TRB_TO_SLOT_ID(
 665                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 666                 virt_dev = xhci->devs[slot_id];
 667                 if (virt_dev)
 668                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 669                                 event);
 670                 else
 671                         xhci_warn(xhci, "Stop endpoint command "
 672                                 "completion for disabled slot %u\n",
 673                                 slot_id);
 674                 return;
 675         }
 676
 677         memset(&deq_state, 0, sizeof(deq_state));
 678         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 679         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 680         ep = &xhci->devs[slot_id]->eps[ep_index];
 681
 682         if (list_empty(&ep->cancelled_td_list)) {
 683                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 684                 ep->stopped_td = NULL;
 685                 ep->stopped_trb = NULL;
 686                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 687                 return;
 688         }
 689
 690         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 691          * We have the xHCI lock, so nothing can modify this list until we drop
 692          * it.  We're also in the event handler, so we can't get re-interrupted
 693          * if another Stop Endpoint command completes
 694          */
 695         list_for_each(entry, &ep->cancelled_td_list) {
 696                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 697                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 698                                 (unsigned long long)xhci_trb_virt_to_dma(
 699                                         cur_td->start_seg, cur_td->first_trb));
 700                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 701                 if (!ep_ring) {
 702                         /* This shouldn't happen unless a driver is mucking
 703                          * with the stream ID after submission.  This will
 704                          * leave the TD on the hardware ring, and the hardware
 705                          * will try to execute it, and may access a buffer
 706                          * that has already been freed.  In the best case, the
 707                          * hardware will execute it, and the event handler will
 708                          * ignore the completion event for that TD, since it was
 709                          * removed from the td_list for that endpoint.  In
 710                          * short, don't muck with the stream ID after
 711                          * submission.
 712                          */
 713                         xhci_warn(xhci, "WARN Cancelled URB %p "
 714                                         "has invalid stream ID %u.\n",
 715                                         cur_td->urb,
 716                                         cur_td->urb->stream_id);
 717                         goto remove_finished_td;
 718                 }
 719                 /*
 720                  * If we stopped on the TD we need to cancel, then we have to
 721                  * move the xHC endpoint ring dequeue pointer past this TD.
 722                  */
 723                 if (cur_td == ep->stopped_td)
 724                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 725                                         cur_td->urb->stream_id,
 726                                         cur_td, &deq_state);
 727                 else
 728                         td_to_noop(xhci, ep_ring, cur_td, false);
 729 remove_finished_td:
 730                 /*
 731                  * The event handler won't see a completion for this TD anymore,
 732                  * so remove it from the endpoint ring's TD list.  Keep it in
 733                  * the cancelled TD list for URB completion later.
 734                  */
 735                 list_del_init(&cur_td->td_list);
 736         }
 737         last_unlinked_td = cur_td;
 738         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 739
 740         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 741         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 742                 xhci_queue_new_dequeue_state(xhci,
 743                                 slot_id, ep_index,
 744                                 ep->stopped_td->urb->stream_id,
 745                                 &deq_state);
 746                 xhci_ring_cmd_db(xhci);
 747         } else {
 748                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 749                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 750         }
 751         ep->stopped_td = NULL;
 752         ep->stopped_trb = NULL;
 753
 754         /*
 755          * Drop the lock and complete the URBs in the cancelled TD list.
 756          * New TDs to be cancelled might be added to the end of the list before
 757          * we can complete all the URBs for the TDs we already unlinked.
 758          * So stop when we've completed the URB for the last TD we unlinked.
 759          */
 760         do {
 761                 cur_td = list_entry(ep->cancelled_td_list.next,
 762                                 struct xhci_td, cancelled_td_list);
 763                 list_del_init(&cur_td->cancelled_td_list);
 764
 765                 /* Clean up the cancelled URB */
 766                 /* Doesn't matter what we pass for status, since the core will
 767                  * just overwrite it (because the URB has been unlinked).
 768                  */
 769                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 770
 771                 /* Stop processing the cancelled list if the watchdog timer is
 772                  * running.
 773                  */
 774                 if (xhci->xhc_state & XHCI_STATE_DYING)
 775                         return;
 776         } while (cur_td != last_unlinked_td);
 777
 778         /* Return to the event handler with xhci->lock re-acquired */
 779 }
 780
 781 /* Watchdog timer function for when a stop endpoint command fails to complete.
 782  * In this case, we assume the host controller is broken or dying or dead.  The
 783  * host may still be completing some other events, so we have to be careful to
 784  * let the event ring handler and the URB dequeueing/enqueueing functions know
 785  * through xhci->state.
 786  *
 787  * The timer may also fire if the host takes a very long time to respond to the
 788  * command, and the stop endpoint command completion handler cannot delete the
 789  * timer before the timer function is called.  Another endpoint cancellation may
 790  * sneak in before the timer function can grab the lock, and that may queue
 791  * another stop endpoint command and add the timer back.  So we cannot use a
 792  * simple flag to say whether there is a pending stop endpoint command for a
 793  * particular endpoint.
 794  *
 795  * Instead we use a combination of that flag and a counter for the number of
 796  * pending stop endpoint commands.  If the timer is the tail end of the last
 797  * stop endpoint command, and the endpoint's command is still pending, we assume
 798  * the host is dying.
 799  */
 800 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 801 {
 802         struct xhci_hcd *xhci;
 803         struct xhci_virt_ep *ep;
 804         struct xhci_virt_ep *temp_ep;
 805         struct xhci_ring *ring;
 806         struct xhci_td *cur_td;
 807         int ret, i, j;
 808         unsigned long flags;
 809
 810         ep = (struct xhci_virt_ep *) arg;
 811         xhci = ep->xhci;
 812
 813         spin_lock_irqsave(&xhci->lock, flags);
 814
 815         ep->stop_cmds_pending--;
 816         if (xhci->xhc_state & XHCI_STATE_DYING) {
 817                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 818                                 "xHCI as DYING, exiting.\n");
 819                 spin_unlock_irqrestore(&xhci->lock, flags);
 820                 return;
 821         }
 822         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 823                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 824                                 "exiting.\n");
 825                 spin_unlock_irqrestore(&xhci->lock, flags);
 826                 return;
 827         }
 828
 829         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 830         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 831         /* Oops, HC is dead or dying or at least not responding to the stop
 832          * endpoint command.
 833          */
 834         xhci->xhc_state |= XHCI_STATE_DYING;
 835         /* Disable interrupts from the host controller and start halting it */
 836         xhci_quiesce(xhci);
 837         spin_unlock_irqrestore(&xhci->lock, flags);
 838
 839         ret = xhci_halt(xhci);
 840
 841         spin_lock_irqsave(&xhci->lock, flags);
 842         if (ret < 0) {
 843                 /* This is bad; the host is not responding to commands and it's
 844                  * not allowing itself to be halted.  At least interrupts are
 845                  * disabled. If we call usb_hc_died(), it will attempt to
 846                  * disconnect all device drivers under this host.  Those
 847                  * disconnect() methods will wait for all URBs to be unlinked,
 848                  * so we must complete them.
 849                  */
 850                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 851                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 852                 /* We could turn all TDs on the rings to no-ops.  This won't
 853                  * help if the host has cached part of the ring, and is slow if
 854                  * we want to preserve the cycle bit.  Skip it and hope the host
 855                  * doesn't touch the memory.
 856                  */
 857         }
 858         for (i = 0; i < MAX_HC_SLOTS; i++) {
 859                 if (!xhci->devs[i])
 860                         continue;
 861                 for (j = 0; j < 31; j++) {
 862                         temp_ep = &xhci->devs[i]->eps[j];
 863                         ring = temp_ep->ring;
 864                         if (!ring)
 865                                 continue;
 866                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 867                                         "ep index %u\n", i, j);
 868                         while (!list_empty(&ring->td_list)) {
 869                                 cur_td = list_first_entry(&ring->td_list,
 870                                                 struct xhci_td,
 871                                                 td_list);
 872                                 list_del_init(&cur_td->td_list);
 873                                 if (!list_empty(&cur_td->cancelled_td_list))
 874                                         list_del_init(&cur_td->cancelled_td_list);
 875                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 876                                                 -ESHUTDOWN, "killed");
 877                         }
 878                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 879                                 cur_td = list_first_entry(
 880                                                 &temp_ep->cancelled_td_list,
 881                                                 struct xhci_td,
 882                                                 cancelled_td_list);
 883                                 list_del_init(&cur_td->cancelled_td_list);
 884                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 885                                                 -ESHUTDOWN, "killed");
 886                         }
 887                 }
 888         }
 889         spin_unlock_irqrestore(&xhci->lock, flags);
 890         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 891         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 892         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 893 }
 894
 895 /*
 896  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 897  * we need to clear the set deq pending flag in the endpoint ring state, so that
 898  * the TD queueing code can ring the doorbell again.  We also need to ring the
 899  * endpoint doorbell to restart the ring, but only if there aren't more
 900  * cancellations pending.
 901  */
 902 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 903                 struct xhci_event_cmd *event,
 904                 union xhci_trb *trb)
 905 {
 906         unsigned int slot_id;
 907         unsigned int ep_index;
 908         unsigned int stream_id;
 909         struct xhci_ring *ep_ring;
 910         struct xhci_virt_device *dev;
 911         struct xhci_ep_ctx *ep_ctx;
 912         struct xhci_slot_ctx *slot_ctx;
 913
 914         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 915         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 916         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 917         dev = xhci->devs[slot_id];
 918
 919         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 920         if (!ep_ring) {
 921                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 922                                 "freed stream ID %u\n",
 923                                 stream_id);
 924                 /* XXX: Harmless??? */
 925                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 926                 return;
 927         }
 928
 929         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 930         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 931
 932         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 933                 unsigned int ep_state;
 934                 unsigned int slot_state;
 935
 936                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 937                 case COMP_TRB_ERR:
 938                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 939                                         "of stream ID configuration\n");
 940                         break;
 941                 case COMP_CTX_STATE:
 942                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 943                                         "to incorrect slot or ep state.\n");
 944                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 945                         ep_state &= EP_STATE_MASK;
 946                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 947                         slot_state = GET_SLOT_STATE(slot_state);
 948                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 949                                         slot_state, ep_state);
 950                         break;
 951                 case COMP_EBADSLT:
 952                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 953                                         "slot %u was not enabled.\n", slot_id);
 954                         break;
 955                 default:
 956                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 957                                         "completion code of %u.\n",
 958                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 959                         break;
 960                 }
 961                 /* OK what do we do now?  The endpoint state is hosed, and we
 962                  * should never get to this point if the synchronization between
 963                  * queueing, and endpoint state are correct.  This might happen
 964                  * if the device gets disconnected after we've finished
 965                  * cancelling URBs, which might not be an error...
 966                  */
 967         } else {
 968                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 969                          le64_to_cpu(ep_ctx->deq));
 970                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 971                                          dev->eps[ep_index].queued_deq_ptr) ==
 972                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 973                         /* Update the ring's dequeue segment and dequeue pointer
 974                          * to reflect the new position.
 975                          */
 976                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 977                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 978                 } else {
 979                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 980                                         "Ptr command & xHCI internal state.\n");
 981                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 982                                         dev->eps[ep_index].queued_deq_seg,
 983                                         dev->eps[ep_index].queued_deq_ptr);
 984                 }
 985         }
 986
 987         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 988         dev->eps[ep_index].queued_deq_seg = NULL;
 989         dev->eps[ep_index].queued_deq_ptr = NULL;
 990         /* Restart any rings with pending URBs */
 991         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 992 }
 993
 994 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 995                 struct xhci_event_cmd *event,
 996                 union xhci_trb *trb)
 997 {
 998         int slot_id;
 999         unsigned int ep_index;
1000
1001         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1002         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1003         /* This command will only fail if the endpoint wasn't halted,
1004          * but we don't care.
1005          */
1006         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1007                  GET_COMP_CODE(le32_to_cpu(event->status)));
1008
1009         /* HW with the reset endpoint quirk needs to have a configure endpoint
1010          * command complete before the endpoint can be used.  Queue that here
1011          * because the HW can't handle two commands being queued in a row.
1012          */
1013         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1014                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1015                 xhci_queue_configure_endpoint(xhci,
1016                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1017                                 false);
1018                 xhci_ring_cmd_db(xhci);
1019         } else {
1020                 /* Clear our internal halted state and restart the ring(s) */
1021                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1022                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1023         }
1024 }
1025
1026 /* Check to see if a command in the device's command queue matches this one.
1027  * Signal the completion or free the command, and return 1.  Return 0 if the
1028  * completed command isn't at the head of the command list.
1029  */
1030 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1031                 struct xhci_virt_device *virt_dev,
1032                 struct xhci_event_cmd *event)
1033 {
1034         struct xhci_command *command;
1035
1036         if (list_empty(&virt_dev->cmd_list))
1037                 return 0;
1038
1039         command = list_entry(virt_dev->cmd_list.next,
1040                         struct xhci_command, cmd_list);
1041         if (xhci->cmd_ring->dequeue != command->command_trb)
1042                 return 0;
1043
1044         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1045         list_del(&command->cmd_list);
1046         if (command->completion)
1047                 complete(command->completion);
1048         else
1049                 xhci_free_command(xhci, command);
1050         return 1;
1051 }
1052
1053 static void handle_cmd_completion(struct xhci_hcd *xhci,
1054                 struct xhci_event_cmd *event)
1055 {
1056         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1057         u64 cmd_dma;
1058         dma_addr_t cmd_dequeue_dma;
1059         struct xhci_input_control_ctx *ctrl_ctx;
1060         struct xhci_virt_device *virt_dev;
1061         unsigned int ep_index;
1062         struct xhci_ring *ep_ring;
1063         unsigned int ep_state;
1064
1065         cmd_dma = le64_to_cpu(event->cmd_trb);
1066         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1067                         xhci->cmd_ring->dequeue);
1068         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1069         if (cmd_dequeue_dma == 0) {
1070                 xhci->error_bitmask |= 1 << 4;
1071                 return;
1072         }
1073         /* Does the DMA address match our internal dequeue pointer address? */
1074         if (cmd_dma != (u64) cmd_dequeue_dma) {
1075                 xhci->error_bitmask |= 1 << 5;
1076                 return;
1077         }
1078         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1079                 & TRB_TYPE_BITMASK) {
1080         case TRB_TYPE(TRB_ENABLE_SLOT):
1081                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1082                         xhci->slot_id = slot_id;
1083                 else
1084                         xhci->slot_id = 0;
1085                 complete(&xhci->addr_dev);
1086                 break;
1087         case TRB_TYPE(TRB_DISABLE_SLOT):
1088                 if (xhci->devs[slot_id]) {
1089                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1090                                 /* Delete default control endpoint resources */
1091                                 xhci_free_device_endpoint_resources(xhci,
1092                                                 xhci->devs[slot_id], true);
1093                         xhci_free_virt_device(xhci, slot_id);
1094                 }
1095                 break;
1096         case TRB_TYPE(TRB_CONFIG_EP):
1097                 virt_dev = xhci->devs[slot_id];
1098                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1099                         break;
1100                 /*
1101                  * Configure endpoint commands can come from the USB core
1102                  * configuration or alt setting changes, or because the HW
1103                  * needed an extra configure endpoint command after a reset
1104                  * endpoint command or streams were being configured.
1105                  * If the command was for a halted endpoint, the xHCI driver
1106                  * is not waiting on the configure endpoint command.
1107                  */
1108                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1109                                 virt_dev->in_ctx);
1110                 /* Input ctx add_flags are the endpoint index plus one */
1111                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1112                 /* A usb_set_interface() call directly after clearing a halted
1113                  * condition may race on this quirky hardware.  Not worth
1114                  * worrying about, since this is prototype hardware.  Not sure
1115                  * if this will work for streams, but streams support was
1116                  * untested on this prototype.
1117                  */
1118                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1119                                 ep_index != (unsigned int) -1 &&
1120                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1121                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1122                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1123                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1124                         if (!(ep_state & EP_HALTED))
1125                                 goto bandwidth_change;
1126                         xhci_dbg(xhci, "Completed config ep cmd - "
1127                                         "last ep index = %d, state = %d\n",
1128                                         ep_index, ep_state);
1129                         /* Clear internal halted state and restart ring(s) */
1130                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1131                                 ~EP_HALTED;
1132                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1133                         break;
1134                 }
1135 bandwidth_change:
1136                 xhci_dbg(xhci, "Completed config ep cmd\n");
1137                 xhci->devs[slot_id]->cmd_status =
1138                         GET_COMP_CODE(le32_to_cpu(event->status));
1139                 complete(&xhci->devs[slot_id]->cmd_completion);
1140                 break;
1141         case TRB_TYPE(TRB_EVAL_CONTEXT):
1142                 virt_dev = xhci->devs[slot_id];
1143                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1144                         break;
1145                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1146                 complete(&xhci->devs[slot_id]->cmd_completion);
1147                 break;
1148         case TRB_TYPE(TRB_ADDR_DEV):
1149                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1150                 complete(&xhci->addr_dev);
1151                 break;
1152         case TRB_TYPE(TRB_STOP_RING):
1153                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1154                 break;
1155         case TRB_TYPE(TRB_SET_DEQ):
1156                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1157                 break;
1158         case TRB_TYPE(TRB_CMD_NOOP):
1159                 break;
1160         case TRB_TYPE(TRB_RESET_EP):
1161                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1162                 break;
1163         case TRB_TYPE(TRB_RESET_DEV):
1164                 xhci_dbg(xhci, "Completed reset device command.\n");
1165                 slot_id = TRB_TO_SLOT_ID(
1166                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1167                 virt_dev = xhci->devs[slot_id];
1168                 if (virt_dev)
1169                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1170                 else
1171                         xhci_warn(xhci, "Reset device command completion "
1172                                         "for disabled slot %u\n", slot_id);
1173                 break;
1174         case TRB_TYPE(TRB_NEC_GET_FW):
1175                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1176                         xhci->error_bitmask |= 1 << 6;
1177                         break;
1178                 }
1179                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1180                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1181                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1182                 break;
1183         default:
1184                 /* Skip over unknown commands on the event ring */
1185                 xhci->error_bitmask |= 1 << 6;
1186                 break;
1187         }
1188         inc_deq(xhci, xhci->cmd_ring, false);
1189 }
1190
1191 static void handle_vendor_event(struct xhci_hcd *xhci,
1192                 union xhci_trb *event)
1193 {
1194         u32 trb_type;
1195
1196         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1197         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1198         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1199                 handle_cmd_completion(xhci, &event->event_cmd);
1200 }
1201
1202 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1203  * port registers -- USB 3.0 and USB 2.0).
1204  *
1205  * Returns a zero-based port number, which is suitable for indexing into each of
1206  * the split roothubs' port arrays and bus state arrays.
1207  * Add one to it in order to call xhci_find_slot_id_by_port.
1208  */
1209 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1210                 struct xhci_hcd *xhci, u32 port_id)
1211 {
1212         unsigned int i;
1213         unsigned int num_similar_speed_ports = 0;
1214
1215         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1216          * and usb2_ports are 0-based indexes.  Count the number of similar
1217          * speed ports, up to 1 port before this port.
1218          */
1219         for (i = 0; i < (port_id - 1); i++) {
1220                 u8 port_speed = xhci->port_array[i];
1221
1222                 /*
1223                  * Skip ports that don't have known speeds, or have duplicate
1224                  * Extended Capabilities port speed entries.
1225                  */
1226                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1227                         continue;
1228
1229                 /*
1230                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1231                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1232                  * matches the device speed, it's a similar speed port.
1233                  */
1234                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1235                         num_similar_speed_ports++;
1236         }
1237         return num_similar_speed_ports;
1238 }
1239
1240 static void handle_device_notification(struct xhci_hcd *xhci,
1241                 union xhci_trb *event)
1242 {
1243         u32 slot_id;
1244         struct usb_device *udev;
1245
1246         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1247         if (!xhci->devs[slot_id]) {
1248                 xhci_warn(xhci, "Device Notification event for "
1249                                 "unused slot %u\n", slot_id);
1250                 return;
1251         }
1252
1253         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1254                         slot_id);
1255         udev = xhci->devs[slot_id]->udev;
1256         if (udev && udev->parent)
1257                 usb_wakeup_notification(udev->parent, udev->portnum);
1258 }
1259
1260 static void handle_port_status(struct xhci_hcd *xhci,
1261                 union xhci_trb *event)
1262 {
1263         struct usb_hcd *hcd;
1264         u32 port_id;
1265         u32 temp, temp1;
1266         int max_ports;
1267         int slot_id;
1268         unsigned int faked_port_index;
1269         u8 major_revision;
1270         struct xhci_bus_state *bus_state;
1271         __le32 __iomem **port_array;
1272         bool bogus_port_status = false;
1273
1274         /* Port status change events always have a successful completion code */
1275         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1276                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1277                 xhci->error_bitmask |= 1 << 8;
1278         }
1279         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1280         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1281
1282         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1283         if ((port_id <= 0) || (port_id > max_ports)) {
1284                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1285                 bogus_port_status = true;
1286                 goto cleanup;
1287         }
1288
1289         /* Figure out which usb_hcd this port is attached to:
1290          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1291          */
1292         major_revision = xhci->port_array[port_id - 1];
1293         if (major_revision == 0) {
1294                 xhci_warn(xhci, "Event for port %u not in "
1295                                 "Extended Capabilities, ignoring.\n",
1296                                 port_id);
1297                 bogus_port_status = true;
1298                 goto cleanup;
1299         }
1300         if (major_revision == DUPLICATE_ENTRY) {
1301                 xhci_warn(xhci, "Event for port %u duplicated in"
1302                                 "Extended Capabilities, ignoring.\n",
1303                                 port_id);
1304                 bogus_port_status = true;
1305                 goto cleanup;
1306         }
1307
1308         /*
1309          * Hardware port IDs reported by a Port Status Change Event include USB
1310          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1311          * resume event, but we first need to translate the hardware port ID
1312          * into the index into the ports on the correct split roothub, and the
1313          * correct bus_state structure.
1314          */
1315         /* Find the right roothub. */
1316         hcd = xhci_to_hcd(xhci);
1317         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1318                 hcd = xhci->shared_hcd;
1319         bus_state = &xhci->bus_state[hcd_index(hcd)];
1320         if (hcd->speed == HCD_USB3)
1321                 port_array = xhci->usb3_ports;
1322         else
1323                 port_array = xhci->usb2_ports;
1324         /* Find the faked port hub number */
1325         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1326                         port_id);
1327
1328         temp = xhci_readl(xhci, port_array[faked_port_index]);
1329         if (hcd->state == HC_STATE_SUSPENDED) {
1330                 xhci_dbg(xhci, "resume root hub\n");
1331                 usb_hcd_resume_root_hub(hcd);
1332         }
1333
1334         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1335                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1336
1337                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1338                 if (!(temp1 & CMD_RUN)) {
1339                         xhci_warn(xhci, "xHC is not running.\n");
1340                         goto cleanup;
1341                 }
1342
1343                 if (DEV_SUPERSPEED(temp)) {
1344                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1345                         /* Set a flag to say the port signaled remote wakeup,
1346                          * so we can tell the difference between the end of
1347                          * device and host initiated resume.
1348                          */
1349                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1350                         xhci_test_and_clear_bit(xhci, port_array,
1351                                         faked_port_index, PORT_PLC);
1352                         xhci_set_link_state(xhci, port_array, faked_port_index,
1353                                                 XDEV_U0);
1354                         /* Need to wait until the next link state change
1355                          * indicates the device is actually in U0.
1356                          */
1357                         bogus_port_status = true;
1358                         goto cleanup;
1359                 } else {
1360                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1361                         bus_state->resume_done[faked_port_index] = jiffies +
1362                                 msecs_to_jiffies(20);
1363                         mod_timer(&hcd->rh_timer,
1364                                   bus_state->resume_done[faked_port_index]);
1365                         /* Do the rest in GetPortStatus */
1366                 }
1367         }
1368
1369         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1370                         DEV_SUPERSPEED(temp)) {
1371                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1372                 /* We've just brought the device into U0 through either the
1373                  * Resume state after a device remote wakeup, or through the
1374                  * U3Exit state after a host-initiated resume.  If it's a device
1375                  * initiated remote wake, don't pass up the link state change,
1376                  * so the roothub behavior is consistent with external
1377                  * USB 3.0 hub behavior.
1378                  */
1379                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1380                                 faked_port_index + 1);
1381                 if (slot_id && xhci->devs[slot_id])
1382                         xhci_ring_device(xhci, slot_id);
1383                 if (bus_state->port_remote_wakeup && (1 << faked_port_index)) {
1384                         bus_state->port_remote_wakeup &=
1385                                 ~(1 << faked_port_index);
1386                         xhci_test_and_clear_bit(xhci, port_array,
1387                                         faked_port_index, PORT_PLC);
1388                         usb_wakeup_notification(hcd->self.root_hub,
1389                                         faked_port_index + 1);
1390                         bogus_port_status = true;
1391                         goto cleanup;
1392                 }
1393         }
1394
1395         if (hcd->speed != HCD_USB3)
1396                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1397                                         PORT_PLC);
1398
1399 cleanup:
1400         /* Update event ring dequeue pointer before dropping the lock */
1401         inc_deq(xhci, xhci->event_ring, true);
1402
1403         /* Don't make the USB core poll the roothub if we got a bad port status
1404          * change event.  Besides, at that point we can't tell which roothub
1405          * (USB 2.0 or USB 3.0) to kick.
1406          */
1407         if (bogus_port_status)
1408                 return;
1409
1410         spin_unlock(&xhci->lock);
1411         /* Pass this up to the core */
1412         usb_hcd_poll_rh_status(hcd);
1413         spin_lock(&xhci->lock);
1414 }
1415
1416 /*
1417  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1418  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1419  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1420  * returns 0.
1421  */
1422 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1423                 union xhci_trb  *start_trb,
1424                 union xhci_trb  *end_trb,
1425                 dma_addr_t      suspect_dma)
1426 {
1427         dma_addr_t start_dma;
1428         dma_addr_t end_seg_dma;
1429         dma_addr_t end_trb_dma;
1430         struct xhci_segment *cur_seg;
1431
1432         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1433         cur_seg = start_seg;
1434
1435         do {
1436                 if (start_dma == 0)
1437                         return NULL;
1438                 /* We may get an event for a Link TRB in the middle of a TD */
1439                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1440                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1441                 /* If the end TRB isn't in this segment, this is set to 0 */
1442                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1443
1444                 if (end_trb_dma > 0) {
1445                         /* The end TRB is in this segment, so suspect should be here */
1446                         if (start_dma <= end_trb_dma) {
1447                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1448                                         return cur_seg;
1449                         } else {
1450                                 /* Case for one segment with
1451                                  * a TD wrapped around to the top
1452                                  */
1453                                 if ((suspect_dma >= start_dma &&
1454                                                         suspect_dma <= end_seg_dma) ||
1455                                                 (suspect_dma >= cur_seg->dma &&
1456                                                  suspect_dma <= end_trb_dma))
1457                                         return cur_seg;
1458                         }
1459                         return NULL;
1460                 } else {
1461                         /* Might still be somewhere in this segment */
1462                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1463                                 return cur_seg;
1464                 }
1465                 cur_seg = cur_seg->next;
1466                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1467         } while (cur_seg != start_seg);
1468
1469         return NULL;
1470 }
1471
1472 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1473                 unsigned int slot_id, unsigned int ep_index,
1474                 unsigned int stream_id,
1475                 struct xhci_td *td, union xhci_trb *event_trb)
1476 {
1477         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1478         ep->ep_state |= EP_HALTED;
1479         ep->stopped_td = td;
1480         ep->stopped_trb = event_trb;
1481         ep->stopped_stream = stream_id;
1482
1483         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1484         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1485
1486         ep->stopped_td = NULL;
1487         ep->stopped_trb = NULL;
1488         ep->stopped_stream = 0;
1489
1490         xhci_ring_cmd_db(xhci);
1491 }
1492
1493 /* Check if an error has halted the endpoint ring.  The class driver will
1494  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1495  * However, a babble and other errors also halt the endpoint ring, and the class
1496  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1497  * Ring Dequeue Pointer command manually.
1498  */
1499 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1500                 struct xhci_ep_ctx *ep_ctx,
1501                 unsigned int trb_comp_code)
1502 {
1503         /* TRB completion codes that may require a manual halt cleanup */
1504         if (trb_comp_code == COMP_TX_ERR ||
1505                         trb_comp_code == COMP_BABBLE ||
1506                         trb_comp_code == COMP_SPLIT_ERR)
1507                 /* The 0.96 spec says a babbling control endpoint
1508                  * is not halted. The 0.96 spec says it is.  Some HW
1509                  * claims to be 0.95 compliant, but it halts the control
1510                  * endpoint anyway.  Check if a babble halted the
1511                  * endpoint.
1512                  */
1513                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1514                     cpu_to_le32(EP_STATE_HALTED))
1515                         return 1;
1516
1517         return 0;
1518 }
1519
1520 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1521 {
1522         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1523                 /* Vendor defined "informational" completion code,
1524                  * treat as not-an-error.
1525                  */
1526                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1527                                 trb_comp_code);
1528                 xhci_dbg(xhci, "Treating code as success.\n");
1529                 return 1;
1530         }
1531         return 0;
1532 }
1533
1534 /*
1535  * Finish the td processing, remove the td from td list;
1536  * Return 1 if the urb can be given back.
1537  */
1538 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1539         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1540         struct xhci_virt_ep *ep, int *status, bool skip)
1541 {
1542         struct xhci_virt_device *xdev;
1543         struct xhci_ring *ep_ring;
1544         unsigned int slot_id;
1545         int ep_index;
1546         struct urb *urb = NULL;
1547         struct xhci_ep_ctx *ep_ctx;
1548         int ret = 0;
1549         struct urb_priv *urb_priv;
1550         u32 trb_comp_code;
1551
1552         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1553         xdev = xhci->devs[slot_id];
1554         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1555         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1556         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1557         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1558
1559         if (skip)
1560                 goto td_cleanup;
1561
1562         if (trb_comp_code == COMP_STOP_INVAL ||
1563                         trb_comp_code == COMP_STOP) {
1564                 /* The Endpoint Stop Command completion will take care of any
1565                  * stopped TDs.  A stopped TD may be restarted, so don't update
1566                  * the ring dequeue pointer or take this TD off any lists yet.
1567                  */
1568                 ep->stopped_td = td;
1569                 ep->stopped_trb = event_trb;
1570                 return 0;
1571         } else {
1572                 if (trb_comp_code == COMP_STALL) {
1573                         /* The transfer is completed from the driver's
1574                          * perspective, but we need to issue a set dequeue
1575                          * command for this stalled endpoint to move the dequeue
1576                          * pointer past the TD.  We can't do that here because
1577                          * the halt condition must be cleared first.  Let the
1578                          * USB class driver clear the stall later.
1579                          */
1580                         ep->stopped_td = td;
1581                         ep->stopped_trb = event_trb;
1582                         ep->stopped_stream = ep_ring->stream_id;
1583                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1584                                         ep_ctx, trb_comp_code)) {
1585                         /* Other types of errors halt the endpoint, but the
1586                          * class driver doesn't call usb_reset_endpoint() unless
1587                          * the error is -EPIPE.  Clear the halted status in the
1588                          * xHCI hardware manually.
1589                          */
1590                         xhci_cleanup_halted_endpoint(xhci,
1591                                         slot_id, ep_index, ep_ring->stream_id,
1592                                         td, event_trb);
1593                 } else {
1594                         /* Update ring dequeue pointer */
1595                         while (ep_ring->dequeue != td->last_trb)
1596                                 inc_deq(xhci, ep_ring, false);
1597                         inc_deq(xhci, ep_ring, false);
1598                 }
1599
1600 td_cleanup:
1601                 /* Clean up the endpoint's TD list */
1602                 urb = td->urb;
1603                 urb_priv = urb->hcpriv;
1604
1605                 /* Do one last check of the actual transfer length.
1606                  * If the host controller said we transferred more data than
1607                  * the buffer length, urb->actual_length will be a very big
1608                  * number (since it's unsigned).  Play it safe and say we didn't
1609                  * transfer anything.
1610                  */
1611                 if (urb->actual_length > urb->transfer_buffer_length) {
1612                         xhci_warn(xhci, "URB transfer length is wrong, "
1613                                         "xHC issue? req. len = %u, "
1614                                         "act. len = %u\n",
1615                                         urb->transfer_buffer_length,
1616                                         urb->actual_length);
1617                         urb->actual_length = 0;
1618                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1619                                 *status = -EREMOTEIO;
1620                         else
1621                                 *status = 0;
1622                 }
1623                 list_del_init(&td->td_list);
1624                 /* Was this TD slated to be cancelled but completed anyway? */
1625                 if (!list_empty(&td->cancelled_td_list))
1626                         list_del_init(&td->cancelled_td_list);
1627
1628                 urb_priv->td_cnt++;
1629                 /* Giveback the urb when all the tds are completed */
1630                 if (urb_priv->td_cnt == urb_priv->length) {
1631                         ret = 1;
1632                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1633                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1634                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1635                                         == 0) {
1636                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1637                                                 usb_amd_quirk_pll_enable();
1638                                 }
1639                         }
1640                 }
1641         }
1642
1643         return ret;
1644 }
1645
1646 /*
1647  * Process control tds, update urb status and actual_length.
1648  */
1649 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1650         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1651         struct xhci_virt_ep *ep, int *status)
1652 {
1653         struct xhci_virt_device *xdev;
1654         struct xhci_ring *ep_ring;
1655         unsigned int slot_id;
1656         int ep_index;
1657         struct xhci_ep_ctx *ep_ctx;
1658         u32 trb_comp_code;
1659
1660         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1661         xdev = xhci->devs[slot_id];
1662         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1663         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1664         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1665         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1666
1667         switch (trb_comp_code) {
1668         case COMP_SUCCESS:
1669                 if (event_trb == ep_ring->dequeue) {
1670                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1671                                         "without IOC set??\n");
1672                         *status = -ESHUTDOWN;
1673                 } else if (event_trb != td->last_trb) {
1674                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1675                                         "without IOC set??\n");
1676                         *status = -ESHUTDOWN;
1677                 } else {
1678                         *status = 0;
1679                 }
1680                 break;
1681         case COMP_SHORT_TX:
1682                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1683                         *status = -EREMOTEIO;
1684                 else
1685                         *status = 0;
1686                 break;
1687         case COMP_STOP_INVAL:
1688         case COMP_STOP:
1689                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1690         default:
1691                 if (!xhci_requires_manual_halt_cleanup(xhci,
1692                                         ep_ctx, trb_comp_code))
1693                         break;
1694                 xhci_dbg(xhci, "TRB error code %u, "
1695                                 "halted endpoint index = %u\n",
1696                                 trb_comp_code, ep_index);
1697                 /* else fall through */
1698         case COMP_STALL:
1699                 /* Did we transfer part of the data (middle) phase? */
1700                 if (event_trb != ep_ring->dequeue &&
1701                                 event_trb != td->last_trb)
1702                         td->urb->actual_length =
1703                                 td->urb->transfer_buffer_length
1704                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1705                 else
1706                         td->urb->actual_length = 0;
1707
1708                 xhci_cleanup_halted_endpoint(xhci,
1709                         slot_id, ep_index, 0, td, event_trb);
1710                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1711         }
1712         /*
1713          * Did we transfer any data, despite the errors that might have
1714          * happened?  I.e. did we get past the setup stage?
1715          */
1716         if (event_trb != ep_ring->dequeue) {
1717                 /* The event was for the status stage */
1718                 if (event_trb == td->last_trb) {
1719                         if (td->urb->actual_length != 0) {
1720                                 /* Don't overwrite a previously set error code
1721                                  */
1722                                 if ((*status == -EINPROGRESS || *status == 0) &&
1723                                                 (td->urb->transfer_flags
1724                                                  & URB_SHORT_NOT_OK))
1725                                         /* Did we already see a short data
1726                                          * stage? */
1727                                         *status = -EREMOTEIO;
1728                         } else {
1729                                 td->urb->actual_length =
1730                                         td->urb->transfer_buffer_length;
1731                         }
1732                 } else {
1733                 /* Maybe the event was for the data stage? */
1734                         td->urb->actual_length =
1735                                 td->urb->transfer_buffer_length -
1736                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1737                         xhci_dbg(xhci, "Waiting for status "
1738                                         "stage event\n");
1739                         return 0;
1740                 }
1741         }
1742
1743         return finish_td(xhci, td, event_trb, event, ep, status, false);
1744 }
1745
1746 /*
1747  * Process isochronous tds, update urb packet status and actual_length.
1748  */
1749 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1750         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1751         struct xhci_virt_ep *ep, int *status)
1752 {
1753         struct xhci_ring *ep_ring;
1754         struct urb_priv *urb_priv;
1755         int idx;
1756         int len = 0;
1757         union xhci_trb *cur_trb;
1758         struct xhci_segment *cur_seg;
1759         struct usb_iso_packet_descriptor *frame;
1760         u32 trb_comp_code;
1761         bool skip_td = false;
1762
1763         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1764         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1765         urb_priv = td->urb->hcpriv;
1766         idx = urb_priv->td_cnt;
1767         frame = &td->urb->iso_frame_desc[idx];
1768
1769         /* handle completion code */
1770         switch (trb_comp_code) {
1771         case COMP_SUCCESS:
1772                 frame->status = 0;
1773                 break;
1774         case COMP_SHORT_TX:
1775                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1776                                 -EREMOTEIO : 0;
1777                 break;
1778         case COMP_BW_OVER:
1779                 frame->status = -ECOMM;
1780                 skip_td = true;
1781                 break;
1782         case COMP_BUFF_OVER:
1783         case COMP_BABBLE:
1784                 frame->status = -EOVERFLOW;
1785                 skip_td = true;
1786                 break;
1787         case COMP_DEV_ERR:
1788         case COMP_STALL:
1789                 frame->status = -EPROTO;
1790                 skip_td = true;
1791                 break;
1792         case COMP_STOP:
1793         case COMP_STOP_INVAL:
1794                 break;
1795         default:
1796                 frame->status = -1;
1797                 break;
1798         }
1799
1800         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1801                 frame->actual_length = frame->length;
1802                 td->urb->actual_length += frame->length;
1803         } else {
1804                 for (cur_trb = ep_ring->dequeue,
1805                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1806                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1807                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1808                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1809                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1810                 }
1811                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1812                         TRB_LEN(le32_to_cpu(event->transfer_len));
1813
1814                 if (trb_comp_code != COMP_STOP_INVAL) {
1815                         frame->actual_length = len;
1816                         td->urb->actual_length += len;
1817                 }
1818         }
1819
1820         return finish_td(xhci, td, event_trb, event, ep, status, false);
1821 }
1822
1823 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1824                         struct xhci_transfer_event *event,
1825                         struct xhci_virt_ep *ep, int *status)
1826 {
1827         struct xhci_ring *ep_ring;
1828         struct urb_priv *urb_priv;
1829         struct usb_iso_packet_descriptor *frame;
1830         int idx;
1831
1832         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1833         urb_priv = td->urb->hcpriv;
1834         idx = urb_priv->td_cnt;
1835         frame = &td->urb->iso_frame_desc[idx];
1836
1837         /* The transfer is partly done. */
1838         frame->status = -EXDEV;
1839
1840         /* calc actual length */
1841         frame->actual_length = 0;
1842
1843         /* Update ring dequeue pointer */
1844         while (ep_ring->dequeue != td->last_trb)
1845                 inc_deq(xhci, ep_ring, false);
1846         inc_deq(xhci, ep_ring, false);
1847
1848         return finish_td(xhci, td, NULL, event, ep, status, true);
1849 }
1850
1851 /*
1852  * Process bulk and interrupt tds, update urb status and actual_length.
1853  */
1854 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1855         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1856         struct xhci_virt_ep *ep, int *status)
1857 {
1858         struct xhci_ring *ep_ring;
1859         union xhci_trb *cur_trb;
1860         struct xhci_segment *cur_seg;
1861         u32 trb_comp_code;
1862
1863         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1864         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1865
1866         switch (trb_comp_code) {
1867         case COMP_SUCCESS:
1868                 /* Double check that the HW transferred everything. */
1869                 if (event_trb != td->last_trb) {
1870                         xhci_warn(xhci, "WARN Successful completion "
1871                                         "on short TX\n");
1872                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1873                                 *status = -EREMOTEIO;
1874                         else
1875                                 *status = 0;
1876                 } else {
1877                         *status = 0;
1878                 }
1879                 break;
1880         case COMP_SHORT_TX:
1881                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1882                         *status = -EREMOTEIO;
1883                 else
1884                         *status = 0;
1885                 break;
1886         default:
1887                 /* Others already handled above */
1888                 break;
1889         }
1890         if (trb_comp_code == COMP_SHORT_TX)
1891                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1892                                 "%d bytes untransferred\n",
1893                                 td->urb->ep->desc.bEndpointAddress,
1894                                 td->urb->transfer_buffer_length,
1895                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1896         /* Fast path - was this the last TRB in the TD for this URB? */
1897         if (event_trb == td->last_trb) {
1898                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1899                         td->urb->actual_length =
1900                                 td->urb->transfer_buffer_length -
1901                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1902                         if (td->urb->transfer_buffer_length <
1903                                         td->urb->actual_length) {
1904                                 xhci_warn(xhci, "HC gave bad length "
1905                                                 "of %d bytes left\n",
1906                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1907                                 td->urb->actual_length = 0;
1908                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1909                                         *status = -EREMOTEIO;
1910                                 else
1911                                         *status = 0;
1912                         }
1913                         /* Don't overwrite a previously set error code */
1914                         if (*status == -EINPROGRESS) {
1915                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1916                                         *status = -EREMOTEIO;
1917                                 else
1918                                         *status = 0;
1919                         }
1920                 } else {
1921                         td->urb->actual_length =
1922                                 td->urb->transfer_buffer_length;
1923                         /* Ignore a short packet completion if the
1924                          * untransferred length was zero.
1925                          */
1926                         if (*status == -EREMOTEIO)
1927                                 *status = 0;
1928                 }
1929         } else {
1930                 /* Slow path - walk the list, starting from the dequeue
1931                  * pointer, to get the actual length transferred.
1932                  */
1933                 td->urb->actual_length = 0;
1934                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1935                                 cur_trb != event_trb;
1936                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1937                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1938                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1939                                 td->urb->actual_length +=
1940                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1941                 }
1942                 /* If the ring didn't stop on a Link or No-op TRB, add
1943                  * in the actual bytes transferred from the Normal TRB
1944                  */
1945                 if (trb_comp_code != COMP_STOP_INVAL)
1946                         td->urb->actual_length +=
1947                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1948                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1949         }
1950
1951         return finish_td(xhci, td, event_trb, event, ep, status, false);
1952 }
1953
1954 /*
1955  * If this function returns an error condition, it means it got a Transfer
1956  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1957  * At this point, the host controller is probably hosed and should be reset.
1958  */
1959 static int handle_tx_event(struct xhci_hcd *xhci,
1960                 struct xhci_transfer_event *event)
1961 {
1962         struct xhci_virt_device *xdev;
1963         struct xhci_virt_ep *ep;
1964         struct xhci_ring *ep_ring;
1965         unsigned int slot_id;
1966         int ep_index;
1967         struct xhci_td *td = NULL;
1968         dma_addr_t event_dma;
1969         struct xhci_segment *event_seg;
1970         union xhci_trb *event_trb;
1971         struct urb *urb = NULL;
1972         int status = -EINPROGRESS;
1973         struct urb_priv *urb_priv;
1974         struct xhci_ep_ctx *ep_ctx;
1975         struct list_head *tmp;
1976         u32 trb_comp_code;
1977         int ret = 0;
1978         int td_num = 0;
1979
1980         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1981         xdev = xhci->devs[slot_id];
1982         if (!xdev) {
1983                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1984                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
1985                          (unsigned long long) xhci_trb_virt_to_dma(
1986                                  xhci->event_ring->deq_seg,
1987                                  xhci->event_ring->dequeue),
1988                          lower_32_bits(le64_to_cpu(event->buffer)),
1989                          upper_32_bits(le64_to_cpu(event->buffer)),
1990                          le32_to_cpu(event->transfer_len),
1991                          le32_to_cpu(event->flags));
1992                 xhci_dbg(xhci, "Event ring:\n");
1993                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
1994                 return -ENODEV;
1995         }
1996
1997         /* Endpoint ID is 1 based, our index is zero based */
1998         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1999         ep = &xdev->eps[ep_index];
2000         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2001         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2002         if (!ep_ring ||
2003             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2004             EP_STATE_DISABLED) {
2005                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2006                                 "or incorrect stream ring\n");
2007                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2008                          (unsigned long long) xhci_trb_virt_to_dma(
2009                                  xhci->event_ring->deq_seg,
2010                                  xhci->event_ring->dequeue),
2011                          lower_32_bits(le64_to_cpu(event->buffer)),
2012                          upper_32_bits(le64_to_cpu(event->buffer)),
2013                          le32_to_cpu(event->transfer_len),
2014                          le32_to_cpu(event->flags));
2015                 xhci_dbg(xhci, "Event ring:\n");
2016                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2017                 return -ENODEV;
2018         }
2019
2020         /* Count current td numbers if ep->skip is set */
2021         if (ep->skip) {
2022                 list_for_each(tmp, &ep_ring->td_list)
2023                         td_num++;
2024         }
2025
2026         event_dma = le64_to_cpu(event->buffer);
2027         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2028         /* Look for common error cases */
2029         switch (trb_comp_code) {
2030         /* Skip codes that require special handling depending on
2031          * transfer type
2032          */
2033         case COMP_SUCCESS:
2034         case COMP_SHORT_TX:
2035                 break;
2036         case COMP_STOP:
2037                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2038                 break;
2039         case COMP_STOP_INVAL:
2040                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2041                 break;
2042         case COMP_STALL:
2043                 xhci_dbg(xhci, "Stalled endpoint\n");
2044                 ep->ep_state |= EP_HALTED;
2045                 status = -EPIPE;
2046                 break;
2047         case COMP_TRB_ERR:
2048                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2049                 status = -EILSEQ;
2050                 break;
2051         case COMP_SPLIT_ERR:
2052         case COMP_TX_ERR:
2053                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2054                 status = -EPROTO;
2055                 break;
2056         case COMP_BABBLE:
2057                 xhci_dbg(xhci, "Babble error on endpoint\n");
2058                 status = -EOVERFLOW;
2059                 break;
2060         case COMP_DB_ERR:
2061                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2062                 status = -ENOSR;
2063                 break;
2064         case COMP_BW_OVER:
2065                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2066                 break;
2067         case COMP_BUFF_OVER:
2068                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2069                 break;
2070         case COMP_UNDERRUN:
2071                 /*
2072                  * When the Isoch ring is empty, the xHC will generate
2073                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2074                  * Underrun Event for OUT Isoch endpoint.
2075                  */
2076                 xhci_dbg(xhci, "underrun event on endpoint\n");
2077                 if (!list_empty(&ep_ring->td_list))
2078                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2079                                         "still with TDs queued?\n",
2080                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2081                                  ep_index);
2082                 goto cleanup;
2083         case COMP_OVERRUN:
2084                 xhci_dbg(xhci, "overrun event on endpoint\n");
2085                 if (!list_empty(&ep_ring->td_list))
2086                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2087                                         "still with TDs queued?\n",
2088                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2089                                  ep_index);
2090                 goto cleanup;
2091         case COMP_DEV_ERR:
2092                 xhci_warn(xhci, "WARN: detect an incompatible device");
2093                 status = -EPROTO;
2094                 break;
2095         case COMP_MISSED_INT:
2096                 /*
2097                  * When encounter missed service error, one or more isoc tds
2098                  * may be missed by xHC.
2099                  * Set skip flag of the ep_ring; Complete the missed tds as
2100                  * short transfer when process the ep_ring next time.
2101                  */
2102                 ep->skip = true;
2103                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2104                 goto cleanup;
2105         default:
2106                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2107                         status = 0;
2108                         break;
2109                 }
2110                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2111                                 "busted\n");
2112                 goto cleanup;
2113         }
2114
2115         do {
2116                 /* This TRB should be in the TD at the head of this ring's
2117                  * TD list.
2118                  */
2119                 if (list_empty(&ep_ring->td_list)) {
2120                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2121                                         "with no TDs queued?\n",
2122                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2123                                   ep_index);
2124                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2125                                  (le32_to_cpu(event->flags) &
2126                                   TRB_TYPE_BITMASK)>>10);
2127                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2128                         if (ep->skip) {
2129                                 ep->skip = false;
2130                                 xhci_dbg(xhci, "td_list is empty while skip "
2131                                                 "flag set. Clear skip flag.\n");
2132                         }
2133                         ret = 0;
2134                         goto cleanup;
2135                 }
2136
2137                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2138                 if (ep->skip && td_num == 0) {
2139                         ep->skip = false;
2140                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2141                                                 "Clear skip flag.\n");
2142                         ret = 0;
2143                         goto cleanup;
2144                 }
2145
2146                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2147                 if (ep->skip)
2148                         td_num--;
2149
2150                 /* Is this a TRB in the currently executing TD? */
2151                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2152                                 td->last_trb, event_dma);
2153
2154                 /*
2155                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2156                  * is not in the current TD pointed by ep_ring->dequeue because
2157                  * that the hardware dequeue pointer still at the previous TRB
2158                  * of the current TD. The previous TRB maybe a Link TD or the
2159                  * last TRB of the previous TD. The command completion handle
2160                  * will take care the rest.
2161                  */
2162                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2163                         ret = 0;
2164                         goto cleanup;
2165                 }
2166
2167                 if (!event_seg) {
2168                         if (!ep->skip ||
2169                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2170                                 /* Some host controllers give a spurious
2171                                  * successful event after a short transfer.
2172                                  * Ignore it.
2173                                  */
2174                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2175                                                 ep_ring->last_td_was_short) {
2176                                         ep_ring->last_td_was_short = false;
2177                                         ret = 0;
2178                                         goto cleanup;
2179                                 }
2180                                 /* HC is busted, give up! */
2181                                 xhci_err(xhci,
2182                                         "ERROR Transfer event TRB DMA ptr not "
2183                                         "part of current TD\n");
2184                                 return -ESHUTDOWN;
2185                         }
2186
2187                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2188                         goto cleanup;
2189                 }
2190                 if (trb_comp_code == COMP_SHORT_TX)
2191                         ep_ring->last_td_was_short = true;
2192                 else
2193                         ep_ring->last_td_was_short = false;
2194
2195                 if (ep->skip) {
2196                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2197                         ep->skip = false;
2198                 }
2199
2200                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2201                                                 sizeof(*event_trb)];
2202                 /*
2203                  * No-op TRB should not trigger interrupts.
2204                  * If event_trb is a no-op TRB, it means the
2205                  * corresponding TD has been cancelled. Just ignore
2206                  * the TD.
2207                  */
2208                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2209                         xhci_dbg(xhci,
2210                                  "event_trb is a no-op TRB. Skip it\n");
2211                         goto cleanup;
2212                 }
2213
2214                 /* Now update the urb's actual_length and give back to
2215                  * the core
2216                  */
2217                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2218                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2219                                                  &status);
2220                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2221                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2222                                                  &status);
2223                 else
2224                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2225                                                  ep, &status);
2226
2227 cleanup:
2228                 /*
2229                  * Do not update event ring dequeue pointer if ep->skip is set.
2230                  * Will roll back to continue process missed tds.
2231                  */
2232                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2233                         inc_deq(xhci, xhci->event_ring, true);
2234                 }
2235
2236                 if (ret) {
2237                         urb = td->urb;
2238                         urb_priv = urb->hcpriv;
2239                         /* Leave the TD around for the reset endpoint function
2240                          * to use(but only if it's not a control endpoint,
2241                          * since we already queued the Set TR dequeue pointer
2242                          * command for stalled control endpoints).
2243                          */
2244                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2245                                 (trb_comp_code != COMP_STALL &&
2246                                         trb_comp_code != COMP_BABBLE))
2247                                 xhci_urb_free_priv(xhci, urb_priv);
2248
2249                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2250                         if ((urb->actual_length != urb->transfer_buffer_length &&
2251                                                 (urb->transfer_flags &
2252                                                  URB_SHORT_NOT_OK)) ||
2253                                         (status != 0 &&
2254                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2255                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2256                                                 "expected = %x, status = %d\n",
2257                                                 urb, urb->actual_length,
2258                                                 urb->transfer_buffer_length,
2259                                                 status);
2260                         spin_unlock(&xhci->lock);
2261                         /* EHCI, UHCI, and OHCI always unconditionally set the
2262                          * urb->status of an isochronous endpoint to 0.
2263                          */
2264                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2265                                 status = 0;
2266                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2267                         spin_lock(&xhci->lock);
2268                 }
2269
2270         /*
2271          * If ep->skip is set, it means there are missed tds on the
2272          * endpoint ring need to take care of.
2273          * Process them as short transfer until reach the td pointed by
2274          * the event.
2275          */
2276         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2277
2278         return 0;
2279 }
2280
2281 /*
2282  * This function handles all OS-owned events on the event ring.  It may drop
2283  * xhci->lock between event processing (e.g. to pass up port status changes).
2284  * Returns >0 for "possibly more events to process" (caller should call again),
2285  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2286  */
2287 static int xhci_handle_event(struct xhci_hcd *xhci)
2288 {
2289         union xhci_trb *event;
2290         int update_ptrs = 1;
2291         int ret;
2292
2293         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2294                 xhci->error_bitmask |= 1 << 1;
2295                 return 0;
2296         }
2297
2298         event = xhci->event_ring->dequeue;
2299         /* Does the HC or OS own the TRB? */
2300         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2301             xhci->event_ring->cycle_state) {
2302                 xhci->error_bitmask |= 1 << 2;
2303                 return 0;
2304         }
2305
2306         /*
2307          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2308          * speculative reads of the event's flags/data below.
2309          */
2310         rmb();
2311         /* FIXME: Handle more event types. */
2312         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2313         case TRB_TYPE(TRB_COMPLETION):
2314                 handle_cmd_completion(xhci, &event->event_cmd);
2315                 break;
2316         case TRB_TYPE(TRB_PORT_STATUS):
2317                 handle_port_status(xhci, event);
2318                 update_ptrs = 0;
2319                 break;
2320         case TRB_TYPE(TRB_TRANSFER):
2321                 ret = handle_tx_event(xhci, &event->trans_event);
2322                 if (ret < 0)
2323                         xhci->error_bitmask |= 1 << 9;
2324                 else
2325                         update_ptrs = 0;
2326                 break;
2327         case TRB_TYPE(TRB_DEV_NOTE):
2328                 handle_device_notification(xhci, event);
2329                 break;
2330         default:
2331                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2332                     TRB_TYPE(48))
2333                         handle_vendor_event(xhci, event);
2334                 else
2335                         xhci->error_bitmask |= 1 << 3;
2336         }
2337         /* Any of the above functions may drop and re-acquire the lock, so check
2338          * to make sure a watchdog timer didn't mark the host as non-responsive.
2339          */
2340         if (xhci->xhc_state & XHCI_STATE_DYING) {
2341                 xhci_dbg(xhci, "xHCI host dying, returning from "
2342                                 "event handler.\n");
2343                 return 0;
2344         }
2345
2346         if (update_ptrs)
2347                 /* Update SW event ring dequeue pointer */
2348                 inc_deq(xhci, xhci->event_ring, true);
2349
2350         /* Are there more items on the event ring?  Caller will call us again to
2351          * check.
2352          */
2353         return 1;
2354 }
2355
2356 /*
2357  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2358  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2359  * indicators of an event TRB error, but we check the status *first* to be safe.
2360  */
2361 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2362 {
2363         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2364         u32 status;
2365         union xhci_trb *trb;
2366         u64 temp_64;
2367         union xhci_trb *event_ring_deq;
2368         dma_addr_t deq;
2369
2370         spin_lock(&xhci->lock);
2371         trb = xhci->event_ring->dequeue;
2372         /* Check if the xHC generated the interrupt, or the irq is shared */
2373         status = xhci_readl(xhci, &xhci->op_regs->status);
2374         if (status == 0xffffffff)
2375                 goto hw_died;
2376
2377         if (!(status & STS_EINT)) {
2378                 spin_unlock(&xhci->lock);
2379                 return IRQ_NONE;
2380         }
2381         if (status & STS_FATAL) {
2382                 xhci_warn(xhci, "WARNING: Host System Error\n");
2383                 xhci_halt(xhci);
2384 hw_died:
2385                 spin_unlock(&xhci->lock);
2386                 return -ESHUTDOWN;
2387         }
2388
2389         /*
2390          * Clear the op reg interrupt status first,
2391          * so we can receive interrupts from other MSI-X interrupters.
2392          * Write 1 to clear the interrupt status.
2393          */
2394         status |= STS_EINT;
2395         xhci_writel(xhci, status, &xhci->op_regs->status);
2396         /* FIXME when MSI-X is supported and there are multiple vectors */
2397         /* Clear the MSI-X event interrupt status */
2398
2399         if (hcd->irq) {
2400                 u32 irq_pending;
2401                 /* Acknowledge the PCI interrupt */
2402                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2403                 irq_pending |= 0x3;
2404                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2405         }
2406
2407         if (xhci->xhc_state & XHCI_STATE_DYING) {
2408                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2409                                 "Shouldn't IRQs be disabled?\n");
2410                 /* Clear the event handler busy flag (RW1C);
2411                  * the event ring should be empty.
2412                  */
2413                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2414                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2415                                 &xhci->ir_set->erst_dequeue);
2416                 spin_unlock(&xhci->lock);
2417
2418                 return IRQ_HANDLED;
2419         }
2420
2421         event_ring_deq = xhci->event_ring->dequeue;
2422         /* FIXME this should be a delayed service routine
2423          * that clears the EHB.
2424          */
2425         while (xhci_handle_event(xhci) > 0) {}
2426
2427         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2428         /* If necessary, update the HW's version of the event ring deq ptr. */
2429         if (event_ring_deq != xhci->event_ring->dequeue) {
2430                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2431                                 xhci->event_ring->dequeue);
2432                 if (deq == 0)
2433                         xhci_warn(xhci, "WARN something wrong with SW event "
2434                                         "ring dequeue ptr.\n");
2435                 /* Update HC event ring dequeue pointer */
2436                 temp_64 &= ERST_PTR_MASK;
2437                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2438         }
2439
2440         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2441         temp_64 |= ERST_EHB;
2442         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2443
2444         spin_unlock(&xhci->lock);
2445
2446         return IRQ_HANDLED;
2447 }
2448
2449 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2450 {
2451         return xhci_irq(hcd);
2452 }
2453
2454 /****           Endpoint Ring Operations        ****/
2455
2456 /*
2457  * Generic function for queueing a TRB on a ring.
2458  * The caller must have checked to make sure there's room on the ring.
2459  *
2460  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2461  *                      prepare_transfer()?
2462  */
2463 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2464                 bool consumer, bool more_trbs_coming, bool isoc,
2465                 u32 field1, u32 field2, u32 field3, u32 field4)
2466 {
2467         struct xhci_generic_trb *trb;
2468
2469         trb = &ring->enqueue->generic;
2470         trb->field[0] = cpu_to_le32(field1);
2471         trb->field[1] = cpu_to_le32(field2);
2472         trb->field[2] = cpu_to_le32(field3);
2473         trb->field[3] = cpu_to_le32(field4);
2474         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2475 }
2476
2477 /*
2478  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2479  * FIXME allocate segments if the ring is full.
2480  */
2481 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2482                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2483 {
2484         /* Make sure the endpoint has been added to xHC schedule */
2485         switch (ep_state) {
2486         case EP_STATE_DISABLED:
2487                 /*
2488                  * USB core changed config/interfaces without notifying us,
2489                  * or hardware is reporting the wrong state.
2490                  */
2491                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2492                 return -ENOENT;
2493         case EP_STATE_ERROR:
2494                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2495                 /* FIXME event handling code for error needs to clear it */
2496                 /* XXX not sure if this should be -ENOENT or not */
2497                 return -EINVAL;
2498         case EP_STATE_HALTED:
2499                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2500         case EP_STATE_STOPPED:
2501         case EP_STATE_RUNNING:
2502                 break;
2503         default:
2504                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2505                 /*
2506                  * FIXME issue Configure Endpoint command to try to get the HC
2507                  * back into a known state.
2508                  */
2509                 return -EINVAL;
2510         }
2511         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2512                 /* FIXME allocate more room */
2513                 xhci_err(xhci, "ERROR no room on ep ring\n");
2514                 return -ENOMEM;
2515         }
2516
2517         if (enqueue_is_link_trb(ep_ring)) {
2518                 struct xhci_ring *ring = ep_ring;
2519                 union xhci_trb *next;
2520
2521                 next = ring->enqueue;
2522
2523                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2524                         /* If we're not dealing with 0.95 hardware or isoc rings
2525                          * on AMD 0.96 host, clear the chain bit.
2526                          */
2527                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2528                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2529                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2530                         else
2531                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2532
2533                         wmb();
2534                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2535
2536                         /* Toggle the cycle bit after the last ring segment. */
2537                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2538                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2539                         }
2540                         ring->enq_seg = ring->enq_seg->next;
2541                         ring->enqueue = ring->enq_seg->trbs;
2542                         next = ring->enqueue;
2543                 }
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int prepare_transfer(struct xhci_hcd *xhci,
2550                 struct xhci_virt_device *xdev,
2551                 unsigned int ep_index,
2552                 unsigned int stream_id,
2553                 unsigned int num_trbs,
2554                 struct urb *urb,
2555                 unsigned int td_index,
2556                 bool isoc,
2557                 gfp_t mem_flags)
2558 {
2559         int ret;
2560         struct urb_priv *urb_priv;
2561         struct xhci_td  *td;
2562         struct xhci_ring *ep_ring;
2563         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2564
2565         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2566         if (!ep_ring) {
2567                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2568                                 stream_id);
2569                 return -EINVAL;
2570         }
2571
2572         ret = prepare_ring(xhci, ep_ring,
2573                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2574                            num_trbs, isoc, mem_flags);
2575         if (ret)
2576                 return ret;
2577
2578         urb_priv = urb->hcpriv;
2579         td = urb_priv->td[td_index];
2580
2581         INIT_LIST_HEAD(&td->td_list);
2582         INIT_LIST_HEAD(&td->cancelled_td_list);
2583
2584         if (td_index == 0) {
2585                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2586                 if (unlikely(ret))
2587                         return ret;
2588         }
2589
2590         td->urb = urb;
2591         /* Add this TD to the tail of the endpoint ring's TD list */
2592         list_add_tail(&td->td_list, &ep_ring->td_list);
2593         td->start_seg = ep_ring->enq_seg;
2594         td->first_trb = ep_ring->enqueue;
2595
2596         urb_priv->td[td_index] = td;
2597
2598         return 0;
2599 }
2600
2601 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2602 {
2603         int num_sgs, num_trbs, running_total, temp, i;
2604         struct scatterlist *sg;
2605
2606         sg = NULL;
2607         num_sgs = urb->num_mapped_sgs;
2608         temp = urb->transfer_buffer_length;
2609
2610         num_trbs = 0;
2611         for_each_sg(urb->sg, sg, num_sgs, i) {
2612                 unsigned int len = sg_dma_len(sg);
2613
2614                 /* Scatter gather list entries may cross 64KB boundaries */
2615                 running_total = TRB_MAX_BUFF_SIZE -
2616                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2617                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2618                 if (running_total != 0)
2619                         num_trbs++;
2620
2621                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2622                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2623                         num_trbs++;
2624                         running_total += TRB_MAX_BUFF_SIZE;
2625                 }
2626                 len = min_t(int, len, temp);
2627                 temp -= len;
2628                 if (temp == 0)
2629                         break;
2630         }
2631         return num_trbs;
2632 }
2633
2634 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2635 {
2636         if (num_trbs != 0)
2637                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2638                                 "TRBs, %d left\n", __func__,
2639                                 urb->ep->desc.bEndpointAddress, num_trbs);
2640         if (running_total != urb->transfer_buffer_length)
2641                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2642                                 "queued %#x (%d), asked for %#x (%d)\n",
2643                                 __func__,
2644                                 urb->ep->desc.bEndpointAddress,
2645                                 running_total, running_total,
2646                                 urb->transfer_buffer_length,
2647                                 urb->transfer_buffer_length);
2648 }
2649
2650 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2651                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2652                 struct xhci_generic_trb *start_trb)
2653 {
2654         /*
2655          * Pass all the TRBs to the hardware at once and make sure this write
2656          * isn't reordered.
2657          */
2658         wmb();
2659         if (start_cycle)
2660                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2661         else
2662                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2663         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2664 }
2665
2666 /*
2667  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2668  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2669  * (comprised of sg list entries) can take several service intervals to
2670  * transmit.
2671  */
2672 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2673                 struct urb *urb, int slot_id, unsigned int ep_index)
2674 {
2675         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2676                         xhci->devs[slot_id]->out_ctx, ep_index);
2677         int xhci_interval;
2678         int ep_interval;
2679
2680         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2681         ep_interval = urb->interval;
2682         /* Convert to microframes */
2683         if (urb->dev->speed == USB_SPEED_LOW ||
2684                         urb->dev->speed == USB_SPEED_FULL)
2685                 ep_interval *= 8;
2686         /* FIXME change this to a warning and a suggestion to use the new API
2687          * to set the polling interval (once the API is added).
2688          */
2689         if (xhci_interval != ep_interval) {
2690                 if (printk_ratelimit())
2691                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2692                                         " (%d microframe%s) than xHCI "
2693                                         "(%d microframe%s)\n",
2694                                         ep_interval,
2695                                         ep_interval == 1 ? "" : "s",
2696                                         xhci_interval,
2697                                         xhci_interval == 1 ? "" : "s");
2698                 urb->interval = xhci_interval;
2699                 /* Convert back to frames for LS/FS devices */
2700                 if (urb->dev->speed == USB_SPEED_LOW ||
2701                                 urb->dev->speed == USB_SPEED_FULL)
2702                         urb->interval /= 8;
2703         }
2704         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2705 }
2706
2707 /*
2708  * The TD size is the number of bytes remaining in the TD (including this TRB),
2709  * right shifted by 10.
2710  * It must fit in bits 21:17, so it can't be bigger than 31.
2711  */
2712 static u32 xhci_td_remainder(unsigned int remainder)
2713 {
2714         u32 max = (1 << (21 - 17 + 1)) - 1;
2715
2716         if ((remainder >> 10) >= max)
2717                 return max << 17;
2718         else
2719                 return (remainder >> 10) << 17;
2720 }
2721
2722 /*
2723  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2724  * the TD (*not* including this TRB).
2725  *
2726  * Total TD packet count = total_packet_count =
2727  *     roundup(TD size in bytes / wMaxPacketSize)
2728  *
2729  * Packets transferred up to and including this TRB = packets_transferred =
2730  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2731  *
2732  * TD size = total_packet_count - packets_transferred
2733  *
2734  * It must fit in bits 21:17, so it can't be bigger than 31.
2735  */
2736
2737 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2738                 unsigned int total_packet_count, struct urb *urb)
2739 {
2740         int packets_transferred;
2741
2742         /* One TRB with a zero-length data packet. */
2743         if (running_total == 0 && trb_buff_len == 0)
2744                 return 0;
2745
2746         /* All the TRB queueing functions don't count the current TRB in
2747          * running_total.
2748          */
2749         packets_transferred = (running_total + trb_buff_len) /
2750                 usb_endpoint_maxp(&urb->ep->desc);
2751
2752         return xhci_td_remainder(total_packet_count - packets_transferred);
2753 }
2754
2755 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2756                 struct urb *urb, int slot_id, unsigned int ep_index)
2757 {
2758         struct xhci_ring *ep_ring;
2759         unsigned int num_trbs;
2760         struct urb_priv *urb_priv;
2761         struct xhci_td *td;
2762         struct scatterlist *sg;
2763         int num_sgs;
2764         int trb_buff_len, this_sg_len, running_total;
2765         unsigned int total_packet_count;
2766         bool first_trb;
2767         u64 addr;
2768         bool more_trbs_coming;
2769
2770         struct xhci_generic_trb *start_trb;
2771         int start_cycle;
2772
2773         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2774         if (!ep_ring)
2775                 return -EINVAL;
2776
2777         num_trbs = count_sg_trbs_needed(xhci, urb);
2778         num_sgs = urb->num_mapped_sgs;
2779         total_packet_count = roundup(urb->transfer_buffer_length,
2780                         usb_endpoint_maxp(&urb->ep->desc));
2781
2782         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2783                         ep_index, urb->stream_id,
2784                         num_trbs, urb, 0, false, mem_flags);
2785         if (trb_buff_len < 0)
2786                 return trb_buff_len;
2787
2788         urb_priv = urb->hcpriv;
2789         td = urb_priv->td[0];
2790
2791         /*
2792          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2793          * until we've finished creating all the other TRBs.  The ring's cycle
2794          * state may change as we enqueue the other TRBs, so save it too.
2795          */
2796         start_trb = &ep_ring->enqueue->generic;
2797         start_cycle = ep_ring->cycle_state;
2798
2799         running_total = 0;
2800         /*
2801          * How much data is in the first TRB?
2802          *
2803          * There are three forces at work for TRB buffer pointers and lengths:
2804          * 1. We don't want to walk off the end of this sg-list entry buffer.
2805          * 2. The transfer length that the driver requested may be smaller than
2806          *    the amount of memory allocated for this scatter-gather list.
2807          * 3. TRBs buffers can't cross 64KB boundaries.
2808          */
2809         sg = urb->sg;
2810         addr = (u64) sg_dma_address(sg);
2811         this_sg_len = sg_dma_len(sg);
2812         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2813         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2814         if (trb_buff_len > urb->transfer_buffer_length)
2815                 trb_buff_len = urb->transfer_buffer_length;
2816
2817         first_trb = true;
2818         /* Queue the first TRB, even if it's zero-length */
2819         do {
2820                 u32 field = 0;
2821                 u32 length_field = 0;
2822                 u32 remainder = 0;
2823
2824                 /* Don't change the cycle bit of the first TRB until later */
2825                 if (first_trb) {
2826                         first_trb = false;
2827                         if (start_cycle == 0)
2828                                 field |= 0x1;
2829                 } else
2830                         field |= ep_ring->cycle_state;
2831
2832                 /* Chain all the TRBs together; clear the chain bit in the last
2833                  * TRB to indicate it's the last TRB in the chain.
2834                  */
2835                 if (num_trbs > 1) {
2836                         field |= TRB_CHAIN;
2837                 } else {
2838                         /* FIXME - add check for ZERO_PACKET flag before this */
2839                         td->last_trb = ep_ring->enqueue;
2840                         field |= TRB_IOC;
2841                 }
2842
2843                 /* Only set interrupt on short packet for IN endpoints */
2844                 if (usb_urb_dir_in(urb))
2845                         field |= TRB_ISP;
2846
2847                 if (TRB_MAX_BUFF_SIZE -
2848                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2849                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2850                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2851                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2852                                         (unsigned int) addr + trb_buff_len);
2853                 }
2854
2855                 /* Set the TRB length, TD size, and interrupter fields. */
2856                 if (xhci->hci_version < 0x100) {
2857                         remainder = xhci_td_remainder(
2858                                         urb->transfer_buffer_length -
2859                                         running_total);
2860                 } else {
2861                         remainder = xhci_v1_0_td_remainder(running_total,
2862                                         trb_buff_len, total_packet_count, urb);
2863                 }
2864                 length_field = TRB_LEN(trb_buff_len) |
2865                         remainder |
2866                         TRB_INTR_TARGET(0);
2867
2868                 if (num_trbs > 1)
2869                         more_trbs_coming = true;
2870                 else
2871                         more_trbs_coming = false;
2872                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2873                                 lower_32_bits(addr),
2874                                 upper_32_bits(addr),
2875                                 length_field,
2876                                 field | TRB_TYPE(TRB_NORMAL));
2877                 --num_trbs;
2878                 running_total += trb_buff_len;
2879
2880                 /* Calculate length for next transfer --
2881                  * Are we done queueing all the TRBs for this sg entry?
2882                  */
2883                 this_sg_len -= trb_buff_len;
2884                 if (this_sg_len == 0) {
2885                         --num_sgs;
2886                         if (num_sgs == 0)
2887                                 break;
2888                         sg = sg_next(sg);
2889                         addr = (u64) sg_dma_address(sg);
2890                         this_sg_len = sg_dma_len(sg);
2891                 } else {
2892                         addr += trb_buff_len;
2893                 }
2894
2895                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2896                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2897                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2898                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2899                         trb_buff_len =
2900                                 urb->transfer_buffer_length - running_total;
2901         } while (running_total < urb->transfer_buffer_length);
2902
2903         check_trb_math(urb, num_trbs, running_total);
2904         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2905                         start_cycle, start_trb);
2906         return 0;
2907 }
2908
2909 /* This is very similar to what ehci-q.c qtd_fill() does */
2910 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2911                 struct urb *urb, int slot_id, unsigned int ep_index)
2912 {
2913         struct xhci_ring *ep_ring;
2914         struct urb_priv *urb_priv;
2915         struct xhci_td *td;
2916         int num_trbs;
2917         struct xhci_generic_trb *start_trb;
2918         bool first_trb;
2919         bool more_trbs_coming;
2920         int start_cycle;
2921         u32 field, length_field;
2922
2923         int running_total, trb_buff_len, ret;
2924         unsigned int total_packet_count;
2925         u64 addr;
2926
2927         if (urb->num_sgs)
2928                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2929
2930         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2931         if (!ep_ring)
2932                 return -EINVAL;
2933
2934         num_trbs = 0;
2935         /* How much data is (potentially) left before the 64KB boundary? */
2936         running_total = TRB_MAX_BUFF_SIZE -
2937                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2938         running_total &= TRB_MAX_BUFF_SIZE - 1;
2939
2940         /* If there's some data on this 64KB chunk, or we have to send a
2941          * zero-length transfer, we need at least one TRB
2942          */
2943         if (running_total != 0 || urb->transfer_buffer_length == 0)
2944                 num_trbs++;
2945         /* How many more 64KB chunks to transfer, how many more TRBs? */
2946         while (running_total < urb->transfer_buffer_length) {
2947                 num_trbs++;
2948                 running_total += TRB_MAX_BUFF_SIZE;
2949         }
2950         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2951
2952         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2953                         ep_index, urb->stream_id,
2954                         num_trbs, urb, 0, false, mem_flags);
2955         if (ret < 0)
2956                 return ret;
2957
2958         urb_priv = urb->hcpriv;
2959         td = urb_priv->td[0];
2960
2961         /*
2962          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2963          * until we've finished creating all the other TRBs.  The ring's cycle
2964          * state may change as we enqueue the other TRBs, so save it too.
2965          */
2966         start_trb = &ep_ring->enqueue->generic;
2967         start_cycle = ep_ring->cycle_state;
2968
2969         running_total = 0;
2970         total_packet_count = roundup(urb->transfer_buffer_length,
2971                         usb_endpoint_maxp(&urb->ep->desc));
2972         /* How much data is in the first TRB? */
2973         addr = (u64) urb->transfer_dma;
2974         trb_buff_len = TRB_MAX_BUFF_SIZE -
2975                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2976         if (trb_buff_len > urb->transfer_buffer_length)
2977                 trb_buff_len = urb->transfer_buffer_length;
2978
2979         first_trb = true;
2980
2981         /* Queue the first TRB, even if it's zero-length */
2982         do {
2983                 u32 remainder = 0;
2984                 field = 0;
2985
2986                 /* Don't change the cycle bit of the first TRB until later */
2987                 if (first_trb) {
2988                         first_trb = false;
2989                         if (start_cycle == 0)
2990                                 field |= 0x1;
2991                 } else
2992                         field |= ep_ring->cycle_state;
2993
2994                 /* Chain all the TRBs together; clear the chain bit in the last
2995                  * TRB to indicate it's the last TRB in the chain.
2996                  */
2997                 if (num_trbs > 1) {
2998                         field |= TRB_CHAIN;
2999                 } else {
3000                         /* FIXME - add check for ZERO_PACKET flag before this */
3001                         td->last_trb = ep_ring->enqueue;
3002                         field |= TRB_IOC;
3003                 }
3004
3005                 /* Only set interrupt on short packet for IN endpoints */
3006                 if (usb_urb_dir_in(urb))
3007                         field |= TRB_ISP;
3008
3009                 /* Set the TRB length, TD size, and interrupter fields. */
3010                 if (xhci->hci_version < 0x100) {
3011                         remainder = xhci_td_remainder(
3012                                         urb->transfer_buffer_length -
3013                                         running_total);
3014                 } else {
3015                         remainder = xhci_v1_0_td_remainder(running_total,
3016                                         trb_buff_len, total_packet_count, urb);
3017                 }
3018                 length_field = TRB_LEN(trb_buff_len) |
3019                         remainder |
3020                         TRB_INTR_TARGET(0);
3021
3022                 if (num_trbs > 1)
3023                         more_trbs_coming = true;
3024                 else
3025                         more_trbs_coming = false;
3026                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3027                                 lower_32_bits(addr),
3028                                 upper_32_bits(addr),
3029                                 length_field,
3030                                 field | TRB_TYPE(TRB_NORMAL));
3031                 --num_trbs;
3032                 running_total += trb_buff_len;
3033
3034                 /* Calculate length for next transfer */
3035                 addr += trb_buff_len;
3036                 trb_buff_len = urb->transfer_buffer_length - running_total;
3037                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3038                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3039         } while (running_total < urb->transfer_buffer_length);
3040
3041         check_trb_math(urb, num_trbs, running_total);
3042         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3043                         start_cycle, start_trb);
3044         return 0;
3045 }
3046
3047 /* Caller must have locked xhci->lock */
3048 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3049                 struct urb *urb, int slot_id, unsigned int ep_index)
3050 {
3051         struct xhci_ring *ep_ring;
3052         int num_trbs;
3053         int ret;
3054         struct usb_ctrlrequest *setup;
3055         struct xhci_generic_trb *start_trb;
3056         int start_cycle;
3057         u32 field, length_field;
3058         struct urb_priv *urb_priv;
3059         struct xhci_td *td;
3060
3061         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3062         if (!ep_ring)
3063                 return -EINVAL;
3064
3065         /*
3066          * Need to copy setup packet into setup TRB, so we can't use the setup
3067          * DMA address.
3068          */
3069         if (!urb->setup_packet)
3070                 return -EINVAL;
3071
3072         /* 1 TRB for setup, 1 for status */
3073         num_trbs = 2;
3074         /*
3075          * Don't need to check if we need additional event data and normal TRBs,
3076          * since data in control transfers will never get bigger than 16MB
3077          * XXX: can we get a buffer that crosses 64KB boundaries?
3078          */
3079         if (urb->transfer_buffer_length > 0)
3080                 num_trbs++;
3081         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3082                         ep_index, urb->stream_id,
3083                         num_trbs, urb, 0, false, mem_flags);
3084         if (ret < 0)
3085                 return ret;
3086
3087         urb_priv = urb->hcpriv;
3088         td = urb_priv->td[0];
3089
3090         /*
3091          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3092          * until we've finished creating all the other TRBs.  The ring's cycle
3093          * state may change as we enqueue the other TRBs, so save it too.
3094          */
3095         start_trb = &ep_ring->enqueue->generic;
3096         start_cycle = ep_ring->cycle_state;
3097
3098         /* Queue setup TRB - see section 6.4.1.2.1 */
3099         /* FIXME better way to translate setup_packet into two u32 fields? */
3100         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3101         field = 0;
3102         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3103         if (start_cycle == 0)
3104                 field |= 0x1;
3105
3106         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3107         if (xhci->hci_version == 0x100) {
3108                 if (urb->transfer_buffer_length > 0) {
3109                         if (setup->bRequestType & USB_DIR_IN)
3110                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3111                         else
3112                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3113                 }
3114         }
3115
3116         queue_trb(xhci, ep_ring, false, true, false,
3117                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3118                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3119                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3120                   /* Immediate data in pointer */
3121                   field);
3122
3123         /* If there's data, queue data TRBs */
3124         /* Only set interrupt on short packet for IN endpoints */
3125         if (usb_urb_dir_in(urb))
3126                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3127         else
3128                 field = TRB_TYPE(TRB_DATA);
3129
3130         length_field = TRB_LEN(urb->transfer_buffer_length) |
3131                 xhci_td_remainder(urb->transfer_buffer_length) |
3132                 TRB_INTR_TARGET(0);
3133         if (urb->transfer_buffer_length > 0) {
3134                 if (setup->bRequestType & USB_DIR_IN)
3135                         field |= TRB_DIR_IN;
3136                 queue_trb(xhci, ep_ring, false, true, false,
3137                                 lower_32_bits(urb->transfer_dma),
3138                                 upper_32_bits(urb->transfer_dma),
3139                                 length_field,
3140                                 field | ep_ring->cycle_state);
3141         }
3142
3143         /* Save the DMA address of the last TRB in the TD */
3144         td->last_trb = ep_ring->enqueue;
3145
3146         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3147         /* If the device sent data, the status stage is an OUT transfer */
3148         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3149                 field = 0;
3150         else
3151                 field = TRB_DIR_IN;
3152         queue_trb(xhci, ep_ring, false, false, false,
3153                         0,
3154                         0,
3155                         TRB_INTR_TARGET(0),
3156                         /* Event on completion */
3157                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3158
3159         giveback_first_trb(xhci, slot_id, ep_index, 0,
3160                         start_cycle, start_trb);
3161         return 0;
3162 }
3163
3164 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3165                 struct urb *urb, int i)
3166 {
3167         int num_trbs = 0;
3168         u64 addr, td_len;
3169
3170         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3171         td_len = urb->iso_frame_desc[i].length;
3172
3173         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3174                         TRB_MAX_BUFF_SIZE);
3175         if (num_trbs == 0)
3176                 num_trbs++;
3177
3178         return num_trbs;
3179 }
3180
3181 /*
3182  * The transfer burst count field of the isochronous TRB defines the number of
3183  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3184  * devices can burst up to bMaxBurst number of packets per service interval.
3185  * This field is zero based, meaning a value of zero in the field means one
3186  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3187  * zero.  Only xHCI 1.0 host controllers support this field.
3188  */
3189 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3190                 struct usb_device *udev,
3191                 struct urb *urb, unsigned int total_packet_count)
3192 {
3193         unsigned int max_burst;
3194
3195         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3196                 return 0;
3197
3198         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3199         return roundup(total_packet_count, max_burst + 1) - 1;
3200 }
3201
3202 /*
3203  * Returns the number of packets in the last "burst" of packets.  This field is
3204  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3205  * the last burst packet count is equal to the total number of packets in the
3206  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3207  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3208  * contain 1 to (bMaxBurst + 1) packets.
3209  */
3210 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3211                 struct usb_device *udev,
3212                 struct urb *urb, unsigned int total_packet_count)
3213 {
3214         unsigned int max_burst;
3215         unsigned int residue;
3216
3217         if (xhci->hci_version < 0x100)
3218                 return 0;
3219
3220         switch (udev->speed) {
3221         case USB_SPEED_SUPER:
3222                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3223                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3224                 residue = total_packet_count % (max_burst + 1);
3225                 /* If residue is zero, the last burst contains (max_burst + 1)
3226                  * number of packets, but the TLBPC field is zero-based.
3227                  */
3228                 if (residue == 0)
3229                         return max_burst;
3230                 return residue - 1;
3231         default:
3232                 if (total_packet_count == 0)
3233                         return 0;
3234                 return total_packet_count - 1;
3235         }
3236 }
3237
3238 /* This is for isoc transfer */
3239 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3240                 struct urb *urb, int slot_id, unsigned int ep_index)
3241 {
3242         struct xhci_ring *ep_ring;
3243         struct urb_priv *urb_priv;
3244         struct xhci_td *td;
3245         int num_tds, trbs_per_td;
3246         struct xhci_generic_trb *start_trb;
3247         bool first_trb;
3248         int start_cycle;
3249         u32 field, length_field;
3250         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3251         u64 start_addr, addr;
3252         int i, j;
3253         bool more_trbs_coming;
3254
3255         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3256
3257         num_tds = urb->number_of_packets;
3258         if (num_tds < 1) {
3259                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3260                 return -EINVAL;
3261         }
3262
3263         start_addr = (u64) urb->transfer_dma;
3264         start_trb = &ep_ring->enqueue->generic;
3265         start_cycle = ep_ring->cycle_state;
3266
3267         urb_priv = urb->hcpriv;
3268         /* Queue the first TRB, even if it's zero-length */
3269         for (i = 0; i < num_tds; i++) {
3270                 unsigned int total_packet_count;
3271                 unsigned int burst_count;
3272                 unsigned int residue;
3273
3274                 first_trb = true;
3275                 running_total = 0;
3276                 addr = start_addr + urb->iso_frame_desc[i].offset;
3277                 td_len = urb->iso_frame_desc[i].length;
3278                 td_remain_len = td_len;
3279                 total_packet_count = roundup(td_len,
3280                                 usb_endpoint_maxp(&urb->ep->desc));
3281                 /* A zero-length transfer still involves at least one packet. */
3282                 if (total_packet_count == 0)
3283                         total_packet_count++;
3284                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3285                                 total_packet_count);
3286                 residue = xhci_get_last_burst_packet_count(xhci,
3287                                 urb->dev, urb, total_packet_count);
3288
3289                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3290
3291                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3292                                 urb->stream_id, trbs_per_td, urb, i, true,
3293                                 mem_flags);
3294                 if (ret < 0) {
3295                         if (i == 0)
3296                                 return ret;
3297                         goto cleanup;
3298                 }
3299
3300                 td = urb_priv->td[i];
3301                 for (j = 0; j < trbs_per_td; j++) {
3302                         u32 remainder = 0;
3303                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3304
3305                         if (first_trb) {
3306                                 /* Queue the isoc TRB */
3307                                 field |= TRB_TYPE(TRB_ISOC);
3308                                 /* Assume URB_ISO_ASAP is set */
3309                                 field |= TRB_SIA;
3310                                 if (i == 0) {
3311                                         if (start_cycle == 0)
3312                                                 field |= 0x1;
3313                                 } else
3314                                         field |= ep_ring->cycle_state;
3315                                 first_trb = false;
3316                         } else {
3317                                 /* Queue other normal TRBs */
3318                                 field |= TRB_TYPE(TRB_NORMAL);
3319                                 field |= ep_ring->cycle_state;
3320                         }
3321
3322                         /* Only set interrupt on short packet for IN EPs */
3323                         if (usb_urb_dir_in(urb))
3324                                 field |= TRB_ISP;
3325
3326                         /* Chain all the TRBs together; clear the chain bit in
3327                          * the last TRB to indicate it's the last TRB in the
3328                          * chain.
3329                          */
3330                         if (j < trbs_per_td - 1) {
3331                                 field |= TRB_CHAIN;
3332                                 more_trbs_coming = true;
3333                         } else {
3334                                 td->last_trb = ep_ring->enqueue;
3335                                 field |= TRB_IOC;
3336                                 if (xhci->hci_version == 0x100) {
3337                                         /* Set BEI bit except for the last td */
3338                                         if (i < num_tds - 1)
3339                                                 field |= TRB_BEI;
3340                                 }
3341                                 more_trbs_coming = false;
3342                         }
3343
3344                         /* Calculate TRB length */
3345                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3346                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3347                         if (trb_buff_len > td_remain_len)
3348                                 trb_buff_len = td_remain_len;
3349
3350                         /* Set the TRB length, TD size, & interrupter fields. */
3351                         if (xhci->hci_version < 0x100) {
3352                                 remainder = xhci_td_remainder(
3353                                                 td_len - running_total);
3354                         } else {
3355                                 remainder = xhci_v1_0_td_remainder(
3356                                                 running_total, trb_buff_len,
3357                                                 total_packet_count, urb);
3358                         }
3359                         length_field = TRB_LEN(trb_buff_len) |
3360                                 remainder |
3361                                 TRB_INTR_TARGET(0);
3362
3363                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3364                                 lower_32_bits(addr),
3365                                 upper_32_bits(addr),
3366                                 length_field,
3367                                 field);
3368                         running_total += trb_buff_len;
3369
3370                         addr += trb_buff_len;
3371                         td_remain_len -= trb_buff_len;
3372                 }
3373
3374                 /* Check TD length */
3375                 if (running_total != td_len) {
3376                         xhci_err(xhci, "ISOC TD length unmatch\n");
3377                         ret = -EINVAL;
3378                         goto cleanup;
3379                 }
3380         }
3381
3382         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3383                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3384                         usb_amd_quirk_pll_disable();
3385         }
3386         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3387
3388         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3389                         start_cycle, start_trb);
3390         return 0;
3391 cleanup:
3392         /* Clean up a partially enqueued isoc transfer. */
3393
3394         for (i--; i >= 0; i--)
3395                 list_del_init(&urb_priv->td[i]->td_list);
3396
3397         /* Use the first TD as a temporary variable to turn the TDs we've queued
3398          * into No-ops with a software-owned cycle bit. That way the hardware
3399          * won't accidentally start executing bogus TDs when we partially
3400          * overwrite them.  td->first_trb and td->start_seg are already set.
3401          */
3402         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3403         /* Every TRB except the first & last will have its cycle bit flipped. */
3404         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3405
3406         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3407         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3408         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3409         ep_ring->cycle_state = start_cycle;
3410         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3411         return ret;
3412 }
3413
3414 /*
3415  * Check transfer ring to guarantee there is enough room for the urb.
3416  * Update ISO URB start_frame and interval.
3417  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3418  * update the urb->start_frame by now.
3419  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3420  */
3421 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3422                 struct urb *urb, int slot_id, unsigned int ep_index)
3423 {
3424         struct xhci_virt_device *xdev;
3425         struct xhci_ring *ep_ring;
3426         struct xhci_ep_ctx *ep_ctx;
3427         int start_frame;
3428         int xhci_interval;
3429         int ep_interval;
3430         int num_tds, num_trbs, i;
3431         int ret;
3432
3433         xdev = xhci->devs[slot_id];
3434         ep_ring = xdev->eps[ep_index].ring;
3435         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3436
3437         num_trbs = 0;
3438         num_tds = urb->number_of_packets;
3439         for (i = 0; i < num_tds; i++)
3440                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3441
3442         /* Check the ring to guarantee there is enough room for the whole urb.
3443          * Do not insert any td of the urb to the ring if the check failed.
3444          */
3445         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3446                            num_trbs, true, mem_flags);
3447         if (ret)
3448                 return ret;
3449
3450         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3451         start_frame &= 0x3fff;
3452
3453         urb->start_frame = start_frame;
3454         if (urb->dev->speed == USB_SPEED_LOW ||
3455                         urb->dev->speed == USB_SPEED_FULL)
3456                 urb->start_frame >>= 3;
3457
3458         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3459         ep_interval = urb->interval;
3460         /* Convert to microframes */
3461         if (urb->dev->speed == USB_SPEED_LOW ||
3462                         urb->dev->speed == USB_SPEED_FULL)
3463                 ep_interval *= 8;
3464         /* FIXME change this to a warning and a suggestion to use the new API
3465          * to set the polling interval (once the API is added).
3466          */
3467         if (xhci_interval != ep_interval) {
3468                 if (printk_ratelimit())
3469                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3470                                         " (%d microframe%s) than xHCI "
3471                                         "(%d microframe%s)\n",
3472                                         ep_interval,
3473                                         ep_interval == 1 ? "" : "s",
3474                                         xhci_interval,
3475                                         xhci_interval == 1 ? "" : "s");
3476                 urb->interval = xhci_interval;
3477                 /* Convert back to frames for LS/FS devices */
3478                 if (urb->dev->speed == USB_SPEED_LOW ||
3479                                 urb->dev->speed == USB_SPEED_FULL)
3480                         urb->interval /= 8;
3481         }
3482         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3483 }
3484
3485 /****           Command Ring Operations         ****/
3486
3487 /* Generic function for queueing a command TRB on the command ring.
3488  * Check to make sure there's room on the command ring for one command TRB.
3489  * Also check that there's room reserved for commands that must not fail.
3490  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3491  * then only check for the number of reserved spots.
3492  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3493  * because the command event handler may want to resubmit a failed command.
3494  */
3495 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3496                 u32 field3, u32 field4, bool command_must_succeed)
3497 {
3498         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3499         int ret;
3500
3501         if (!command_must_succeed)
3502                 reserved_trbs++;
3503
3504         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3505                         reserved_trbs, false, GFP_ATOMIC);
3506         if (ret < 0) {
3507                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3508                 if (command_must_succeed)
3509                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3510                                         "unfailable commands failed.\n");
3511                 return ret;
3512         }
3513         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3514                         field3, field4 | xhci->cmd_ring->cycle_state);
3515         return 0;
3516 }
3517
3518 /* Queue a slot enable or disable request on the command ring */
3519 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3520 {
3521         return queue_command(xhci, 0, 0, 0,
3522                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3523 }
3524
3525 /* Queue an address device command TRB */
3526 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3527                 u32 slot_id)
3528 {
3529         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3530                         upper_32_bits(in_ctx_ptr), 0,
3531                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3532                         false);
3533 }
3534
3535 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3536                 u32 field1, u32 field2, u32 field3, u32 field4)
3537 {
3538         return queue_command(xhci, field1, field2, field3, field4, false);
3539 }
3540
3541 /* Queue a reset device command TRB */
3542 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3543 {
3544         return queue_command(xhci, 0, 0, 0,
3545                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3546                         false);
3547 }
3548
3549 /* Queue a configure endpoint command TRB */
3550 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3551                 u32 slot_id, bool command_must_succeed)
3552 {
3553         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3554                         upper_32_bits(in_ctx_ptr), 0,
3555                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3556                         command_must_succeed);
3557 }
3558
3559 /* Queue an evaluate context command TRB */
3560 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3561                 u32 slot_id)
3562 {
3563         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3564                         upper_32_bits(in_ctx_ptr), 0,
3565                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3566                         false);
3567 }
3568
3569 /*
3570  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3571  * activity on an endpoint that is about to be suspended.
3572  */
3573 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3574                 unsigned int ep_index, int suspend)
3575 {
3576         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3577         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3578         u32 type = TRB_TYPE(TRB_STOP_RING);
3579         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3580
3581         return queue_command(xhci, 0, 0, 0,
3582                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3583 }
3584
3585 /* Set Transfer Ring Dequeue Pointer command.
3586  * This should not be used for endpoints that have streams enabled.
3587  */
3588 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3589                 unsigned int ep_index, unsigned int stream_id,
3590                 struct xhci_segment *deq_seg,
3591                 union xhci_trb *deq_ptr, u32 cycle_state)
3592 {
3593         dma_addr_t addr;
3594         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3595         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3596         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3597         u32 type = TRB_TYPE(TRB_SET_DEQ);
3598         struct xhci_virt_ep *ep;
3599
3600         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3601         if (addr == 0) {
3602                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3603                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3604                                 deq_seg, deq_ptr);
3605                 return 0;
3606         }
3607         ep = &xhci->devs[slot_id]->eps[ep_index];
3608         if ((ep->ep_state & SET_DEQ_PENDING)) {
3609                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3610                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3611                 return 0;
3612         }
3613         ep->queued_deq_seg = deq_seg;
3614         ep->queued_deq_ptr = deq_ptr;
3615         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3616                         upper_32_bits(addr), trb_stream_id,
3617                         trb_slot_id | trb_ep_index | type, false);
3618 }
3619
3620 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3621                 unsigned int ep_index)
3622 {
3623         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3624         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3625         u32 type = TRB_TYPE(TRB_RESET_EP);
3626
3627         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3628                         false);
3629 }