2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
43 #define PCI_VENDOR_ID_ETRON 0x1b6f
44 #define PCI_DEVICE_ID_EJ168 0x7023
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
57 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
59 static const char hcd_name[] = "xhci_hcd";
61 static struct hc_driver __read_mostly xhci_pci_hc_driver;
63 static int xhci_pci_setup(struct usb_hcd *hcd);
65 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
66 .reset = xhci_pci_setup,
69 /* called after powerup, by probe or system-pm "wakeup" */
70 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
73 * TODO: Implement finding debug ports later.
74 * TODO: see if there are any quirks that need to be added to handle
75 * new extended capabilities.
78 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
79 if (!pci_set_mwi(pdev))
80 xhci_dbg(xhci, "MWI active\n");
82 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
86 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
88 struct pci_dev *pdev = to_pci_dev(dev);
90 /* Look for vendor-specific quirks */
91 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
92 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
93 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
94 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
95 pdev->revision == 0x0) {
96 xhci->quirks |= XHCI_RESET_EP_QUIRK;
97 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
98 "QUIRK: Fresco Logic xHC needs configure"
99 " endpoint cmd after reset endpoint");
101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
102 pdev->revision == 0x4) {
103 xhci->quirks |= XHCI_SLOW_SUSPEND;
104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
105 "QUIRK: Fresco Logic xHC revision %u"
106 "must be suspended extra slowly",
109 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
110 xhci->quirks |= XHCI_BROKEN_STREAMS;
111 /* Fresco Logic confirms: all revisions of this chip do not
112 * support MSI, even though some of them claim to in their PCI
115 xhci->quirks |= XHCI_BROKEN_MSI;
116 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
117 "QUIRK: Fresco Logic revision %u "
118 "has broken MSI implementation",
120 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
123 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
124 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
125 xhci->quirks |= XHCI_BROKEN_STREAMS;
127 if (pdev->vendor == PCI_VENDOR_ID_NEC)
128 xhci->quirks |= XHCI_NEC_HOST;
130 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
131 xhci->quirks |= XHCI_AMD_0x96_HOST;
134 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
135 xhci->quirks |= XHCI_AMD_PLL_FIX;
137 if (pdev->vendor == PCI_VENDOR_ID_AMD)
138 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
140 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
141 xhci->quirks |= XHCI_LPM_SUPPORT;
142 xhci->quirks |= XHCI_INTEL_HOST;
143 xhci->quirks |= XHCI_AVOID_BEI;
145 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
146 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
147 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
148 xhci->limit_active_eps = 64;
149 xhci->quirks |= XHCI_SW_BW_CHECKING;
151 * PPT desktop boards DH77EB and DH77DF will power back on after
152 * a few seconds of being shutdown. The fix for this is to
153 * switch the ports from xHCI to EHCI on shutdown. We can't use
154 * DMI information to find those particular boards (since each
155 * vendor will change the board name), so we have to key off all
158 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
160 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
161 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
162 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
163 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
164 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
166 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
167 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
168 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
169 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
170 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
171 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
172 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
173 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
174 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
176 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
177 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
178 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
180 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
181 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
182 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
183 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
184 xhci->quirks |= XHCI_MISSING_CAS;
186 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
187 pdev->device == PCI_DEVICE_ID_EJ168) {
188 xhci->quirks |= XHCI_RESET_ON_RESUME;
189 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
190 xhci->quirks |= XHCI_BROKEN_STREAMS;
192 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
193 pdev->device == 0x0015)
194 xhci->quirks |= XHCI_RESET_ON_RESUME;
195 if (pdev->vendor == PCI_VENDOR_ID_VIA)
196 xhci->quirks |= XHCI_RESET_ON_RESUME;
198 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
199 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
200 pdev->device == 0x3432)
201 xhci->quirks |= XHCI_BROKEN_STREAMS;
203 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
204 pdev->device == 0x1042)
205 xhci->quirks |= XHCI_BROKEN_STREAMS;
206 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
207 pdev->device == 0x1142)
208 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
210 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
211 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
212 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
214 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
215 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
217 if (xhci->quirks & XHCI_RESET_ON_RESUME)
218 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
219 "QUIRK: Resetting on resume");
223 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
225 static const guid_t intel_dsm_guid =
226 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
227 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
228 union acpi_object *obj;
230 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
235 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
236 #endif /* CONFIG_ACPI */
238 /* called during probe() after chip reset completes */
239 static int xhci_pci_setup(struct usb_hcd *hcd)
241 struct xhci_hcd *xhci;
242 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
245 xhci = hcd_to_xhci(hcd);
247 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
249 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
253 if (!usb_hcd_is_primary_hcd(hcd))
256 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
258 /* Find any debug ports */
259 return xhci_pci_reinit(xhci, pdev);
263 * We need to register our own PCI probe function (instead of the USB core's
264 * function) in order to create a second roothub under xHCI.
266 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
269 struct xhci_hcd *xhci;
270 struct hc_driver *driver;
273 driver = (struct hc_driver *)id->driver_data;
275 /* For some HW implementation, a XHCI reset is just not enough... */
276 if (usb_xhci_needs_pci_reset(dev)) {
277 dev_info(&dev->dev, "Resetting\n");
278 if (pci_reset_function_locked(dev))
279 dev_warn(&dev->dev, "Reset failed");
282 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
283 pm_runtime_get_noresume(&dev->dev);
285 /* Register the USB 2.0 roothub.
286 * FIXME: USB core must know to register the USB 2.0 roothub first.
287 * This is sort of silly, because we could just set the HCD driver flags
288 * to say USB 2.0, but I'm not sure what the implications would be in
289 * the other parts of the HCD code.
291 retval = usb_hcd_pci_probe(dev, id);
296 /* USB 2.0 roothub is stored in the PCI device now. */
297 hcd = dev_get_drvdata(&dev->dev);
298 xhci = hcd_to_xhci(hcd);
299 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
301 if (!xhci->shared_hcd) {
303 goto dealloc_usb2_hcd;
306 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
310 /* Roothub already marked as USB 3.0 speed */
312 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
313 HCC_MAX_PSA(xhci->hcc_params) >= 4)
314 xhci->shared_hcd->can_do_streams = 1;
316 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
317 xhci_pme_acpi_rtd3_enable(dev);
319 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
320 pm_runtime_put_noidle(&dev->dev);
325 usb_put_hcd(xhci->shared_hcd);
327 usb_hcd_pci_remove(dev);
329 pm_runtime_put_noidle(&dev->dev);
333 static void xhci_pci_remove(struct pci_dev *dev)
335 struct xhci_hcd *xhci;
337 xhci = hcd_to_xhci(pci_get_drvdata(dev));
338 xhci->xhc_state |= XHCI_STATE_REMOVING;
339 if (xhci->shared_hcd) {
340 usb_remove_hcd(xhci->shared_hcd);
341 usb_put_hcd(xhci->shared_hcd);
344 /* Workaround for spurious wakeups at shutdown with HSW */
345 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
346 pci_set_power_state(dev, PCI_D3hot);
348 usb_hcd_pci_remove(dev);
353 * In some Intel xHCI controllers, in order to get D3 working,
354 * through a vendor specific SSIC CONFIG register at offset 0x883c,
355 * SSIC PORT need to be marked as "unused" before putting xHCI
356 * into D3. After D3 exit, the SSIC port need to be marked as "used".
357 * Without this change, xHCI might not enter D3 state.
359 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
361 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
366 for (i = 0; i < SSIC_PORT_NUM; i++) {
367 reg = (void __iomem *) xhci->cap_regs +
369 i * SSIC_PORT_CFG2_OFFSET;
371 /* Notify SSIC that SSIC profile programming is not done. */
372 val = readl(reg) & ~PROG_DONE;
375 /* Mark SSIC port as unused(suspend) or used(resume) */
378 val |= SSIC_PORT_UNUSED;
380 val &= ~SSIC_PORT_UNUSED;
383 /* Notify SSIC that SSIC profile programming is done */
384 val = readl(reg) | PROG_DONE;
391 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
392 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
394 static void xhci_pme_quirk(struct usb_hcd *hcd)
396 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
400 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
402 writel(val | BIT(28), reg);
406 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
408 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
409 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
413 * Systems with the TI redriver that loses port status change events
414 * need to have the registers polled during D3, so avoid D3cold.
416 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
417 pci_d3cold_disable(pdev);
419 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
422 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
423 xhci_ssic_port_unused_quirk(hcd, true);
425 ret = xhci_suspend(xhci, do_wakeup);
426 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
427 xhci_ssic_port_unused_quirk(hcd, false);
432 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
434 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
435 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
438 /* The BIOS on systems with the Intel Panther Point chipset may or may
439 * not support xHCI natively. That means that during system resume, it
440 * may switch the ports back to EHCI so that users can use their
441 * keyboard to select a kernel from GRUB after resume from hibernate.
443 * The BIOS is supposed to remember whether the OS had xHCI ports
444 * enabled before resume, and switch the ports back to xHCI when the
445 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
448 * Unconditionally switch the ports back to xHCI after a system resume.
449 * It should not matter whether the EHCI or xHCI controller is
450 * resumed first. It's enough to do the switchover in xHCI because
451 * USB core won't notice anything as the hub driver doesn't start
452 * running again until after all the devices (including both EHCI and
453 * xHCI host controllers) have been resumed.
456 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
457 usb_enable_intel_xhci_ports(pdev);
459 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
460 xhci_ssic_port_unused_quirk(hcd, false);
462 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
465 retval = xhci_resume(xhci, hibernated);
468 #endif /* CONFIG_PM */
470 /*-------------------------------------------------------------------------*/
472 /* PCI driver selection metadata; PCI hotplugging uses this */
473 static const struct pci_device_id pci_ids[] = { {
474 /* handle any USB 3.0 xHCI controller */
475 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
476 .driver_data = (unsigned long) &xhci_pci_hc_driver,
478 { /* end: all zeroes */ }
480 MODULE_DEVICE_TABLE(pci, pci_ids);
482 /* pci driver glue; this is a "new style" PCI driver module */
483 static struct pci_driver xhci_pci_driver = {
484 .name = (char *) hcd_name,
487 .probe = xhci_pci_probe,
488 .remove = xhci_pci_remove,
489 /* suspend and resume implemented later */
491 .shutdown = usb_hcd_pci_shutdown,
494 .pm = &usb_hcd_pci_pm_ops
499 static int __init xhci_pci_init(void)
501 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
503 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
504 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
506 return pci_register_driver(&xhci_pci_driver);
508 module_init(xhci_pci_init);
510 static void __exit xhci_pci_exit(void)
512 pci_unregister_driver(&xhci_pci_driver);
514 module_exit(xhci_pci_exit);
516 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
517 MODULE_LICENSE("GPL");