1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver PCI Bus Glue.
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
17 #include "xhci-trace.h"
19 #define SSIC_PORT_NUM 2
20 #define SSIC_PORT_CFG2 0x880c
21 #define SSIC_PORT_CFG2_OFFSET 0x30
22 #define PROG_DONE (1 << 30)
23 #define SSIC_PORT_UNUSED (1 << 31)
25 /* Device for a quirk */
26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
31 #define PCI_VENDOR_ID_ETRON 0x1b6f
32 #define PCI_DEVICE_ID_EJ168 0x7023
34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
45 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
49 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
51 static const char hcd_name[] = "xhci_hcd";
53 static struct hc_driver __read_mostly xhci_pci_hc_driver;
55 static int xhci_pci_setup(struct usb_hcd *hcd);
57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
58 .reset = xhci_pci_setup,
61 /* called after powerup, by probe or system-pm "wakeup" */
62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
65 * TODO: Implement finding debug ports later.
66 * TODO: see if there are any quirks that need to be added to handle
67 * new extended capabilities.
70 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
71 if (!pci_set_mwi(pdev))
72 xhci_dbg(xhci, "MWI active\n");
74 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
80 struct pci_dev *pdev = to_pci_dev(dev);
82 /* Look for vendor-specific quirks */
83 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
84 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
85 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
86 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
87 pdev->revision == 0x0) {
88 xhci->quirks |= XHCI_RESET_EP_QUIRK;
89 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
90 "QUIRK: Fresco Logic xHC needs configure"
91 " endpoint cmd after reset endpoint");
93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
94 pdev->revision == 0x4) {
95 xhci->quirks |= XHCI_SLOW_SUSPEND;
96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
97 "QUIRK: Fresco Logic xHC revision %u"
98 "must be suspended extra slowly",
101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
102 xhci->quirks |= XHCI_BROKEN_STREAMS;
103 /* Fresco Logic confirms: all revisions of this chip do not
104 * support MSI, even though some of them claim to in their PCI
107 xhci->quirks |= XHCI_BROKEN_MSI;
108 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
109 "QUIRK: Fresco Logic revision %u "
110 "has broken MSI implementation",
112 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
115 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
116 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
117 xhci->quirks |= XHCI_BROKEN_STREAMS;
119 if (pdev->vendor == PCI_VENDOR_ID_NEC)
120 xhci->quirks |= XHCI_NEC_HOST;
122 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
123 xhci->quirks |= XHCI_AMD_0x96_HOST;
126 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
127 xhci->quirks |= XHCI_AMD_PLL_FIX;
129 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43bb)
130 xhci->quirks |= XHCI_SUSPEND_DELAY;
132 if (pdev->vendor == PCI_VENDOR_ID_AMD)
133 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
135 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
136 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
137 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
138 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
139 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
140 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
142 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
143 xhci->quirks |= XHCI_LPM_SUPPORT;
144 xhci->quirks |= XHCI_INTEL_HOST;
145 xhci->quirks |= XHCI_AVOID_BEI;
147 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
148 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
149 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
150 xhci->limit_active_eps = 64;
151 xhci->quirks |= XHCI_SW_BW_CHECKING;
153 * PPT desktop boards DH77EB and DH77DF will power back on after
154 * a few seconds of being shutdown. The fix for this is to
155 * switch the ports from xHCI to EHCI on shutdown. We can't use
156 * DMI information to find those particular boards (since each
157 * vendor will change the board name), so we have to key off all
160 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
162 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
163 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
164 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
165 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
166 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
168 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
169 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
170 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
171 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
172 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
173 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
174 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
175 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
176 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
178 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
179 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
180 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
182 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
183 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
184 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
185 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
186 xhci->quirks |= XHCI_MISSING_CAS;
188 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
189 pdev->device == PCI_DEVICE_ID_EJ168) {
190 xhci->quirks |= XHCI_RESET_ON_RESUME;
191 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
192 xhci->quirks |= XHCI_BROKEN_STREAMS;
194 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
195 pdev->device == 0x0014)
196 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
197 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
198 pdev->device == 0x0015)
199 xhci->quirks |= XHCI_RESET_ON_RESUME;
200 if (pdev->vendor == PCI_VENDOR_ID_VIA)
201 xhci->quirks |= XHCI_RESET_ON_RESUME;
203 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
204 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
205 pdev->device == 0x3432)
206 xhci->quirks |= XHCI_BROKEN_STREAMS;
208 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
209 pdev->device == 0x1042)
210 xhci->quirks |= XHCI_BROKEN_STREAMS;
211 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
212 pdev->device == 0x1142)
213 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
215 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
216 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
217 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
219 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
220 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
222 if (xhci->quirks & XHCI_RESET_ON_RESUME)
223 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
224 "QUIRK: Resetting on resume");
228 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
230 static const guid_t intel_dsm_guid =
231 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
232 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
233 union acpi_object *obj;
235 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
240 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
241 #endif /* CONFIG_ACPI */
243 /* called during probe() after chip reset completes */
244 static int xhci_pci_setup(struct usb_hcd *hcd)
246 struct xhci_hcd *xhci;
247 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
250 xhci = hcd_to_xhci(hcd);
252 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
254 /* imod_interval is the interrupt moderation value in nanoseconds. */
255 xhci->imod_interval = 40000;
257 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
261 if (!usb_hcd_is_primary_hcd(hcd))
264 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
266 /* Find any debug ports */
267 return xhci_pci_reinit(xhci, pdev);
271 * We need to register our own PCI probe function (instead of the USB core's
272 * function) in order to create a second roothub under xHCI.
274 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
277 struct xhci_hcd *xhci;
278 struct hc_driver *driver;
281 driver = (struct hc_driver *)id->driver_data;
283 /* For some HW implementation, a XHCI reset is just not enough... */
284 if (usb_xhci_needs_pci_reset(dev)) {
285 dev_info(&dev->dev, "Resetting\n");
286 if (pci_reset_function_locked(dev))
287 dev_warn(&dev->dev, "Reset failed");
290 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
291 pm_runtime_get_noresume(&dev->dev);
293 /* Register the USB 2.0 roothub.
294 * FIXME: USB core must know to register the USB 2.0 roothub first.
295 * This is sort of silly, because we could just set the HCD driver flags
296 * to say USB 2.0, but I'm not sure what the implications would be in
297 * the other parts of the HCD code.
299 retval = usb_hcd_pci_probe(dev, id);
304 /* USB 2.0 roothub is stored in the PCI device now. */
305 hcd = dev_get_drvdata(&dev->dev);
306 xhci = hcd_to_xhci(hcd);
307 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
309 if (!xhci->shared_hcd) {
311 goto dealloc_usb2_hcd;
314 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
318 /* Roothub already marked as USB 3.0 speed */
320 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
321 HCC_MAX_PSA(xhci->hcc_params) >= 4)
322 xhci->shared_hcd->can_do_streams = 1;
324 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
325 xhci_pme_acpi_rtd3_enable(dev);
327 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
328 pm_runtime_put_noidle(&dev->dev);
333 usb_put_hcd(xhci->shared_hcd);
335 usb_hcd_pci_remove(dev);
337 pm_runtime_put_noidle(&dev->dev);
341 static void xhci_pci_remove(struct pci_dev *dev)
343 struct xhci_hcd *xhci;
345 xhci = hcd_to_xhci(pci_get_drvdata(dev));
346 xhci->xhc_state |= XHCI_STATE_REMOVING;
347 if (xhci->shared_hcd) {
348 usb_remove_hcd(xhci->shared_hcd);
349 usb_put_hcd(xhci->shared_hcd);
352 /* Workaround for spurious wakeups at shutdown with HSW */
353 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
354 pci_set_power_state(dev, PCI_D3hot);
356 usb_hcd_pci_remove(dev);
361 * In some Intel xHCI controllers, in order to get D3 working,
362 * through a vendor specific SSIC CONFIG register at offset 0x883c,
363 * SSIC PORT need to be marked as "unused" before putting xHCI
364 * into D3. After D3 exit, the SSIC port need to be marked as "used".
365 * Without this change, xHCI might not enter D3 state.
367 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
369 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
374 for (i = 0; i < SSIC_PORT_NUM; i++) {
375 reg = (void __iomem *) xhci->cap_regs +
377 i * SSIC_PORT_CFG2_OFFSET;
379 /* Notify SSIC that SSIC profile programming is not done. */
380 val = readl(reg) & ~PROG_DONE;
383 /* Mark SSIC port as unused(suspend) or used(resume) */
386 val |= SSIC_PORT_UNUSED;
388 val &= ~SSIC_PORT_UNUSED;
391 /* Notify SSIC that SSIC profile programming is done */
392 val = readl(reg) | PROG_DONE;
399 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
400 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
402 static void xhci_pme_quirk(struct usb_hcd *hcd)
404 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
408 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
410 writel(val | BIT(28), reg);
414 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
416 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
417 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
421 * Systems with the TI redriver that loses port status change events
422 * need to have the registers polled during D3, so avoid D3cold.
424 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
425 pci_d3cold_disable(pdev);
427 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
430 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
431 xhci_ssic_port_unused_quirk(hcd, true);
433 ret = xhci_suspend(xhci, do_wakeup);
434 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
435 xhci_ssic_port_unused_quirk(hcd, false);
440 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
442 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
443 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
446 /* The BIOS on systems with the Intel Panther Point chipset may or may
447 * not support xHCI natively. That means that during system resume, it
448 * may switch the ports back to EHCI so that users can use their
449 * keyboard to select a kernel from GRUB after resume from hibernate.
451 * The BIOS is supposed to remember whether the OS had xHCI ports
452 * enabled before resume, and switch the ports back to xHCI when the
453 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
456 * Unconditionally switch the ports back to xHCI after a system resume.
457 * It should not matter whether the EHCI or xHCI controller is
458 * resumed first. It's enough to do the switchover in xHCI because
459 * USB core won't notice anything as the hub driver doesn't start
460 * running again until after all the devices (including both EHCI and
461 * xHCI host controllers) have been resumed.
464 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
465 usb_enable_intel_xhci_ports(pdev);
467 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
468 xhci_ssic_port_unused_quirk(hcd, false);
470 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
473 retval = xhci_resume(xhci, hibernated);
476 #endif /* CONFIG_PM */
478 /*-------------------------------------------------------------------------*/
480 /* PCI driver selection metadata; PCI hotplugging uses this */
481 static const struct pci_device_id pci_ids[] = { {
482 /* handle any USB 3.0 xHCI controller */
483 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
484 .driver_data = (unsigned long) &xhci_pci_hc_driver,
486 { /* end: all zeroes */ }
488 MODULE_DEVICE_TABLE(pci, pci_ids);
490 /* pci driver glue; this is a "new style" PCI driver module */
491 static struct pci_driver xhci_pci_driver = {
492 .name = (char *) hcd_name,
495 .probe = xhci_pci_probe,
496 .remove = xhci_pci_remove,
497 /* suspend and resume implemented later */
499 .shutdown = usb_hcd_pci_shutdown,
502 .pm = &usb_hcd_pci_pm_ops
507 static int __init xhci_pci_init(void)
509 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
511 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
512 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
514 return pci_register_driver(&xhci_pci_driver);
516 module_init(xhci_pci_init);
518 static void __exit xhci_pci_exit(void)
520 pci_unregister_driver(&xhci_pci_driver);
522 module_exit(xhci_pci_exit);
524 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
525 MODULE_LICENSE("GPL");