drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  34
  35 #define PCI_VENDOR_ID_ETRON             0x1b6f
  36 #define PCI_DEVICE_ID_EJ168             0x7023
  37
  38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  40 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  41 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  44 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  46 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  47 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  53 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  56 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  57 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  58 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  60
  61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  65 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  66 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  67 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  68 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  69
  70 static const char hcd_name[] = "xhci_hcd";
  71
  72 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  73
  74 static int xhci_pci_setup(struct usb_hcd *hcd);
  75
  76 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  77         .reset = xhci_pci_setup,
  78 };
  79
  80 /* called after powerup, by probe or system-pm "wakeup" */
  81 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  82 {
  83         /*
  84          * TODO: Implement finding debug ports later.
  85          * TODO: see if there are any quirks that need to be added to handle
  86          * new extended capabilities.
  87          */
  88
  89         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  90         if (!pci_set_mwi(pdev))
  91                 xhci_dbg(xhci, "MWI active\n");
  92
  93         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  94         return 0;
  95 }
  96
  97 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  98 {
  99         struct pci_dev                  *pdev = to_pci_dev(dev);
 100         struct xhci_driver_data         *driver_data;
 101         const struct pci_device_id      *id;
 102
 103         id = pci_match_id(pdev->driver->id_table, pdev);
 104
 105         if (id && id->driver_data) {
 106                 driver_data = (struct xhci_driver_data *)id->driver_data;
 107                 xhci->quirks |= driver_data->quirks;
 108         }
 109
 110         /* Look for vendor-specific quirks */
 111         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 112                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 113                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 114                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 115                                 pdev->revision == 0x0) {
 116                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 117                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 118                                 "QUIRK: Fresco Logic xHC needs configure"
 119                                 " endpoint cmd after reset endpoint");
 120                 }
 121                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 122                                 pdev->revision == 0x4) {
 123                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 124                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 125                                 "QUIRK: Fresco Logic xHC revision %u"
 126                                 "must be suspended extra slowly",
 127                                 pdev->revision);
 128                 }
 129                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 130                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 131                 /* Fresco Logic confirms: all revisions of this chip do not
 132                  * support MSI, even though some of them claim to in their PCI
 133                  * capabilities.
 134                  */
 135                 xhci->quirks |= XHCI_BROKEN_MSI;
 136                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 137                                 "QUIRK: Fresco Logic revision %u "
 138                                 "has broken MSI implementation",
 139                                 pdev->revision);
 140                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 141         }
 142
 143         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 144                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 145                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 146
 147         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 148                 xhci->quirks |= XHCI_NEC_HOST;
 149
 150         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 151                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 152
 153         /* AMD PLL quirk */
 154         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 155                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 156
 157         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 158                 (pdev->device == 0x145c ||
 159                  pdev->device == 0x15e0 ||
 160                  pdev->device == 0x15e1 ||
 161                  pdev->device == 0x43bb))
 162                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 163
 164         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 165             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 166                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 167
 168         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
 169                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 170
 171         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 172                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 173
 174         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 175                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 176                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 177                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 178                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 179                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 180
 181         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 182                 xhci->quirks |= XHCI_LPM_SUPPORT;
 183                 xhci->quirks |= XHCI_INTEL_HOST;
 184                 xhci->quirks |= XHCI_AVOID_BEI;
 185         }
 186         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 187                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 188                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 189                 xhci->limit_active_eps = 64;
 190                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 191                 /*
 192                  * PPT desktop boards DH77EB and DH77DF will power back on after
 193                  * a few seconds of being shutdown.  The fix for this is to
 194                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 195                  * DMI information to find those particular boards (since each
 196                  * vendor will change the board name), so we have to key off all
 197                  * PPT chipsets.
 198                  */
 199                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 200         }
 201         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 202                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 203                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 204                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 205                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 206         }
 207         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 208                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 209                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 210                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 211                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 212                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 213                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 214                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 215                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 216                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 217         }
 218         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 219             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 220                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 221         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 222             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 223              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 224              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 225                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 226         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 227             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 228              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 229              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 230              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 231              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 232                 xhci->quirks |= XHCI_MISSING_CAS;
 233
 234         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 235             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 236              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 237              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 238              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 239              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 240              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 241              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 242              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 243              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 244              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 245              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
 246                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 247
 248         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 249                         pdev->device == PCI_DEVICE_ID_EJ168) {
 250                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 251                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 252                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 253         }
 254         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 255             pdev->device == 0x0014) {
 256                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 257                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 258         }
 259         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 260             pdev->device == 0x0015) {
 261                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 262                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 263         }
 264         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 265                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 266
 267         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 268         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 269                         pdev->device == 0x3432)
 270                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 271
 272         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
 273                 xhci->quirks |= XHCI_LPM_SUPPORT;
 274
 275         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 276                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 277                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 278         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 279                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 280                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 281         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 282             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 283              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI))
 284                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 285
 286         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 287                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 288                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 289
 290         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 291                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 292
 293         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 294              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 295              pdev->device == 0x9026)
 296                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 297
 298         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 299             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 300              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 301                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 302
 303         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 304                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 305                                 "QUIRK: Resetting on resume");
 306 }
 307
 308 #ifdef CONFIG_ACPI
 309 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 310 {
 311         static const guid_t intel_dsm_guid =
 312                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 313                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 314         union acpi_object *obj;
 315
 316         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 317                                 NULL);
 318         ACPI_FREE(obj);
 319 }
 320 #else
 321 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 322 #endif /* CONFIG_ACPI */
 323
 324 /* called during probe() after chip reset completes */
 325 static int xhci_pci_setup(struct usb_hcd *hcd)
 326 {
 327         struct xhci_hcd         *xhci;
 328         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 329         int                     retval;
 330
 331         xhci = hcd_to_xhci(hcd);
 332         if (!xhci->sbrn)
 333                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 334
 335         /* imod_interval is the interrupt moderation value in nanoseconds. */
 336         xhci->imod_interval = 40000;
 337
 338         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 339         if (retval)
 340                 return retval;
 341
 342         if (!usb_hcd_is_primary_hcd(hcd))
 343                 return 0;
 344
 345         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 346                 xhci_pme_acpi_rtd3_enable(pdev);
 347
 348         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 349
 350         /* Find any debug ports */
 351         return xhci_pci_reinit(xhci, pdev);
 352 }
 353
 354 /*
 355  * We need to register our own PCI probe function (instead of the USB core's
 356  * function) in order to create a second roothub under xHCI.
 357  */
 358 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 359 {
 360         int retval;
 361         struct xhci_hcd *xhci;
 362         struct usb_hcd *hcd;
 363         struct xhci_driver_data *driver_data;
 364         struct reset_control *reset;
 365
 366         driver_data = (struct xhci_driver_data *)id->driver_data;
 367         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 368                 retval = renesas_xhci_check_request_fw(dev, id);
 369                 if (retval)
 370                         return retval;
 371         }
 372
 373         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 374         if (IS_ERR(reset))
 375                 return PTR_ERR(reset);
 376         reset_control_reset(reset);
 377
 378         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 379         pm_runtime_get_noresume(&dev->dev);
 380
 381         /* Register the USB 2.0 roothub.
 382          * FIXME: USB core must know to register the USB 2.0 roothub first.
 383          * This is sort of silly, because we could just set the HCD driver flags
 384          * to say USB 2.0, but I'm not sure what the implications would be in
 385          * the other parts of the HCD code.
 386          */
 387         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 388
 389         if (retval)
 390                 goto put_runtime_pm;
 391
 392         /* USB 2.0 roothub is stored in the PCI device now. */
 393         hcd = dev_get_drvdata(&dev->dev);
 394         xhci = hcd_to_xhci(hcd);
 395         xhci->reset = reset;
 396         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 397                                                  pci_name(dev), hcd);
 398         if (!xhci->shared_hcd) {
 399                 retval = -ENOMEM;
 400                 goto dealloc_usb2_hcd;
 401         }
 402
 403         retval = xhci_ext_cap_init(xhci);
 404         if (retval)
 405                 goto put_usb3_hcd;
 406
 407         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 408                         IRQF_SHARED);
 409         if (retval)
 410                 goto put_usb3_hcd;
 411         /* Roothub already marked as USB 3.0 speed */
 412
 413         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 414                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 415                 xhci->shared_hcd->can_do_streams = 1;
 416
 417         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 418         pm_runtime_put_noidle(&dev->dev);
 419
 420         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 421                 pm_runtime_allow(&dev->dev);
 422
 423         return 0;
 424
 425 put_usb3_hcd:
 426         usb_put_hcd(xhci->shared_hcd);
 427 dealloc_usb2_hcd:
 428         usb_hcd_pci_remove(dev);
 429 put_runtime_pm:
 430         pm_runtime_put_noidle(&dev->dev);
 431         return retval;
 432 }
 433
 434 static void xhci_pci_remove(struct pci_dev *dev)
 435 {
 436         struct xhci_hcd *xhci;
 437
 438         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 439         if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
 440                 renesas_xhci_pci_exit(dev);
 441
 442         xhci->xhc_state |= XHCI_STATE_REMOVING;
 443
 444         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 445                 pm_runtime_forbid(&dev->dev);
 446
 447         if (xhci->shared_hcd) {
 448                 usb_remove_hcd(xhci->shared_hcd);
 449                 usb_put_hcd(xhci->shared_hcd);
 450                 xhci->shared_hcd = NULL;
 451         }
 452
 453         /* Workaround for spurious wakeups at shutdown with HSW */
 454         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 455                 pci_set_power_state(dev, PCI_D3hot);
 456
 457         usb_hcd_pci_remove(dev);
 458 }
 459
 460 #ifdef CONFIG_PM
 461 /*
 462  * In some Intel xHCI controllers, in order to get D3 working,
 463  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 464  * SSIC PORT need to be marked as "unused" before putting xHCI
 465  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 466  * Without this change, xHCI might not enter D3 state.
 467  */
 468 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 469 {
 470         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 471         u32 val;
 472         void __iomem *reg;
 473         int i;
 474
 475         for (i = 0; i < SSIC_PORT_NUM; i++) {
 476                 reg = (void __iomem *) xhci->cap_regs +
 477                                 SSIC_PORT_CFG2 +
 478                                 i * SSIC_PORT_CFG2_OFFSET;
 479
 480                 /* Notify SSIC that SSIC profile programming is not done. */
 481                 val = readl(reg) & ~PROG_DONE;
 482                 writel(val, reg);
 483
 484                 /* Mark SSIC port as unused(suspend) or used(resume) */
 485                 val = readl(reg);
 486                 if (suspend)
 487                         val |= SSIC_PORT_UNUSED;
 488                 else
 489                         val &= ~SSIC_PORT_UNUSED;
 490                 writel(val, reg);
 491
 492                 /* Notify SSIC that SSIC profile programming is done */
 493                 val = readl(reg) | PROG_DONE;
 494                 writel(val, reg);
 495                 readl(reg);
 496         }
 497 }
 498
 499 /*
 500  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 501  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 502  */
 503 static void xhci_pme_quirk(struct usb_hcd *hcd)
 504 {
 505         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 506         void __iomem *reg;
 507         u32 val;
 508
 509         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 510         val = readl(reg);
 511         writel(val | BIT(28), reg);
 512         readl(reg);
 513 }
 514
 515 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 516 {
 517         u32 reg;
 518
 519         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 520         reg &= ~BIT(SPARSE_DISABLE_BIT);
 521         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 522 }
 523
 524 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 525 {
 526         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 527         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 528         int                     ret;
 529
 530         /*
 531          * Systems with the TI redriver that loses port status change events
 532          * need to have the registers polled during D3, so avoid D3cold.
 533          */
 534         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 535                 pci_d3cold_disable(pdev);
 536
 537         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 538                 xhci_pme_quirk(hcd);
 539
 540         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 541                 xhci_ssic_port_unused_quirk(hcd, true);
 542
 543         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 544                 xhci_sparse_control_quirk(hcd);
 545
 546         ret = xhci_suspend(xhci, do_wakeup);
 547         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 548                 xhci_ssic_port_unused_quirk(hcd, false);
 549
 550         return ret;
 551 }
 552
 553 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 554 {
 555         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 556         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 557         int                     retval = 0;
 558
 559         reset_control_reset(xhci->reset);
 560
 561         /* The BIOS on systems with the Intel Panther Point chipset may or may
 562          * not support xHCI natively.  That means that during system resume, it
 563          * may switch the ports back to EHCI so that users can use their
 564          * keyboard to select a kernel from GRUB after resume from hibernate.
 565          *
 566          * The BIOS is supposed to remember whether the OS had xHCI ports
 567          * enabled before resume, and switch the ports back to xHCI when the
 568          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 569          * writers.
 570          *
 571          * Unconditionally switch the ports back to xHCI after a system resume.
 572          * It should not matter whether the EHCI or xHCI controller is
 573          * resumed first. It's enough to do the switchover in xHCI because
 574          * USB core won't notice anything as the hub driver doesn't start
 575          * running again until after all the devices (including both EHCI and
 576          * xHCI host controllers) have been resumed.
 577          */
 578
 579         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 580                 usb_enable_intel_xhci_ports(pdev);
 581
 582         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 583                 xhci_ssic_port_unused_quirk(hcd, false);
 584
 585         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 586                 xhci_pme_quirk(hcd);
 587
 588         retval = xhci_resume(xhci, hibernated);
 589         return retval;
 590 }
 591
 592 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 593 {
 594         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 595         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 596
 597         xhci_shutdown(hcd);
 598
 599         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 600         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 601                 pci_set_power_state(pdev, PCI_D3hot);
 602 }
 603 #endif /* CONFIG_PM */
 604
 605 /*-------------------------------------------------------------------------*/
 606
 607 static const struct xhci_driver_data reneses_data = {
 608         .quirks  = XHCI_RENESAS_FW_QUIRK,
 609         .firmware = "renesas_usb_fw.mem",
 610 };
 611
 612 /* PCI driver selection metadata; PCI hotplugging uses this */
 613 static const struct pci_device_id pci_ids[] = {
 614         { PCI_DEVICE(0x1912, 0x0014),
 615                 .driver_data =  (unsigned long)&reneses_data,
 616         },
 617         { PCI_DEVICE(0x1912, 0x0015),
 618                 .driver_data =  (unsigned long)&reneses_data,
 619         },
 620         /* handle any USB 3.0 xHCI controller */
 621         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 622         },
 623         { /* end: all zeroes */ }
 624 };
 625 MODULE_DEVICE_TABLE(pci, pci_ids);
 626 MODULE_FIRMWARE("renesas_usb_fw.mem");
 627
 628 /* pci driver glue; this is a "new style" PCI driver module */
 629 static struct pci_driver xhci_pci_driver = {
 630         .name =         hcd_name,
 631         .id_table =     pci_ids,
 632
 633         .probe =        xhci_pci_probe,
 634         .remove =       xhci_pci_remove,
 635         /* suspend and resume implemented later */
 636
 637         .shutdown =     usb_hcd_pci_shutdown,
 638 #ifdef CONFIG_PM
 639         .driver = {
 640                 .pm = &usb_hcd_pci_pm_ops
 641         },
 642 #endif
 643 };
 644
 645 static int __init xhci_pci_init(void)
 646 {
 647         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 648 #ifdef CONFIG_PM
 649         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 650         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 651         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 652 #endif
 653         return pci_register_driver(&xhci_pci_driver);
 654 }
 655 module_init(xhci_pci_init);
 656
 657 static void __exit xhci_pci_exit(void)
 658 {
 659         pci_unregister_driver(&xhci_pci_driver);
 660 }
 661 module_exit(xhci_pci_exit);
 662
 663 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 664 MODULE_LICENSE("GPL");