drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         struct xhci_port_cap *port_cap = NULL;
  59         int i, ssa_count;
  60         u32 temp;
  61         u16 desc_size, ssp_cap_size, ssa_size = 0;
  62         bool usb3_1 = false;
  63
  64         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  65         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  66
  67         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  68         for (i = 0; i < xhci->num_port_caps; i++) {
  69                 if (xhci->port_caps[i].maj_rev == 0x03 &&
  70                     xhci->port_caps[i].min_rev >= 0x01) {
  71                         usb3_1 = true;
  72                         port_cap = &xhci->port_caps[i];
  73                         break;
  74                 }
  75         }
  76
  77         if (usb3_1) {
  78                 /* does xhci provide a PSI table for SSA speed attributes? */
  79                 if (port_cap->psi_count) {
  80                         /* two SSA entries for each unique PSI ID, RX and TX */
  81                         ssa_count = port_cap->psi_uid_count * 2;
  82                         ssa_size = ssa_count * sizeof(u32);
  83                         ssp_cap_size -= 16; /* skip copying the default SSA */
  84                 }
  85                 desc_size += ssp_cap_size;
  86         }
  87         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  88
  89         if (usb3_1) {
  90                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  91                 buf[4] += 1;
  92                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  93         }
  94
  95         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  96                 return wLength;
  97
  98         /* Indicate whether the host has LTM support. */
  99         temp = readl(&xhci->cap_regs->hcc_params);
 100         if (HCC_LTC(temp))
 101                 buf[8] |= USB_LTM_SUPPORT;
 102
 103         /* Set the U1 and U2 exit latencies. */
 104         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 105                 temp = readl(&xhci->cap_regs->hcs_params3);
 106                 buf[12] = HCS_U1_LATENCY(temp);
 107                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 108         }
 109
 110         /* If PSI table exists, add the custom speed attributes from it */
 111         if (usb3_1 && port_cap->psi_count) {
 112                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 113                 int offset;
 114
 115                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 116
 117                 if (wLength < desc_size)
 118                         return wLength;
 119                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 120
 121                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 122                 bm_attrib = (ssa_count - 1) & 0x1f;
 123                 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
 124                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 125
 126                 if (wLength < desc_size + ssa_size)
 127                         return wLength;
 128                 /*
 129                  * Create the Sublink Speed Attributes (SSA) array.
 130                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 131                  * but link type bits 7:6 differ for values 01b and 10b.
 132                  * xhci has also only one PSI entry for a symmetric link when
 133                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 134                  */
 135                 offset = desc_size;
 136                 for (i = 0; i < port_cap->psi_count; i++) {
 137                         psi = port_cap->psi[i];
 138                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 139                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 140                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 141
 142                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 143                         for (; psi_exp < 3; psi_exp++)
 144                                 psi_mant /= 1000;
 145                         if (psi_mant >= 10)
 146                                 psi |= BIT(14);
 147
 148                         if ((psi & PLT_MASK) == PLT_SYM) {
 149                         /* Symmetric, create SSA RX and TX from one PSI entry */
 150                                 put_unaligned_le32(psi, &buf[offset]);
 151                                 psi |= 1 << 7;  /* turn entry to TX */
 152                                 offset += 4;
 153                                 if (offset >= desc_size + ssa_size)
 154                                         return desc_size + ssa_size;
 155                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 156                                 /* Asymetric RX, flip bits 7:6 for SSA */
 157                                 psi ^= PLT_MASK;
 158                         }
 159                         put_unaligned_le32(psi, &buf[offset]);
 160                         offset += 4;
 161                         if (offset >= desc_size + ssa_size)
 162                                 return desc_size + ssa_size;
 163                 }
 164         }
 165         /* ssa_size is 0 for other than usb 3.1 hosts */
 166         return desc_size + ssa_size;
 167 }
 168
 169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 170                 struct usb_hub_descriptor *desc, int ports)
 171 {
 172         u16 temp;
 173
 174         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 175         desc->bHubContrCurrent = 0;
 176
 177         desc->bNbrPorts = ports;
 178         temp = 0;
 179         /* Bits 1:0 - support per-port power switching, or power always on */
 180         if (HCC_PPC(xhci->hcc_params))
 181                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 182         else
 183                 temp |= HUB_CHAR_NO_LPSM;
 184         /* Bit  2 - root hubs are not part of a compound device */
 185         /* Bits 4:3 - individual port over current protection */
 186         temp |= HUB_CHAR_INDV_PORT_OCPM;
 187         /* Bits 6:5 - no TTs in root ports */
 188         /* Bit  7 - no port indicators */
 189         desc->wHubCharacteristics = cpu_to_le16(temp);
 190 }
 191
 192 /* Fill in the USB 2.0 roothub descriptor */
 193 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 194                 struct usb_hub_descriptor *desc)
 195 {
 196         int ports;
 197         u16 temp;
 198         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 199         u32 portsc;
 200         unsigned int i;
 201         struct xhci_hub *rhub;
 202
 203         rhub = &xhci->usb2_rhub;
 204         ports = rhub->num_ports;
 205         xhci_common_hub_descriptor(xhci, desc, ports);
 206         desc->bDescriptorType = USB_DT_HUB;
 207         temp = 1 + (ports / 8);
 208         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 209
 210         /* The Device Removable bits are reported on a byte granularity.
 211          * If the port doesn't exist within that byte, the bit is set to 0.
 212          */
 213         memset(port_removable, 0, sizeof(port_removable));
 214         for (i = 0; i < ports; i++) {
 215                 portsc = readl(rhub->ports[i]->addr);
 216                 /* If a device is removable, PORTSC reports a 0, same as in the
 217                  * hub descriptor DeviceRemovable bits.
 218                  */
 219                 if (portsc & PORT_DEV_REMOVE)
 220                         /* This math is hairy because bit 0 of DeviceRemovable
 221                          * is reserved, and bit 1 is for port 1, etc.
 222                          */
 223                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 224         }
 225
 226         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 227          * ports on it.  The USB 2.0 specification says that there are two
 228          * variable length fields at the end of the hub descriptor:
 229          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 230          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 231          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 232          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 233          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 234          * set of ports that actually exist.
 235          */
 236         memset(desc->u.hs.DeviceRemovable, 0xff,
 237                         sizeof(desc->u.hs.DeviceRemovable));
 238         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 239                         sizeof(desc->u.hs.PortPwrCtrlMask));
 240
 241         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 242                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 243                                 sizeof(__u8));
 244 }
 245
 246 /* Fill in the USB 3.0 roothub descriptor */
 247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 248                 struct usb_hub_descriptor *desc)
 249 {
 250         int ports;
 251         u16 port_removable;
 252         u32 portsc;
 253         unsigned int i;
 254         struct xhci_hub *rhub;
 255
 256         rhub = &xhci->usb3_rhub;
 257         ports = rhub->num_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261
 262         /* header decode latency should be zero for roothubs,
 263          * see section 4.23.5.2.
 264          */
 265         desc->u.ss.bHubHdrDecLat = 0;
 266         desc->u.ss.wHubDelay = 0;
 267
 268         port_removable = 0;
 269         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 270         for (i = 0; i < ports; i++) {
 271                 portsc = readl(rhub->ports[i]->addr);
 272                 if (portsc & PORT_DEV_REMOVE)
 273                         port_removable |= 1 << (i + 1);
 274         }
 275
 276         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 277 }
 278
 279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 280                 struct usb_hub_descriptor *desc)
 281 {
 282
 283         if (hcd->speed >= HCD_USB3)
 284                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 285         else
 286                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 287
 288 }
 289
 290 static unsigned int xhci_port_speed(unsigned int port_status)
 291 {
 292         if (DEV_LOWSPEED(port_status))
 293                 return USB_PORT_STAT_LOW_SPEED;
 294         if (DEV_HIGHSPEED(port_status))
 295                 return USB_PORT_STAT_HIGH_SPEED;
 296         /*
 297          * FIXME: Yes, we should check for full speed, but the core uses that as
 298          * a default in portspeed() in usb/core/hub.c (which is the only place
 299          * USB_PORT_STAT_*_SPEED is used).
 300          */
 301         return 0;
 302 }
 303
 304 /*
 305  * These bits are Read Only (RO) and should be saved and written to the
 306  * registers: 0, 3, 10:13, 30
 307  * connect status, over-current status, port speed, and device removable.
 308  * connect status and port speed are also sticky - meaning they're in
 309  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 310  */
 311 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 312 /*
 313  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 314  * bits 5:8, 9, 14:15, 25:27
 315  * link state, port power, port indicator state, "wake on" enable state
 316  */
 317 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 318 /*
 319  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 320  * bit 4 (port reset)
 321  */
 322 #define XHCI_PORT_RW1S  ((1<<4))
 323 /*
 324  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 325  * bits 1, 17, 18, 19, 20, 21, 22, 23
 326  * port enable/disable, and
 327  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 328  * over-current, reset, link state, and L1 change
 329  */
 330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 331 /*
 332  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 333  * latched in
 334  */
 335 #define XHCI_PORT_RW    ((1<<16))
 336 /*
 337  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 338  * bits 2, 24, 28:31
 339  */
 340 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 341
 342 /*
 343  * Given a port state, this function returns a value that would result in the
 344  * port being in the same state, if the value was written to the port status
 345  * control register.
 346  * Save Read Only (RO) bits and save read/write bits where
 347  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 348  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 349  */
 350 u32 xhci_port_state_to_neutral(u32 state)
 351 {
 352         /* Save read-only status and port state */
 353         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 354 }
 355
 356 /*
 357  * find slot id based on port number.
 358  * @port: The one-based port number from one of the two split roothubs.
 359  */
 360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 361                 u16 port)
 362 {
 363         int slot_id;
 364         int i;
 365         enum usb_device_speed speed;
 366
 367         slot_id = 0;
 368         for (i = 0; i < MAX_HC_SLOTS; i++) {
 369                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 370                         continue;
 371                 speed = xhci->devs[i]->udev->speed;
 372                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 373                                 && xhci->devs[i]->fake_port == port) {
 374                         slot_id = i;
 375                         break;
 376                 }
 377         }
 378
 379         return slot_id;
 380 }
 381
 382 /*
 383  * Stop device
 384  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 385  * to complete.
 386  * suspend will set to 1, if suspend bit need to set in command.
 387  */
 388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 389 {
 390         struct xhci_virt_device *virt_dev;
 391         struct xhci_command *cmd;
 392         unsigned long flags;
 393         int ret;
 394         int i;
 395
 396         ret = 0;
 397         virt_dev = xhci->devs[slot_id];
 398         if (!virt_dev)
 399                 return -ENODEV;
 400
 401         trace_xhci_stop_device(virt_dev);
 402
 403         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 404         if (!cmd)
 405                 return -ENOMEM;
 406
 407         spin_lock_irqsave(&xhci->lock, flags);
 408         for (i = LAST_EP_INDEX; i > 0; i--) {
 409                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 410                         struct xhci_ep_ctx *ep_ctx;
 411                         struct xhci_command *command;
 412
 413                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 414
 415                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 416                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 417                                 continue;
 418
 419                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 420                         if (!command) {
 421                                 spin_unlock_irqrestore(&xhci->lock, flags);
 422                                 ret = -ENOMEM;
 423                                 goto cmd_cleanup;
 424                         }
 425
 426                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 427                                                        i, suspend);
 428                         if (ret) {
 429                                 spin_unlock_irqrestore(&xhci->lock, flags);
 430                                 xhci_free_command(xhci, command);
 431                                 goto cmd_cleanup;
 432                         }
 433                 }
 434         }
 435         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 436         if (ret) {
 437                 spin_unlock_irqrestore(&xhci->lock, flags);
 438                 goto cmd_cleanup;
 439         }
 440
 441         xhci_ring_cmd_db(xhci);
 442         spin_unlock_irqrestore(&xhci->lock, flags);
 443
 444         /* Wait for last stop endpoint command to finish */
 445         wait_for_completion(cmd->completion);
 446
 447         if (cmd->status == COMP_COMMAND_ABORTED ||
 448             cmd->status == COMP_COMMAND_RING_STOPPED) {
 449                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 450                 ret = -ETIME;
 451         }
 452
 453 cmd_cleanup:
 454         xhci_free_command(xhci, cmd);
 455         return ret;
 456 }
 457
 458 /*
 459  * Ring device, it rings the all doorbells unconditionally.
 460  */
 461 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 462 {
 463         int i, s;
 464         struct xhci_virt_ep *ep;
 465
 466         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 467                 ep = &xhci->devs[slot_id]->eps[i];
 468
 469                 if (ep->ep_state & EP_HAS_STREAMS) {
 470                         for (s = 1; s < ep->stream_info->num_streams; s++)
 471                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 472                 } else if (ep->ring && ep->ring->dequeue) {
 473                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 474                 }
 475         }
 476
 477         return;
 478 }
 479
 480 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 481                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 482 {
 483         /* Don't allow the USB core to disable SuperSpeed ports. */
 484         if (hcd->speed >= HCD_USB3) {
 485                 xhci_dbg(xhci, "Ignoring request to disable "
 486                                 "SuperSpeed port.\n");
 487                 return;
 488         }
 489
 490         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 491                 xhci_dbg(xhci,
 492                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 493                 return;
 494         }
 495
 496         /* Write 1 to disable the port */
 497         writel(port_status | PORT_PE, addr);
 498         port_status = readl(addr);
 499         xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
 500                  hcd->self.busnum, wIndex + 1, port_status);
 501 }
 502
 503 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 504                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 505 {
 506         char *port_change_bit;
 507         u32 status;
 508
 509         switch (wValue) {
 510         case USB_PORT_FEAT_C_RESET:
 511                 status = PORT_RC;
 512                 port_change_bit = "reset";
 513                 break;
 514         case USB_PORT_FEAT_C_BH_PORT_RESET:
 515                 status = PORT_WRC;
 516                 port_change_bit = "warm(BH) reset";
 517                 break;
 518         case USB_PORT_FEAT_C_CONNECTION:
 519                 status = PORT_CSC;
 520                 port_change_bit = "connect";
 521                 break;
 522         case USB_PORT_FEAT_C_OVER_CURRENT:
 523                 status = PORT_OCC;
 524                 port_change_bit = "over-current";
 525                 break;
 526         case USB_PORT_FEAT_C_ENABLE:
 527                 status = PORT_PEC;
 528                 port_change_bit = "enable/disable";
 529                 break;
 530         case USB_PORT_FEAT_C_SUSPEND:
 531                 status = PORT_PLC;
 532                 port_change_bit = "suspend/resume";
 533                 break;
 534         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 535                 status = PORT_PLC;
 536                 port_change_bit = "link state";
 537                 break;
 538         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 539                 status = PORT_CEC;
 540                 port_change_bit = "config error";
 541                 break;
 542         default:
 543                 /* Should never happen */
 544                 return;
 545         }
 546         /* Change bits are all write 1 to clear */
 547         writel(port_status | status, addr);
 548         port_status = readl(addr);
 549
 550         xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
 551                  wIndex + 1, port_change_bit, port_status);
 552 }
 553
 554 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 555 {
 556         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 557
 558         if (hcd->speed >= HCD_USB3)
 559                 return &xhci->usb3_rhub;
 560         return &xhci->usb2_rhub;
 561 }
 562
 563 /*
 564  * xhci_set_port_power() must be called with xhci->lock held.
 565  * It will release and re-aquire the lock while calling ACPI
 566  * method.
 567  */
 568 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 569                                 u16 index, bool on, unsigned long *flags)
 570         __must_hold(&xhci->lock)
 571 {
 572         struct xhci_hub *rhub;
 573         struct xhci_port *port;
 574         u32 temp;
 575
 576         rhub = xhci_get_rhub(hcd);
 577         port = rhub->ports[index];
 578         temp = readl(port->addr);
 579
 580         xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
 581                  hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
 582
 583         temp = xhci_port_state_to_neutral(temp);
 584
 585         if (on) {
 586                 /* Power on */
 587                 writel(temp | PORT_POWER, port->addr);
 588                 readl(port->addr);
 589         } else {
 590                 /* Power off */
 591                 writel(temp & ~PORT_POWER, port->addr);
 592         }
 593
 594         spin_unlock_irqrestore(&xhci->lock, *flags);
 595         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 596                                         index);
 597         if (temp)
 598                 usb_acpi_set_power_state(hcd->self.root_hub,
 599                         index, on);
 600         spin_lock_irqsave(&xhci->lock, *flags);
 601 }
 602
 603 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 604         u16 test_mode, u16 wIndex)
 605 {
 606         u32 temp;
 607         struct xhci_port *port;
 608
 609         /* xhci only supports test mode for usb2 ports */
 610         port = xhci->usb2_rhub.ports[wIndex];
 611         temp = readl(port->addr + PORTPMSC);
 612         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 613         writel(temp, port->addr + PORTPMSC);
 614         xhci->test_mode = test_mode;
 615         if (test_mode == TEST_FORCE_EN)
 616                 xhci_start(xhci);
 617 }
 618
 619 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 620                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 621         __must_hold(&xhci->lock)
 622 {
 623         int i, retval;
 624
 625         /* Disable all Device Slots */
 626         xhci_dbg(xhci, "Disable all slots\n");
 627         spin_unlock_irqrestore(&xhci->lock, *flags);
 628         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 629                 if (!xhci->devs[i])
 630                         continue;
 631
 632                 retval = xhci_disable_slot(xhci, i);
 633                 if (retval)
 634                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 635                                  i, retval);
 636         }
 637         spin_lock_irqsave(&xhci->lock, *flags);
 638         /* Put all ports to the Disable state by clear PP */
 639         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 640         /* Power off USB3 ports*/
 641         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 642                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 643         /* Power off USB2 ports*/
 644         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 645                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 646         /* Stop the controller */
 647         xhci_dbg(xhci, "Stop controller\n");
 648         retval = xhci_halt(xhci);
 649         if (retval)
 650                 return retval;
 651         /* Disable runtime PM for test mode */
 652         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 653         /* Set PORTPMSC.PTC field to enter selected test mode */
 654         /* Port is selected by wIndex. port_id = wIndex + 1 */
 655         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 656                                         test_mode, wIndex + 1);
 657         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 658         return retval;
 659 }
 660
 661 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 662 {
 663         int retval;
 664
 665         if (!xhci->test_mode) {
 666                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 667                 return 0;
 668         }
 669         if (xhci->test_mode == TEST_FORCE_EN &&
 670                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 671                 retval = xhci_halt(xhci);
 672                 if (retval)
 673                         return retval;
 674         }
 675         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 676         xhci->test_mode = 0;
 677         return xhci_reset(xhci);
 678 }
 679
 680 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 681                          u32 link_state)
 682 {
 683         u32 temp;
 684         u32 portsc;
 685
 686         portsc = readl(port->addr);
 687         temp = xhci_port_state_to_neutral(portsc);
 688         temp &= ~PORT_PLS_MASK;
 689         temp |= PORT_LINK_STROBE | link_state;
 690         writel(temp, port->addr);
 691
 692         xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
 693                  port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
 694                  portsc, temp);
 695 }
 696
 697 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 698                                       struct xhci_port *port, u16 wake_mask)
 699 {
 700         u32 temp;
 701
 702         temp = readl(port->addr);
 703         temp = xhci_port_state_to_neutral(temp);
 704
 705         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 706                 temp |= PORT_WKCONN_E;
 707         else
 708                 temp &= ~PORT_WKCONN_E;
 709
 710         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 711                 temp |= PORT_WKDISC_E;
 712         else
 713                 temp &= ~PORT_WKDISC_E;
 714
 715         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 716                 temp |= PORT_WKOC_E;
 717         else
 718                 temp &= ~PORT_WKOC_E;
 719
 720         writel(temp, port->addr);
 721 }
 722
 723 /* Test and clear port RWC bit */
 724 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 725                              u32 port_bit)
 726 {
 727         u32 temp;
 728
 729         temp = readl(port->addr);
 730         if (temp & port_bit) {
 731                 temp = xhci_port_state_to_neutral(temp);
 732                 temp |= port_bit;
 733                 writel(temp, port->addr);
 734         }
 735 }
 736
 737 /* Updates Link Status for super Speed port */
 738 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 739                 u32 *status, u32 status_reg)
 740 {
 741         u32 pls = status_reg & PORT_PLS_MASK;
 742
 743         /* resume state is a xHCI internal state.
 744          * Do not report it to usb core, instead, pretend to be U3,
 745          * thus usb core knows it's not ready for transfer
 746          */
 747         if (pls == XDEV_RESUME) {
 748                 *status |= USB_SS_PORT_LS_U3;
 749                 return;
 750         }
 751
 752         /* When the CAS bit is set then warm reset
 753          * should be performed on port
 754          */
 755         if (status_reg & PORT_CAS) {
 756                 /* The CAS bit can be set while the port is
 757                  * in any link state.
 758                  * Only roothubs have CAS bit, so we
 759                  * pretend to be in compliance mode
 760                  * unless we're already in compliance
 761                  * or the inactive state.
 762                  */
 763                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 764                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 765                         pls = USB_SS_PORT_LS_COMP_MOD;
 766                 }
 767                 /* Return also connection bit -
 768                  * hub state machine resets port
 769                  * when this bit is set.
 770                  */
 771                 pls |= USB_PORT_STAT_CONNECTION;
 772         } else {
 773                 /*
 774                  * If CAS bit isn't set but the Port is already at
 775                  * Compliance Mode, fake a connection so the USB core
 776                  * notices the Compliance state and resets the port.
 777                  * This resolves an issue generated by the SN65LVPE502CP
 778                  * in which sometimes the port enters compliance mode
 779                  * caused by a delay on the host-device negotiation.
 780                  */
 781                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 782                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 783                         pls |= USB_PORT_STAT_CONNECTION;
 784         }
 785
 786         /* update status field */
 787         *status |= pls;
 788 }
 789
 790 /*
 791  * Function for Compliance Mode Quirk.
 792  *
 793  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 794  * the compliance mode timer is deleted. A port won't enter
 795  * compliance mode if it has previously entered U0.
 796  */
 797 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 798                                     u16 wIndex)
 799 {
 800         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 801         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 802
 803         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 804                 return;
 805
 806         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 807                 xhci->port_status_u0 |= 1 << wIndex;
 808                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 809                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 810                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 811                                 "All USB3 ports have entered U0 already!");
 812                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 813                                 "Compliance Mode Recovery Timer Deleted.");
 814                 }
 815         }
 816 }
 817
 818 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 819                                              u32 *status, u32 portsc,
 820                                              unsigned long *flags)
 821 {
 822         struct xhci_bus_state *bus_state;
 823         struct xhci_hcd *xhci;
 824         struct usb_hcd *hcd;
 825         int slot_id;
 826         u32 wIndex;
 827
 828         hcd = port->rhub->hcd;
 829         bus_state = &port->rhub->bus_state;
 830         xhci = hcd_to_xhci(hcd);
 831         wIndex = port->hcd_portnum;
 832
 833         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
 834                 *status = 0xffffffff;
 835                 return -EINVAL;
 836         }
 837         /* did port event handler already start resume timing? */
 838         if (!bus_state->resume_done[wIndex]) {
 839                 /* If not, maybe we are in a host initated resume? */
 840                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
 841                         /* Host initated resume doesn't time the resume
 842                          * signalling using resume_done[].
 843                          * It manually sets RESUME state, sleeps 20ms
 844                          * and sets U0 state. This should probably be
 845                          * changed, but not right now.
 846                          */
 847                 } else {
 848                         /* port resume was discovered now and here,
 849                          * start resume timing
 850                          */
 851                         unsigned long timeout = jiffies +
 852                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
 853
 854                         set_bit(wIndex, &bus_state->resuming_ports);
 855                         bus_state->resume_done[wIndex] = timeout;
 856                         mod_timer(&hcd->rh_timer, timeout);
 857                         usb_hcd_start_port_resume(&hcd->self, wIndex);
 858                 }
 859         /* Has resume been signalled for USB_RESUME_TIME yet? */
 860         } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
 861                 int time_left;
 862
 863                 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
 864                          hcd->self.busnum, wIndex + 1);
 865
 866                 bus_state->resume_done[wIndex] = 0;
 867                 clear_bit(wIndex, &bus_state->resuming_ports);
 868
 869                 set_bit(wIndex, &bus_state->rexit_ports);
 870
 871                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 872                 xhci_set_link_state(xhci, port, XDEV_U0);
 873
 874                 spin_unlock_irqrestore(&xhci->lock, *flags);
 875                 time_left = wait_for_completion_timeout(
 876                         &bus_state->rexit_done[wIndex],
 877                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
 878                 spin_lock_irqsave(&xhci->lock, *flags);
 879
 880                 if (time_left) {
 881                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 882                                                             wIndex + 1);
 883                         if (!slot_id) {
 884                                 xhci_dbg(xhci, "slot_id is zero\n");
 885                                 *status = 0xffffffff;
 886                                 return -ENODEV;
 887                         }
 888                         xhci_ring_device(xhci, slot_id);
 889                 } else {
 890                         int port_status = readl(port->addr);
 891
 892                         xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
 893                                   hcd->self.busnum, wIndex + 1, port_status);
 894                         *status |= USB_PORT_STAT_SUSPEND;
 895                         clear_bit(wIndex, &bus_state->rexit_ports);
 896                 }
 897
 898                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 899                 bus_state->port_c_suspend |= 1 << wIndex;
 900                 bus_state->suspended_ports &= ~(1 << wIndex);
 901         } else {
 902                 /*
 903                  * The resume has been signaling for less than
 904                  * USB_RESUME_TIME. Report the port status as SUSPEND,
 905                  * let the usbcore check port status again and clear
 906                  * resume signaling later.
 907                  */
 908                 *status |= USB_PORT_STAT_SUSPEND;
 909         }
 910         return 0;
 911 }
 912
 913 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 914 {
 915         u32 ext_stat = 0;
 916         int speed_id;
 917
 918         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 919         speed_id = DEV_PORT_SPEED(raw_port_status);
 920         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 921         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 922
 923         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 924         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 925
 926         return ext_stat;
 927 }
 928
 929 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
 930                                       u32 portsc)
 931 {
 932         struct xhci_bus_state *bus_state;
 933         struct xhci_hcd *xhci;
 934         struct usb_hcd *hcd;
 935         u32 link_state;
 936         u32 portnum;
 937
 938         bus_state = &port->rhub->bus_state;
 939         xhci = hcd_to_xhci(port->rhub->hcd);
 940         hcd = port->rhub->hcd;
 941         link_state = portsc & PORT_PLS_MASK;
 942         portnum = port->hcd_portnum;
 943
 944         /* USB3 specific wPortChange bits
 945          *
 946          * Port link change with port in resume state should not be
 947          * reported to usbcore, as this is an internal state to be
 948          * handled by xhci driver. Reporting PLC to usbcore may
 949          * cause usbcore clearing PLC first and port change event
 950          * irq won't be generated.
 951          */
 952
 953         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
 954                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
 955         if (portsc & PORT_WRC)
 956                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
 957         if (portsc & PORT_CEC)
 958                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 959
 960         /* USB3 specific wPortStatus bits */
 961         if (portsc & PORT_POWER) {
 962                 *status |= USB_SS_PORT_STAT_POWER;
 963                 /* link state handling */
 964                 if (link_state == XDEV_U0)
 965                         bus_state->suspended_ports &= ~(1 << portnum);
 966         }
 967
 968         /* remote wake resume signaling complete */
 969         if (bus_state->port_remote_wakeup & (1 << portnum) &&
 970             link_state != XDEV_RESUME &&
 971             link_state != XDEV_RECOVERY) {
 972                 bus_state->port_remote_wakeup &= ~(1 << portnum);
 973                 usb_hcd_end_port_resume(&hcd->self, portnum);
 974         }
 975
 976         xhci_hub_report_usb3_link_state(xhci, status, portsc);
 977         xhci_del_comp_mod_timer(xhci, portsc, portnum);
 978 }
 979
 980 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
 981                                       u32 portsc, unsigned long *flags)
 982 {
 983         struct xhci_bus_state *bus_state;
 984         u32 link_state;
 985         u32 portnum;
 986         int ret;
 987
 988         bus_state = &port->rhub->bus_state;
 989         link_state = portsc & PORT_PLS_MASK;
 990         portnum = port->hcd_portnum;
 991
 992         /* USB2 wPortStatus bits */
 993         if (portsc & PORT_POWER) {
 994                 *status |= USB_PORT_STAT_POWER;
 995
 996                 /* link state is only valid if port is powered */
 997                 if (link_state == XDEV_U3)
 998                         *status |= USB_PORT_STAT_SUSPEND;
 999                 if (link_state == XDEV_U2)
1000                         *status |= USB_PORT_STAT_L1;
1001                 if (link_state == XDEV_U0) {
1002                         bus_state->resume_done[portnum] = 0;
1003                         clear_bit(portnum, &bus_state->resuming_ports);
1004                         if (bus_state->suspended_ports & (1 << portnum)) {
1005                                 bus_state->suspended_ports &= ~(1 << portnum);
1006                                 bus_state->port_c_suspend |= 1 << portnum;
1007                         }
1008                 }
1009                 if (link_state == XDEV_RESUME) {
1010                         ret = xhci_handle_usb2_port_link_resume(port, status,
1011                                                                 portsc, flags);
1012                         if (ret)
1013                                 return;
1014                 }
1015         }
1016 }
1017
1018 /*
1019  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1020  * 3.0 hubs use.
1021  *
1022  * Possible side effects:
1023  *  - Mark a port as being done with device resume,
1024  *    and ring the endpoint doorbells.
1025  *  - Stop the Synopsys redriver Compliance Mode polling.
1026  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1027  */
1028 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1029                 struct xhci_bus_state *bus_state,
1030         u16 wIndex, u32 raw_port_status,
1031                 unsigned long *flags)
1032         __releases(&xhci->lock)
1033         __acquires(&xhci->lock)
1034 {
1035         u32 status = 0;
1036         struct xhci_hub *rhub;
1037         struct xhci_port *port;
1038
1039         rhub = xhci_get_rhub(hcd);
1040         port = rhub->ports[wIndex];
1041
1042         /* common wPortChange bits */
1043         if (raw_port_status & PORT_CSC)
1044                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1045         if (raw_port_status & PORT_PEC)
1046                 status |= USB_PORT_STAT_C_ENABLE << 16;
1047         if ((raw_port_status & PORT_OCC))
1048                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1049         if ((raw_port_status & PORT_RC))
1050                 status |= USB_PORT_STAT_C_RESET << 16;
1051
1052         /* common wPortStatus bits */
1053         if (raw_port_status & PORT_CONNECT) {
1054                 status |= USB_PORT_STAT_CONNECTION;
1055                 status |= xhci_port_speed(raw_port_status);
1056         }
1057         if (raw_port_status & PORT_PE)
1058                 status |= USB_PORT_STAT_ENABLE;
1059         if (raw_port_status & PORT_OC)
1060                 status |= USB_PORT_STAT_OVERCURRENT;
1061         if (raw_port_status & PORT_RESET)
1062                 status |= USB_PORT_STAT_RESET;
1063
1064         /* USB2 and USB3 specific bits, including Port Link State */
1065         if (hcd->speed >= HCD_USB3)
1066                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1067         else
1068                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1069                                           flags);
1070         /*
1071          * Clear stale usb2 resume signalling variables in case port changed
1072          * state during resume signalling. For example on error
1073          */
1074         if ((bus_state->resume_done[wIndex] ||
1075              test_bit(wIndex, &bus_state->resuming_ports)) &&
1076             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1077             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1078                 bus_state->resume_done[wIndex] = 0;
1079                 clear_bit(wIndex, &bus_state->resuming_ports);
1080                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1081         }
1082
1083         if (bus_state->port_c_suspend & (1 << wIndex))
1084                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1085
1086         return status;
1087 }
1088
1089 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1090                 u16 wIndex, char *buf, u16 wLength)
1091 {
1092         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1093         int max_ports;
1094         unsigned long flags;
1095         u32 temp, status;
1096         int retval = 0;
1097         int slot_id;
1098         struct xhci_bus_state *bus_state;
1099         u16 link_state = 0;
1100         u16 wake_mask = 0;
1101         u16 timeout = 0;
1102         u16 test_mode = 0;
1103         struct xhci_hub *rhub;
1104         struct xhci_port **ports;
1105
1106         rhub = xhci_get_rhub(hcd);
1107         ports = rhub->ports;
1108         max_ports = rhub->num_ports;
1109         bus_state = &rhub->bus_state;
1110
1111         spin_lock_irqsave(&xhci->lock, flags);
1112         switch (typeReq) {
1113         case GetHubStatus:
1114                 /* No power source, over-current reported per port */
1115                 memset(buf, 0, 4);
1116                 break;
1117         case GetHubDescriptor:
1118                 /* Check to make sure userspace is asking for the USB 3.0 hub
1119                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1120                  * endpoint, like external hubs do.
1121                  */
1122                 if (hcd->speed >= HCD_USB3 &&
1123                                 (wLength < USB_DT_SS_HUB_SIZE ||
1124                                  wValue != (USB_DT_SS_HUB << 8))) {
1125                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1126                                         "USB 3.0 roothub.\n");
1127                         goto error;
1128                 }
1129                 xhci_hub_descriptor(hcd, xhci,
1130                                 (struct usb_hub_descriptor *) buf);
1131                 break;
1132         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1133                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1134                         goto error;
1135
1136                 if (hcd->speed < HCD_USB3)
1137                         goto error;
1138
1139                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1140                 spin_unlock_irqrestore(&xhci->lock, flags);
1141                 return retval;
1142         case GetPortStatus:
1143                 if (!wIndex || wIndex > max_ports)
1144                         goto error;
1145                 wIndex--;
1146                 temp = readl(ports[wIndex]->addr);
1147                 if (temp == ~(u32)0) {
1148                         xhci_hc_died(xhci);
1149                         retval = -ENODEV;
1150                         break;
1151                 }
1152                 trace_xhci_get_port_status(wIndex, temp);
1153                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1154                                               &flags);
1155                 if (status == 0xffffffff)
1156                         goto error;
1157
1158                 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1159                          hcd->self.busnum, wIndex + 1, temp, status);
1160
1161                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1162                 /* if USB 3.1 extended port status return additional 4 bytes */
1163                 if (wValue == 0x02) {
1164                         u32 port_li;
1165
1166                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1167                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1168                                 retval = -EINVAL;
1169                                 break;
1170                         }
1171                         port_li = readl(ports[wIndex]->addr + PORTLI);
1172                         status = xhci_get_ext_port_status(temp, port_li);
1173                         put_unaligned_le32(status, &buf[4]);
1174                 }
1175                 break;
1176         case SetPortFeature:
1177                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1178                         link_state = (wIndex & 0xff00) >> 3;
1179                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1180                         wake_mask = wIndex & 0xff00;
1181                 if (wValue == USB_PORT_FEAT_TEST)
1182                         test_mode = (wIndex & 0xff00) >> 8;
1183                 /* The MSB of wIndex is the U1/U2 timeout */
1184                 timeout = (wIndex & 0xff00) >> 8;
1185                 wIndex &= 0xff;
1186                 if (!wIndex || wIndex > max_ports)
1187                         goto error;
1188                 wIndex--;
1189                 temp = readl(ports[wIndex]->addr);
1190                 if (temp == ~(u32)0) {
1191                         xhci_hc_died(xhci);
1192                         retval = -ENODEV;
1193                         break;
1194                 }
1195                 temp = xhci_port_state_to_neutral(temp);
1196                 /* FIXME: What new port features do we need to support? */
1197                 switch (wValue) {
1198                 case USB_PORT_FEAT_SUSPEND:
1199                         temp = readl(ports[wIndex]->addr);
1200                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1201                                 /* Resume the port to U0 first */
1202                                 xhci_set_link_state(xhci, ports[wIndex],
1203                                                         XDEV_U0);
1204                                 spin_unlock_irqrestore(&xhci->lock, flags);
1205                                 msleep(10);
1206                                 spin_lock_irqsave(&xhci->lock, flags);
1207                         }
1208                         /* In spec software should not attempt to suspend
1209                          * a port unless the port reports that it is in the
1210                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1211                          */
1212                         temp = readl(ports[wIndex]->addr);
1213                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1214                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1215                                 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1216                                           hcd->self.busnum, wIndex + 1);
1217                                 goto error;
1218                         }
1219
1220                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1221                                         wIndex + 1);
1222                         if (!slot_id) {
1223                                 xhci_warn(xhci, "slot_id is zero\n");
1224                                 goto error;
1225                         }
1226                         /* unlock to execute stop endpoint commands */
1227                         spin_unlock_irqrestore(&xhci->lock, flags);
1228                         xhci_stop_device(xhci, slot_id, 1);
1229                         spin_lock_irqsave(&xhci->lock, flags);
1230
1231                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1232
1233                         spin_unlock_irqrestore(&xhci->lock, flags);
1234                         msleep(10); /* wait device to enter */
1235                         spin_lock_irqsave(&xhci->lock, flags);
1236
1237                         temp = readl(ports[wIndex]->addr);
1238                         bus_state->suspended_ports |= 1 << wIndex;
1239                         break;
1240                 case USB_PORT_FEAT_LINK_STATE:
1241                         temp = readl(ports[wIndex]->addr);
1242                         /* Disable port */
1243                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1244                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1245                                 temp = xhci_port_state_to_neutral(temp);
1246                                 /*
1247                                  * Clear all change bits, so that we get a new
1248                                  * connection event.
1249                                  */
1250                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1251                                         PORT_OCC | PORT_RC | PORT_PLC |
1252                                         PORT_CEC;
1253                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1254                                 temp = readl(ports[wIndex]->addr);
1255                                 break;
1256                         }
1257
1258                         /* Put link in RxDetect (enable port) */
1259                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1260                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1261                                 xhci_set_link_state(xhci, ports[wIndex],
1262                                                         link_state);
1263                                 temp = readl(ports[wIndex]->addr);
1264                                 break;
1265                         }
1266
1267                         /*
1268                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1269                          * root hub port's transition to compliance mode upon
1270                          * detecting LFPS timeout may be controlled by an
1271                          * Compliance Transition Enabled (CTE) flag (not
1272                          * software visible). This flag is set by writing 0xA
1273                          * to PORTSC PLS field which will allow transition to
1274                          * compliance mode the next time LFPS timeout is
1275                          * encountered. A warm reset will clear it.
1276                          *
1277                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1278                          * flag is set, otherwise, the compliance substate is
1279                          * automatically entered as on 1.0 and prior.
1280                          */
1281                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1282                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1283                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1284                                         break;
1285                                 }
1286
1287                                 if ((temp & PORT_CONNECT)) {
1288                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1289                                         goto error;
1290                                 }
1291
1292                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1293                                                 wIndex);
1294                                 xhci_set_link_state(xhci, ports[wIndex],
1295                                                 link_state);
1296
1297                                 temp = readl(ports[wIndex]->addr);
1298                                 break;
1299                         }
1300                         /* Port must be enabled */
1301                         if (!(temp & PORT_PE)) {
1302                                 retval = -ENODEV;
1303                                 break;
1304                         }
1305                         /* Can't set port link state above '3' (U3) */
1306                         if (link_state > USB_SS_PORT_LS_U3) {
1307                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1308                                          wIndex, link_state);
1309                                 goto error;
1310                         }
1311
1312                         /*
1313                          * set link to U0, steps depend on current link state.
1314                          * U3: set link to U0 and wait for u3exit completion.
1315                          * U1/U2:  no PLC complete event, only set link to U0.
1316                          * Resume/Recovery: device initiated U0, only wait for
1317                          * completion
1318                          */
1319                         if (link_state == USB_SS_PORT_LS_U0) {
1320                                 u32 pls = temp & PORT_PLS_MASK;
1321                                 bool wait_u0 = false;
1322
1323                                 /* already in U0 */
1324                                 if (pls == XDEV_U0)
1325                                         break;
1326                                 if (pls == XDEV_U3 ||
1327                                     pls == XDEV_RESUME ||
1328                                     pls == XDEV_RECOVERY) {
1329                                         wait_u0 = true;
1330                                         reinit_completion(&bus_state->u3exit_done[wIndex]);
1331                                 }
1332                                 if (pls <= XDEV_U3) /* U1, U2, U3 */
1333                                         xhci_set_link_state(xhci, ports[wIndex],
1334                                                             USB_SS_PORT_LS_U0);
1335                                 if (!wait_u0) {
1336                                         if (pls > XDEV_U3)
1337                                                 goto error;
1338                                         break;
1339                                 }
1340                                 spin_unlock_irqrestore(&xhci->lock, flags);
1341                                 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1342                                                                  msecs_to_jiffies(100)))
1343                                         xhci_dbg(xhci, "missing U0 port change event for port %d\n",
1344                                                  wIndex);
1345                                 spin_lock_irqsave(&xhci->lock, flags);
1346                                 temp = readl(ports[wIndex]->addr);
1347                                 break;
1348                         }
1349
1350                         if (link_state == USB_SS_PORT_LS_U3) {
1351                                 int retries = 16;
1352                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1353                                                 wIndex + 1);
1354                                 if (slot_id) {
1355                                         /* unlock to execute stop endpoint
1356                                          * commands */
1357                                         spin_unlock_irqrestore(&xhci->lock,
1358                                                                 flags);
1359                                         xhci_stop_device(xhci, slot_id, 1);
1360                                         spin_lock_irqsave(&xhci->lock, flags);
1361                                 }
1362                                 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1363                                 spin_unlock_irqrestore(&xhci->lock, flags);
1364                                 while (retries--) {
1365                                         usleep_range(4000, 8000);
1366                                         temp = readl(ports[wIndex]->addr);
1367                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1368                                                 break;
1369                                 }
1370                                 spin_lock_irqsave(&xhci->lock, flags);
1371                                 temp = readl(ports[wIndex]->addr);
1372                                 bus_state->suspended_ports |= 1 << wIndex;
1373                         }
1374                         break;
1375                 case USB_PORT_FEAT_POWER:
1376                         /*
1377                          * Turn on ports, even if there isn't per-port switching.
1378                          * HC will report connect events even before this is set.
1379                          * However, hub_wq will ignore the roothub events until
1380                          * the roothub is registered.
1381                          */
1382                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1383                         break;
1384                 case USB_PORT_FEAT_RESET:
1385                         temp = (temp | PORT_RESET);
1386                         writel(temp, ports[wIndex]->addr);
1387
1388                         temp = readl(ports[wIndex]->addr);
1389                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1390                         break;
1391                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1392                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1393                                                   wake_mask);
1394                         temp = readl(ports[wIndex]->addr);
1395                         xhci_dbg(xhci, "set port remote wake mask, "
1396                                         "actual port %d status  = 0x%x\n",
1397                                         wIndex, temp);
1398                         break;
1399                 case USB_PORT_FEAT_BH_PORT_RESET:
1400                         temp |= PORT_WR;
1401                         writel(temp, ports[wIndex]->addr);
1402                         temp = readl(ports[wIndex]->addr);
1403                         break;
1404                 case USB_PORT_FEAT_U1_TIMEOUT:
1405                         if (hcd->speed < HCD_USB3)
1406                                 goto error;
1407                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1408                         temp &= ~PORT_U1_TIMEOUT_MASK;
1409                         temp |= PORT_U1_TIMEOUT(timeout);
1410                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1411                         break;
1412                 case USB_PORT_FEAT_U2_TIMEOUT:
1413                         if (hcd->speed < HCD_USB3)
1414                                 goto error;
1415                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1416                         temp &= ~PORT_U2_TIMEOUT_MASK;
1417                         temp |= PORT_U2_TIMEOUT(timeout);
1418                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1419                         break;
1420                 case USB_PORT_FEAT_TEST:
1421                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1422                         if (hcd->speed != HCD_USB2)
1423                                 goto error;
1424                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1425                                 goto error;
1426                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1427                                                       &flags);
1428                         break;
1429                 default:
1430                         goto error;
1431                 }
1432                 /* unblock any posted writes */
1433                 temp = readl(ports[wIndex]->addr);
1434                 break;
1435         case ClearPortFeature:
1436                 if (!wIndex || wIndex > max_ports)
1437                         goto error;
1438                 wIndex--;
1439                 temp = readl(ports[wIndex]->addr);
1440                 if (temp == ~(u32)0) {
1441                         xhci_hc_died(xhci);
1442                         retval = -ENODEV;
1443                         break;
1444                 }
1445                 /* FIXME: What new port features do we need to support? */
1446                 temp = xhci_port_state_to_neutral(temp);
1447                 switch (wValue) {
1448                 case USB_PORT_FEAT_SUSPEND:
1449                         temp = readl(ports[wIndex]->addr);
1450                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1451                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1452                         if (temp & PORT_RESET)
1453                                 goto error;
1454                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1455                                 if ((temp & PORT_PE) == 0)
1456                                         goto error;
1457
1458                                 set_bit(wIndex, &bus_state->resuming_ports);
1459                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1460                                 xhci_set_link_state(xhci, ports[wIndex],
1461                                                     XDEV_RESUME);
1462                                 spin_unlock_irqrestore(&xhci->lock, flags);
1463                                 msleep(USB_RESUME_TIMEOUT);
1464                                 spin_lock_irqsave(&xhci->lock, flags);
1465                                 xhci_set_link_state(xhci, ports[wIndex],
1466                                                         XDEV_U0);
1467                                 clear_bit(wIndex, &bus_state->resuming_ports);
1468                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1469                         }
1470                         bus_state->port_c_suspend |= 1 << wIndex;
1471
1472                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1473                                         wIndex + 1);
1474                         if (!slot_id) {
1475                                 xhci_dbg(xhci, "slot_id is zero\n");
1476                                 goto error;
1477                         }
1478                         xhci_ring_device(xhci, slot_id);
1479                         break;
1480                 case USB_PORT_FEAT_C_SUSPEND:
1481                         bus_state->port_c_suspend &= ~(1 << wIndex);
1482                         /* fall through */
1483                 case USB_PORT_FEAT_C_RESET:
1484                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1485                 case USB_PORT_FEAT_C_CONNECTION:
1486                 case USB_PORT_FEAT_C_OVER_CURRENT:
1487                 case USB_PORT_FEAT_C_ENABLE:
1488                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1489                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1490                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1491                                         ports[wIndex]->addr, temp);
1492                         break;
1493                 case USB_PORT_FEAT_ENABLE:
1494                         xhci_disable_port(hcd, xhci, wIndex,
1495                                         ports[wIndex]->addr, temp);
1496                         break;
1497                 case USB_PORT_FEAT_POWER:
1498                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1499                         break;
1500                 case USB_PORT_FEAT_TEST:
1501                         retval = xhci_exit_test_mode(xhci);
1502                         break;
1503                 default:
1504                         goto error;
1505                 }
1506                 break;
1507         default:
1508 error:
1509                 /* "stall" on error */
1510                 retval = -EPIPE;
1511         }
1512         spin_unlock_irqrestore(&xhci->lock, flags);
1513         return retval;
1514 }
1515
1516 /*
1517  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1518  * Ports are 0-indexed from the HCD point of view,
1519  * and 1-indexed from the USB core pointer of view.
1520  *
1521  * Note that the status change bits will be cleared as soon as a port status
1522  * change event is generated, so we use the saved status from that event.
1523  */
1524 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1525 {
1526         unsigned long flags;
1527         u32 temp, status;
1528         u32 mask;
1529         int i, retval;
1530         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1531         int max_ports;
1532         struct xhci_bus_state *bus_state;
1533         bool reset_change = false;
1534         struct xhci_hub *rhub;
1535         struct xhci_port **ports;
1536
1537         rhub = xhci_get_rhub(hcd);
1538         ports = rhub->ports;
1539         max_ports = rhub->num_ports;
1540         bus_state = &rhub->bus_state;
1541
1542         /* Initial status is no changes */
1543         retval = (max_ports + 8) / 8;
1544         memset(buf, 0, retval);
1545
1546         /*
1547          * Inform the usbcore about resume-in-progress by returning
1548          * a non-zero value even if there are no status changes.
1549          */
1550         status = bus_state->resuming_ports;
1551
1552         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1553
1554         spin_lock_irqsave(&xhci->lock, flags);
1555         /* For each port, did anything change?  If so, set that bit in buf. */
1556         for (i = 0; i < max_ports; i++) {
1557                 temp = readl(ports[i]->addr);
1558                 if (temp == ~(u32)0) {
1559                         xhci_hc_died(xhci);
1560                         retval = -ENODEV;
1561                         break;
1562                 }
1563                 trace_xhci_hub_status_data(i, temp);
1564
1565                 if ((temp & mask) != 0 ||
1566                         (bus_state->port_c_suspend & 1 << i) ||
1567                         (bus_state->resume_done[i] && time_after_eq(
1568                             jiffies, bus_state->resume_done[i]))) {
1569                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1570                         status = 1;
1571                 }
1572                 if ((temp & PORT_RC))
1573                         reset_change = true;
1574         }
1575         if (!status && !reset_change) {
1576                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1577                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1578         }
1579         spin_unlock_irqrestore(&xhci->lock, flags);
1580         return status ? retval : 0;
1581 }
1582
1583 #ifdef CONFIG_PM
1584
1585 int xhci_bus_suspend(struct usb_hcd *hcd)
1586 {
1587         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1588         int max_ports, port_index;
1589         struct xhci_bus_state *bus_state;
1590         unsigned long flags;
1591         struct xhci_hub *rhub;
1592         struct xhci_port **ports;
1593         u32 portsc_buf[USB_MAXCHILDREN];
1594         bool wake_enabled;
1595
1596         rhub = xhci_get_rhub(hcd);
1597         ports = rhub->ports;
1598         max_ports = rhub->num_ports;
1599         bus_state = &rhub->bus_state;
1600         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1601
1602         spin_lock_irqsave(&xhci->lock, flags);
1603
1604         if (wake_enabled) {
1605                 if (bus_state->resuming_ports ||        /* USB2 */
1606                     bus_state->port_remote_wakeup) {    /* USB3 */
1607                         spin_unlock_irqrestore(&xhci->lock, flags);
1608                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1609                         return -EBUSY;
1610                 }
1611         }
1612         /*
1613          * Prepare ports for suspend, but don't write anything before all ports
1614          * are checked and we know bus suspend can proceed
1615          */
1616         bus_state->bus_suspended = 0;
1617         port_index = max_ports;
1618         while (port_index--) {
1619                 u32 t1, t2;
1620                 int retries = 10;
1621 retry:
1622                 t1 = readl(ports[port_index]->addr);
1623                 t2 = xhci_port_state_to_neutral(t1);
1624                 portsc_buf[port_index] = 0;
1625
1626                 /*
1627                  * Give a USB3 port in link training time to finish, but don't
1628                  * prevent suspend as port might be stuck
1629                  */
1630                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1631                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1632                         spin_unlock_irqrestore(&xhci->lock, flags);
1633                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1634                         spin_lock_irqsave(&xhci->lock, flags);
1635                         xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1636                                  port_index);
1637                         goto retry;
1638                 }
1639                 /* suspend ports in U0, or bail out for new connect changes */
1640                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1641                         if ((t1 & PORT_CSC) && wake_enabled) {
1642                                 bus_state->bus_suspended = 0;
1643                                 spin_unlock_irqrestore(&xhci->lock, flags);
1644                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1645                                 return -EBUSY;
1646                         }
1647                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1648                         t2 &= ~PORT_PLS_MASK;
1649                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1650                         set_bit(port_index, &bus_state->bus_suspended);
1651                 }
1652                 /* USB core sets remote wake mask for USB 3.0 hubs,
1653                  * including the USB 3.0 roothub, but only if CONFIG_PM
1654                  * is enabled, so also enable remote wake here.
1655                  */
1656                 if (wake_enabled) {
1657                         if (t1 & PORT_CONNECT) {
1658                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1659                                 t2 &= ~PORT_WKCONN_E;
1660                         } else {
1661                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1662                                 t2 &= ~PORT_WKDISC_E;
1663                         }
1664
1665                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1666                             (hcd->speed < HCD_USB3)) {
1667                                 if (usb_amd_pt_check_port(hcd->self.controller,
1668                                                           port_index))
1669                                         t2 &= ~PORT_WAKE_BITS;
1670                         }
1671                 } else
1672                         t2 &= ~PORT_WAKE_BITS;
1673
1674                 t1 = xhci_port_state_to_neutral(t1);
1675                 if (t1 != t2)
1676                         portsc_buf[port_index] = t2;
1677         }
1678
1679         /* write port settings, stopping and suspending ports if needed */
1680         port_index = max_ports;
1681         while (port_index--) {
1682                 if (!portsc_buf[port_index])
1683                         continue;
1684                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1685                         int slot_id;
1686
1687                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1688                                                             port_index + 1);
1689                         if (slot_id) {
1690                                 spin_unlock_irqrestore(&xhci->lock, flags);
1691                                 xhci_stop_device(xhci, slot_id, 1);
1692                                 spin_lock_irqsave(&xhci->lock, flags);
1693                         }
1694                 }
1695                 writel(portsc_buf[port_index], ports[port_index]->addr);
1696         }
1697         hcd->state = HC_STATE_SUSPENDED;
1698         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1699         spin_unlock_irqrestore(&xhci->lock, flags);
1700         return 0;
1701 }
1702
1703 /*
1704  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1705  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1706  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1707  */
1708 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1709 {
1710         u32 portsc;
1711
1712         portsc = readl(port->addr);
1713
1714         /* if any of these are set we are not stuck */
1715         if (portsc & (PORT_CONNECT | PORT_CAS))
1716                 return false;
1717
1718         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1719             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1720                 return false;
1721
1722         /* clear wakeup/change bits, and do a warm port reset */
1723         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1724         portsc |= PORT_WR;
1725         writel(portsc, port->addr);
1726         /* flush write */
1727         readl(port->addr);
1728         return true;
1729 }
1730
1731 int xhci_bus_resume(struct usb_hcd *hcd)
1732 {
1733         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1734         struct xhci_bus_state *bus_state;
1735         unsigned long flags;
1736         int max_ports, port_index;
1737         int slot_id;
1738         int sret;
1739         u32 next_state;
1740         u32 temp, portsc;
1741         struct xhci_hub *rhub;
1742         struct xhci_port **ports;
1743
1744         rhub = xhci_get_rhub(hcd);
1745         ports = rhub->ports;
1746         max_ports = rhub->num_ports;
1747         bus_state = &rhub->bus_state;
1748
1749         if (time_before(jiffies, bus_state->next_statechange))
1750                 msleep(5);
1751
1752         spin_lock_irqsave(&xhci->lock, flags);
1753         if (!HCD_HW_ACCESSIBLE(hcd)) {
1754                 spin_unlock_irqrestore(&xhci->lock, flags);
1755                 return -ESHUTDOWN;
1756         }
1757
1758         /* delay the irqs */
1759         temp = readl(&xhci->op_regs->command);
1760         temp &= ~CMD_EIE;
1761         writel(temp, &xhci->op_regs->command);
1762
1763         /* bus specific resume for ports we suspended at bus_suspend */
1764         if (hcd->speed >= HCD_USB3)
1765                 next_state = XDEV_U0;
1766         else
1767                 next_state = XDEV_RESUME;
1768
1769         port_index = max_ports;
1770         while (port_index--) {
1771                 portsc = readl(ports[port_index]->addr);
1772
1773                 /* warm reset CAS limited ports stuck in polling/compliance */
1774                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1775                     (hcd->speed >= HCD_USB3) &&
1776                     xhci_port_missing_cas_quirk(ports[port_index])) {
1777                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1778                         clear_bit(port_index, &bus_state->bus_suspended);
1779                         continue;
1780                 }
1781                 /* resume if we suspended the link, and it is still suspended */
1782                 if (test_bit(port_index, &bus_state->bus_suspended))
1783                         switch (portsc & PORT_PLS_MASK) {
1784                         case XDEV_U3:
1785                                 portsc = xhci_port_state_to_neutral(portsc);
1786                                 portsc &= ~PORT_PLS_MASK;
1787                                 portsc |= PORT_LINK_STROBE | next_state;
1788                                 break;
1789                         case XDEV_RESUME:
1790                                 /* resume already initiated */
1791                                 break;
1792                         default:
1793                                 /* not in a resumeable state, ignore it */
1794                                 clear_bit(port_index,
1795                                           &bus_state->bus_suspended);
1796                                 break;
1797                         }
1798                 /* disable wake for all ports, write new link state if needed */
1799                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1800                 writel(portsc, ports[port_index]->addr);
1801         }
1802
1803         /* USB2 specific resume signaling delay and U0 link state transition */
1804         if (hcd->speed < HCD_USB3) {
1805                 if (bus_state->bus_suspended) {
1806                         spin_unlock_irqrestore(&xhci->lock, flags);
1807                         msleep(USB_RESUME_TIMEOUT);
1808                         spin_lock_irqsave(&xhci->lock, flags);
1809                 }
1810                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1811                                  BITS_PER_LONG) {
1812                         /* Clear PLC to poll it later for U0 transition */
1813                         xhci_test_and_clear_bit(xhci, ports[port_index],
1814                                                 PORT_PLC);
1815                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1816                 }
1817         }
1818
1819         /* poll for U0 link state complete, both USB2 and USB3 */
1820         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1821                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1822                                       PORT_PLC, 10 * 1000);
1823                 if (sret) {
1824                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1825                                   port_index);
1826                         continue;
1827                 }
1828                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1829                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1830                 if (slot_id)
1831                         xhci_ring_device(xhci, slot_id);
1832         }
1833         (void) readl(&xhci->op_regs->command);
1834
1835         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1836         /* re-enable irqs */
1837         temp = readl(&xhci->op_regs->command);
1838         temp |= CMD_EIE;
1839         writel(temp, &xhci->op_regs->command);
1840         temp = readl(&xhci->op_regs->command);
1841
1842         spin_unlock_irqrestore(&xhci->lock, flags);
1843         return 0;
1844 }
1845
1846 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1847 {
1848         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1849
1850         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1851         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1852 }
1853
1854 #endif  /* CONFIG_PM */