drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  * for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software Foundation,
  21  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24
  25 #include <linux/slab.h>
  26 #include <asm/unaligned.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  32 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  33                          PORT_RC | PORT_PLC | PORT_PE)
  34
  35 /* USB 3 BOS descriptor and a capability descriptors, combined.
  36  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  37  */
  38 static u8 usb_bos_descriptor [] = {
  39         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  40         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  41         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  42         0x1,                            /*  __u8 bNumDeviceCaps */
  43         /* First device capability, SuperSpeed */
  44         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  45         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  46         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  47         0x00,                           /* bmAttributes, LTM off by default */
  48         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  49         0x03,                           /* bFunctionalitySupport,
  50                                            USB 3.0 speed only */
  51         0x00,                           /* bU1DevExitLat, set later. */
  52         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  53         /* Second device capability, SuperSpeedPlus */
  54         0x1c,                           /* bLength 28, will be adjusted later */
  55         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  56         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  57         0x00,                           /* bReserved 0 */
  58         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  59         0x01, 0x00,                     /* wFunctionalitySupport */
  60         0x00, 0x00,                     /* wReserved 0 */
  61         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  62         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  63         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  64         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  65         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  66 };
  67
  68 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  69                                      u16 wLength)
  70 {
  71         int i, ssa_count;
  72         u32 temp;
  73         u16 desc_size, ssp_cap_size, ssa_size = 0;
  74         bool usb3_1 = false;
  75
  76         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  77         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  78
  79         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  80         if (xhci->usb3_rhub.min_rev >= 0x01) {
  81                 /* does xhci provide a PSI table for SSA speed attributes? */
  82                 if (xhci->usb3_rhub.psi_count) {
  83                         /* two SSA entries for each unique PSI ID, RX and TX */
  84                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  85                         ssa_size = ssa_count * sizeof(u32);
  86                         ssp_cap_size -= 16; /* skip copying the default SSA */
  87                 }
  88                 desc_size += ssp_cap_size;
  89                 usb3_1 = true;
  90         }
  91         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  92
  93         if (usb3_1) {
  94                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  95                 buf[4] += 1;
  96                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  97         }
  98
  99         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
 100                 return wLength;
 101
 102         /* Indicate whether the host has LTM support. */
 103         temp = readl(&xhci->cap_regs->hcc_params);
 104         if (HCC_LTC(temp))
 105                 buf[8] |= USB_LTM_SUPPORT;
 106
 107         /* Set the U1 and U2 exit latencies. */
 108         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 109                 temp = readl(&xhci->cap_regs->hcs_params3);
 110                 buf[12] = HCS_U1_LATENCY(temp);
 111                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 112         }
 113
 114         /* If PSI table exists, add the custom speed attributes from it */
 115         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 116                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 117                 int offset;
 118
 119                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 120
 121                 if (wLength < desc_size)
 122                         return wLength;
 123                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 124
 125                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 126                 bm_attrib = (ssa_count - 1) & 0x1f;
 127                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 128                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 129
 130                 if (wLength < desc_size + ssa_size)
 131                         return wLength;
 132                 /*
 133                  * Create the Sublink Speed Attributes (SSA) array.
 134                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 135                  * but link type bits 7:6 differ for values 01b and 10b.
 136                  * xhci has also only one PSI entry for a symmetric link when
 137                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 138                  */
 139                 offset = desc_size;
 140                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 141                         psi = xhci->usb3_rhub.psi[i];
 142                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 143                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 144                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 145
 146                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 147                         for (; psi_exp < 3; psi_exp++)
 148                                 psi_mant /= 1000;
 149                         if (psi_mant >= 10)
 150                                 psi |= BIT(14);
 151
 152                         if ((psi & PLT_MASK) == PLT_SYM) {
 153                         /* Symmetric, create SSA RX and TX from one PSI entry */
 154                                 put_unaligned_le32(psi, &buf[offset]);
 155                                 psi |= 1 << 7;  /* turn entry to TX */
 156                                 offset += 4;
 157                                 if (offset >= desc_size + ssa_size)
 158                                         return desc_size + ssa_size;
 159                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 160                                 /* Asymetric RX, flip bits 7:6 for SSA */
 161                                 psi ^= PLT_MASK;
 162                         }
 163                         put_unaligned_le32(psi, &buf[offset]);
 164                         offset += 4;
 165                         if (offset >= desc_size + ssa_size)
 166                                 return desc_size + ssa_size;
 167                 }
 168         }
 169         /* ssa_size is 0 for other than usb 3.1 hosts */
 170         return desc_size + ssa_size;
 171 }
 172
 173 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 174                 struct usb_hub_descriptor *desc, int ports)
 175 {
 176         u16 temp;
 177
 178         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 179         desc->bHubContrCurrent = 0;
 180
 181         desc->bNbrPorts = ports;
 182         temp = 0;
 183         /* Bits 1:0 - support per-port power switching, or power always on */
 184         if (HCC_PPC(xhci->hcc_params))
 185                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 186         else
 187                 temp |= HUB_CHAR_NO_LPSM;
 188         /* Bit  2 - root hubs are not part of a compound device */
 189         /* Bits 4:3 - individual port over current protection */
 190         temp |= HUB_CHAR_INDV_PORT_OCPM;
 191         /* Bits 6:5 - no TTs in root ports */
 192         /* Bit  7 - no port indicators */
 193         desc->wHubCharacteristics = cpu_to_le16(temp);
 194 }
 195
 196 /* Fill in the USB 2.0 roothub descriptor */
 197 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 198                 struct usb_hub_descriptor *desc)
 199 {
 200         int ports;
 201         u16 temp;
 202         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 203         u32 portsc;
 204         unsigned int i;
 205
 206         ports = xhci->num_usb2_ports;
 207
 208         xhci_common_hub_descriptor(xhci, desc, ports);
 209         desc->bDescriptorType = USB_DT_HUB;
 210         temp = 1 + (ports / 8);
 211         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 212
 213         /* The Device Removable bits are reported on a byte granularity.
 214          * If the port doesn't exist within that byte, the bit is set to 0.
 215          */
 216         memset(port_removable, 0, sizeof(port_removable));
 217         for (i = 0; i < ports; i++) {
 218                 portsc = readl(xhci->usb2_ports[i]);
 219                 /* If a device is removable, PORTSC reports a 0, same as in the
 220                  * hub descriptor DeviceRemovable bits.
 221                  */
 222                 if (portsc & PORT_DEV_REMOVE)
 223                         /* This math is hairy because bit 0 of DeviceRemovable
 224                          * is reserved, and bit 1 is for port 1, etc.
 225                          */
 226                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 227         }
 228
 229         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 230          * ports on it.  The USB 2.0 specification says that there are two
 231          * variable length fields at the end of the hub descriptor:
 232          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 233          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 234          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 235          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 236          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 237          * set of ports that actually exist.
 238          */
 239         memset(desc->u.hs.DeviceRemovable, 0xff,
 240                         sizeof(desc->u.hs.DeviceRemovable));
 241         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 242                         sizeof(desc->u.hs.PortPwrCtrlMask));
 243
 244         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 245                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 246                                 sizeof(__u8));
 247 }
 248
 249 /* Fill in the USB 3.0 roothub descriptor */
 250 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 251                 struct usb_hub_descriptor *desc)
 252 {
 253         int ports;
 254         u16 port_removable;
 255         u32 portsc;
 256         unsigned int i;
 257
 258         ports = xhci->num_usb3_ports;
 259         xhci_common_hub_descriptor(xhci, desc, ports);
 260         desc->bDescriptorType = USB_DT_SS_HUB;
 261         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 262
 263         /* header decode latency should be zero for roothubs,
 264          * see section 4.23.5.2.
 265          */
 266         desc->u.ss.bHubHdrDecLat = 0;
 267         desc->u.ss.wHubDelay = 0;
 268
 269         port_removable = 0;
 270         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 271         for (i = 0; i < ports; i++) {
 272                 portsc = readl(xhci->usb3_ports[i]);
 273                 if (portsc & PORT_DEV_REMOVE)
 274                         port_removable |= 1 << (i + 1);
 275         }
 276
 277         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 278 }
 279
 280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 281                 struct usb_hub_descriptor *desc)
 282 {
 283
 284         if (hcd->speed >= HCD_USB3)
 285                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 286         else
 287                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 288
 289 }
 290
 291 static unsigned int xhci_port_speed(unsigned int port_status)
 292 {
 293         if (DEV_LOWSPEED(port_status))
 294                 return USB_PORT_STAT_LOW_SPEED;
 295         if (DEV_HIGHSPEED(port_status))
 296                 return USB_PORT_STAT_HIGH_SPEED;
 297         /*
 298          * FIXME: Yes, we should check for full speed, but the core uses that as
 299          * a default in portspeed() in usb/core/hub.c (which is the only place
 300          * USB_PORT_STAT_*_SPEED is used).
 301          */
 302         return 0;
 303 }
 304
 305 /*
 306  * These bits are Read Only (RO) and should be saved and written to the
 307  * registers: 0, 3, 10:13, 30
 308  * connect status, over-current status, port speed, and device removable.
 309  * connect status and port speed are also sticky - meaning they're in
 310  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 311  */
 312 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 313 /*
 314  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 315  * bits 5:8, 9, 14:15, 25:27
 316  * link state, port power, port indicator state, "wake on" enable state
 317  */
 318 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 319 /*
 320  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 321  * bit 4 (port reset)
 322  */
 323 #define XHCI_PORT_RW1S  ((1<<4))
 324 /*
 325  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 326  * bits 1, 17, 18, 19, 20, 21, 22, 23
 327  * port enable/disable, and
 328  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 329  * over-current, reset, link state, and L1 change
 330  */
 331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 332 /*
 333  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 334  * latched in
 335  */
 336 #define XHCI_PORT_RW    ((1<<16))
 337 /*
 338  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 339  * bits 2, 24, 28:31
 340  */
 341 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 342
 343 /*
 344  * Given a port state, this function returns a value that would result in the
 345  * port being in the same state, if the value was written to the port status
 346  * control register.
 347  * Save Read Only (RO) bits and save read/write bits where
 348  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 349  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 350  */
 351 u32 xhci_port_state_to_neutral(u32 state)
 352 {
 353         /* Save read-only status and port state */
 354         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 355 }
 356
 357 /*
 358  * find slot id based on port number.
 359  * @port: The one-based port number from one of the two split roothubs.
 360  */
 361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 362                 u16 port)
 363 {
 364         int slot_id;
 365         int i;
 366         enum usb_device_speed speed;
 367
 368         slot_id = 0;
 369         for (i = 0; i < MAX_HC_SLOTS; i++) {
 370                 if (!xhci->devs[i])
 371                         continue;
 372                 speed = xhci->devs[i]->udev->speed;
 373                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 374                                 && xhci->devs[i]->fake_port == port) {
 375                         slot_id = i;
 376                         break;
 377                 }
 378         }
 379
 380         return slot_id;
 381 }
 382
 383 /*
 384  * Stop device
 385  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 386  * to complete.
 387  * suspend will set to 1, if suspend bit need to set in command.
 388  */
 389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 390 {
 391         struct xhci_virt_device *virt_dev;
 392         struct xhci_command *cmd;
 393         unsigned long flags;
 394         int ret;
 395         int i;
 396
 397         ret = 0;
 398         virt_dev = xhci->devs[slot_id];
 399         if (!virt_dev)
 400                 return -ENODEV;
 401
 402         trace_xhci_stop_device(virt_dev);
 403
 404         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 405         if (!cmd)
 406                 return -ENOMEM;
 407
 408         spin_lock_irqsave(&xhci->lock, flags);
 409         for (i = LAST_EP_INDEX; i > 0; i--) {
 410                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 411                         struct xhci_ep_ctx *ep_ctx;
 412                         struct xhci_command *command;
 413
 414                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 415
 416                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 417                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 418                                 continue;
 419
 420                         command = xhci_alloc_command(xhci, false, false,
 421                                                      GFP_NOWAIT);
 422                         if (!command) {
 423                                 spin_unlock_irqrestore(&xhci->lock, flags);
 424                                 ret = -ENOMEM;
 425                                 goto cmd_cleanup;
 426                         }
 427
 428                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 429                                                        i, suspend);
 430                         if (ret) {
 431                                 spin_unlock_irqrestore(&xhci->lock, flags);
 432                                 xhci_free_command(xhci, command);
 433                                 goto cmd_cleanup;
 434                         }
 435                 }
 436         }
 437         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 438         if (ret) {
 439                 spin_unlock_irqrestore(&xhci->lock, flags);
 440                 goto cmd_cleanup;
 441         }
 442
 443         xhci_ring_cmd_db(xhci);
 444         spin_unlock_irqrestore(&xhci->lock, flags);
 445
 446         /* Wait for last stop endpoint command to finish */
 447         wait_for_completion(cmd->completion);
 448
 449         if (cmd->status == COMP_COMMAND_ABORTED ||
 450             cmd->status == COMP_COMMAND_RING_STOPPED) {
 451                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 452                 ret = -ETIME;
 453         }
 454
 455 cmd_cleanup:
 456         xhci_free_command(xhci, cmd);
 457         return ret;
 458 }
 459
 460 /*
 461  * Ring device, it rings the all doorbells unconditionally.
 462  */
 463 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 464 {
 465         int i, s;
 466         struct xhci_virt_ep *ep;
 467
 468         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 469                 ep = &xhci->devs[slot_id]->eps[i];
 470
 471                 if (ep->ep_state & EP_HAS_STREAMS) {
 472                         for (s = 1; s < ep->stream_info->num_streams; s++)
 473                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 474                 } else if (ep->ring && ep->ring->dequeue) {
 475                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 476                 }
 477         }
 478
 479         return;
 480 }
 481
 482 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 483                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 484 {
 485         /* Don't allow the USB core to disable SuperSpeed ports. */
 486         if (hcd->speed >= HCD_USB3) {
 487                 xhci_dbg(xhci, "Ignoring request to disable "
 488                                 "SuperSpeed port.\n");
 489                 return;
 490         }
 491
 492         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 493                 xhci_dbg(xhci,
 494                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 495                 return;
 496         }
 497
 498         /* Write 1 to disable the port */
 499         writel(port_status | PORT_PE, addr);
 500         port_status = readl(addr);
 501         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 502                         wIndex, port_status);
 503 }
 504
 505 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 506                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 507 {
 508         char *port_change_bit;
 509         u32 status;
 510
 511         switch (wValue) {
 512         case USB_PORT_FEAT_C_RESET:
 513                 status = PORT_RC;
 514                 port_change_bit = "reset";
 515                 break;
 516         case USB_PORT_FEAT_C_BH_PORT_RESET:
 517                 status = PORT_WRC;
 518                 port_change_bit = "warm(BH) reset";
 519                 break;
 520         case USB_PORT_FEAT_C_CONNECTION:
 521                 status = PORT_CSC;
 522                 port_change_bit = "connect";
 523                 break;
 524         case USB_PORT_FEAT_C_OVER_CURRENT:
 525                 status = PORT_OCC;
 526                 port_change_bit = "over-current";
 527                 break;
 528         case USB_PORT_FEAT_C_ENABLE:
 529                 status = PORT_PEC;
 530                 port_change_bit = "enable/disable";
 531                 break;
 532         case USB_PORT_FEAT_C_SUSPEND:
 533                 status = PORT_PLC;
 534                 port_change_bit = "suspend/resume";
 535                 break;
 536         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 537                 status = PORT_PLC;
 538                 port_change_bit = "link state";
 539                 break;
 540         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 541                 status = PORT_CEC;
 542                 port_change_bit = "config error";
 543                 break;
 544         default:
 545                 /* Should never happen */
 546                 return;
 547         }
 548         /* Change bits are all write 1 to clear */
 549         writel(port_status | status, addr);
 550         port_status = readl(addr);
 551         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 552                         port_change_bit, wIndex, port_status);
 553 }
 554
 555 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 556 {
 557         int max_ports;
 558         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 559
 560         if (hcd->speed >= HCD_USB3) {
 561                 max_ports = xhci->num_usb3_ports;
 562                 *port_array = xhci->usb3_ports;
 563         } else {
 564                 max_ports = xhci->num_usb2_ports;
 565                 *port_array = xhci->usb2_ports;
 566         }
 567
 568         return max_ports;
 569 }
 570
 571 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 572 {
 573         __le32 __iomem **port_array;
 574
 575         xhci_get_ports(hcd, &port_array);
 576         return port_array[index];
 577 }
 578
 579 /*
 580  * xhci_set_port_power() must be called with xhci->lock held.
 581  * It will release and re-aquire the lock while calling ACPI
 582  * method.
 583  */
 584 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 585                                 u16 index, bool on, unsigned long *flags)
 586 {
 587         __le32 __iomem *addr;
 588         u32 temp;
 589
 590         addr = xhci_get_port_io_addr(hcd, index);
 591         temp = readl(addr);
 592         temp = xhci_port_state_to_neutral(temp);
 593         if (on) {
 594                 /* Power on */
 595                 writel(temp | PORT_POWER, addr);
 596                 temp = readl(addr);
 597                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 598                                                 index, temp);
 599         } else {
 600                 /* Power off */
 601                 writel(temp & ~PORT_POWER, addr);
 602         }
 603
 604         spin_unlock_irqrestore(&xhci->lock, *flags);
 605         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 606                                         index);
 607         if (temp)
 608                 usb_acpi_set_power_state(hcd->self.root_hub,
 609                         index, on);
 610         spin_lock_irqsave(&xhci->lock, *flags);
 611 }
 612
 613 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 614         u16 test_mode, u16 wIndex)
 615 {
 616         u32 temp;
 617         __le32 __iomem *addr;
 618
 619         /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 620         addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 621         temp = readl(addr + PORTPMSC);
 622         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 623         writel(temp, addr + PORTPMSC);
 624         xhci->test_mode = test_mode;
 625         if (test_mode == TEST_FORCE_EN)
 626                 xhci_start(xhci);
 627 }
 628
 629 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 630                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 631 {
 632         int i, retval;
 633
 634         /* Disable all Device Slots */
 635         xhci_dbg(xhci, "Disable all slots\n");
 636         spin_unlock_irqrestore(&xhci->lock, *flags);
 637         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 638                 if (!xhci->devs[i])
 639                         continue;
 640
 641                 retval = xhci_disable_slot(xhci, i);
 642                 if (retval)
 643                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 644                                  i, retval);
 645         }
 646         spin_lock_irqsave(&xhci->lock, *flags);
 647         /* Put all ports to the Disable state by clear PP */
 648         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 649         /* Power off USB3 ports*/
 650         for (i = 0; i < xhci->num_usb3_ports; i++)
 651                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 652         /* Power off USB2 ports*/
 653         for (i = 0; i < xhci->num_usb2_ports; i++)
 654                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 655         /* Stop the controller */
 656         xhci_dbg(xhci, "Stop controller\n");
 657         retval = xhci_halt(xhci);
 658         if (retval)
 659                 return retval;
 660         /* Disable runtime PM for test mode */
 661         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 662         /* Set PORTPMSC.PTC field to enter selected test mode */
 663         /* Port is selected by wIndex. port_id = wIndex + 1 */
 664         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 665                                         test_mode, wIndex + 1);
 666         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 667         return retval;
 668 }
 669
 670 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 671 {
 672         int retval;
 673
 674         if (!xhci->test_mode) {
 675                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 676                 return 0;
 677         }
 678         if (xhci->test_mode == TEST_FORCE_EN &&
 679                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 680                 retval = xhci_halt(xhci);
 681                 if (retval)
 682                         return retval;
 683         }
 684         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 685         xhci->test_mode = 0;
 686         return xhci_reset(xhci);
 687 }
 688
 689 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 690                                 int port_id, u32 link_state)
 691 {
 692         u32 temp;
 693
 694         temp = readl(port_array[port_id]);
 695         temp = xhci_port_state_to_neutral(temp);
 696         temp &= ~PORT_PLS_MASK;
 697         temp |= PORT_LINK_STROBE | link_state;
 698         writel(temp, port_array[port_id]);
 699 }
 700
 701 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 702                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 703 {
 704         u32 temp;
 705
 706         temp = readl(port_array[port_id]);
 707         temp = xhci_port_state_to_neutral(temp);
 708
 709         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 710                 temp |= PORT_WKCONN_E;
 711         else
 712                 temp &= ~PORT_WKCONN_E;
 713
 714         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 715                 temp |= PORT_WKDISC_E;
 716         else
 717                 temp &= ~PORT_WKDISC_E;
 718
 719         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 720                 temp |= PORT_WKOC_E;
 721         else
 722                 temp &= ~PORT_WKOC_E;
 723
 724         writel(temp, port_array[port_id]);
 725 }
 726
 727 /* Test and clear port RWC bit */
 728 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 729                                 int port_id, u32 port_bit)
 730 {
 731         u32 temp;
 732
 733         temp = readl(port_array[port_id]);
 734         if (temp & port_bit) {
 735                 temp = xhci_port_state_to_neutral(temp);
 736                 temp |= port_bit;
 737                 writel(temp, port_array[port_id]);
 738         }
 739 }
 740
 741 /* Updates Link Status for USB 2.1 port */
 742 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 743 {
 744         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 745                 *status |= USB_PORT_STAT_L1;
 746 }
 747
 748 /* Updates Link Status for super Speed port */
 749 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 750                 u32 *status, u32 status_reg)
 751 {
 752         u32 pls = status_reg & PORT_PLS_MASK;
 753
 754         /* resume state is a xHCI internal state.
 755          * Do not report it to usb core, instead, pretend to be U3,
 756          * thus usb core knows it's not ready for transfer
 757          */
 758         if (pls == XDEV_RESUME) {
 759                 *status |= USB_SS_PORT_LS_U3;
 760                 return;
 761         }
 762
 763         /* When the CAS bit is set then warm reset
 764          * should be performed on port
 765          */
 766         if (status_reg & PORT_CAS) {
 767                 /* The CAS bit can be set while the port is
 768                  * in any link state.
 769                  * Only roothubs have CAS bit, so we
 770                  * pretend to be in compliance mode
 771                  * unless we're already in compliance
 772                  * or the inactive state.
 773                  */
 774                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 775                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 776                         pls = USB_SS_PORT_LS_COMP_MOD;
 777                 }
 778                 /* Return also connection bit -
 779                  * hub state machine resets port
 780                  * when this bit is set.
 781                  */
 782                 pls |= USB_PORT_STAT_CONNECTION;
 783         } else {
 784                 /*
 785                  * If CAS bit isn't set but the Port is already at
 786                  * Compliance Mode, fake a connection so the USB core
 787                  * notices the Compliance state and resets the port.
 788                  * This resolves an issue generated by the SN65LVPE502CP
 789                  * in which sometimes the port enters compliance mode
 790                  * caused by a delay on the host-device negotiation.
 791                  */
 792                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 793                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 794                         pls |= USB_PORT_STAT_CONNECTION;
 795         }
 796
 797         /* update status field */
 798         *status |= pls;
 799 }
 800
 801 /*
 802  * Function for Compliance Mode Quirk.
 803  *
 804  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 805  * the compliance mode timer is deleted. A port won't enter
 806  * compliance mode if it has previously entered U0.
 807  */
 808 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 809                                     u16 wIndex)
 810 {
 811         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 812         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 813
 814         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 815                 return;
 816
 817         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 818                 xhci->port_status_u0 |= 1 << wIndex;
 819                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 820                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 821                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 822                                 "All USB3 ports have entered U0 already!");
 823                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 824                                 "Compliance Mode Recovery Timer Deleted.");
 825                 }
 826         }
 827 }
 828
 829 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 830 {
 831         u32 ext_stat = 0;
 832         int speed_id;
 833
 834         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 835         speed_id = DEV_PORT_SPEED(raw_port_status);
 836         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 837         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 838
 839         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 840         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 841
 842         return ext_stat;
 843 }
 844
 845 /*
 846  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 847  * 3.0 hubs use.
 848  *
 849  * Possible side effects:
 850  *  - Mark a port as being done with device resume,
 851  *    and ring the endpoint doorbells.
 852  *  - Stop the Synopsys redriver Compliance Mode polling.
 853  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 854  */
 855 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 856                 struct xhci_bus_state *bus_state,
 857                 __le32 __iomem **port_array,
 858                 u16 wIndex, u32 raw_port_status,
 859                 unsigned long flags)
 860         __releases(&xhci->lock)
 861         __acquires(&xhci->lock)
 862 {
 863         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 864         u32 status = 0;
 865         int slot_id;
 866
 867         /* wPortChange bits */
 868         if (raw_port_status & PORT_CSC)
 869                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 870         if (raw_port_status & PORT_PEC)
 871                 status |= USB_PORT_STAT_C_ENABLE << 16;
 872         if ((raw_port_status & PORT_OCC))
 873                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 874         if ((raw_port_status & PORT_RC))
 875                 status |= USB_PORT_STAT_C_RESET << 16;
 876         /* USB3.0 only */
 877         if (hcd->speed >= HCD_USB3) {
 878                 /* Port link change with port in resume state should not be
 879                  * reported to usbcore, as this is an internal state to be
 880                  * handled by xhci driver. Reporting PLC to usbcore may
 881                  * cause usbcore clearing PLC first and port change event
 882                  * irq won't be generated.
 883                  */
 884                 if ((raw_port_status & PORT_PLC) &&
 885                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 886                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 887                 if ((raw_port_status & PORT_WRC))
 888                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 889                 if ((raw_port_status & PORT_CEC))
 890                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 891         }
 892
 893         if (hcd->speed < HCD_USB3) {
 894                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 895                                 && (raw_port_status & PORT_POWER))
 896                         status |= USB_PORT_STAT_SUSPEND;
 897         }
 898         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 899                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 900                 if ((raw_port_status & PORT_RESET) ||
 901                                 !(raw_port_status & PORT_PE))
 902                         return 0xffffffff;
 903                 /* did port event handler already start resume timing? */
 904                 if (!bus_state->resume_done[wIndex]) {
 905                         /* If not, maybe we are in a host initated resume? */
 906                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 907                                 /* Host initated resume doesn't time the resume
 908                                  * signalling using resume_done[].
 909                                  * It manually sets RESUME state, sleeps 20ms
 910                                  * and sets U0 state. This should probably be
 911                                  * changed, but not right now.
 912                                  */
 913                         } else {
 914                                 /* port resume was discovered now and here,
 915                                  * start resume timing
 916                                  */
 917                                 unsigned long timeout = jiffies +
 918                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 919
 920                                 set_bit(wIndex, &bus_state->resuming_ports);
 921                                 bus_state->resume_done[wIndex] = timeout;
 922                                 mod_timer(&hcd->rh_timer, timeout);
 923                         }
 924                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 925                 } else if (time_after_eq(jiffies,
 926                                          bus_state->resume_done[wIndex])) {
 927                         int time_left;
 928
 929                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 930                                         wIndex + 1);
 931                         bus_state->resume_done[wIndex] = 0;
 932                         clear_bit(wIndex, &bus_state->resuming_ports);
 933
 934                         set_bit(wIndex, &bus_state->rexit_ports);
 935
 936                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 937                                                 PORT_PLC);
 938                         xhci_set_link_state(xhci, port_array, wIndex,
 939                                         XDEV_U0);
 940
 941                         spin_unlock_irqrestore(&xhci->lock, flags);
 942                         time_left = wait_for_completion_timeout(
 943                                         &bus_state->rexit_done[wIndex],
 944                                         msecs_to_jiffies(
 945                                                 XHCI_MAX_REXIT_TIMEOUT));
 946                         spin_lock_irqsave(&xhci->lock, flags);
 947
 948                         if (time_left) {
 949                                 slot_id = xhci_find_slot_id_by_port(hcd,
 950                                                 xhci, wIndex + 1);
 951                                 if (!slot_id) {
 952                                         xhci_dbg(xhci, "slot_id is zero\n");
 953                                         return 0xffffffff;
 954                                 }
 955                                 xhci_ring_device(xhci, slot_id);
 956                         } else {
 957                                 int port_status = readl(port_array[wIndex]);
 958                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 959                                                 XHCI_MAX_REXIT_TIMEOUT,
 960                                                 port_status);
 961                                 status |= USB_PORT_STAT_SUSPEND;
 962                                 clear_bit(wIndex, &bus_state->rexit_ports);
 963                         }
 964
 965                         bus_state->port_c_suspend |= 1 << wIndex;
 966                         bus_state->suspended_ports &= ~(1 << wIndex);
 967                 } else {
 968                         /*
 969                          * The resume has been signaling for less than
 970                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 971                          * let the usbcore check port status again and clear
 972                          * resume signaling later.
 973                          */
 974                         status |= USB_PORT_STAT_SUSPEND;
 975                 }
 976         }
 977         /*
 978          * Clear stale usb2 resume signalling variables in case port changed
 979          * state during resume signalling. For example on error
 980          */
 981         if ((bus_state->resume_done[wIndex] ||
 982              test_bit(wIndex, &bus_state->resuming_ports)) &&
 983             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 984             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 985                 bus_state->resume_done[wIndex] = 0;
 986                 clear_bit(wIndex, &bus_state->resuming_ports);
 987         }
 988
 989
 990         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 991             (raw_port_status & PORT_POWER)) {
 992                 if (bus_state->suspended_ports & (1 << wIndex)) {
 993                         bus_state->suspended_ports &= ~(1 << wIndex);
 994                         if (hcd->speed < HCD_USB3)
 995                                 bus_state->port_c_suspend |= 1 << wIndex;
 996                 }
 997                 bus_state->resume_done[wIndex] = 0;
 998                 clear_bit(wIndex, &bus_state->resuming_ports);
 999         }
1000         if (raw_port_status & PORT_CONNECT) {
1001                 status |= USB_PORT_STAT_CONNECTION;
1002                 status |= xhci_port_speed(raw_port_status);
1003         }
1004         if (raw_port_status & PORT_PE)
1005                 status |= USB_PORT_STAT_ENABLE;
1006         if (raw_port_status & PORT_OC)
1007                 status |= USB_PORT_STAT_OVERCURRENT;
1008         if (raw_port_status & PORT_RESET)
1009                 status |= USB_PORT_STAT_RESET;
1010         if (raw_port_status & PORT_POWER) {
1011                 if (hcd->speed >= HCD_USB3)
1012                         status |= USB_SS_PORT_STAT_POWER;
1013                 else
1014                         status |= USB_PORT_STAT_POWER;
1015         }
1016         /* Update Port Link State */
1017         if (hcd->speed >= HCD_USB3) {
1018                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1019                 /*
1020                  * Verify if all USB3 Ports Have entered U0 already.
1021                  * Delete Compliance Mode Timer if so.
1022                  */
1023                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1024         } else {
1025                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1026         }
1027         if (bus_state->port_c_suspend & (1 << wIndex))
1028                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1029
1030         return status;
1031 }
1032
1033 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1034                 u16 wIndex, char *buf, u16 wLength)
1035 {
1036         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1037         int max_ports;
1038         unsigned long flags;
1039         u32 temp, status;
1040         int retval = 0;
1041         __le32 __iomem **port_array;
1042         int slot_id;
1043         struct xhci_bus_state *bus_state;
1044         u16 link_state = 0;
1045         u16 wake_mask = 0;
1046         u16 timeout = 0;
1047         u16 test_mode = 0;
1048
1049         max_ports = xhci_get_ports(hcd, &port_array);
1050         bus_state = &xhci->bus_state[hcd_index(hcd)];
1051
1052         spin_lock_irqsave(&xhci->lock, flags);
1053         switch (typeReq) {
1054         case GetHubStatus:
1055                 /* No power source, over-current reported per port */
1056                 memset(buf, 0, 4);
1057                 break;
1058         case GetHubDescriptor:
1059                 /* Check to make sure userspace is asking for the USB 3.0 hub
1060                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1061                  * endpoint, like external hubs do.
1062                  */
1063                 if (hcd->speed >= HCD_USB3 &&
1064                                 (wLength < USB_DT_SS_HUB_SIZE ||
1065                                  wValue != (USB_DT_SS_HUB << 8))) {
1066                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1067                                         "USB 3.0 roothub.\n");
1068                         goto error;
1069                 }
1070                 xhci_hub_descriptor(hcd, xhci,
1071                                 (struct usb_hub_descriptor *) buf);
1072                 break;
1073         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1074                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1075                         goto error;
1076
1077                 if (hcd->speed < HCD_USB3)
1078                         goto error;
1079
1080                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1081                 spin_unlock_irqrestore(&xhci->lock, flags);
1082                 return retval;
1083         case GetPortStatus:
1084                 if (!wIndex || wIndex > max_ports)
1085                         goto error;
1086                 wIndex--;
1087                 temp = readl(port_array[wIndex]);
1088                 if (temp == ~(u32)0) {
1089                         xhci_hc_died(xhci);
1090                         retval = -ENODEV;
1091                         break;
1092                 }
1093                 status = xhci_get_port_status(hcd, bus_state, port_array,
1094                                 wIndex, temp, flags);
1095                 if (status == 0xffffffff)
1096                         goto error;
1097
1098                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1099                                 wIndex, temp);
1100                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1101
1102                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1103                 /* if USB 3.1 extended port status return additional 4 bytes */
1104                 if (wValue == 0x02) {
1105                         u32 port_li;
1106
1107                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1108                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1109                                 retval = -EINVAL;
1110                                 break;
1111                         }
1112                         port_li = readl(port_array[wIndex] + PORTLI);
1113                         status = xhci_get_ext_port_status(temp, port_li);
1114                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1115                 }
1116                 break;
1117         case SetPortFeature:
1118                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1119                         link_state = (wIndex & 0xff00) >> 3;
1120                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1121                         wake_mask = wIndex & 0xff00;
1122                 if (wValue == USB_PORT_FEAT_TEST)
1123                         test_mode = (wIndex & 0xff00) >> 8;
1124                 /* The MSB of wIndex is the U1/U2 timeout */
1125                 timeout = (wIndex & 0xff00) >> 8;
1126                 wIndex &= 0xff;
1127                 if (!wIndex || wIndex > max_ports)
1128                         goto error;
1129                 wIndex--;
1130                 temp = readl(port_array[wIndex]);
1131                 if (temp == ~(u32)0) {
1132                         xhci_hc_died(xhci);
1133                         retval = -ENODEV;
1134                         break;
1135                 }
1136                 temp = xhci_port_state_to_neutral(temp);
1137                 /* FIXME: What new port features do we need to support? */
1138                 switch (wValue) {
1139                 case USB_PORT_FEAT_SUSPEND:
1140                         temp = readl(port_array[wIndex]);
1141                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1142                                 /* Resume the port to U0 first */
1143                                 xhci_set_link_state(xhci, port_array, wIndex,
1144                                                         XDEV_U0);
1145                                 spin_unlock_irqrestore(&xhci->lock, flags);
1146                                 msleep(10);
1147                                 spin_lock_irqsave(&xhci->lock, flags);
1148                         }
1149                         /* In spec software should not attempt to suspend
1150                          * a port unless the port reports that it is in the
1151                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1152                          */
1153                         temp = readl(port_array[wIndex]);
1154                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1155                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1156                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1157                                 goto error;
1158                         }
1159
1160                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1161                                         wIndex + 1);
1162                         if (!slot_id) {
1163                                 xhci_warn(xhci, "slot_id is zero\n");
1164                                 goto error;
1165                         }
1166                         /* unlock to execute stop endpoint commands */
1167                         spin_unlock_irqrestore(&xhci->lock, flags);
1168                         xhci_stop_device(xhci, slot_id, 1);
1169                         spin_lock_irqsave(&xhci->lock, flags);
1170
1171                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1172
1173                         spin_unlock_irqrestore(&xhci->lock, flags);
1174                         msleep(10); /* wait device to enter */
1175                         spin_lock_irqsave(&xhci->lock, flags);
1176
1177                         temp = readl(port_array[wIndex]);
1178                         bus_state->suspended_ports |= 1 << wIndex;
1179                         break;
1180                 case USB_PORT_FEAT_LINK_STATE:
1181                         temp = readl(port_array[wIndex]);
1182
1183                         /* Disable port */
1184                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1185                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1186                                 temp = xhci_port_state_to_neutral(temp);
1187                                 /*
1188                                  * Clear all change bits, so that we get a new
1189                                  * connection event.
1190                                  */
1191                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1192                                         PORT_OCC | PORT_RC | PORT_PLC |
1193                                         PORT_CEC;
1194                                 writel(temp | PORT_PE, port_array[wIndex]);
1195                                 temp = readl(port_array[wIndex]);
1196                                 break;
1197                         }
1198
1199                         /* Put link in RxDetect (enable port) */
1200                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1201                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1202                                 xhci_set_link_state(xhci, port_array, wIndex,
1203                                                 link_state);
1204                                 temp = readl(port_array[wIndex]);
1205                                 break;
1206                         }
1207
1208                         /*
1209                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1210                          * root hub port's transition to compliance mode upon
1211                          * detecting LFPS timeout may be controlled by an
1212                          * Compliance Transition Enabled (CTE) flag (not
1213                          * software visible). This flag is set by writing 0xA
1214                          * to PORTSC PLS field which will allow transition to
1215                          * compliance mode the next time LFPS timeout is
1216                          * encountered. A warm reset will clear it.
1217                          *
1218                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1219                          * flag is set, otherwise, the compliance substate is
1220                          * automatically entered as on 1.0 and prior.
1221                          */
1222                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1223                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1224                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1225                                         break;
1226                                 }
1227
1228                                 if ((temp & PORT_CONNECT)) {
1229                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1230                                         goto error;
1231                                 }
1232
1233                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1234                                                 wIndex);
1235                                 xhci_set_link_state(xhci, port_array, wIndex,
1236                                                 link_state);
1237                                 temp = readl(port_array[wIndex]);
1238                                 break;
1239                         }
1240
1241                         /* Software should not attempt to set
1242                          * port link state above '3' (U3) and the port
1243                          * must be enabled.
1244                          */
1245                         if ((temp & PORT_PE) == 0 ||
1246                                 (link_state > USB_SS_PORT_LS_U3)) {
1247                                 xhci_warn(xhci, "Cannot set link state.\n");
1248                                 goto error;
1249                         }
1250
1251                         if (link_state == USB_SS_PORT_LS_U3) {
1252                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1253                                                 wIndex + 1);
1254                                 if (slot_id) {
1255                                         /* unlock to execute stop endpoint
1256                                          * commands */
1257                                         spin_unlock_irqrestore(&xhci->lock,
1258                                                                 flags);
1259                                         xhci_stop_device(xhci, slot_id, 1);
1260                                         spin_lock_irqsave(&xhci->lock, flags);
1261                                 }
1262                         }
1263
1264                         xhci_set_link_state(xhci, port_array, wIndex,
1265                                                 link_state);
1266
1267                         spin_unlock_irqrestore(&xhci->lock, flags);
1268                         msleep(20); /* wait device to enter */
1269                         spin_lock_irqsave(&xhci->lock, flags);
1270
1271                         temp = readl(port_array[wIndex]);
1272                         if (link_state == USB_SS_PORT_LS_U3)
1273                                 bus_state->suspended_ports |= 1 << wIndex;
1274                         break;
1275                 case USB_PORT_FEAT_POWER:
1276                         /*
1277                          * Turn on ports, even if there isn't per-port switching.
1278                          * HC will report connect events even before this is set.
1279                          * However, hub_wq will ignore the roothub events until
1280                          * the roothub is registered.
1281                          */
1282                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1283                         break;
1284                 case USB_PORT_FEAT_RESET:
1285                         temp = (temp | PORT_RESET);
1286                         writel(temp, port_array[wIndex]);
1287
1288                         temp = readl(port_array[wIndex]);
1289                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1290                         break;
1291                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1292                         xhci_set_remote_wake_mask(xhci, port_array,
1293                                         wIndex, wake_mask);
1294                         temp = readl(port_array[wIndex]);
1295                         xhci_dbg(xhci, "set port remote wake mask, "
1296                                         "actual port %d status  = 0x%x\n",
1297                                         wIndex, temp);
1298                         break;
1299                 case USB_PORT_FEAT_BH_PORT_RESET:
1300                         temp |= PORT_WR;
1301                         writel(temp, port_array[wIndex]);
1302
1303                         temp = readl(port_array[wIndex]);
1304                         break;
1305                 case USB_PORT_FEAT_U1_TIMEOUT:
1306                         if (hcd->speed < HCD_USB3)
1307                                 goto error;
1308                         temp = readl(port_array[wIndex] + PORTPMSC);
1309                         temp &= ~PORT_U1_TIMEOUT_MASK;
1310                         temp |= PORT_U1_TIMEOUT(timeout);
1311                         writel(temp, port_array[wIndex] + PORTPMSC);
1312                         break;
1313                 case USB_PORT_FEAT_U2_TIMEOUT:
1314                         if (hcd->speed < HCD_USB3)
1315                                 goto error;
1316                         temp = readl(port_array[wIndex] + PORTPMSC);
1317                         temp &= ~PORT_U2_TIMEOUT_MASK;
1318                         temp |= PORT_U2_TIMEOUT(timeout);
1319                         writel(temp, port_array[wIndex] + PORTPMSC);
1320                         break;
1321                 case USB_PORT_FEAT_TEST:
1322                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1323                         if (hcd->speed != HCD_USB2)
1324                                 goto error;
1325                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1326                                 goto error;
1327                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1328                                                       &flags);
1329                         break;
1330                 default:
1331                         goto error;
1332                 }
1333                 /* unblock any posted writes */
1334                 temp = readl(port_array[wIndex]);
1335                 break;
1336         case ClearPortFeature:
1337                 if (!wIndex || wIndex > max_ports)
1338                         goto error;
1339                 wIndex--;
1340                 temp = readl(port_array[wIndex]);
1341                 if (temp == ~(u32)0) {
1342                         xhci_hc_died(xhci);
1343                         retval = -ENODEV;
1344                         break;
1345                 }
1346                 /* FIXME: What new port features do we need to support? */
1347                 temp = xhci_port_state_to_neutral(temp);
1348                 switch (wValue) {
1349                 case USB_PORT_FEAT_SUSPEND:
1350                         temp = readl(port_array[wIndex]);
1351                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1352                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1353                         if (temp & PORT_RESET)
1354                                 goto error;
1355                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1356                                 if ((temp & PORT_PE) == 0)
1357                                         goto error;
1358
1359                                 set_bit(wIndex, &bus_state->resuming_ports);
1360                                 xhci_set_link_state(xhci, port_array, wIndex,
1361                                                         XDEV_RESUME);
1362                                 spin_unlock_irqrestore(&xhci->lock, flags);
1363                                 msleep(USB_RESUME_TIMEOUT);
1364                                 spin_lock_irqsave(&xhci->lock, flags);
1365                                 xhci_set_link_state(xhci, port_array, wIndex,
1366                                                         XDEV_U0);
1367                                 clear_bit(wIndex, &bus_state->resuming_ports);
1368                         }
1369                         bus_state->port_c_suspend |= 1 << wIndex;
1370
1371                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1372                                         wIndex + 1);
1373                         if (!slot_id) {
1374                                 xhci_dbg(xhci, "slot_id is zero\n");
1375                                 goto error;
1376                         }
1377                         xhci_ring_device(xhci, slot_id);
1378                         break;
1379                 case USB_PORT_FEAT_C_SUSPEND:
1380                         bus_state->port_c_suspend &= ~(1 << wIndex);
1381                         /* fall through */
1382                 case USB_PORT_FEAT_C_RESET:
1383                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1384                 case USB_PORT_FEAT_C_CONNECTION:
1385                 case USB_PORT_FEAT_C_OVER_CURRENT:
1386                 case USB_PORT_FEAT_C_ENABLE:
1387                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1388                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1389                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1390                                         port_array[wIndex], temp);
1391                         break;
1392                 case USB_PORT_FEAT_ENABLE:
1393                         xhci_disable_port(hcd, xhci, wIndex,
1394                                         port_array[wIndex], temp);
1395                         break;
1396                 case USB_PORT_FEAT_POWER:
1397                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1398                         break;
1399                 case USB_PORT_FEAT_TEST:
1400                         retval = xhci_exit_test_mode(xhci);
1401                         break;
1402                 default:
1403                         goto error;
1404                 }
1405                 break;
1406         default:
1407 error:
1408                 /* "stall" on error */
1409                 retval = -EPIPE;
1410         }
1411         spin_unlock_irqrestore(&xhci->lock, flags);
1412         return retval;
1413 }
1414
1415 /*
1416  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1417  * Ports are 0-indexed from the HCD point of view,
1418  * and 1-indexed from the USB core pointer of view.
1419  *
1420  * Note that the status change bits will be cleared as soon as a port status
1421  * change event is generated, so we use the saved status from that event.
1422  */
1423 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1424 {
1425         unsigned long flags;
1426         u32 temp, status;
1427         u32 mask;
1428         int i, retval;
1429         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1430         int max_ports;
1431         __le32 __iomem **port_array;
1432         struct xhci_bus_state *bus_state;
1433         bool reset_change = false;
1434
1435         max_ports = xhci_get_ports(hcd, &port_array);
1436         bus_state = &xhci->bus_state[hcd_index(hcd)];
1437
1438         /* Initial status is no changes */
1439         retval = (max_ports + 8) / 8;
1440         memset(buf, 0, retval);
1441
1442         /*
1443          * Inform the usbcore about resume-in-progress by returning
1444          * a non-zero value even if there are no status changes.
1445          */
1446         status = bus_state->resuming_ports;
1447
1448         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1449
1450         spin_lock_irqsave(&xhci->lock, flags);
1451         /* For each port, did anything change?  If so, set that bit in buf. */
1452         for (i = 0; i < max_ports; i++) {
1453                 temp = readl(port_array[i]);
1454                 if (temp == ~(u32)0) {
1455                         xhci_hc_died(xhci);
1456                         retval = -ENODEV;
1457                         break;
1458                 }
1459                 if ((temp & mask) != 0 ||
1460                         (bus_state->port_c_suspend & 1 << i) ||
1461                         (bus_state->resume_done[i] && time_after_eq(
1462                             jiffies, bus_state->resume_done[i]))) {
1463                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1464                         status = 1;
1465                 }
1466                 if ((temp & PORT_RC))
1467                         reset_change = true;
1468         }
1469         if (!status && !reset_change) {
1470                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1471                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1472         }
1473         spin_unlock_irqrestore(&xhci->lock, flags);
1474         return status ? retval : 0;
1475 }
1476
1477 #ifdef CONFIG_PM
1478
1479 int xhci_bus_suspend(struct usb_hcd *hcd)
1480 {
1481         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1482         int max_ports, port_index;
1483         __le32 __iomem **port_array;
1484         struct xhci_bus_state *bus_state;
1485         unsigned long flags;
1486
1487         max_ports = xhci_get_ports(hcd, &port_array);
1488         bus_state = &xhci->bus_state[hcd_index(hcd)];
1489
1490         spin_lock_irqsave(&xhci->lock, flags);
1491
1492         if (hcd->self.root_hub->do_remote_wakeup) {
1493                 if (bus_state->resuming_ports ||        /* USB2 */
1494                     bus_state->port_remote_wakeup) {    /* USB3 */
1495                         spin_unlock_irqrestore(&xhci->lock, flags);
1496                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1497                         return -EBUSY;
1498                 }
1499         }
1500
1501         port_index = max_ports;
1502         bus_state->bus_suspended = 0;
1503         while (port_index--) {
1504                 /* suspend the port if the port is not suspended */
1505                 u32 t1, t2;
1506                 int slot_id;
1507
1508                 t1 = readl(port_array[port_index]);
1509                 t2 = xhci_port_state_to_neutral(t1);
1510
1511                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1512                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1513                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1514                                         port_index + 1);
1515                         if (slot_id) {
1516                                 spin_unlock_irqrestore(&xhci->lock, flags);
1517                                 xhci_stop_device(xhci, slot_id, 1);
1518                                 spin_lock_irqsave(&xhci->lock, flags);
1519                         }
1520                         t2 &= ~PORT_PLS_MASK;
1521                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1522                         set_bit(port_index, &bus_state->bus_suspended);
1523                 }
1524                 /* USB core sets remote wake mask for USB 3.0 hubs,
1525                  * including the USB 3.0 roothub, but only if CONFIG_PM
1526                  * is enabled, so also enable remote wake here.
1527                  */
1528                 if (hcd->self.root_hub->do_remote_wakeup) {
1529                         if (t1 & PORT_CONNECT) {
1530                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1531                                 t2 &= ~PORT_WKCONN_E;
1532                         } else {
1533                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1534                                 t2 &= ~PORT_WKDISC_E;
1535                         }
1536                 } else
1537                         t2 &= ~PORT_WAKE_BITS;
1538
1539                 t1 = xhci_port_state_to_neutral(t1);
1540                 if (t1 != t2)
1541                         writel(t2, port_array[port_index]);
1542         }
1543         hcd->state = HC_STATE_SUSPENDED;
1544         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1545         spin_unlock_irqrestore(&xhci->lock, flags);
1546         return 0;
1547 }
1548
1549 /*
1550  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1551  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1552  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1553  */
1554 static bool xhci_port_missing_cas_quirk(int port_index,
1555                                              __le32 __iomem **port_array)
1556 {
1557         u32 portsc;
1558
1559         portsc = readl(port_array[port_index]);
1560
1561         /* if any of these are set we are not stuck */
1562         if (portsc & (PORT_CONNECT | PORT_CAS))
1563                 return false;
1564
1565         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1566             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1567                 return false;
1568
1569         /* clear wakeup/change bits, and do a warm port reset */
1570         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1571         portsc |= PORT_WR;
1572         writel(portsc, port_array[port_index]);
1573         /* flush write */
1574         readl(port_array[port_index]);
1575         return true;
1576 }
1577
1578 int xhci_bus_resume(struct usb_hcd *hcd)
1579 {
1580         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1581         struct xhci_bus_state *bus_state;
1582         __le32 __iomem **port_array;
1583         unsigned long flags;
1584         int max_ports, port_index;
1585         int slot_id;
1586         int sret;
1587         u32 next_state;
1588         u32 temp, portsc;
1589
1590         max_ports = xhci_get_ports(hcd, &port_array);
1591         bus_state = &xhci->bus_state[hcd_index(hcd)];
1592
1593         if (time_before(jiffies, bus_state->next_statechange))
1594                 msleep(5);
1595
1596         spin_lock_irqsave(&xhci->lock, flags);
1597         if (!HCD_HW_ACCESSIBLE(hcd)) {
1598                 spin_unlock_irqrestore(&xhci->lock, flags);
1599                 return -ESHUTDOWN;
1600         }
1601
1602         /* delay the irqs */
1603         temp = readl(&xhci->op_regs->command);
1604         temp &= ~CMD_EIE;
1605         writel(temp, &xhci->op_regs->command);
1606
1607         /* bus specific resume for ports we suspended at bus_suspend */
1608         if (hcd->speed >= HCD_USB3)
1609                 next_state = XDEV_U0;
1610         else
1611                 next_state = XDEV_RESUME;
1612
1613         port_index = max_ports;
1614         while (port_index--) {
1615                 portsc = readl(port_array[port_index]);
1616
1617                 /* warm reset CAS limited ports stuck in polling/compliance */
1618                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1619                     (hcd->speed >= HCD_USB3) &&
1620                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1621                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1622                         clear_bit(port_index, &bus_state->bus_suspended);
1623                         continue;
1624                 }
1625                 /* resume if we suspended the link, and it is still suspended */
1626                 if (test_bit(port_index, &bus_state->bus_suspended))
1627                         switch (portsc & PORT_PLS_MASK) {
1628                         case XDEV_U3:
1629                                 portsc = xhci_port_state_to_neutral(portsc);
1630                                 portsc &= ~PORT_PLS_MASK;
1631                                 portsc |= PORT_LINK_STROBE | next_state;
1632                                 break;
1633                         case XDEV_RESUME:
1634                                 /* resume already initiated */
1635                                 break;
1636                         default:
1637                                 /* not in a resumeable state, ignore it */
1638                                 clear_bit(port_index,
1639                                           &bus_state->bus_suspended);
1640                                 break;
1641                         }
1642                 /* disable wake for all ports, write new link state if needed */
1643                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1644                 writel(portsc, port_array[port_index]);
1645         }
1646
1647         /* USB2 specific resume signaling delay and U0 link state transition */
1648         if (hcd->speed < HCD_USB3) {
1649                 if (bus_state->bus_suspended) {
1650                         spin_unlock_irqrestore(&xhci->lock, flags);
1651                         msleep(USB_RESUME_TIMEOUT);
1652                         spin_lock_irqsave(&xhci->lock, flags);
1653                 }
1654                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1655                                  BITS_PER_LONG) {
1656                         /* Clear PLC to poll it later for U0 transition */
1657                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1658                                                 PORT_PLC);
1659                         xhci_set_link_state(xhci, port_array, port_index,
1660                                             XDEV_U0);
1661                 }
1662         }
1663
1664         /* poll for U0 link state complete, both USB2 and USB3 */
1665         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1666                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1667                                       PORT_PLC, 10 * 1000);
1668                 if (sret) {
1669                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1670                                   port_index);
1671                         continue;
1672                 }
1673                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1674                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1675                 if (slot_id)
1676                         xhci_ring_device(xhci, slot_id);
1677         }
1678         (void) readl(&xhci->op_regs->command);
1679
1680         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1681         /* re-enable irqs */
1682         temp = readl(&xhci->op_regs->command);
1683         temp |= CMD_EIE;
1684         writel(temp, &xhci->op_regs->command);
1685         temp = readl(&xhci->op_regs->command);
1686
1687         spin_unlock_irqrestore(&xhci->lock, flags);
1688         return 0;
1689 }
1690
1691 #endif  /* CONFIG_PM */