drivers/usb/host/xhci-dbg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  * for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software Foundation,
  21  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include "xhci.h"
  25
  26 #define XHCI_INIT_VALUE 0x0
  27
  28 /* Add verbose debugging later, just print everything for now */
  29
  30 void xhci_dbg_regs(struct xhci_hcd *xhci)
  31 {
  32         u32 temp;
  33
  34         xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
  35                         xhci->cap_regs);
  36         temp = readl(&xhci->cap_regs->hc_capbase);
  37         xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
  38                         &xhci->cap_regs->hc_capbase, temp);
  39         xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
  40                         (unsigned int) HC_LENGTH(temp));
  41         xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
  42                         (unsigned int) HC_VERSION(temp));
  43
  44         xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
  45
  46         temp = readl(&xhci->cap_regs->run_regs_off);
  47         xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
  48                         &xhci->cap_regs->run_regs_off,
  49                         (unsigned int) temp & RTSOFF_MASK);
  50         xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
  51
  52         temp = readl(&xhci->cap_regs->db_off);
  53         xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
  54         xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
  55 }
  56
  57 static void xhci_print_cap_regs(struct xhci_hcd *xhci)
  58 {
  59         u32 temp;
  60         u32 hci_version;
  61
  62         xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
  63
  64         temp = readl(&xhci->cap_regs->hc_capbase);
  65         hci_version = HC_VERSION(temp);
  66         xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
  67                         (unsigned int) temp);
  68         xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
  69                         (unsigned int) HC_LENGTH(temp));
  70         xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version);
  71
  72         temp = readl(&xhci->cap_regs->hcs_params1);
  73         xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
  74                         (unsigned int) temp);
  75         xhci_dbg(xhci, "  Max device slots: %u\n",
  76                         (unsigned int) HCS_MAX_SLOTS(temp));
  77         xhci_dbg(xhci, "  Max interrupters: %u\n",
  78                         (unsigned int) HCS_MAX_INTRS(temp));
  79         xhci_dbg(xhci, "  Max ports: %u\n",
  80                         (unsigned int) HCS_MAX_PORTS(temp));
  81
  82         temp = readl(&xhci->cap_regs->hcs_params2);
  83         xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
  84                         (unsigned int) temp);
  85         xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
  86                         (unsigned int) HCS_IST(temp));
  87         xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
  88                         (unsigned int) HCS_ERST_MAX(temp));
  89
  90         temp = readl(&xhci->cap_regs->hcs_params3);
  91         xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
  92                         (unsigned int) temp);
  93         xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
  94                         (unsigned int) HCS_U1_LATENCY(temp));
  95         xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
  96                         (unsigned int) HCS_U2_LATENCY(temp));
  97
  98         temp = readl(&xhci->cap_regs->hcc_params);
  99         xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
 100         xhci_dbg(xhci, "  HC generates %s bit addresses\n",
 101                         HCC_64BIT_ADDR(temp) ? "64" : "32");
 102         xhci_dbg(xhci, "  HC %s Contiguous Frame ID Capability\n",
 103                         HCC_CFC(temp) ? "has" : "hasn't");
 104         xhci_dbg(xhci, "  HC %s generate Stopped - Short Package event\n",
 105                         HCC_SPC(temp) ? "can" : "can't");
 106         /* FIXME */
 107         xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");
 108
 109         temp = readl(&xhci->cap_regs->run_regs_off);
 110         xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
 111
 112         /* xhci 1.1 controllers have the HCCPARAMS2 register */
 113         if (hci_version > 0x100) {
 114                 temp = readl(&xhci->cap_regs->hcc_params2);
 115                 xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp);
 116                 xhci_dbg(xhci, "  HC %s Force save context capability",
 117                          HCC2_FSC(temp) ? "supports" : "doesn't support");
 118                 xhci_dbg(xhci, "  HC %s Large ESIT Payload Capability",
 119                          HCC2_LEC(temp) ? "supports" : "doesn't support");
 120                 xhci_dbg(xhci, "  HC %s Extended TBC capability",
 121                          HCC2_ETC(temp) ? "supports" : "doesn't support");
 122         }
 123 }
 124
 125 static void xhci_print_command_reg(struct xhci_hcd *xhci)
 126 {
 127         u32 temp;
 128
 129         temp = readl(&xhci->op_regs->command);
 130         xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
 131         xhci_dbg(xhci, "  HC is %s\n",
 132                         (temp & CMD_RUN) ? "running" : "being stopped");
 133         xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
 134                         (temp & CMD_RESET) ? "not " : "");
 135         xhci_dbg(xhci, "  Event Interrupts %s\n",
 136                         (temp & CMD_EIE) ? "enabled " : "disabled");
 137         xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
 138                         (temp & CMD_HSEIE) ? "enabled " : "disabled");
 139         xhci_dbg(xhci, "  HC has %sfinished light reset\n",
 140                         (temp & CMD_LRESET) ? "not " : "");
 141 }
 142
 143 static void xhci_print_status(struct xhci_hcd *xhci)
 144 {
 145         u32 temp;
 146
 147         temp = readl(&xhci->op_regs->status);
 148         xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
 149         xhci_dbg(xhci, "  Event ring is %sempty\n",
 150                         (temp & STS_EINT) ? "not " : "");
 151         xhci_dbg(xhci, "  %sHost System Error\n",
 152                         (temp & STS_FATAL) ? "WARNING: " : "No ");
 153         xhci_dbg(xhci, "  HC is %s\n",
 154                         (temp & STS_HALT) ? "halted" : "running");
 155 }
 156
 157 static void xhci_print_op_regs(struct xhci_hcd *xhci)
 158 {
 159         xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
 160         xhci_print_command_reg(xhci);
 161         xhci_print_status(xhci);
 162 }
 163
 164 static void xhci_print_ports(struct xhci_hcd *xhci)
 165 {
 166         __le32 __iomem *addr;
 167         int i, j;
 168         int ports;
 169         char *names[NUM_PORT_REGS] = {
 170                 "status",
 171                 "power",
 172                 "link",
 173                 "reserved",
 174         };
 175
 176         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 177         addr = &xhci->op_regs->port_status_base;
 178         for (i = 0; i < ports; i++) {
 179                 for (j = 0; j < NUM_PORT_REGS; j++) {
 180                         xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
 181                                         addr, names[j],
 182                                         (unsigned int) readl(addr));
 183                         addr++;
 184                 }
 185         }
 186 }
 187
 188 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
 189 {
 190         struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
 191         void __iomem *addr;
 192         u32 temp;
 193         u64 temp_64;
 194
 195         addr = &ir_set->irq_pending;
 196         temp = readl(addr);
 197         if (temp == XHCI_INIT_VALUE)
 198                 return;
 199
 200         xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);
 201
 202         xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
 203                         (unsigned int)temp);
 204
 205         addr = &ir_set->irq_control;
 206         temp = readl(addr);
 207         xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
 208                         (unsigned int)temp);
 209
 210         addr = &ir_set->erst_size;
 211         temp = readl(addr);
 212         xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
 213                         (unsigned int)temp);
 214
 215         addr = &ir_set->rsvd;
 216         temp = readl(addr);
 217         if (temp != XHCI_INIT_VALUE)
 218                 xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
 219                                 addr, (unsigned int)temp);
 220
 221         addr = &ir_set->erst_base;
 222         temp_64 = xhci_read_64(xhci, addr);
 223         xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
 224                         addr, temp_64);
 225
 226         addr = &ir_set->erst_dequeue;
 227         temp_64 = xhci_read_64(xhci, addr);
 228         xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
 229                         addr, temp_64);
 230 }
 231
 232 void xhci_print_run_regs(struct xhci_hcd *xhci)
 233 {
 234         u32 temp;
 235         int i;
 236
 237         xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
 238         temp = readl(&xhci->run_regs->microframe_index);
 239         xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
 240                         &xhci->run_regs->microframe_index,
 241                         (unsigned int) temp);
 242         for (i = 0; i < 7; i++) {
 243                 temp = readl(&xhci->run_regs->rsvd[i]);
 244                 if (temp != XHCI_INIT_VALUE)
 245                         xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
 246                                         &xhci->run_regs->rsvd[i],
 247                                         i, (unsigned int) temp);
 248         }
 249 }
 250
 251 void xhci_print_registers(struct xhci_hcd *xhci)
 252 {
 253         xhci_print_cap_regs(xhci);
 254         xhci_print_op_regs(xhci);
 255         xhci_print_ports(xhci);
 256 }
 257
 258 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
 259 {
 260         u64 addr = erst->erst_dma_addr;
 261         int i;
 262         struct xhci_erst_entry *entry;
 263
 264         for (i = 0; i < erst->num_entries; i++) {
 265                 entry = &erst->entries[i];
 266                 xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
 267                          addr,
 268                          lower_32_bits(le64_to_cpu(entry->seg_addr)),
 269                          upper_32_bits(le64_to_cpu(entry->seg_addr)),
 270                          le32_to_cpu(entry->seg_size),
 271                          le32_to_cpu(entry->rsvd));
 272                 addr += sizeof(*entry);
 273         }
 274 }
 275
 276 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
 277 {
 278         u64 val;
 279
 280         val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 281         xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
 282                         lower_32_bits(val));
 283         xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
 284                         upper_32_bits(val));
 285 }
 286
 287 char *xhci_get_slot_state(struct xhci_hcd *xhci,
 288                 struct xhci_container_ctx *ctx)
 289 {
 290         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 291         int state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
 292
 293         return xhci_slot_state_string(state);
 294 }
 295
 296 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
 297                         const char *fmt, ...)
 298 {
 299         struct va_format vaf;
 300         va_list args;
 301
 302         va_start(args, fmt);
 303         vaf.fmt = fmt;
 304         vaf.va = &args;
 305         xhci_dbg(xhci, "%pV\n", &vaf);
 306         trace(&vaf);
 307         va_end(args);
 308 }
 309 EXPORT_SYMBOL_GPL(xhci_dbg_trace);