2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 - 2013 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/platform_device.h>
22 #include <linux/platform_data/tegra_usb.h>
23 #include <linux/irq.h>
24 #include <linux/usb/otg.h>
25 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/usb/ehci_def.h>
30 #include <linux/usb/tegra_usb_phy.h>
31 #include <linux/clk/tegra.h>
33 #define TEGRA_USB_BASE 0xC5000000
34 #define TEGRA_USB2_BASE 0xC5004000
35 #define TEGRA_USB3_BASE 0xC5008000
37 /* PORTSC registers */
38 #define TEGRA_USB_PORTSC1 0x184
39 #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
40 #define TEGRA_USB_PORTSC1_PHCD (1 << 23)
42 #define TEGRA_USB_DMA_ALIGN 32
44 struct tegra_ehci_hcd {
45 struct ehci_hcd *ehci;
46 struct tegra_usb_phy *phy;
48 struct usb_phy *transceiver;
51 bool needs_double_reset;
52 enum tegra_usb_phy_port_speed port_speed;
55 static void tegra_ehci_power_up(struct usb_hcd *hcd)
57 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
59 clk_prepare_enable(tegra->clk);
60 usb_phy_set_suspend(hcd->phy, 0);
61 tegra->host_resumed = 1;
64 static void tegra_ehci_power_down(struct usb_hcd *hcd)
66 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
68 tegra->host_resumed = 0;
69 usb_phy_set_suspend(hcd->phy, 1);
70 clk_disable_unprepare(tegra->clk);
73 static int tegra_ehci_internal_port_reset(
74 struct ehci_hcd *ehci,
75 u32 __iomem *portsc_reg
84 spin_lock_irqsave(&ehci->lock, flags);
85 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
86 /* disable USB interrupt */
87 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
88 spin_unlock_irqrestore(&ehci->lock, flags);
91 * Here we have to do Port Reset at most twice for
92 * Port Enable bit to be set.
94 for (i = 0; i < 2; i++) {
95 temp = ehci_readl(ehci, portsc_reg);
97 ehci_writel(ehci, temp, portsc_reg);
100 ehci_writel(ehci, temp, portsc_reg);
106 * Up to this point, Port Enable bit is
107 * expected to be set after 2 ms waiting.
108 * USB1 usually takes extra 45 ms, for safety,
109 * we take 100 ms as timeout.
111 temp = ehci_readl(ehci, portsc_reg);
112 } while (!(temp & PORT_PE) && tries--);
120 * Clear Connect Status Change bit if it's set.
121 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
124 ehci_writel(ehci, PORT_CSC, portsc_reg);
127 * Write to clear any interrupt status bits that might be set
130 temp = ehci_readl(ehci, &ehci->regs->status);
131 ehci_writel(ehci, temp, &ehci->regs->status);
133 /* restore original interrupt enable bits */
134 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
138 static int tegra_ehci_hub_control(
147 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
148 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
149 u32 __iomem *status_reg;
154 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
156 spin_lock_irqsave(&ehci->lock, flags);
158 if (typeReq == GetPortStatus) {
159 temp = ehci_readl(ehci, status_reg);
160 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
161 /* Resume completed, re-enable disconnect detection */
162 tegra->port_resuming = 0;
163 tegra_usb_phy_postresume(hcd->phy);
167 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
168 temp = ehci_readl(ehci, status_reg);
169 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
174 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
175 temp |= PORT_WKDISC_E | PORT_WKOC_E;
176 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
179 * If a transaction is in progress, there may be a delay in
180 * suspending the port. Poll until the port is suspended.
182 if (handshake(ehci, status_reg, PORT_SUSPEND,
184 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
186 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
190 /* For USB1 port we need to issue Port Reset twice internally */
191 if (tegra->needs_double_reset &&
192 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
193 spin_unlock_irqrestore(&ehci->lock, flags);
194 return tegra_ehci_internal_port_reset(ehci, status_reg);
198 * Tegra host controller will time the resume operation to clear the bit
199 * when the port control state switches to HS or FS Idle. This behavior
200 * is different from EHCI where the host controller driver is required
201 * to set this bit to a zero after the resume duration is timed in the
204 else if (typeReq == ClearPortFeature &&
205 wValue == USB_PORT_FEAT_SUSPEND) {
206 temp = ehci_readl(ehci, status_reg);
207 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
212 if (!(temp & PORT_SUSPEND))
215 /* Disable disconnect detection during port resume */
216 tegra_usb_phy_preresume(hcd->phy);
218 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
220 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
221 /* start resume signalling */
222 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
223 set_bit(wIndex-1, &ehci->resuming_ports);
225 spin_unlock_irqrestore(&ehci->lock, flags);
227 spin_lock_irqsave(&ehci->lock, flags);
229 /* Poll until the controller clears RESUME and SUSPEND */
230 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
231 pr_err("%s: timeout waiting for RESUME\n", __func__);
232 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
233 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
235 ehci->reset_done[wIndex-1] = 0;
236 clear_bit(wIndex-1, &ehci->resuming_ports);
238 tegra->port_resuming = 1;
242 spin_unlock_irqrestore(&ehci->lock, flags);
244 /* Handle the hub control events here */
245 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
247 spin_unlock_irqrestore(&ehci->lock, flags);
251 static void tegra_ehci_restart(struct usb_hcd *hcd)
253 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
257 /* setup the frame list and Async q heads */
258 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
259 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
260 /* setup the command register and set the controller in RUN mode */
261 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
262 ehci->command |= CMD_RUN;
263 ehci_writel(ehci, ehci->command, &ehci->regs->command);
265 down_write(&ehci_cf_port_reset_rwsem);
266 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
267 /* flush posted writes */
268 ehci_readl(ehci, &ehci->regs->command);
269 up_write(&ehci_cf_port_reset_rwsem);
272 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
274 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
276 /* ehci_shutdown touches the USB controller registers, make sure
277 * controller has clocks to it */
278 if (!tegra->host_resumed)
279 tegra_ehci_power_up(hcd);
284 static int tegra_ehci_setup(struct usb_hcd *hcd)
286 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
288 /* EHCI registers start at offset 0x100 */
289 ehci->caps = hcd->regs + 0x100;
291 /* switch to host mode */
294 return ehci_setup(hcd);
297 struct dma_aligned_buffer {
299 void *old_xfer_buffer;
303 static void free_dma_aligned_buffer(struct urb *urb)
305 struct dma_aligned_buffer *temp;
307 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
310 temp = container_of(urb->transfer_buffer,
311 struct dma_aligned_buffer, data);
313 if (usb_urb_dir_in(urb))
314 memcpy(temp->old_xfer_buffer, temp->data,
315 urb->transfer_buffer_length);
316 urb->transfer_buffer = temp->old_xfer_buffer;
317 kfree(temp->kmalloc_ptr);
319 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
322 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
324 struct dma_aligned_buffer *temp, *kmalloc_ptr;
327 if (urb->num_sgs || urb->sg ||
328 urb->transfer_buffer_length == 0 ||
329 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
332 /* Allocate a buffer with enough padding for alignment */
333 kmalloc_size = urb->transfer_buffer_length +
334 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
336 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
340 /* Position our struct dma_aligned_buffer such that data is aligned */
341 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
342 temp->kmalloc_ptr = kmalloc_ptr;
343 temp->old_xfer_buffer = urb->transfer_buffer;
344 if (usb_urb_dir_out(urb))
345 memcpy(temp->data, urb->transfer_buffer,
346 urb->transfer_buffer_length);
347 urb->transfer_buffer = temp->data;
349 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
354 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
359 ret = alloc_dma_aligned_buffer(urb, mem_flags);
363 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
365 free_dma_aligned_buffer(urb);
370 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
372 usb_hcd_unmap_urb_for_dma(hcd, urb);
373 free_dma_aligned_buffer(urb);
376 static const struct hc_driver tegra_ehci_hc_driver = {
377 .description = hcd_name,
378 .product_desc = "Tegra EHCI Host Controller",
379 .hcd_priv_size = sizeof(struct ehci_hcd),
380 .flags = HCD_USB2 | HCD_MEMORY,
382 /* standard ehci functions */
386 .urb_enqueue = ehci_urb_enqueue,
387 .urb_dequeue = ehci_urb_dequeue,
388 .endpoint_disable = ehci_endpoint_disable,
389 .endpoint_reset = ehci_endpoint_reset,
390 .get_frame_number = ehci_get_frame,
391 .hub_status_data = ehci_hub_status_data,
392 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
393 .relinquish_port = ehci_relinquish_port,
394 .port_handed_over = ehci_port_handed_over,
396 /* modified ehci functions for tegra */
397 .reset = tegra_ehci_setup,
398 .shutdown = tegra_ehci_shutdown,
399 .map_urb_for_dma = tegra_ehci_map_urb_for_dma,
400 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
401 .hub_control = tegra_ehci_hub_control,
403 .bus_suspend = ehci_bus_suspend,
404 .bus_resume = ehci_bus_resume,
408 static int setup_vbus_gpio(struct platform_device *pdev,
409 struct tegra_ehci_platform_data *pdata)
414 gpio = pdata->vbus_gpio;
415 if (!gpio_is_valid(gpio))
416 gpio = of_get_named_gpio(pdev->dev.of_node,
417 "nvidia,vbus-gpio", 0);
418 if (!gpio_is_valid(gpio))
421 err = gpio_request(gpio, "vbus_gpio");
423 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
426 err = gpio_direction_output(gpio, 1);
428 dev_err(&pdev->dev, "can't enable vbus\n");
437 static int controller_suspend(struct device *dev)
439 struct tegra_ehci_hcd *tegra =
440 platform_get_drvdata(to_platform_device(dev));
441 struct ehci_hcd *ehci = tegra->ehci;
442 struct usb_hcd *hcd = ehci_to_hcd(ehci);
443 struct ehci_regs __iomem *hw = ehci->regs;
446 if (time_before(jiffies, ehci->next_statechange))
451 spin_lock_irqsave(&ehci->lock, flags);
452 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
453 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
454 spin_unlock_irqrestore(&ehci->lock, flags);
456 tegra_ehci_power_down(hcd);
460 static int controller_resume(struct device *dev)
462 struct tegra_ehci_hcd *tegra =
463 platform_get_drvdata(to_platform_device(dev));
464 struct ehci_hcd *ehci = tegra->ehci;
465 struct usb_hcd *hcd = ehci_to_hcd(ehci);
466 struct ehci_regs __iomem *hw = ehci->regs;
469 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
470 tegra_ehci_power_up(hcd);
472 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
473 /* Wait for the phy to detect new devices
474 * before we restart the controller */
479 /* Force the phy to keep data lines in suspend state */
480 tegra_ehci_phy_restore_start(hcd->phy, tegra->port_speed);
482 /* Enable host mode */
485 /* Enable Port Power */
486 val = readl(&hw->port_status[0]);
488 writel(val, &hw->port_status[0]);
491 /* Check if the phy resume from LP0. When the phy resume from LP0
492 * USB register will be reset. */
493 if (!readl(&hw->async_next)) {
494 /* Program the field PTC based on the saved speed mode */
495 val = readl(&hw->port_status[0]);
496 val &= ~PORT_TEST(~0);
497 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
498 val |= PORT_TEST_FORCE;
499 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
501 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
503 writel(val, &hw->port_status[0]);
506 /* Disable test mode by setting PTC field to NORMAL_OP */
507 val = readl(&hw->port_status[0]);
508 val &= ~PORT_TEST(~0);
509 writel(val, &hw->port_status[0]);
513 /* Poll until CCS is enabled */
514 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
515 PORT_CONNECT, 2000)) {
516 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
520 /* Poll until PE is enabled */
521 if (handshake(ehci, &hw->port_status[0], PORT_PE,
523 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
527 /* Clear the PCI status, to avoid an interrupt taken upon resume */
528 val = readl(&hw->status);
530 writel(val, &hw->status);
532 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
533 val = readl(&hw->port_status[0]);
534 if ((val & PORT_POWER) && (val & PORT_PE)) {
536 writel(val, &hw->port_status[0]);
538 /* Wait until port suspend completes */
539 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
540 PORT_SUSPEND, 1000)) {
541 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
547 tegra_ehci_phy_restore_end(hcd->phy);
551 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
552 tegra_ehci_phy_restore_end(hcd->phy);
554 tegra_ehci_restart(hcd);
557 tegra_usb_phy_preresume(hcd->phy);
558 tegra->port_resuming = 1;
562 static int tegra_ehci_suspend(struct device *dev)
564 struct tegra_ehci_hcd *tegra =
565 platform_get_drvdata(to_platform_device(dev));
566 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
570 * When system sleep is supported and USB controller wakeup is
571 * implemented: If the controller is runtime-suspended and the
572 * wakeup setting needs to be changed, call pm_runtime_resume().
574 if (HCD_HW_ACCESSIBLE(hcd))
575 rc = controller_suspend(dev);
579 static int tegra_ehci_resume(struct device *dev)
583 rc = controller_resume(dev);
585 pm_runtime_disable(dev);
586 pm_runtime_set_active(dev);
587 pm_runtime_enable(dev);
592 static int tegra_ehci_runtime_suspend(struct device *dev)
594 return controller_suspend(dev);
597 static int tegra_ehci_runtime_resume(struct device *dev)
599 return controller_resume(dev);
602 static const struct dev_pm_ops tegra_ehci_pm_ops = {
603 .suspend = tegra_ehci_suspend,
604 .resume = tegra_ehci_resume,
605 .runtime_suspend = tegra_ehci_runtime_suspend,
606 .runtime_resume = tegra_ehci_runtime_resume,
611 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
612 #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
614 void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val)
617 struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
618 void __iomem *base = hcd->regs;
620 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
621 val &= ~TEGRA_USB_PORTSC1_PTS(3);
622 val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
623 writel(val, base + TEGRA_USB_PORTSC1);
625 EXPORT_SYMBOL_GPL(tegra_ehci_set_pts);
627 void tegra_ehci_set_phcd(struct usb_phy *x, bool enable)
630 struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
631 void __iomem *base = hcd->regs;
633 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
635 val |= TEGRA_USB_PORTSC1_PHCD;
637 val &= ~TEGRA_USB_PORTSC1_PHCD;
638 writel(val, base + TEGRA_USB_PORTSC1);
640 EXPORT_SYMBOL_GPL(tegra_ehci_set_phcd);
642 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
644 static int tegra_ehci_probe(struct platform_device *pdev)
646 struct resource *res;
648 struct tegra_ehci_hcd *tegra;
649 struct tegra_ehci_platform_data *pdata;
652 int instance = pdev->id;
653 struct usb_phy *u_phy;
655 pdata = pdev->dev.platform_data;
657 dev_err(&pdev->dev, "Platform data missing\n");
661 /* Right now device-tree probed devices don't get dma_mask set.
662 * Since shared usb code relies on it, set it here for now.
663 * Once we have dma capability bindings this can go away.
665 if (!pdev->dev.dma_mask)
666 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
668 setup_vbus_gpio(pdev, pdata);
670 tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
675 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
676 dev_name(&pdev->dev));
678 dev_err(&pdev->dev, "Unable to create HCD\n");
682 platform_set_drvdata(pdev, tegra);
684 tegra->clk = devm_clk_get(&pdev->dev, NULL);
685 if (IS_ERR(tegra->clk)) {
686 dev_err(&pdev->dev, "Can't get ehci clock\n");
687 err = PTR_ERR(tegra->clk);
691 err = clk_prepare_enable(tegra->clk);
695 tegra_periph_reset_assert(tegra->clk);
697 tegra_periph_reset_deassert(tegra->clk);
699 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
700 "nvidia,needs-double-reset");
702 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
704 dev_err(&pdev->dev, "Failed to get I/O memory\n");
708 hcd->rsrc_start = res->start;
709 hcd->rsrc_len = resource_size(res);
710 hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
712 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
717 /* This is pretty ugly and needs to be fixed when we do only
718 * device-tree probing. Old code relies on the platform_device
719 * numbering that we lack for device-tree-instantiated devices.
722 switch (res->start) {
726 case TEGRA_USB2_BASE:
729 case TEGRA_USB3_BASE:
734 dev_err(&pdev->dev, "unknown usb instance\n");
739 tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
741 TEGRA_USB_PHY_MODE_HOST);
742 if (IS_ERR(tegra->phy)) {
743 dev_err(&pdev->dev, "Failed to open USB phy\n");
748 hcd->phy = u_phy = &tegra->phy->u_phy;
749 usb_phy_init(hcd->phy);
751 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
754 dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
758 u_phy->otg->host = hcd_to_bus(hcd);
760 err = usb_phy_set_suspend(hcd->phy, 0);
762 dev_err(&pdev->dev, "Failed to power on the phy\n");
766 tegra->host_resumed = 1;
767 tegra->ehci = hcd_to_ehci(hcd);
769 irq = platform_get_irq(pdev, 0);
771 dev_err(&pdev->dev, "Failed to get IRQ\n");
776 #ifdef CONFIG_USB_OTG_UTILS
777 if (pdata->operating_mode == TEGRA_USB_OTG) {
779 devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
780 if (!IS_ERR_OR_NULL(tegra->transceiver))
781 otg_set_host(tegra->transceiver->otg, &hcd->self);
783 tegra->transceiver = ERR_PTR(-ENODEV);
787 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
789 dev_err(&pdev->dev, "Failed to add USB HCD\n");
793 pm_runtime_set_active(&pdev->dev);
794 pm_runtime_get_noresume(&pdev->dev);
796 /* Don't skip the pm_runtime_forbid call if wakeup isn't working */
797 /* if (!pdata->power_down_on_bus_suspend) */
798 pm_runtime_forbid(&pdev->dev);
799 pm_runtime_enable(&pdev->dev);
800 pm_runtime_put_sync(&pdev->dev);
804 #ifdef CONFIG_USB_OTG_UTILS
805 if (!IS_ERR_OR_NULL(tegra->transceiver))
806 otg_set_host(tegra->transceiver->otg, NULL);
809 usb_phy_shutdown(hcd->phy);
811 clk_disable_unprepare(tegra->clk);
817 static int tegra_ehci_remove(struct platform_device *pdev)
819 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
820 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
822 pm_runtime_get_sync(&pdev->dev);
823 pm_runtime_disable(&pdev->dev);
824 pm_runtime_put_noidle(&pdev->dev);
826 #ifdef CONFIG_USB_OTG_UTILS
827 if (!IS_ERR_OR_NULL(tegra->transceiver))
828 otg_set_host(tegra->transceiver->otg, NULL);
831 usb_phy_shutdown(hcd->phy);
835 clk_disable_unprepare(tegra->clk);
840 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
842 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
843 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
845 if (hcd->driver->shutdown)
846 hcd->driver->shutdown(hcd);
849 static struct of_device_id tegra_ehci_of_match[] = {
850 { .compatible = "nvidia,tegra20-ehci", },
854 static struct platform_driver tegra_ehci_driver = {
855 .probe = tegra_ehci_probe,
856 .remove = tegra_ehci_remove,
857 .shutdown = tegra_ehci_hcd_shutdown,
859 .name = "tegra-ehci",
860 .of_match_table = tegra_ehci_of_match,
862 .pm = &tegra_ehci_pm_ops,