2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
40 * periodic_next_shadow - return "next" pointer on shadow list
41 * @periodic: host pointer to qh/itd/sitd
42 * @tag: hardware tag for type of this record
44 static union ehci_shadow *
45 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 switch (hc32_to_cpu(ehci, tag)) {
50 return &periodic->qh->qh_next;
52 return &periodic->fstn->fstn_next;
54 return &periodic->itd->itd_next;
57 return &periodic->sitd->sitd_next;
62 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
65 switch (hc32_to_cpu(ehci, tag)) {
66 /* our ehci_shadow.qh is actually software part */
68 return &periodic->qh->hw->hw_next;
69 /* others are hw parts */
71 return periodic->hw_next;
75 /* caller must hold ehci->lock */
76 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
78 union ehci_shadow *prev_p = &ehci->pshadow[frame];
79 __hc32 *hw_p = &ehci->periodic[frame];
80 union ehci_shadow here = *prev_p;
82 /* find predecessor of "ptr"; hw and shadow lists are in sync */
83 while (here.ptr && here.ptr != ptr) {
84 prev_p = periodic_next_shadow(ehci, prev_p,
85 Q_NEXT_TYPE(ehci, *hw_p));
86 hw_p = shadow_next_periodic(ehci, &here,
87 Q_NEXT_TYPE(ehci, *hw_p));
90 /* an interrupt entry (at list end) could have been shared */
94 /* update shadow and hardware lists ... the old "next" pointers
95 * from ptr may still be in use, the caller updates them.
97 *prev_p = *periodic_next_shadow(ehci, &here,
98 Q_NEXT_TYPE(ehci, *hw_p));
100 if (!ehci->use_dummy_qh ||
101 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
102 != EHCI_LIST_END(ehci))
103 *hw_p = *shadow_next_periodic(ehci, &here,
104 Q_NEXT_TYPE(ehci, *hw_p));
106 *hw_p = ehci->dummy->qh_dma;
109 /* how many of the uframe's 125 usecs are allocated? */
110 static unsigned short
111 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
113 __hc32 *hw_p = &ehci->periodic [frame];
114 union ehci_shadow *q = &ehci->pshadow [frame];
116 struct ehci_qh_hw *hw;
119 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
122 /* is it in the S-mask? */
123 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
124 usecs += q->qh->usecs;
126 if (hw->hw_info2 & cpu_to_hc32(ehci,
128 usecs += q->qh->c_usecs;
134 /* for "save place" FSTNs, count the relevant INTR
135 * bandwidth from the previous frame
137 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
138 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
140 hw_p = &q->fstn->hw_next;
141 q = &q->fstn->fstn_next;
144 if (q->itd->hw_transaction[uframe])
145 usecs += q->itd->stream->usecs;
146 hw_p = &q->itd->hw_next;
147 q = &q->itd->itd_next;
150 /* is it in the S-mask? (count SPLIT, DATA) */
151 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
153 if (q->sitd->hw_fullspeed_ep &
154 cpu_to_hc32(ehci, 1<<31))
155 usecs += q->sitd->stream->usecs;
156 else /* worst case for OUT start-split */
157 usecs += HS_USECS_ISO (188);
160 /* ... C-mask? (count CSPLIT, DATA) */
161 if (q->sitd->hw_uframe &
162 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
163 /* worst case for IN complete-split */
164 usecs += q->sitd->stream->c_usecs;
167 hw_p = &q->sitd->hw_next;
168 q = &q->sitd->sitd_next;
173 if (usecs > ehci->uframe_periodic_max)
174 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
175 frame * 8 + uframe, usecs);
180 /*-------------------------------------------------------------------------*/
182 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
184 if (!dev1->tt || !dev2->tt)
186 if (dev1->tt != dev2->tt)
189 return dev1->ttport == dev2->ttport;
194 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
196 /* Which uframe does the low/fullspeed transfer start in?
198 * The parameter is the mask of ssplits in "H-frame" terms
199 * and this returns the transfer start uframe in "B-frame" terms,
200 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
201 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
202 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
204 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
206 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
208 ehci_err(ehci, "invalid empty smask!\n");
209 /* uframe 7 can't have bw so this will indicate failure */
212 return ffs(smask) - 1;
215 static const unsigned char
216 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
218 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
219 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
222 for (i=0; i<7; i++) {
223 if (max_tt_usecs[i] < tt_usecs[i]) {
224 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
225 tt_usecs[i] = max_tt_usecs[i];
230 /* How many of the tt's periodic downstream 1000 usecs are allocated?
232 * While this measures the bandwidth in terms of usecs/uframe,
233 * the low/fullspeed bus has no notion of uframes, so any particular
234 * low/fullspeed transfer can "carry over" from one uframe to the next,
235 * since the TT just performs downstream transfers in sequence.
237 * For example two separate 100 usec transfers can start in the same uframe,
238 * and the second one would "carry over" 75 usecs into the next uframe.
242 struct ehci_hcd *ehci,
243 struct usb_device *dev,
245 unsigned short tt_usecs[8]
248 __hc32 *hw_p = &ehci->periodic [frame];
249 union ehci_shadow *q = &ehci->pshadow [frame];
252 memset(tt_usecs, 0, 16);
255 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
257 hw_p = &q->itd->hw_next;
258 q = &q->itd->itd_next;
261 if (same_tt(dev, q->qh->dev)) {
262 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
263 tt_usecs[uf] += q->qh->tt_usecs;
265 hw_p = &q->qh->hw->hw_next;
269 if (same_tt(dev, q->sitd->urb->dev)) {
270 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
271 tt_usecs[uf] += q->sitd->stream->tt_usecs;
273 hw_p = &q->sitd->hw_next;
274 q = &q->sitd->sitd_next;
278 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
280 hw_p = &q->fstn->hw_next;
281 q = &q->fstn->fstn_next;
285 carryover_tt_bandwidth(tt_usecs);
287 if (max_tt_usecs[7] < tt_usecs[7])
288 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
289 frame, tt_usecs[7] - max_tt_usecs[7]);
293 * Return true if the device's tt's downstream bus is available for a
294 * periodic transfer of the specified length (usecs), starting at the
295 * specified frame/uframe. Note that (as summarized in section 11.19
296 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
299 * The uframe parameter is when the fullspeed/lowspeed transfer
300 * should be executed in "B-frame" terms, which is the same as the
301 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
302 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
303 * See the EHCI spec sec 4.5 and fig 4.7.
305 * This checks if the full/lowspeed bus, at the specified starting uframe,
306 * has the specified bandwidth available, according to rules listed
307 * in USB 2.0 spec section 11.18.1 fig 11-60.
309 * This does not check if the transfer would exceed the max ssplit
310 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
311 * since proper scheduling limits ssplits to less than 16 per uframe.
313 static int tt_available (
314 struct ehci_hcd *ehci,
316 struct usb_device *dev,
322 if ((period == 0) || (uframe >= 7)) /* error */
325 for (; frame < ehci->periodic_size; frame += period) {
326 unsigned short tt_usecs[8];
328 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
330 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
331 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
332 frame, usecs, uframe,
333 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
334 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
336 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
337 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
342 /* special case for isoc transfers larger than 125us:
343 * the first and each subsequent fully used uframe
344 * must be empty, so as to not illegally delay
345 * already scheduled transactions
348 int ufs = (usecs / 125);
350 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
351 if (0 < tt_usecs[i]) {
353 "multi-uframe xfer can't fit "
354 "in frame %d uframe %d\n",
360 tt_usecs[uframe] += usecs;
362 carryover_tt_bandwidth(tt_usecs);
364 /* fail if the carryover pushed bw past the last uframe's limit */
365 if (max_tt_usecs[7] < tt_usecs[7]) {
367 "tt unavailable usecs %d frame %d uframe %d\n",
368 usecs, frame, uframe);
378 /* return true iff the device's transaction translator is available
379 * for a periodic transfer starting at the specified frame, using
380 * all the uframes in the mask.
382 static int tt_no_collision (
383 struct ehci_hcd *ehci,
385 struct usb_device *dev,
390 if (period == 0) /* error */
393 /* note bandwidth wastage: split never follows csplit
394 * (different dev or endpoint) until the next uframe.
395 * calling convention doesn't make that distinction.
397 for (; frame < ehci->periodic_size; frame += period) {
398 union ehci_shadow here;
400 struct ehci_qh_hw *hw;
402 here = ehci->pshadow [frame];
403 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
405 switch (hc32_to_cpu(ehci, type)) {
407 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
408 here = here.itd->itd_next;
412 if (same_tt (dev, here.qh->dev)) {
415 mask = hc32_to_cpu(ehci,
417 /* "knows" no gap is needed */
422 type = Q_NEXT_TYPE(ehci, hw->hw_next);
423 here = here.qh->qh_next;
426 if (same_tt (dev, here.sitd->urb->dev)) {
429 mask = hc32_to_cpu(ehci, here.sitd
431 /* FIXME assumes no gap for IN! */
436 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
437 here = here.sitd->sitd_next;
442 "periodic frame %d bogus type %d\n",
446 /* collision or error */
455 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
457 /*-------------------------------------------------------------------------*/
459 static void enable_periodic(struct ehci_hcd *ehci)
461 if (ehci->periodic_count++)
464 /* Stop waiting to turn off the periodic schedule */
465 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC);
467 /* Don't start the schedule until PSS is 0 */
469 turn_on_io_watchdog(ehci);
472 static void disable_periodic(struct ehci_hcd *ehci)
474 if (--ehci->periodic_count)
477 /* Don't turn off the schedule until PSS is 1 */
481 /*-------------------------------------------------------------------------*/
483 /* periodic schedule slots have iso tds (normal or split) first, then a
484 * sparse tree for active interrupt transfers.
486 * this just links in a qh; caller guarantees uframe masks are set right.
487 * no FSTN support (yet; ehci 0.96+)
489 static void qh_link_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
492 unsigned period = qh->period;
494 dev_dbg (&qh->dev->dev,
495 "link qh%d-%04x/%p start %d [%d/%d us]\n",
496 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
497 & (QH_CMASK | QH_SMASK),
498 qh, qh->start, qh->usecs, qh->c_usecs);
500 /* high bandwidth, or otherwise every microframe */
504 for (i = qh->start; i < ehci->periodic_size; i += period) {
505 union ehci_shadow *prev = &ehci->pshadow[i];
506 __hc32 *hw_p = &ehci->periodic[i];
507 union ehci_shadow here = *prev;
510 /* skip the iso nodes at list head */
512 type = Q_NEXT_TYPE(ehci, *hw_p);
513 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
515 prev = periodic_next_shadow(ehci, prev, type);
516 hw_p = shadow_next_periodic(ehci, &here, type);
520 /* sorting each branch by period (slow-->fast)
521 * enables sharing interior tree nodes
523 while (here.ptr && qh != here.qh) {
524 if (qh->period > here.qh->period)
526 prev = &here.qh->qh_next;
527 hw_p = &here.qh->hw->hw_next;
530 /* link in this qh, unless some earlier pass did that */
534 qh->hw->hw_next = *hw_p;
537 *hw_p = QH_NEXT (ehci, qh->qh_dma);
540 qh->qh_state = QH_STATE_LINKED;
544 /* update per-qh bandwidth for usbfs */
545 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
546 ? ((qh->usecs + qh->c_usecs) / qh->period)
549 list_add(&qh->intr_node, &ehci->intr_qh_list);
551 /* maybe enable periodic schedule processing */
553 enable_periodic(ehci);
556 static void qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
562 * If qh is for a low/full-speed device, simply unlinking it
563 * could interfere with an ongoing split transaction. To unlink
564 * it safely would require setting the QH_INACTIVATE bit and
565 * waiting at least one frame, as described in EHCI 4.12.2.5.
567 * We won't bother with any of this. Instead, we assume that the
568 * only reason for unlinking an interrupt QH while the current URB
569 * is still active is to dequeue all the URBs (flush the whole
572 * If rebalancing the periodic schedule is ever implemented, this
573 * approach will no longer be valid.
576 /* high bandwidth, or otherwise part of every microframe */
577 if ((period = qh->period) == 0)
580 for (i = qh->start; i < ehci->periodic_size; i += period)
581 periodic_unlink (ehci, i, qh);
583 /* update per-qh bandwidth for usbfs */
584 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
585 ? ((qh->usecs + qh->c_usecs) / qh->period)
588 dev_dbg (&qh->dev->dev,
589 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
591 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
592 qh, qh->start, qh->usecs, qh->c_usecs);
594 /* qh->qh_next still "live" to HC */
595 qh->qh_state = QH_STATE_UNLINK;
596 qh->qh_next.ptr = NULL;
598 if (ehci->qh_scan_next == qh)
599 ehci->qh_scan_next = list_entry(qh->intr_node.next,
600 struct ehci_qh, intr_node);
601 list_del(&qh->intr_node);
604 static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
606 /* If the QH isn't linked then there's nothing we can do. */
607 if (qh->qh_state != QH_STATE_LINKED)
610 qh_unlink_periodic (ehci, qh);
612 /* Make sure the unlinks are visible before starting the timer */
616 * The EHCI spec doesn't say how long it takes the controller to
617 * stop accessing an unlinked interrupt QH. The timer delay is
618 * 9 uframes; presumably that will be long enough.
620 qh->unlink_cycle = ehci->intr_unlink_cycle;
622 /* New entries go at the end of the intr_unlink list */
623 list_add_tail(&qh->unlink_node, &ehci->intr_unlink);
625 if (ehci->intr_unlinking)
626 ; /* Avoid recursive calls */
627 else if (ehci->rh_state < EHCI_RH_RUNNING)
628 ehci_handle_intr_unlinks(ehci);
629 else if (ehci->intr_unlink.next == &qh->unlink_node) {
630 ehci_enable_event(ehci, EHCI_HRTIMER_UNLINK_INTR, true);
631 ++ehci->intr_unlink_cycle;
635 static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
637 struct ehci_qh_hw *hw = qh->hw;
640 qh->qh_state = QH_STATE_IDLE;
641 hw->hw_next = EHCI_LIST_END(ehci);
643 if (!list_empty(&qh->qtd_list))
644 qh_completions(ehci, qh);
646 /* reschedule QH iff another request is queued */
647 if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) {
648 rc = qh_schedule(ehci, qh);
650 /* An error here likely indicates handshake failure
651 * or no space left in the schedule. Neither fault
652 * should happen often ...
654 * FIXME kill the now-dysfunctional queued urbs
657 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
661 /* maybe turn off periodic schedule */
663 disable_periodic(ehci);
666 /*-------------------------------------------------------------------------*/
668 static int check_period (
669 struct ehci_hcd *ehci,
677 /* complete split running into next frame?
678 * given FSTN support, we could sometimes check...
683 /* convert "usecs we need" to "max already claimed" */
684 usecs = ehci->uframe_periodic_max - usecs;
686 /* we "know" 2 and 4 uframe intervals were rejected; so
687 * for period 0, check _every_ microframe in the schedule.
689 if (unlikely (period == 0)) {
691 for (uframe = 0; uframe < 7; uframe++) {
692 claimed = periodic_usecs (ehci, frame, uframe);
696 } while ((frame += 1) < ehci->periodic_size);
698 /* just check the specified uframe, at that period */
701 claimed = periodic_usecs (ehci, frame, uframe);
704 } while ((frame += period) < ehci->periodic_size);
711 static int check_intr_schedule (
712 struct ehci_hcd *ehci,
715 const struct ehci_qh *qh,
719 int retval = -ENOSPC;
722 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
725 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
733 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
734 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
738 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
739 for (i=uframe+1; i<8 && i<uframe+4; i++)
740 if (!check_period (ehci, frame, i,
741 qh->period, qh->c_usecs))
748 *c_maskp = cpu_to_hc32(ehci, mask << 8);
751 /* Make sure this tt's buffer is also available for CSPLITs.
752 * We pessimize a bit; probably the typical full speed case
753 * doesn't need the second CSPLIT.
755 * NOTE: both SPLIT and CSPLIT could be checked in just
758 mask = 0x03 << (uframe + qh->gap_uf);
759 *c_maskp = cpu_to_hc32(ehci, mask << 8);
762 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
763 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
764 qh->period, qh->c_usecs))
766 if (!check_period (ehci, frame, uframe + qh->gap_uf,
767 qh->period, qh->c_usecs))
776 /* "first fit" scheduling policy used the first time through,
777 * or when the previous schedule slot can't be re-used.
779 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
784 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
785 struct ehci_qh_hw *hw = qh->hw;
787 hw->hw_next = EHCI_LIST_END(ehci);
790 /* reuse the previous schedule slots, if we can */
791 if (frame < qh->period) {
792 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
793 status = check_intr_schedule (ehci, frame, --uframe,
801 /* else scan the schedule to find a group of slots such that all
802 * uframes have enough periodic bandwidth available.
805 /* "normal" case, uframing flexible except with splits */
809 for (i = qh->period; status && i > 0; --i) {
810 frame = ++ehci->random_frame % qh->period;
811 for (uframe = 0; uframe < 8; uframe++) {
812 status = check_intr_schedule (ehci,
820 /* qh->period == 0 means every uframe */
823 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
829 /* reset S-frame and (maybe) C-frame masks */
830 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
831 hw->hw_info2 |= qh->period
832 ? cpu_to_hc32(ehci, 1 << uframe)
833 : cpu_to_hc32(ehci, QH_SMASK);
834 hw->hw_info2 |= c_mask;
836 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
842 static int intr_submit (
843 struct ehci_hcd *ehci,
845 struct list_head *qtd_list,
852 struct list_head empty;
854 /* get endpoint and transfer/schedule data */
855 epnum = urb->ep->desc.bEndpointAddress;
857 spin_lock_irqsave (&ehci->lock, flags);
859 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
861 goto done_not_linked;
863 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
864 if (unlikely(status))
865 goto done_not_linked;
867 /* get qh and force any scheduling errors */
868 INIT_LIST_HEAD (&empty);
869 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
874 if (qh->qh_state == QH_STATE_IDLE) {
875 if ((status = qh_schedule (ehci, qh)) != 0)
879 /* then queue the urb's tds to the qh */
880 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
883 /* stuff into the periodic schedule */
884 if (qh->qh_state == QH_STATE_IDLE) {
885 qh_refresh(ehci, qh);
886 qh_link_periodic(ehci, qh);
889 /* ... update usbfs periodic stats */
890 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
893 if (unlikely(status))
894 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
896 spin_unlock_irqrestore (&ehci->lock, flags);
898 qtd_list_free (ehci, urb, qtd_list);
903 static void scan_intr(struct ehci_hcd *ehci)
907 list_for_each_entry_safe(qh, ehci->qh_scan_next, &ehci->intr_qh_list,
910 /* clean any finished work for this qh */
911 if (!list_empty(&qh->qtd_list)) {
915 * Unlinks could happen here; completion reporting
916 * drops the lock. That's why ehci->qh_scan_next
917 * always holds the next qh to scan; if the next qh
918 * gets unlinked then ehci->qh_scan_next is adjusted
919 * in qh_unlink_periodic().
921 temp = qh_completions(ehci, qh);
922 if (unlikely(temp || (list_empty(&qh->qtd_list) &&
923 qh->qh_state == QH_STATE_LINKED)))
924 start_unlink_intr(ehci, qh);
929 /*-------------------------------------------------------------------------*/
931 /* ehci_iso_stream ops work with both ITD and SITD */
933 static struct ehci_iso_stream *
934 iso_stream_alloc (gfp_t mem_flags)
936 struct ehci_iso_stream *stream;
938 stream = kzalloc(sizeof *stream, mem_flags);
939 if (likely (stream != NULL)) {
940 INIT_LIST_HEAD(&stream->td_list);
941 INIT_LIST_HEAD(&stream->free_list);
942 stream->next_uframe = -1;
949 struct ehci_hcd *ehci,
950 struct ehci_iso_stream *stream,
951 struct usb_device *dev,
956 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
959 unsigned epnum, maxp;
964 * this might be a "high bandwidth" highspeed endpoint,
965 * as encoded in the ep descriptor's wMaxPacket field
967 epnum = usb_pipeendpoint (pipe);
968 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
969 maxp = usb_maxpacket(dev, pipe, !is_input);
976 /* knows about ITD vs SITD */
977 if (dev->speed == USB_SPEED_HIGH) {
978 unsigned multi = hb_mult(maxp);
980 stream->highspeed = 1;
982 maxp = max_packet(maxp);
986 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
987 stream->buf1 = cpu_to_hc32(ehci, buf1);
988 stream->buf2 = cpu_to_hc32(ehci, multi);
990 /* usbfs wants to report the average usecs per frame tied up
991 * when transfers on this endpoint are scheduled ...
993 stream->usecs = HS_USECS_ISO (maxp);
994 bandwidth = stream->usecs * 8;
995 bandwidth /= interval;
1002 addr = dev->ttport << 24;
1003 if (!ehci_is_TDI(ehci)
1005 ehci_to_hcd(ehci)->self.root_hub))
1006 addr |= dev->tt->hub->devnum << 16;
1008 addr |= dev->devnum;
1009 stream->usecs = HS_USECS_ISO (maxp);
1010 think_time = dev->tt ? dev->tt->think_time : 0;
1011 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1012 dev->speed, is_input, 1, maxp));
1013 hs_transfers = max (1u, (maxp + 187) / 188);
1018 stream->c_usecs = stream->usecs;
1019 stream->usecs = HS_USECS_ISO (1);
1020 stream->raw_mask = 1;
1022 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1023 tmp = (1 << (hs_transfers + 2)) - 1;
1024 stream->raw_mask |= tmp << (8 + 2);
1026 stream->raw_mask = smask_out [hs_transfers - 1];
1027 bandwidth = stream->usecs + stream->c_usecs;
1028 bandwidth /= interval << 3;
1030 /* stream->splits gets created from raw_mask later */
1031 stream->address = cpu_to_hc32(ehci, addr);
1033 stream->bandwidth = bandwidth;
1037 stream->bEndpointAddress = is_input | epnum;
1038 stream->interval = interval;
1039 stream->maxp = maxp;
1042 static struct ehci_iso_stream *
1043 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1046 struct ehci_iso_stream *stream;
1047 struct usb_host_endpoint *ep;
1048 unsigned long flags;
1050 epnum = usb_pipeendpoint (urb->pipe);
1051 if (usb_pipein(urb->pipe))
1052 ep = urb->dev->ep_in[epnum];
1054 ep = urb->dev->ep_out[epnum];
1056 spin_lock_irqsave (&ehci->lock, flags);
1057 stream = ep->hcpriv;
1059 if (unlikely (stream == NULL)) {
1060 stream = iso_stream_alloc(GFP_ATOMIC);
1061 if (likely (stream != NULL)) {
1062 ep->hcpriv = stream;
1064 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1068 /* if dev->ep [epnum] is a QH, hw is set */
1069 } else if (unlikely (stream->hw != NULL)) {
1070 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1071 urb->dev->devpath, epnum,
1072 usb_pipein(urb->pipe) ? "in" : "out");
1076 spin_unlock_irqrestore (&ehci->lock, flags);
1080 /*-------------------------------------------------------------------------*/
1082 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1084 static struct ehci_iso_sched *
1085 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1087 struct ehci_iso_sched *iso_sched;
1088 int size = sizeof *iso_sched;
1090 size += packets * sizeof (struct ehci_iso_packet);
1091 iso_sched = kzalloc(size, mem_flags);
1092 if (likely (iso_sched != NULL)) {
1093 INIT_LIST_HEAD (&iso_sched->td_list);
1100 struct ehci_hcd *ehci,
1101 struct ehci_iso_sched *iso_sched,
1102 struct ehci_iso_stream *stream,
1107 dma_addr_t dma = urb->transfer_dma;
1109 /* how many uframes are needed for these transfers */
1110 iso_sched->span = urb->number_of_packets * stream->interval;
1112 /* figure out per-uframe itd fields that we'll need later
1113 * when we fit new itds into the schedule.
1115 for (i = 0; i < urb->number_of_packets; i++) {
1116 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1121 length = urb->iso_frame_desc [i].length;
1122 buf = dma + urb->iso_frame_desc [i].offset;
1124 trans = EHCI_ISOC_ACTIVE;
1125 trans |= buf & 0x0fff;
1126 if (unlikely (((i + 1) == urb->number_of_packets))
1127 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1128 trans |= EHCI_ITD_IOC;
1129 trans |= length << 16;
1130 uframe->transaction = cpu_to_hc32(ehci, trans);
1132 /* might need to cross a buffer page within a uframe */
1133 uframe->bufp = (buf & ~(u64)0x0fff);
1135 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1142 struct ehci_iso_stream *stream,
1143 struct ehci_iso_sched *iso_sched
1148 // caller must hold ehci->lock!
1149 list_splice (&iso_sched->td_list, &stream->free_list);
1154 itd_urb_transaction (
1155 struct ehci_iso_stream *stream,
1156 struct ehci_hcd *ehci,
1161 struct ehci_itd *itd;
1165 struct ehci_iso_sched *sched;
1166 unsigned long flags;
1168 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1169 if (unlikely (sched == NULL))
1172 itd_sched_init(ehci, sched, stream, urb);
1174 if (urb->interval < 8)
1175 num_itds = 1 + (sched->span + 7) / 8;
1177 num_itds = urb->number_of_packets;
1179 /* allocate/init ITDs */
1180 spin_lock_irqsave (&ehci->lock, flags);
1181 for (i = 0; i < num_itds; i++) {
1184 * Use iTDs from the free list, but not iTDs that may
1185 * still be in use by the hardware.
1187 if (likely(!list_empty(&stream->free_list))) {
1188 itd = list_first_entry(&stream->free_list,
1189 struct ehci_itd, itd_list);
1190 if (itd->frame == ehci->now_frame)
1192 list_del (&itd->itd_list);
1193 itd_dma = itd->itd_dma;
1196 spin_unlock_irqrestore (&ehci->lock, flags);
1197 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1199 spin_lock_irqsave (&ehci->lock, flags);
1201 iso_sched_free(stream, sched);
1202 spin_unlock_irqrestore(&ehci->lock, flags);
1207 memset (itd, 0, sizeof *itd);
1208 itd->itd_dma = itd_dma;
1209 itd->frame = 9999; /* an invalid value */
1210 list_add (&itd->itd_list, &sched->td_list);
1212 spin_unlock_irqrestore (&ehci->lock, flags);
1214 /* temporarily store schedule info in hcpriv */
1215 urb->hcpriv = sched;
1216 urb->error_count = 0;
1220 /*-------------------------------------------------------------------------*/
1224 struct ehci_hcd *ehci,
1233 /* can't commit more than uframe_periodic_max usec */
1234 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1235 > (ehci->uframe_periodic_max - usecs))
1238 /* we know urb->interval is 2^N uframes */
1240 } while (uframe < mod);
1246 struct ehci_hcd *ehci,
1248 struct ehci_iso_stream *stream,
1250 struct ehci_iso_sched *sched,
1257 mask = stream->raw_mask << (uframe & 7);
1259 /* for IN, don't wrap CSPLIT into the next frame */
1263 /* check bandwidth */
1264 uframe %= period_uframes;
1265 frame = uframe >> 3;
1267 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1268 /* The tt's fullspeed bus bandwidth must be available.
1269 * tt_available scheduling guarantees 10+% for control/bulk.
1272 if (!tt_available(ehci, period_uframes >> 3,
1273 stream->udev, frame, uf, stream->tt_usecs))
1276 /* tt must be idle for start(s), any gap, and csplit.
1277 * assume scheduling slop leaves 10+% for control/bulk.
1279 if (!tt_no_collision(ehci, period_uframes >> 3,
1280 stream->udev, frame, mask))
1284 /* this multi-pass logic is simple, but performance may
1285 * suffer when the schedule data isn't cached.
1290 frame = uframe >> 3;
1293 /* check starts (OUT uses more than one) */
1294 max_used = ehci->uframe_periodic_max - stream->usecs;
1295 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1296 if (periodic_usecs (ehci, frame, uf) > max_used)
1300 /* for IN, check CSPLIT */
1301 if (stream->c_usecs) {
1303 max_used = ehci->uframe_periodic_max - stream->c_usecs;
1307 if ((stream->raw_mask & tmp) == 0)
1309 if (periodic_usecs (ehci, frame, uf)
1315 /* we know urb->interval is 2^N uframes */
1316 uframe += period_uframes;
1317 } while (uframe < mod);
1319 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1324 * This scheduler plans almost as far into the future as it has actual
1325 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1326 * "as small as possible" to be cache-friendlier.) That limits the size
1327 * transfers you can stream reliably; avoid more than 64 msec per urb.
1328 * Also avoid queue depths of less than ehci's worst irq latency (affected
1329 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1330 * and other factors); or more than about 230 msec total (for portability,
1331 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1334 #define SCHEDULING_DELAY 40 /* microframes */
1337 iso_stream_schedule (
1338 struct ehci_hcd *ehci,
1340 struct ehci_iso_stream *stream
1343 u32 now, base, next, start, period, span;
1345 unsigned mod = ehci->periodic_size << 3;
1346 struct ehci_iso_sched *sched = urb->hcpriv;
1348 period = urb->interval;
1350 if (!stream->highspeed) {
1355 now = ehci_read_frame_index(ehci) & (mod - 1);
1357 /* Typical case: reuse current schedule, stream is still active.
1358 * Hopefully there are no gaps from the host falling behind
1359 * (irq delays etc). If there are, the behavior depends on
1360 * whether URB_ISO_ASAP is set.
1362 if (likely (!list_empty (&stream->td_list))) {
1364 /* Take the isochronous scheduling threshold into account */
1366 next = now + ehci->i_thresh; /* uframe cache */
1368 next = (now + 2 + 7) & ~0x07; /* full frame cache */
1371 * Use ehci->last_iso_frame as the base. There can't be any
1372 * TDs scheduled for earlier than that.
1374 base = ehci->last_iso_frame << 3;
1375 next = (next - base) & (mod - 1);
1376 start = (stream->next_uframe - base) & (mod - 1);
1378 /* Is the schedule already full? */
1379 if (unlikely(start < period)) {
1380 ehci_dbg(ehci, "iso sched full %p (%u-%u < %u mod %u)\n",
1381 urb, stream->next_uframe, base,
1387 /* Behind the scheduling threshold? */
1388 if (unlikely(start < next)) {
1390 /* USB_ISO_ASAP: Round up to the first available slot */
1391 if (urb->transfer_flags & URB_ISO_ASAP)
1392 start += (next - start + period - 1) & -period;
1395 * Not ASAP: Use the next slot in the stream. If
1396 * the entire URB falls before the threshold, fail.
1398 else if (start + span - period < next) {
1399 ehci_dbg(ehci, "iso urb late %p (%u+%u < %u)\n",
1401 span - period, next + base);
1410 /* need to schedule; when's the next (u)frame we could start?
1411 * this is bigger than ehci->i_thresh allows; scheduling itself
1412 * isn't free, the delay should handle reasonably slow cpus. it
1413 * can also help high bandwidth if the dma and irq loads don't
1414 * jump until after the queue is primed.
1420 start = base + SCHEDULING_DELAY;
1422 /* find a uframe slot with enough bandwidth.
1423 * Early uframes are more precious because full-speed
1424 * iso IN transfers can't use late uframes,
1425 * and therefore they should be allocated last.
1431 /* check schedule: enough space? */
1432 if (stream->highspeed) {
1433 if (itd_slot_ok(ehci, mod, start,
1434 stream->usecs, period))
1437 if ((start % 8) >= 6)
1439 if (sitd_slot_ok(ehci, mod, stream,
1440 start, sched, period))
1443 } while (start > next && !done);
1445 /* no room in the schedule */
1447 ehci_dbg(ehci, "iso sched full %p", urb);
1453 /* Tried to schedule too far into the future? */
1454 if (unlikely(start - base + span - period >= mod)) {
1455 ehci_dbg(ehci, "request %p would overflow (%u+%u >= %u)\n",
1456 urb, start - base, span - period, mod);
1461 stream->next_uframe = start & (mod - 1);
1463 /* report high speed start in uframes; full speed, in frames */
1464 urb->start_frame = stream->next_uframe;
1465 if (!stream->highspeed)
1466 urb->start_frame >>= 3;
1468 /* Make sure scan_isoc() sees these */
1469 if (ehci->isoc_count == 0)
1470 ehci->last_iso_frame = now >> 3;
1474 iso_sched_free(stream, sched);
1479 /*-------------------------------------------------------------------------*/
1482 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1483 struct ehci_itd *itd)
1487 /* it's been recently zeroed */
1488 itd->hw_next = EHCI_LIST_END(ehci);
1489 itd->hw_bufp [0] = stream->buf0;
1490 itd->hw_bufp [1] = stream->buf1;
1491 itd->hw_bufp [2] = stream->buf2;
1493 for (i = 0; i < 8; i++)
1496 /* All other fields are filled when scheduling */
1501 struct ehci_hcd *ehci,
1502 struct ehci_itd *itd,
1503 struct ehci_iso_sched *iso_sched,
1508 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1509 unsigned pg = itd->pg;
1511 // BUG_ON (pg == 6 && uf->cross);
1514 itd->index [uframe] = index;
1516 itd->hw_transaction[uframe] = uf->transaction;
1517 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1518 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1519 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1521 /* iso_frame_desc[].offset must be strictly increasing */
1522 if (unlikely (uf->cross)) {
1523 u64 bufp = uf->bufp + 4096;
1526 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1527 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1532 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1534 union ehci_shadow *prev = &ehci->pshadow[frame];
1535 __hc32 *hw_p = &ehci->periodic[frame];
1536 union ehci_shadow here = *prev;
1539 /* skip any iso nodes which might belong to previous microframes */
1541 type = Q_NEXT_TYPE(ehci, *hw_p);
1542 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1544 prev = periodic_next_shadow(ehci, prev, type);
1545 hw_p = shadow_next_periodic(ehci, &here, type);
1549 itd->itd_next = here;
1550 itd->hw_next = *hw_p;
1554 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1557 /* fit urb's itds into the selected schedule slot; activate as needed */
1558 static void itd_link_urb(
1559 struct ehci_hcd *ehci,
1562 struct ehci_iso_stream *stream
1566 unsigned next_uframe, uframe, frame;
1567 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1568 struct ehci_itd *itd;
1570 next_uframe = stream->next_uframe & (mod - 1);
1572 if (unlikely (list_empty(&stream->td_list))) {
1573 ehci_to_hcd(ehci)->self.bandwidth_allocated
1574 += stream->bandwidth;
1576 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1577 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1578 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1580 next_uframe >> 3, next_uframe & 0x7);
1583 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1584 if (ehci->amd_pll_fix == 1)
1585 usb_amd_quirk_pll_disable();
1588 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1590 /* fill iTDs uframe by uframe */
1591 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1593 /* ASSERT: we have all necessary itds */
1594 // BUG_ON (list_empty (&iso_sched->td_list));
1596 /* ASSERT: no itds for this endpoint in this uframe */
1598 itd = list_entry (iso_sched->td_list.next,
1599 struct ehci_itd, itd_list);
1600 list_move_tail (&itd->itd_list, &stream->td_list);
1601 itd->stream = stream;
1603 itd_init (ehci, stream, itd);
1606 uframe = next_uframe & 0x07;
1607 frame = next_uframe >> 3;
1609 itd_patch(ehci, itd, iso_sched, packet, uframe);
1611 next_uframe += stream->interval;
1612 next_uframe &= mod - 1;
1615 /* link completed itds into the schedule */
1616 if (((next_uframe >> 3) != frame)
1617 || packet == urb->number_of_packets) {
1618 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1622 stream->next_uframe = next_uframe;
1624 /* don't need that schedule data any more */
1625 iso_sched_free (stream, iso_sched);
1626 urb->hcpriv = stream;
1629 enable_periodic(ehci);
1632 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1634 /* Process and recycle a completed ITD. Return true iff its urb completed,
1635 * and hence its completion callback probably added things to the hardware
1638 * Note that we carefully avoid recycling this descriptor until after any
1639 * completion callback runs, so that it won't be reused quickly. That is,
1640 * assuming (a) no more than two urbs per frame on this endpoint, and also
1641 * (b) only this endpoint's completions submit URBs. It seems some silicon
1642 * corrupts things if you reuse completed descriptors very quickly...
1644 static bool itd_complete(struct ehci_hcd *ehci, struct ehci_itd *itd)
1646 struct urb *urb = itd->urb;
1647 struct usb_iso_packet_descriptor *desc;
1651 struct ehci_iso_stream *stream = itd->stream;
1652 struct usb_device *dev;
1653 bool retval = false;
1655 /* for each uframe with a packet */
1656 for (uframe = 0; uframe < 8; uframe++) {
1657 if (likely (itd->index[uframe] == -1))
1659 urb_index = itd->index[uframe];
1660 desc = &urb->iso_frame_desc [urb_index];
1662 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1663 itd->hw_transaction [uframe] = 0;
1665 /* report transfer status */
1666 if (unlikely (t & ISO_ERRS)) {
1668 if (t & EHCI_ISOC_BUF_ERR)
1669 desc->status = usb_pipein (urb->pipe)
1670 ? -ENOSR /* hc couldn't read */
1671 : -ECOMM; /* hc couldn't write */
1672 else if (t & EHCI_ISOC_BABBLE)
1673 desc->status = -EOVERFLOW;
1674 else /* (t & EHCI_ISOC_XACTERR) */
1675 desc->status = -EPROTO;
1677 /* HC need not update length with this error */
1678 if (!(t & EHCI_ISOC_BABBLE)) {
1679 desc->actual_length = EHCI_ITD_LENGTH(t);
1680 urb->actual_length += desc->actual_length;
1682 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1684 desc->actual_length = EHCI_ITD_LENGTH(t);
1685 urb->actual_length += desc->actual_length;
1687 /* URB was too late */
1692 /* handle completion now? */
1693 if (likely ((urb_index + 1) != urb->number_of_packets))
1696 /* ASSERT: it's really the last itd for this urb
1697 list_for_each_entry (itd, &stream->td_list, itd_list)
1698 BUG_ON (itd->urb == urb);
1701 /* give urb back to the driver; completion often (re)submits */
1703 ehci_urb_done(ehci, urb, 0);
1708 disable_periodic(ehci);
1710 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1711 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1712 if (ehci->amd_pll_fix == 1)
1713 usb_amd_quirk_pll_enable();
1716 if (unlikely(list_is_singular(&stream->td_list))) {
1717 ehci_to_hcd(ehci)->self.bandwidth_allocated
1718 -= stream->bandwidth;
1720 "deschedule devp %s ep%d%s-iso\n",
1721 dev->devpath, stream->bEndpointAddress & 0x0f,
1722 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1728 /* Add to the end of the free list for later reuse */
1729 list_move_tail(&itd->itd_list, &stream->free_list);
1731 /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
1732 if (list_empty(&stream->td_list)) {
1733 list_splice_tail_init(&stream->free_list,
1734 &ehci->cached_itd_list);
1735 start_free_itds(ehci);
1741 /*-------------------------------------------------------------------------*/
1743 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1746 int status = -EINVAL;
1747 unsigned long flags;
1748 struct ehci_iso_stream *stream;
1750 /* Get iso_stream head */
1751 stream = iso_stream_find (ehci, urb);
1752 if (unlikely (stream == NULL)) {
1753 ehci_dbg (ehci, "can't get iso stream\n");
1756 if (unlikely (urb->interval != stream->interval)) {
1757 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1758 stream->interval, urb->interval);
1762 #ifdef EHCI_URB_TRACE
1764 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1765 __func__, urb->dev->devpath, urb,
1766 usb_pipeendpoint (urb->pipe),
1767 usb_pipein (urb->pipe) ? "in" : "out",
1768 urb->transfer_buffer_length,
1769 urb->number_of_packets, urb->interval,
1773 /* allocate ITDs w/o locking anything */
1774 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1775 if (unlikely (status < 0)) {
1776 ehci_dbg (ehci, "can't init itds\n");
1780 /* schedule ... need to lock */
1781 spin_lock_irqsave (&ehci->lock, flags);
1782 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1783 status = -ESHUTDOWN;
1784 goto done_not_linked;
1786 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1787 if (unlikely(status))
1788 goto done_not_linked;
1789 status = iso_stream_schedule(ehci, urb, stream);
1790 if (likely (status == 0))
1791 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1793 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1795 spin_unlock_irqrestore (&ehci->lock, flags);
1800 /*-------------------------------------------------------------------------*/
1803 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1804 * TTs in USB 2.0 hubs. These need microframe scheduling.
1809 struct ehci_hcd *ehci,
1810 struct ehci_iso_sched *iso_sched,
1811 struct ehci_iso_stream *stream,
1816 dma_addr_t dma = urb->transfer_dma;
1818 /* how many frames are needed for these transfers */
1819 iso_sched->span = urb->number_of_packets * stream->interval;
1821 /* figure out per-frame sitd fields that we'll need later
1822 * when we fit new sitds into the schedule.
1824 for (i = 0; i < urb->number_of_packets; i++) {
1825 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1830 length = urb->iso_frame_desc [i].length & 0x03ff;
1831 buf = dma + urb->iso_frame_desc [i].offset;
1833 trans = SITD_STS_ACTIVE;
1834 if (((i + 1) == urb->number_of_packets)
1835 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1837 trans |= length << 16;
1838 packet->transaction = cpu_to_hc32(ehci, trans);
1840 /* might need to cross a buffer page within a td */
1842 packet->buf1 = (buf + length) & ~0x0fff;
1843 if (packet->buf1 != (buf & ~(u64)0x0fff))
1846 /* OUT uses multiple start-splits */
1847 if (stream->bEndpointAddress & USB_DIR_IN)
1849 length = (length + 187) / 188;
1850 if (length > 1) /* BEGIN vs ALL */
1852 packet->buf1 |= length;
1857 sitd_urb_transaction (
1858 struct ehci_iso_stream *stream,
1859 struct ehci_hcd *ehci,
1864 struct ehci_sitd *sitd;
1865 dma_addr_t sitd_dma;
1867 struct ehci_iso_sched *iso_sched;
1868 unsigned long flags;
1870 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1871 if (iso_sched == NULL)
1874 sitd_sched_init(ehci, iso_sched, stream, urb);
1876 /* allocate/init sITDs */
1877 spin_lock_irqsave (&ehci->lock, flags);
1878 for (i = 0; i < urb->number_of_packets; i++) {
1880 /* NOTE: for now, we don't try to handle wraparound cases
1881 * for IN (using sitd->hw_backpointer, like a FSTN), which
1882 * means we never need two sitds for full speed packets.
1886 * Use siTDs from the free list, but not siTDs that may
1887 * still be in use by the hardware.
1889 if (likely(!list_empty(&stream->free_list))) {
1890 sitd = list_first_entry(&stream->free_list,
1891 struct ehci_sitd, sitd_list);
1892 if (sitd->frame == ehci->now_frame)
1894 list_del (&sitd->sitd_list);
1895 sitd_dma = sitd->sitd_dma;
1898 spin_unlock_irqrestore (&ehci->lock, flags);
1899 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1901 spin_lock_irqsave (&ehci->lock, flags);
1903 iso_sched_free(stream, iso_sched);
1904 spin_unlock_irqrestore(&ehci->lock, flags);
1909 memset (sitd, 0, sizeof *sitd);
1910 sitd->sitd_dma = sitd_dma;
1911 sitd->frame = 9999; /* an invalid value */
1912 list_add (&sitd->sitd_list, &iso_sched->td_list);
1915 /* temporarily store schedule info in hcpriv */
1916 urb->hcpriv = iso_sched;
1917 urb->error_count = 0;
1919 spin_unlock_irqrestore (&ehci->lock, flags);
1923 /*-------------------------------------------------------------------------*/
1927 struct ehci_hcd *ehci,
1928 struct ehci_iso_stream *stream,
1929 struct ehci_sitd *sitd,
1930 struct ehci_iso_sched *iso_sched,
1934 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1935 u64 bufp = uf->bufp;
1937 sitd->hw_next = EHCI_LIST_END(ehci);
1938 sitd->hw_fullspeed_ep = stream->address;
1939 sitd->hw_uframe = stream->splits;
1940 sitd->hw_results = uf->transaction;
1941 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1944 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1945 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1947 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1950 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1951 sitd->index = index;
1955 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1957 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1958 sitd->sitd_next = ehci->pshadow [frame];
1959 sitd->hw_next = ehci->periodic [frame];
1960 ehci->pshadow [frame].sitd = sitd;
1961 sitd->frame = frame;
1963 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1966 /* fit urb's sitds into the selected schedule slot; activate as needed */
1967 static void sitd_link_urb(
1968 struct ehci_hcd *ehci,
1971 struct ehci_iso_stream *stream
1975 unsigned next_uframe;
1976 struct ehci_iso_sched *sched = urb->hcpriv;
1977 struct ehci_sitd *sitd;
1979 next_uframe = stream->next_uframe;
1981 if (list_empty(&stream->td_list)) {
1982 /* usbfs ignores TT bandwidth */
1983 ehci_to_hcd(ehci)->self.bandwidth_allocated
1984 += stream->bandwidth;
1986 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1987 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1988 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1989 (next_uframe >> 3) & (ehci->periodic_size - 1),
1990 stream->interval, hc32_to_cpu(ehci, stream->splits));
1993 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1994 if (ehci->amd_pll_fix == 1)
1995 usb_amd_quirk_pll_disable();
1998 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2000 /* fill sITDs frame by frame */
2001 for (packet = 0, sitd = NULL;
2002 packet < urb->number_of_packets;
2005 /* ASSERT: we have all necessary sitds */
2006 BUG_ON (list_empty (&sched->td_list));
2008 /* ASSERT: no itds for this endpoint in this frame */
2010 sitd = list_entry (sched->td_list.next,
2011 struct ehci_sitd, sitd_list);
2012 list_move_tail (&sitd->sitd_list, &stream->td_list);
2013 sitd->stream = stream;
2016 sitd_patch(ehci, stream, sitd, sched, packet);
2017 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2020 next_uframe += stream->interval << 3;
2022 stream->next_uframe = next_uframe & (mod - 1);
2024 /* don't need that schedule data any more */
2025 iso_sched_free (stream, sched);
2026 urb->hcpriv = stream;
2029 enable_periodic(ehci);
2032 /*-------------------------------------------------------------------------*/
2034 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2035 | SITD_STS_XACT | SITD_STS_MMF)
2037 /* Process and recycle a completed SITD. Return true iff its urb completed,
2038 * and hence its completion callback probably added things to the hardware
2041 * Note that we carefully avoid recycling this descriptor until after any
2042 * completion callback runs, so that it won't be reused quickly. That is,
2043 * assuming (a) no more than two urbs per frame on this endpoint, and also
2044 * (b) only this endpoint's completions submit URBs. It seems some silicon
2045 * corrupts things if you reuse completed descriptors very quickly...
2047 static bool sitd_complete(struct ehci_hcd *ehci, struct ehci_sitd *sitd)
2049 struct urb *urb = sitd->urb;
2050 struct usb_iso_packet_descriptor *desc;
2053 struct ehci_iso_stream *stream = sitd->stream;
2054 struct usb_device *dev;
2055 bool retval = false;
2057 urb_index = sitd->index;
2058 desc = &urb->iso_frame_desc [urb_index];
2059 t = hc32_to_cpup(ehci, &sitd->hw_results);
2061 /* report transfer status */
2062 if (unlikely(t & SITD_ERRS)) {
2064 if (t & SITD_STS_DBE)
2065 desc->status = usb_pipein (urb->pipe)
2066 ? -ENOSR /* hc couldn't read */
2067 : -ECOMM; /* hc couldn't write */
2068 else if (t & SITD_STS_BABBLE)
2069 desc->status = -EOVERFLOW;
2070 else /* XACT, MMF, etc */
2071 desc->status = -EPROTO;
2072 } else if (unlikely(t & SITD_STS_ACTIVE)) {
2073 /* URB was too late */
2077 desc->actual_length = desc->length - SITD_LENGTH(t);
2078 urb->actual_length += desc->actual_length;
2081 /* handle completion now? */
2082 if ((urb_index + 1) != urb->number_of_packets)
2085 /* ASSERT: it's really the last sitd for this urb
2086 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2087 BUG_ON (sitd->urb == urb);
2090 /* give urb back to the driver; completion often (re)submits */
2092 ehci_urb_done(ehci, urb, 0);
2097 disable_periodic(ehci);
2099 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2100 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2101 if (ehci->amd_pll_fix == 1)
2102 usb_amd_quirk_pll_enable();
2105 if (list_is_singular(&stream->td_list)) {
2106 ehci_to_hcd(ehci)->self.bandwidth_allocated
2107 -= stream->bandwidth;
2109 "deschedule devp %s ep%d%s-iso\n",
2110 dev->devpath, stream->bEndpointAddress & 0x0f,
2111 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2117 /* Add to the end of the free list for later reuse */
2118 list_move_tail(&sitd->sitd_list, &stream->free_list);
2120 /* Recycle the siTDs when the pipeline is empty (ep no longer in use) */
2121 if (list_empty(&stream->td_list)) {
2122 list_splice_tail_init(&stream->free_list,
2123 &ehci->cached_sitd_list);
2124 start_free_itds(ehci);
2131 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2134 int status = -EINVAL;
2135 unsigned long flags;
2136 struct ehci_iso_stream *stream;
2138 /* Get iso_stream head */
2139 stream = iso_stream_find (ehci, urb);
2140 if (stream == NULL) {
2141 ehci_dbg (ehci, "can't get iso stream\n");
2144 if (urb->interval != stream->interval) {
2145 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2146 stream->interval, urb->interval);
2150 #ifdef EHCI_URB_TRACE
2152 "submit %p dev%s ep%d%s-iso len %d\n",
2153 urb, urb->dev->devpath,
2154 usb_pipeendpoint (urb->pipe),
2155 usb_pipein (urb->pipe) ? "in" : "out",
2156 urb->transfer_buffer_length);
2159 /* allocate SITDs */
2160 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2162 ehci_dbg (ehci, "can't init sitds\n");
2166 /* schedule ... need to lock */
2167 spin_lock_irqsave (&ehci->lock, flags);
2168 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2169 status = -ESHUTDOWN;
2170 goto done_not_linked;
2172 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2173 if (unlikely(status))
2174 goto done_not_linked;
2175 status = iso_stream_schedule(ehci, urb, stream);
2177 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2179 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2181 spin_unlock_irqrestore (&ehci->lock, flags);
2186 /*-------------------------------------------------------------------------*/
2188 static void scan_isoc(struct ehci_hcd *ehci)
2190 unsigned uf, now_frame, frame;
2191 unsigned fmask = ehci->periodic_size - 1;
2192 bool modified, live;
2195 * When running, scan from last scan point up to "now"
2196 * else clean up by scanning everything that's left.
2197 * Touches as few pages as possible: cache-friendly.
2199 if (ehci->rh_state >= EHCI_RH_RUNNING) {
2200 uf = ehci_read_frame_index(ehci);
2201 now_frame = (uf >> 3) & fmask;
2204 now_frame = (ehci->last_iso_frame - 1) & fmask;
2207 ehci->now_frame = now_frame;
2209 frame = ehci->last_iso_frame;
2211 union ehci_shadow q, *q_p;
2215 /* scan each element in frame's queue for completions */
2216 q_p = &ehci->pshadow [frame];
2217 hw_p = &ehci->periodic [frame];
2219 type = Q_NEXT_TYPE(ehci, *hw_p);
2222 while (q.ptr != NULL) {
2223 switch (hc32_to_cpu(ehci, type)) {
2225 /* If this ITD is still active, leave it for
2226 * later processing ... check the next entry.
2227 * No need to check for activity unless the
2230 if (frame == now_frame && live) {
2232 for (uf = 0; uf < 8; uf++) {
2233 if (q.itd->hw_transaction[uf] &
2238 q_p = &q.itd->itd_next;
2239 hw_p = &q.itd->hw_next;
2240 type = Q_NEXT_TYPE(ehci,
2247 /* Take finished ITDs out of the schedule
2248 * and process them: recycle, maybe report
2249 * URB completion. HC won't cache the
2250 * pointer for much longer, if at all.
2252 *q_p = q.itd->itd_next;
2253 if (!ehci->use_dummy_qh ||
2254 q.itd->hw_next != EHCI_LIST_END(ehci))
2255 *hw_p = q.itd->hw_next;
2257 *hw_p = ehci->dummy->qh_dma;
2258 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2260 modified = itd_complete (ehci, q.itd);
2264 /* If this SITD is still active, leave it for
2265 * later processing ... check the next entry.
2266 * No need to check for activity unless the
2269 if (((frame == now_frame) ||
2270 (((frame + 1) & fmask) == now_frame))
2272 && (q.sitd->hw_results &
2273 SITD_ACTIVE(ehci))) {
2275 q_p = &q.sitd->sitd_next;
2276 hw_p = &q.sitd->hw_next;
2277 type = Q_NEXT_TYPE(ehci,
2283 /* Take finished SITDs out of the schedule
2284 * and process them: recycle, maybe report
2287 *q_p = q.sitd->sitd_next;
2288 if (!ehci->use_dummy_qh ||
2289 q.sitd->hw_next != EHCI_LIST_END(ehci))
2290 *hw_p = q.sitd->hw_next;
2292 *hw_p = ehci->dummy->qh_dma;
2293 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2295 modified = sitd_complete (ehci, q.sitd);
2299 ehci_dbg(ehci, "corrupt type %d frame %d shadow %p\n",
2300 type, frame, q.ptr);
2305 /* End of the iTDs and siTDs */
2310 /* assume completion callbacks modify the queue */
2311 if (unlikely(modified && ehci->isoc_count > 0))
2315 /* Stop when we have reached the current frame */
2316 if (frame == now_frame)
2319 /* The last frame may still have active siTDs */
2320 ehci->last_iso_frame = frame;
2321 frame = (frame + 1) & fmask;