2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/ktime.h>
35 #include <linux/list.h>
36 #include <linux/interrupt.h>
37 #include <linux/usb.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/moduleparam.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/slab.h>
43 #include <linux/uaccess.h>
45 #include <asm/byteorder.h>
48 #include <asm/unaligned.h>
50 #if defined(CONFIG_PPC_PS3)
51 #include <asm/firmware.h>
54 /*-------------------------------------------------------------------------*/
57 * EHCI hc_driver implementation ... experimental, incomplete.
58 * Based on the final 1.0 register interface specification.
60 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
61 * First was PCMCIA, like ISA; then CardBus, which is PCI.
62 * Next comes "CardBay", using USB 2.0 signals.
64 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
65 * Special thanks to Intel and VIA for providing host controllers to
66 * test this driver on, and Cypress (including In-System Design) for
67 * providing early devices for those host controllers to talk to!
70 #define DRIVER_AUTHOR "David Brownell"
71 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
73 static const char hcd_name [] = "ehci_hcd";
83 /* magic numbers that can affect system performance */
84 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
85 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
86 #define EHCI_TUNE_RL_TT 0
87 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
88 #define EHCI_TUNE_MULT_TT 1
90 * Some drivers think it's safe to schedule isochronous transfers more than
91 * 256 ms into the future (partly as a result of an old bug in the scheduling
92 * code). In an attempt to avoid trouble, we will use a minimum scheduling
93 * length of 512 frames instead of 256.
95 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
97 #define EHCI_IAA_MSECS 10 /* arbitrary */
98 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
99 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
100 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
101 /* 5-ms async qh unlink delay */
103 /* Initial IRQ latency: faster than hw default */
104 static int log2_irq_thresh = 0; // 0 to 6
105 module_param (log2_irq_thresh, int, S_IRUGO);
106 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
108 /* initial park setting: slower than hw default */
109 static unsigned park = 0;
110 module_param (park, uint, S_IRUGO);
111 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
113 /* for flakey hardware, ignore overcurrent indicators */
114 static bool ignore_oc = 0;
115 module_param (ignore_oc, bool, S_IRUGO);
116 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
118 /* for link power management(LPM) feature */
119 static unsigned int hird;
120 module_param(hird, int, S_IRUGO);
121 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
123 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
125 /*-------------------------------------------------------------------------*/
128 #include "ehci-dbg.c"
129 #include "pci-quirks.h"
131 /*-------------------------------------------------------------------------*/
134 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
136 /* Don't override timeouts which shrink or (later) disable
137 * the async ring; just the I/O watchdog. Note that if a
138 * SHRINK were pending, OFF would never be requested.
140 if (timer_pending(&ehci->watchdog)
141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
145 if (!test_and_set_bit(action, &ehci->actions)) {
149 case TIMER_IO_WATCHDOG:
150 if (!ehci->need_io_watchdog)
154 case TIMER_ASYNC_OFF:
155 t = EHCI_ASYNC_JIFFIES;
157 /* case TIMER_ASYNC_SHRINK: */
159 t = EHCI_SHRINK_JIFFIES;
162 mod_timer(&ehci->watchdog, t + jiffies);
166 /*-------------------------------------------------------------------------*/
169 * handshake - spin reading hc until handshake completes or fails
170 * @ptr: address of hc register to be read
171 * @mask: bits to look at in result of read
172 * @done: value of those bits when handshake succeeds
173 * @usec: timeout in microseconds
175 * Returns negative errno, or zero on success
177 * Success happens when the "mask" bits have the specified value (hardware
178 * handshake done). There are two failure modes: "usec" have passed (major
179 * hardware flakeout), or the register reads as all-ones (hardware removed).
181 * That last failure should_only happen in cases like physical cardbus eject
182 * before driver shutdown. But it also seems to be caused by bugs in cardbus
183 * bridge shutdown: shutting down the bridge before the devices using it.
185 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
186 u32 mask, u32 done, int usec)
191 result = ehci_readl(ehci, ptr);
192 if (result == ~(u32)0) /* card removed */
203 /* check TDI/ARC silicon is in host mode */
204 static int tdi_in_host_mode (struct ehci_hcd *ehci)
206 u32 __iomem *reg_ptr;
209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
210 tmp = ehci_readl(ehci, reg_ptr);
211 return (tmp & 3) == USBMODE_CM_HC;
214 /* force HC to halt state from unknown (EHCI spec section 2.3) */
215 static int ehci_halt (struct ehci_hcd *ehci)
217 u32 temp = ehci_readl(ehci, &ehci->regs->status);
219 /* disable any irqs left enabled by previous code */
220 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
222 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
226 if ((temp & STS_HALT) != 0)
230 * This routine gets called during probe before ehci->command
231 * has been initialized, so we can't rely on its value.
233 ehci->command &= ~CMD_RUN;
234 temp = ehci_readl(ehci, &ehci->regs->command);
235 temp &= ~(CMD_RUN | CMD_IAAD);
236 ehci_writel(ehci, temp, &ehci->regs->command);
237 return handshake (ehci, &ehci->regs->status,
238 STS_HALT, STS_HALT, 16 * 125);
241 #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3)
244 * The EHCI controller of the Cell Super Companion Chip used in the
245 * PS3 will stop the root hub after all root hub ports are suspended.
246 * When in this condition handshake will return -ETIMEDOUT. The
247 * STS_HLT bit will not be set, so inspection of the frame index is
248 * used here to test for the condition. If the condition is found
249 * return success to allow the USB suspend to complete.
252 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
253 void __iomem *ptr, u32 mask, u32 done,
256 unsigned int old_index;
259 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
262 old_index = ehci_read_frame_index(ehci);
264 error = handshake(ehci, ptr, mask, done, usec);
266 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index)
274 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
275 void __iomem *ptr, u32 mask, u32 done,
283 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
284 u32 mask, u32 done, int usec)
288 error = handshake(ehci, ptr, mask, done, usec);
289 if (error == -ETIMEDOUT)
290 error = handshake_for_broken_root_hub(ehci, ptr, mask, done,
295 ehci->rh_state = EHCI_RH_HALTED;
296 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
297 ptr, mask, done, error);
303 /* put TDI/ARC silicon into EHCI mode */
304 static void tdi_reset (struct ehci_hcd *ehci)
306 u32 __iomem *reg_ptr;
309 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
310 tmp = ehci_readl(ehci, reg_ptr);
311 tmp |= USBMODE_CM_HC;
312 /* The default byte access to MMR space is LE after
313 * controller reset. Set the required endian mode
314 * for transfer buffers to match the host microprocessor
316 if (ehci_big_endian_mmio(ehci))
318 ehci_writel(ehci, tmp, reg_ptr);
321 /* reset a non-running (STS_HALT == 1) controller */
322 static int ehci_reset (struct ehci_hcd *ehci)
325 u32 command = ehci_readl(ehci, &ehci->regs->command);
327 /* If the EHCI debug controller is active, special care must be
328 * taken before and after a host controller reset */
329 if (ehci->debug && !dbgp_reset_prep())
332 command |= CMD_RESET;
333 dbg_cmd (ehci, "reset", command);
334 ehci_writel(ehci, command, &ehci->regs->command);
335 ehci->rh_state = EHCI_RH_HALTED;
336 ehci->next_statechange = jiffies;
337 retval = handshake (ehci, &ehci->regs->command,
338 CMD_RESET, 0, 250 * 1000);
340 if (ehci->has_hostpc) {
341 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
342 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
343 ehci_writel(ehci, TXFIFO_DEFAULT,
344 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
349 if (ehci_is_TDI(ehci))
353 dbgp_external_startup();
355 ehci->command = ehci_readl(ehci, &ehci->regs->command);
356 ehci->port_c_suspend = ehci->suspended_ports =
357 ehci->resuming_ports = 0;
361 /* idle the controller (from running) */
362 static void ehci_quiesce (struct ehci_hcd *ehci)
367 if (ehci->rh_state != EHCI_RH_RUNNING)
371 /* wait for any schedule enables/disables to take effect */
372 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
373 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
374 STS_ASS | STS_PSS, temp, 16 * 125))
377 /* then disable anything that's still active */
378 ehci->command &= ~(CMD_ASE | CMD_PSE);
379 ehci_writel(ehci, ehci->command, &ehci->regs->command);
381 /* hardware can take 16 microframes to turn off ... */
382 handshake_on_error_set_halt(ehci, &ehci->regs->status,
383 STS_ASS | STS_PSS, 0, 16 * 125);
386 /*-------------------------------------------------------------------------*/
388 static void end_unlink_async(struct ehci_hcd *ehci);
389 static void ehci_work(struct ehci_hcd *ehci);
391 #include "ehci-hub.c"
392 #include "ehci-lpm.c"
393 #include "ehci-mem.c"
395 #include "ehci-sched.c"
396 #include "ehci-sysfs.c"
398 /*-------------------------------------------------------------------------*/
400 static void ehci_iaa_watchdog(unsigned long param)
402 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
405 spin_lock_irqsave (&ehci->lock, flags);
407 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
408 * So we need this watchdog, but must protect it against both
409 * (a) SMP races against real IAA firing and retriggering, and
410 * (b) clean HC shutdown, when IAA watchdog was pending.
413 && !timer_pending(&ehci->iaa_watchdog)
414 && ehci->rh_state == EHCI_RH_RUNNING) {
417 /* If we get here, IAA is *REALLY* late. It's barely
418 * conceivable that the system is so busy that CMD_IAAD
419 * is still legitimately set, so let's be sure it's
420 * clear before we read STS_IAA. (The HC should clear
421 * CMD_IAAD when it sets STS_IAA.)
423 cmd = ehci_readl(ehci, &ehci->regs->command);
425 /* If IAA is set here it either legitimately triggered
426 * before we cleared IAAD above (but _way_ late, so we'll
427 * still count it as lost) ... or a silicon erratum:
428 * - VIA seems to set IAA without triggering the IRQ;
429 * - IAAD potentially cleared without setting IAA.
431 status = ehci_readl(ehci, &ehci->regs->status);
432 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
433 COUNT (ehci->stats.lost_iaa);
434 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
437 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
439 end_unlink_async(ehci);
442 spin_unlock_irqrestore(&ehci->lock, flags);
445 static void ehci_watchdog(unsigned long param)
447 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
450 spin_lock_irqsave(&ehci->lock, flags);
452 /* stop async processing after it's idled a bit */
453 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
454 start_unlink_async (ehci, ehci->async);
456 /* ehci could run by timer, without IRQs ... */
459 spin_unlock_irqrestore (&ehci->lock, flags);
462 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
463 * The firmware seems to think that powering off is a wakeup event!
464 * This routine turns off remote wakeup and everything else, on all ports.
466 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
468 int port = HCS_N_PORTS(ehci->hcs_params);
471 ehci_writel(ehci, PORT_RWC_BITS,
472 &ehci->regs->port_status[port]);
476 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
477 * Should be called with ehci->lock held.
479 static void ehci_silence_controller(struct ehci_hcd *ehci)
482 ehci_turn_off_all_ports(ehci);
484 /* make BIOS/etc use companion controller during reboot */
485 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
487 /* unblock posted writes */
488 ehci_readl(ehci, &ehci->regs->configured_flag);
491 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
492 * This forcibly disables dma and IRQs, helping kexec and other cases
493 * where the next system software may expect clean state.
495 static void ehci_shutdown(struct usb_hcd *hcd)
497 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
499 del_timer_sync(&ehci->watchdog);
500 del_timer_sync(&ehci->iaa_watchdog);
502 spin_lock_irq(&ehci->lock);
503 ehci_silence_controller(ehci);
504 spin_unlock_irq(&ehci->lock);
507 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
511 if (!HCS_PPC (ehci->hcs_params))
514 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
515 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
516 (void) ehci_hub_control(ehci_to_hcd(ehci),
517 is_on ? SetPortFeature : ClearPortFeature,
520 /* Flush those writes */
521 ehci_readl(ehci, &ehci->regs->command);
525 /*-------------------------------------------------------------------------*/
528 * ehci_work is called from some interrupts, timers, and so on.
529 * it calls driver completion functions, after dropping ehci->lock.
531 static void ehci_work (struct ehci_hcd *ehci)
533 timer_action_done (ehci, TIMER_IO_WATCHDOG);
535 /* another CPU may drop ehci->lock during a schedule scan while
536 * it reports urb completions. this flag guards against bogus
537 * attempts at re-entrant schedule scanning.
543 if (ehci->next_uframe != -1)
544 scan_periodic (ehci);
547 /* the IO watchdog guards against hardware or driver bugs that
548 * misplace IRQs, and should let us run completely without IRQs.
549 * such lossage has been observed on both VT6202 and VT8235.
551 if (ehci->rh_state == EHCI_RH_RUNNING &&
552 (ehci->async->qh_next.ptr != NULL ||
553 ehci->periodic_sched != 0))
554 timer_action (ehci, TIMER_IO_WATCHDOG);
558 * Called when the ehci_hcd module is removed.
560 static void ehci_stop (struct usb_hcd *hcd)
562 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
564 ehci_dbg (ehci, "stop\n");
566 /* no more interrupts ... */
567 del_timer_sync (&ehci->watchdog);
568 del_timer_sync(&ehci->iaa_watchdog);
570 spin_lock_irq(&ehci->lock);
571 if (ehci->rh_state == EHCI_RH_RUNNING)
574 ehci_silence_controller(ehci);
576 spin_unlock_irq(&ehci->lock);
578 remove_sysfs_files(ehci);
579 remove_debug_files (ehci);
581 /* root hub is shut down separately (first, when possible) */
582 spin_lock_irq (&ehci->lock);
585 spin_unlock_irq (&ehci->lock);
586 ehci_mem_cleanup (ehci);
588 if (ehci->amd_pll_fix == 1)
592 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
593 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
594 ehci->stats.lost_iaa);
595 ehci_dbg (ehci, "complete %ld unlink %ld\n",
596 ehci->stats.complete, ehci->stats.unlink);
599 dbg_status (ehci, "ehci_stop completed",
600 ehci_readl(ehci, &ehci->regs->status));
603 /* one-time init, only for memory state */
604 static int ehci_init(struct usb_hcd *hcd)
606 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
610 struct ehci_qh_hw *hw;
612 spin_lock_init(&ehci->lock);
615 * keep io watchdog by default, those good HCDs could turn off it later
617 ehci->need_io_watchdog = 1;
618 init_timer(&ehci->watchdog);
619 ehci->watchdog.function = ehci_watchdog;
620 ehci->watchdog.data = (unsigned long) ehci;
622 init_timer(&ehci->iaa_watchdog);
623 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
624 ehci->iaa_watchdog.data = (unsigned long) ehci;
626 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
629 * by default set standard 80% (== 100 usec/uframe) max periodic
630 * bandwidth as required by USB 2.0
632 ehci->uframe_periodic_max = 100;
635 * hw default: 1K periodic list heads, one per frame.
636 * periodic_size can shrink by USBCMD update if hcc_params allows.
638 ehci->periodic_size = DEFAULT_I_TDPS;
639 INIT_LIST_HEAD(&ehci->cached_itd_list);
640 INIT_LIST_HEAD(&ehci->cached_sitd_list);
642 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
643 /* periodic schedule size can be smaller than default */
644 switch (EHCI_TUNE_FLS) {
645 case 0: ehci->periodic_size = 1024; break;
646 case 1: ehci->periodic_size = 512; break;
647 case 2: ehci->periodic_size = 256; break;
651 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
654 /* controllers may cache some of the periodic schedule ... */
655 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
656 ehci->i_thresh = 2 + 8;
657 else // N microframes cached
658 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
660 ehci->reclaim = NULL;
661 ehci->next_uframe = -1;
662 ehci->clock_frame = -1;
665 * dedicate a qh for the async ring head, since we couldn't unlink
666 * a 'real' qh without stopping the async schedule [4.8]. use it
667 * as the 'reclamation list head' too.
668 * its dummy is used in hw_alt_next of many tds, to prevent the qh
669 * from automatically advancing to the next td after short reads.
671 ehci->async->qh_next.qh = NULL;
672 hw = ehci->async->hw;
673 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
674 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
675 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */
676 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
677 hw->hw_qtd_next = EHCI_LIST_END(ehci);
678 ehci->async->qh_state = QH_STATE_LINKED;
679 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
681 /* clear interrupt enables, set irq latency */
682 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
684 temp = 1 << (16 + log2_irq_thresh);
685 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
687 ehci_dbg(ehci, "enable per-port change event\n");
690 if (HCC_CANPARK(hcc_params)) {
691 /* HW default park == 3, on hardware that supports it (like
692 * NVidia and ALI silicon), maximizes throughput on the async
693 * schedule by avoiding QH fetches between transfers.
695 * With fast usb storage devices and NForce2, "park" seems to
696 * make problems: throughput reduction (!), data errors...
699 park = min(park, (unsigned) 3);
703 ehci_dbg(ehci, "park %d\n", park);
705 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
706 /* periodic schedule size can be smaller than default */
708 temp |= (EHCI_TUNE_FLS << 2);
710 if (HCC_LPM(hcc_params)) {
711 /* support link power management EHCI 1.1 addendum */
712 ehci_dbg(ehci, "support lpm\n");
715 ehci_dbg(ehci, "hird %d invalid, use default 0",
721 ehci->command = temp;
723 /* Accept arbitrarily long scatter-gather lists */
724 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
725 hcd->self.sg_tablesize = ~0;
729 /* start HC running; it's halted, ehci_init() has been run (once) */
730 static int ehci_run (struct usb_hcd *hcd)
732 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
736 hcd->uses_new_polling = 1;
738 /* EHCI spec section 4.1 */
740 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
741 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
744 * hcc_params controls whether ehci->regs->segment must (!!!)
745 * be used; it constrains QH/ITD/SITD and QTD locations.
746 * pci_pool consistent memory always uses segment zero.
747 * streaming mappings for I/O buffers, like pci_map_single(),
748 * can return segments above 4GB, if the device allows.
750 * NOTE: the dma mask is visible through dma_supported(), so
751 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
752 * Scsi_Host.highmem_io, and so forth. It's readonly to all
753 * host side drivers though.
755 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
756 if (HCC_64BIT_ADDR(hcc_params)) {
757 ehci_writel(ehci, 0, &ehci->regs->segment);
759 // this is deeply broken on almost all architectures
760 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
761 ehci_info(ehci, "enabled 64bit DMA\n");
766 // Philips, Intel, and maybe others need CMD_RUN before the
767 // root hub will detect new devices (why?); NEC doesn't
768 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
769 ehci->command |= CMD_RUN;
770 ehci_writel(ehci, ehci->command, &ehci->regs->command);
771 dbg_cmd (ehci, "init", ehci->command);
774 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
775 * are explicitly handed to companion controller(s), so no TT is
776 * involved with the root hub. (Except where one is integrated,
777 * and there's no companion controller unless maybe for USB OTG.)
779 * Turning on the CF flag will transfer ownership of all ports
780 * from the companions to the EHCI controller. If any of the
781 * companions are in the middle of a port reset at the time, it
782 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
783 * guarantees that no resets are in progress. After we set CF,
784 * a short delay lets the hardware catch up; new resets shouldn't
785 * be started before the port switching actions could complete.
787 down_write(&ehci_cf_port_reset_rwsem);
788 ehci->rh_state = EHCI_RH_RUNNING;
789 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
790 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
792 up_write(&ehci_cf_port_reset_rwsem);
793 ehci->last_periodic_enable = ktime_get_real();
795 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
797 "USB %x.%x started, EHCI %x.%02x%s\n",
798 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
799 temp >> 8, temp & 0xff,
800 ignore_oc ? ", overcurrent ignored" : "");
802 ehci_writel(ehci, INTR_MASK,
803 &ehci->regs->intr_enable); /* Turn On Interrupts */
805 /* GRR this is run-once init(), being done every time the HC starts.
806 * So long as they're part of class devices, we can't do it init()
807 * since the class device isn't created that early.
809 create_debug_files(ehci);
810 create_sysfs_files(ehci);
815 static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
817 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
820 ehci->regs = (void __iomem *)ehci->caps +
821 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
822 dbg_hcs_params(ehci, "reset");
823 dbg_hcc_params(ehci, "reset");
825 /* cache this readonly data; minimize chip reads */
826 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
828 ehci->sbrn = HCD_USB2;
830 retval = ehci_halt(ehci);
834 /* data structure init */
835 retval = ehci_init(hcd);
844 /*-------------------------------------------------------------------------*/
846 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
848 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
849 u32 status, masked_status, pcd_status = 0, cmd;
852 spin_lock (&ehci->lock);
854 status = ehci_readl(ehci, &ehci->regs->status);
856 /* e.g. cardbus physical eject */
857 if (status == ~(u32) 0) {
858 ehci_dbg (ehci, "device removed\n");
863 * We don't use STS_FLR, but some controllers don't like it to
864 * remain on, so mask it out along with the other status bits.
866 masked_status = status & (INTR_MASK | STS_FLR);
869 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
870 spin_unlock(&ehci->lock);
874 /* clear (just) interrupts */
875 ehci_writel(ehci, masked_status, &ehci->regs->status);
876 cmd = ehci_readl(ehci, &ehci->regs->command);
880 /* unrequested/ignored: Frame List Rollover */
881 dbg_status (ehci, "irq", status);
884 /* INT, ERR, and IAA interrupt rates can be throttled */
886 /* normal [4.15.1.2] or error [4.15.1.1] completion */
887 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
888 if (likely ((status & STS_ERR) == 0))
889 COUNT (ehci->stats.normal);
891 COUNT (ehci->stats.error);
895 /* complete the unlinking of some qh [4.15.2.3] */
896 if (status & STS_IAA) {
897 /* guard against (alleged) silicon errata */
899 ehci_dbg(ehci, "IAA with IAAD still set?\n");
901 COUNT(ehci->stats.reclaim);
902 end_unlink_async(ehci);
904 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
907 /* remote wakeup [4.3.1] */
908 if (status & STS_PCD) {
909 unsigned i = HCS_N_PORTS (ehci->hcs_params);
912 /* kick root hub later */
915 /* resume root hub? */
916 if (ehci->rh_state == EHCI_RH_SUSPENDED)
917 usb_hcd_resume_root_hub(hcd);
919 /* get per-port change detect bits */
926 /* leverage per-port change bits feature */
927 if (ehci->has_ppcd && !(ppcd & (1 << i)))
929 pstatus = ehci_readl(ehci,
930 &ehci->regs->port_status[i]);
932 if (pstatus & PORT_OWNER)
934 if (!(test_bit(i, &ehci->suspended_ports) &&
935 ((pstatus & PORT_RESUME) ||
936 !(pstatus & PORT_SUSPEND)) &&
937 (pstatus & PORT_PE) &&
938 ehci->reset_done[i] == 0))
941 /* start 20 msec resume signaling from this port,
942 * and make khubd collect PORT_STAT_C_SUSPEND to
943 * stop that signaling. Use 5 ms extra for safety,
944 * like usb_port_resume() does.
946 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
947 set_bit(i, &ehci->resuming_ports);
948 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
949 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
953 /* PCI errors [4.15.2.4] */
954 if (unlikely ((status & STS_FATAL) != 0)) {
955 ehci_err(ehci, "fatal error\n");
956 dbg_cmd(ehci, "fatal", cmd);
957 dbg_status(ehci, "fatal", status);
961 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
963 /* generic layer kills/unlinks all urbs, then
964 * uses ehci_stop to clean up the rest
971 spin_unlock (&ehci->lock);
973 usb_hcd_poll_rh_status(hcd);
977 /*-------------------------------------------------------------------------*/
980 * non-error returns are a promise to giveback() the urb later
981 * we drop ownership so next owner (or urb unlink) can get it
983 * urb + dev is in hcd.self.controller.urb_list
984 * we're queueing TDs onto software and hardware lists
986 * hcd-specific init for hcpriv hasn't been done yet
988 * NOTE: control, bulk, and interrupt share the same code to append TDs
989 * to a (possibly active) QH, and the same QH scanning code.
991 static int ehci_urb_enqueue (
996 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
997 struct list_head qtd_list;
999 INIT_LIST_HEAD (&qtd_list);
1001 switch (usb_pipetype (urb->pipe)) {
1003 /* qh_completions() code doesn't handle all the fault cases
1004 * in multi-TD control transfers. Even 1KB is rare anyway.
1006 if (urb->transfer_buffer_length > (16 * 1024))
1009 /* case PIPE_BULK: */
1011 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1013 return submit_async(ehci, urb, &qtd_list, mem_flags);
1015 case PIPE_INTERRUPT:
1016 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1018 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1020 case PIPE_ISOCHRONOUS:
1021 if (urb->dev->speed == USB_SPEED_HIGH)
1022 return itd_submit (ehci, urb, mem_flags);
1024 return sitd_submit (ehci, urb, mem_flags);
1028 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
1031 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1032 end_unlink_async(ehci);
1034 /* If the QH isn't linked then there's nothing we can do
1035 * unless we were called during a giveback, in which case
1036 * qh_completions() has to deal with it.
1038 if (qh->qh_state != QH_STATE_LINKED) {
1039 if (qh->qh_state == QH_STATE_COMPLETING)
1040 qh->needs_rescan = 1;
1044 /* defer till later if busy */
1045 if (ehci->reclaim) {
1046 struct ehci_qh *last;
1048 for (last = ehci->reclaim;
1050 last = last->reclaim)
1052 qh->qh_state = QH_STATE_UNLINK_WAIT;
1055 /* start IAA cycle */
1057 start_unlink_async (ehci, qh);
1060 /* remove from hardware lists
1061 * completions normally happen asynchronously
1064 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1066 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1068 unsigned long flags;
1071 spin_lock_irqsave (&ehci->lock, flags);
1072 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1076 switch (usb_pipetype (urb->pipe)) {
1077 // case PIPE_CONTROL:
1080 qh = (struct ehci_qh *) urb->hcpriv;
1083 switch (qh->qh_state) {
1084 case QH_STATE_LINKED:
1085 case QH_STATE_COMPLETING:
1086 unlink_async(ehci, qh);
1088 case QH_STATE_UNLINK:
1089 case QH_STATE_UNLINK_WAIT:
1090 /* already started */
1093 /* QH might be waiting for a Clear-TT-Buffer */
1094 qh_completions(ehci, qh);
1099 case PIPE_INTERRUPT:
1100 qh = (struct ehci_qh *) urb->hcpriv;
1103 switch (qh->qh_state) {
1104 case QH_STATE_LINKED:
1105 case QH_STATE_COMPLETING:
1106 intr_deschedule (ehci, qh);
1109 qh_completions (ehci, qh);
1112 ehci_dbg (ehci, "bogus qh %p state %d\n",
1118 case PIPE_ISOCHRONOUS:
1121 // wait till next completion, do it then.
1122 // completion irqs can wait up to 1024 msec,
1126 spin_unlock_irqrestore (&ehci->lock, flags);
1130 /*-------------------------------------------------------------------------*/
1132 // bulk qh holds the data toggle
1135 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1137 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1138 unsigned long flags;
1139 struct ehci_qh *qh, *tmp;
1141 /* ASSERT: any requests/urbs are being unlinked */
1142 /* ASSERT: nobody can be submitting urbs for this any more */
1145 spin_lock_irqsave (&ehci->lock, flags);
1150 /* endpoints can be iso streams. for now, we don't
1151 * accelerate iso completions ... so spin a while.
1153 if (qh->hw == NULL) {
1154 ehci_vdbg (ehci, "iso delay\n");
1158 if (ehci->rh_state != EHCI_RH_RUNNING)
1159 qh->qh_state = QH_STATE_IDLE;
1160 switch (qh->qh_state) {
1161 case QH_STATE_LINKED:
1162 case QH_STATE_COMPLETING:
1163 for (tmp = ehci->async->qh_next.qh;
1165 tmp = tmp->qh_next.qh)
1167 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1168 * may already be unlinked.
1171 unlink_async(ehci, qh);
1173 case QH_STATE_UNLINK: /* wait for hw to finish? */
1174 case QH_STATE_UNLINK_WAIT:
1176 spin_unlock_irqrestore (&ehci->lock, flags);
1177 schedule_timeout_uninterruptible(1);
1179 case QH_STATE_IDLE: /* fully unlinked */
1180 if (qh->clearing_tt)
1182 if (list_empty (&qh->qtd_list)) {
1186 /* else FALL THROUGH */
1188 /* caller was supposed to have unlinked any requests;
1189 * that's not our job. just leak this memory.
1191 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1192 qh, ep->desc.bEndpointAddress, qh->qh_state,
1193 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1198 spin_unlock_irqrestore (&ehci->lock, flags);
1202 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1204 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1206 int eptype = usb_endpoint_type(&ep->desc);
1207 int epnum = usb_endpoint_num(&ep->desc);
1208 int is_out = usb_endpoint_dir_out(&ep->desc);
1209 unsigned long flags;
1211 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1214 spin_lock_irqsave(&ehci->lock, flags);
1217 /* For Bulk and Interrupt endpoints we maintain the toggle state
1218 * in the hardware; the toggle bits in udev aren't used at all.
1219 * When an endpoint is reset by usb_clear_halt() we must reset
1220 * the toggle bit in the QH.
1223 usb_settoggle(qh->dev, epnum, is_out, 0);
1224 if (!list_empty(&qh->qtd_list)) {
1225 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1226 } else if (qh->qh_state == QH_STATE_LINKED ||
1227 qh->qh_state == QH_STATE_COMPLETING) {
1229 /* The toggle value in the QH can't be updated
1230 * while the QH is active. Unlink it now;
1231 * re-linking will call qh_refresh().
1233 if (eptype == USB_ENDPOINT_XFER_BULK)
1234 unlink_async(ehci, qh);
1236 intr_deschedule(ehci, qh);
1239 spin_unlock_irqrestore(&ehci->lock, flags);
1242 static int ehci_get_frame (struct usb_hcd *hcd)
1244 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1245 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1248 /*-------------------------------------------------------------------------*/
1250 * The EHCI in ChipIdea HDRC cannot be a separate module or device,
1251 * because its registers (and irq) are shared between host/gadget/otg
1252 * functions and in order to facilitate role switching we cannot
1253 * give the ehci driver exclusive access to those.
1255 #ifndef CHIPIDEA_EHCI
1257 MODULE_DESCRIPTION(DRIVER_DESC);
1258 MODULE_AUTHOR (DRIVER_AUTHOR);
1259 MODULE_LICENSE ("GPL");
1262 #include "ehci-pci.c"
1263 #define PCI_DRIVER ehci_pci_driver
1266 #ifdef CONFIG_USB_EHCI_FSL
1267 #include "ehci-fsl.c"
1268 #define PLATFORM_DRIVER ehci_fsl_driver
1271 #ifdef CONFIG_USB_EHCI_MXC
1272 #include "ehci-mxc.c"
1273 #define PLATFORM_DRIVER ehci_mxc_driver
1276 #ifdef CONFIG_USB_EHCI_SH
1277 #include "ehci-sh.c"
1278 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1281 #ifdef CONFIG_MIPS_ALCHEMY
1282 #include "ehci-au1xxx.c"
1283 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1286 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1287 #include "ehci-omap.c"
1288 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1291 #ifdef CONFIG_PPC_PS3
1292 #include "ehci-ps3.c"
1293 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1296 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1297 #include "ehci-ppc-of.c"
1298 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1301 #ifdef CONFIG_XPS_USB_HCD_XILINX
1302 #include "ehci-xilinx-of.c"
1303 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1306 #ifdef CONFIG_PLAT_ORION
1307 #include "ehci-orion.c"
1308 #define PLATFORM_DRIVER ehci_orion_driver
1311 #ifdef CONFIG_ARCH_IXP4XX
1312 #include "ehci-ixp4xx.c"
1313 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1316 #ifdef CONFIG_USB_W90X900_EHCI
1317 #include "ehci-w90x900.c"
1318 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1321 #ifdef CONFIG_ARCH_AT91
1322 #include "ehci-atmel.c"
1323 #define PLATFORM_DRIVER ehci_atmel_driver
1326 #ifdef CONFIG_USB_OCTEON_EHCI
1327 #include "ehci-octeon.c"
1328 #define PLATFORM_DRIVER ehci_octeon_driver
1331 #ifdef CONFIG_USB_CNS3XXX_EHCI
1332 #include "ehci-cns3xxx.c"
1333 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1336 #ifdef CONFIG_ARCH_VT8500
1337 #include "ehci-vt8500.c"
1338 #define PLATFORM_DRIVER vt8500_ehci_driver
1341 #ifdef CONFIG_PLAT_SPEAR
1342 #include "ehci-spear.c"
1343 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1346 #ifdef CONFIG_USB_EHCI_MSM
1347 #include "ehci-msm.c"
1348 #define PLATFORM_DRIVER ehci_msm_driver
1351 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1352 #include "ehci-pmcmsp.c"
1353 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1356 #ifdef CONFIG_USB_EHCI_TEGRA
1357 #include "ehci-tegra.c"
1358 #define PLATFORM_DRIVER tegra_ehci_driver
1361 #ifdef CONFIG_USB_EHCI_S5P
1362 #include "ehci-s5p.c"
1363 #define PLATFORM_DRIVER s5p_ehci_driver
1366 #ifdef CONFIG_SPARC_LEON
1367 #include "ehci-grlib.c"
1368 #define PLATFORM_DRIVER ehci_grlib_driver
1371 #ifdef CONFIG_CPU_XLR
1372 #include "ehci-xls.c"
1373 #define PLATFORM_DRIVER ehci_xls_driver
1376 #ifdef CONFIG_USB_EHCI_MV
1377 #include "ehci-mv.c"
1378 #define PLATFORM_DRIVER ehci_mv_driver
1381 #ifdef CONFIG_MACH_LOONGSON1
1382 #include "ehci-ls1x.c"
1383 #define PLATFORM_DRIVER ehci_ls1x_driver
1386 #ifdef CONFIG_MIPS_SEAD3
1387 #include "ehci-sead3.c"
1388 #define PLATFORM_DRIVER ehci_hcd_sead3_driver
1391 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1392 #include "ehci-platform.c"
1393 #define PLATFORM_DRIVER ehci_platform_driver
1396 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1397 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1398 !defined(XILINX_OF_PLATFORM_DRIVER)
1399 #error "missing bus glue for ehci-hcd"
1402 static int __init ehci_hcd_init(void)
1409 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1410 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1411 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1412 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1413 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1414 " before uhci_hcd and ohci_hcd, not after\n");
1416 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1418 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1419 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1422 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1423 if (!ehci_debug_root) {
1429 #ifdef PLATFORM_DRIVER
1430 retval = platform_driver_register(&PLATFORM_DRIVER);
1436 retval = pci_register_driver(&PCI_DRIVER);
1441 #ifdef PS3_SYSTEM_BUS_DRIVER
1442 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1447 #ifdef OF_PLATFORM_DRIVER
1448 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1453 #ifdef XILINX_OF_PLATFORM_DRIVER
1454 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1460 #ifdef XILINX_OF_PLATFORM_DRIVER
1461 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1464 #ifdef OF_PLATFORM_DRIVER
1465 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1468 #ifdef PS3_SYSTEM_BUS_DRIVER
1469 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1473 pci_unregister_driver(&PCI_DRIVER);
1476 #ifdef PLATFORM_DRIVER
1477 platform_driver_unregister(&PLATFORM_DRIVER);
1481 debugfs_remove(ehci_debug_root);
1482 ehci_debug_root = NULL;
1485 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1488 module_init(ehci_hcd_init);
1490 static void __exit ehci_hcd_cleanup(void)
1492 #ifdef XILINX_OF_PLATFORM_DRIVER
1493 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1495 #ifdef OF_PLATFORM_DRIVER
1496 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1498 #ifdef PLATFORM_DRIVER
1499 platform_driver_unregister(&PLATFORM_DRIVER);
1502 pci_unregister_driver(&PCI_DRIVER);
1504 #ifdef PS3_SYSTEM_BUS_DRIVER
1505 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1508 debugfs_remove(ehci_debug_root);
1510 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1512 module_exit(ehci_hcd_cleanup);
1514 #endif /* CHIPIDEA_EHCI */