drivers/usb/gadget/udc/pxa25x_udc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 /* #define VERBOSE_DEBUG */
  18
  19 #include <linux/device.h>
  20 #include <linux/gpio.h>
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/ioport.h>
  24 #include <linux/types.h>
  25 #include <linux/errno.h>
  26 #include <linux/err.h>
  27 #include <linux/delay.h>
  28 #include <linux/slab.h>
  29 #include <linux/timer.h>
  30 #include <linux/list.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/mm.h>
  33 #include <linux/platform_data/pxa2xx_udc.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/irq.h>
  37 #include <linux/clk.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/io.h>
  41 #include <linux/prefetch.h>
  42
  43 #include <asm/byteorder.h>
  44 #include <asm/dma.h>
  45 #include <asm/mach-types.h>
  46 #include <asm/unaligned.h>
  47
  48 #include <linux/usb/ch9.h>
  49 #include <linux/usb/gadget.h>
  50 #include <linux/usb/otg.h>
  51
  52 #ifdef CONFIG_ARCH_LUBBOCK
  53 #include <mach/lubbock.h>
  54 #endif
  55
  56 #define UDCCR    0x0000 /* UDC Control Register */
  57 #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */
  58 #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */
  59 #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */
  60 #define UDCCS0   0x0010 /* UDC Endpoint 0 Control/Status Register */
  61 #define UDCCS1   0x0014 /* UDC Endpoint 1 (IN) Control/Status Register */
  62 #define UDCCS2   0x0018 /* UDC Endpoint 2 (OUT) Control/Status Register */
  63 #define UDCCS3   0x001C /* UDC Endpoint 3 (IN) Control/Status Register */
  64 #define UDCCS4   0x0020 /* UDC Endpoint 4 (OUT) Control/Status Register */
  65 #define UDCCS5   0x0024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
  66 #define UDCCS6   0x0028 /* UDC Endpoint 6 (IN) Control/Status Register */
  67 #define UDCCS7   0x002C /* UDC Endpoint 7 (OUT) Control/Status Register */
  68 #define UDCCS8   0x0030 /* UDC Endpoint 8 (IN) Control/Status Register */
  69 #define UDCCS9   0x0034 /* UDC Endpoint 9 (OUT) Control/Status Register */
  70 #define UDCCS10  0x0038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
  71 #define UDCCS11  0x003C /* UDC Endpoint 11 (IN) Control/Status Register */
  72 #define UDCCS12  0x0040 /* UDC Endpoint 12 (OUT) Control/Status Register */
  73 #define UDCCS13  0x0044 /* UDC Endpoint 13 (IN) Control/Status Register */
  74 #define UDCCS14  0x0048 /* UDC Endpoint 14 (OUT) Control/Status Register */
  75 #define UDCCS15  0x004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */
  76 #define UFNRH    0x0060 /* UDC Frame Number Register High */
  77 #define UFNRL    0x0064 /* UDC Frame Number Register Low */
  78 #define UBCR2    0x0068 /* UDC Byte Count Reg 2 */
  79 #define UBCR4    0x006c /* UDC Byte Count Reg 4 */
  80 #define UBCR7    0x0070 /* UDC Byte Count Reg 7 */
  81 #define UBCR9    0x0074 /* UDC Byte Count Reg 9 */
  82 #define UBCR12   0x0078 /* UDC Byte Count Reg 12 */
  83 #define UBCR14   0x007c /* UDC Byte Count Reg 14 */
  84 #define UDDR0    0x0080 /* UDC Endpoint 0 Data Register */
  85 #define UDDR1    0x0100 /* UDC Endpoint 1 Data Register */
  86 #define UDDR2    0x0180 /* UDC Endpoint 2 Data Register */
  87 #define UDDR3    0x0200 /* UDC Endpoint 3 Data Register */
  88 #define UDDR4    0x0400 /* UDC Endpoint 4 Data Register */
  89 #define UDDR5    0x00A0 /* UDC Endpoint 5 Data Register */
  90 #define UDDR6    0x0600 /* UDC Endpoint 6 Data Register */
  91 #define UDDR7    0x0680 /* UDC Endpoint 7 Data Register */
  92 #define UDDR8    0x0700 /* UDC Endpoint 8 Data Register */
  93 #define UDDR9    0x0900 /* UDC Endpoint 9 Data Register */
  94 #define UDDR10   0x00C0 /* UDC Endpoint 10 Data Register */
  95 #define UDDR11   0x0B00 /* UDC Endpoint 11 Data Register */
  96 #define UDDR12   0x0B80 /* UDC Endpoint 12 Data Register */
  97 #define UDDR13   0x0C00 /* UDC Endpoint 13 Data Register */
  98 #define UDDR14   0x0E00 /* UDC Endpoint 14 Data Register */
  99 #define UDDR15   0x00E0 /* UDC Endpoint 15 Data Register */
 100
 101 #define UICR0    0x0050 /* UDC Interrupt Control Register 0 */
 102 #define UICR1    0x0054 /* UDC Interrupt Control Register 1 */
 103
 104 #define USIR0    0x0058 /* UDC Status Interrupt Register 0 */
 105 #define USIR1    0x005C /* UDC Status Interrupt Register 1 */
 106
 107 #define UDCCR_UDE       (1 << 0)        /* UDC enable */
 108 #define UDCCR_UDA       (1 << 1)        /* UDC active */
 109 #define UDCCR_RSM       (1 << 2)        /* Device resume */
 110 #define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
 111 #define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
 112 #define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
 113 #define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
 114 #define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
 115
 116 #define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
 117 #define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
 118 #define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
 119 #define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
 120 #define UDCCS0_SST      (1 << 4)        /* Sent stall */
 121 #define UDCCS0_FST      (1 << 5)        /* Force stall */
 122 #define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
 123 #define UDCCS0_SA       (1 << 7)        /* Setup active */
 124
 125 #define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
 126 #define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
 127 #define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
 128 #define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
 129 #define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
 130 #define UDCCS_BI_FST    (1 << 5)        /* Force stall */
 131 #define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
 132
 133 #define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
 134 #define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
 135 #define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
 136 #define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
 137 #define UDCCS_BO_FST    (1 << 5)        /* Force stall */
 138 #define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
 139 #define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
 140
 141 #define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
 142 #define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
 143 #define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
 144 #define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
 145 #define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
 146
 147 #define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
 148 #define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
 149 #ifdef CONFIG_ARCH_IXP4XX /* FIXME: is this right?, datasheed says '2' */
 150 #define UDCCS_IO_ROF    (1 << 3)        /* Receive overflow */
 151 #endif
 152 #ifdef CONFIG_ARCH_PXA
 153 #define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
 154 #endif
 155 #define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
 156 #define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
 157 #define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
 158
 159 #define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
 160 #define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
 161 #define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
 162 #define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
 163 #define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
 164 #define UDCCS_INT_FST   (1 << 5)        /* Force stall */
 165 #define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
 166
 167 #define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
 168 #define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
 169 #define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
 170 #define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
 171 #define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
 172 #define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
 173 #define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
 174 #define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
 175
 176 #define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
 177 #define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
 178 #define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
 179 #define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
 180 #define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
 181 #define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
 182 #define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
 183 #define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
 184
 185 #define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
 186 #define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
 187 #define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
 188 #define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
 189 #define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
 190 #define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
 191 #define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
 192 #define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
 193
 194 #define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
 195 #define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
 196 #define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
 197 #define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
 198 #define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
 199 #define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
 200 #define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
 201 #define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
 202
 203 /*
 204  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
 205  * series processors.  The UDC for the IXP 4xx series is very similar.
 206  * There are fifteen endpoints, in addition to ep0.
 207  *
 208  * Such controller drivers work with a gadget driver.  The gadget driver
 209  * returns descriptors, implements configuration and data protocols used
 210  * by the host to interact with this device, and allocates endpoints to
 211  * the different protocol interfaces.  The controller driver virtualizes
 212  * usb hardware so that the gadget drivers will be more portable.
 213  *
 214  * This UDC hardware wants to implement a bit too much USB protocol, so
 215  * it constrains the sorts of USB configuration change events that work.
 216  * The errata for these chips are misleading; some "fixed" bugs from
 217  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
 218  *
 219  * Note that the UDC hardware supports DMA (except on IXP) but that's
 220  * not used here.  IN-DMA (to host) is simple enough, when the data is
 221  * suitably aligned (16 bytes) ... the network stack doesn't do that,
 222  * other software can.  OUT-DMA is buggy in most chip versions, as well
 223  * as poorly designed (data toggle not automatic).  So this driver won't
 224  * bother using DMA.  (Mostly-working IN-DMA support was available in
 225  * kernels before 2.6.23, but was never enabled or well tested.)
 226  */
 227
 228 #define DRIVER_VERSION  "30-June-2007"
 229 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
 230
 231
 232 static const char driver_name [] = "pxa25x_udc";
 233
 234 static const char ep0name [] = "ep0";
 235
 236
 237 #ifdef CONFIG_ARCH_IXP4XX
 238
 239 /* cpu-specific register addresses are compiled in to this code */
 240 #ifdef CONFIG_ARCH_PXA
 241 #error "Can't configure both IXP and PXA"
 242 #endif
 243
 244 /* IXP doesn't yet support <linux/clk.h> */
 245 #define clk_get(dev,name)       NULL
 246 #define clk_enable(clk)         do { } while (0)
 247 #define clk_disable(clk)        do { } while (0)
 248 #define clk_put(clk)            do { } while (0)
 249
 250 #endif
 251
 252 #include "pxa25x_udc.h"
 253
 254
 255 #ifdef  CONFIG_USB_PXA25X_SMALL
 256 #define SIZE_STR        " (small)"
 257 #else
 258 #define SIZE_STR        ""
 259 #endif
 260
 261 /* ---------------------------------------------------------------------------
 262  *      endpoint related parts of the api to the usb controller hardware,
 263  *      used by gadget driver; and the inner talker-to-hardware core.
 264  * ---------------------------------------------------------------------------
 265  */
 266
 267 static void pxa25x_ep_fifo_flush (struct usb_ep *ep);
 268 static void nuke (struct pxa25x_ep *, int status);
 269
 270 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
 271 static void pullup_off(void)
 272 {
 273         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 274         int off_level = mach->gpio_pullup_inverted;
 275
 276         if (gpio_is_valid(mach->gpio_pullup))
 277                 gpio_set_value(mach->gpio_pullup, off_level);
 278         else if (mach->udc_command)
 279                 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
 280 }
 281
 282 static void pullup_on(void)
 283 {
 284         struct pxa2xx_udc_mach_info             *mach = the_controller->mach;
 285         int on_level = !mach->gpio_pullup_inverted;
 286
 287         if (gpio_is_valid(mach->gpio_pullup))
 288                 gpio_set_value(mach->gpio_pullup, on_level);
 289         else if (mach->udc_command)
 290                 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
 291 }
 292
 293 #if defined(CONFIG_CPU_BIG_ENDIAN)
 294 /*
 295  * IXP4xx has its buses wired up in a way that relies on never doing any
 296  * byte swaps, independent of whether it runs in big-endian or little-endian
 297  * mode, as explained by Krzysztof Hałasa.
 298  *
 299  * We only support pxa25x in little-endian mode, but it is very likely
 300  * that it works the same way.
 301  */
 302 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val)
 303 {
 304         iowrite32be(val, dev->regs + reg);
 305 }
 306
 307 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg)
 308 {
 309         return ioread32be(dev->regs + reg);
 310 }
 311 #else
 312 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val)
 313 {
 314         writel(val, dev->regs + reg);
 315 }
 316
 317 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg)
 318 {
 319         return readl(dev->regs + reg);
 320 }
 321 #endif
 322
 323 static void pio_irq_enable(struct pxa25x_ep *ep)
 324 {
 325         u32 bEndpointAddress = ep->bEndpointAddress & 0xf;
 326
 327         if (bEndpointAddress < 8)
 328                 udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) &
 329                                                 ~(1 << bEndpointAddress));
 330         else {
 331                 bEndpointAddress -= 8;
 332                 udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) &
 333                                                 ~(1 << bEndpointAddress));
 334         }
 335 }
 336
 337 static void pio_irq_disable(struct pxa25x_ep *ep)
 338 {
 339         u32 bEndpointAddress = ep->bEndpointAddress & 0xf;
 340
 341         if (bEndpointAddress < 8)
 342                 udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) |
 343                                                 (1 << bEndpointAddress));
 344         else {
 345                 bEndpointAddress -= 8;
 346                 udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) |
 347                                                 (1 << bEndpointAddress));
 348         }
 349 }
 350
 351 /* The UDCCR reg contains mask and interrupt status bits,
 352  * so using '|=' isn't safe as it may ack an interrupt.
 353  */
 354 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 355
 356 static inline void udc_set_mask_UDCCR(struct pxa25x_udc *dev, int mask)
 357 {
 358         u32 udccr = udc_get_reg(dev, UDCCR);
 359
 360         udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR);
 361 }
 362
 363 static inline void udc_clear_mask_UDCCR(struct pxa25x_udc *dev, int mask)
 364 {
 365         u32 udccr = udc_get_reg(dev, UDCCR);
 366
 367         udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR);
 368 }
 369
 370 static inline void udc_ack_int_UDCCR(struct pxa25x_udc *dev, int mask)
 371 {
 372         /* udccr contains the bits we dont want to change */
 373         u32 udccr = udc_get_reg(dev, UDCCR) & UDCCR_MASK_BITS;
 374
 375         udc_set_reg(dev, udccr | (mask & ~UDCCR_MASK_BITS), UDCCR);
 376 }
 377
 378 static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *ep)
 379 {
 380         return udc_get_reg(ep->dev, ep->regoff_udccs);
 381 }
 382
 383 static inline void udc_ep_set_UDCCS(struct pxa25x_ep *ep, u32 data)
 384 {
 385         udc_set_reg(ep->dev, data, ep->regoff_udccs);
 386 }
 387
 388 static inline u32 udc_ep0_get_UDCCS(struct pxa25x_udc *dev)
 389 {
 390         return udc_get_reg(dev, UDCCS0);
 391 }
 392
 393 static inline void udc_ep0_set_UDCCS(struct pxa25x_udc *dev, u32 data)
 394 {
 395         udc_set_reg(dev, data, UDCCS0);
 396 }
 397
 398 static inline u32 udc_ep_get_UDDR(struct pxa25x_ep *ep)
 399 {
 400         return udc_get_reg(ep->dev, ep->regoff_uddr);
 401 }
 402
 403 static inline void udc_ep_set_UDDR(struct pxa25x_ep *ep, u32 data)
 404 {
 405         udc_set_reg(ep->dev, data, ep->regoff_uddr);
 406 }
 407
 408 static inline u32 udc_ep_get_UBCR(struct pxa25x_ep *ep)
 409 {
 410         return udc_get_reg(ep->dev, ep->regoff_ubcr);
 411 }
 412
 413 /*
 414  * endpoint enable/disable
 415  *
 416  * we need to verify the descriptors used to enable endpoints.  since pxa25x
 417  * endpoint configurations are fixed, and are pretty much always enabled,
 418  * there's not a lot to manage here.
 419  *
 420  * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
 421  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 422  * for a single interface (with only the default altsetting) and for gadget
 423  * drivers that don't halt endpoints (not reset by set_interface).  that also
 424  * means that if you use ISO, you must violate the USB spec rule that all
 425  * iso endpoints must be in non-default altsettings.
 426  */
 427 static int pxa25x_ep_enable (struct usb_ep *_ep,
 428                 const struct usb_endpoint_descriptor *desc)
 429 {
 430         struct pxa25x_ep        *ep;
 431         struct pxa25x_udc       *dev;
 432
 433         ep = container_of (_ep, struct pxa25x_ep, ep);
 434         if (!_ep || !desc || _ep->name == ep0name
 435                         || desc->bDescriptorType != USB_DT_ENDPOINT
 436                         || ep->bEndpointAddress != desc->bEndpointAddress
 437                         || ep->fifo_size < usb_endpoint_maxp (desc)) {
 438                 DMSG("%s, bad ep or descriptor\n", __func__);
 439                 return -EINVAL;
 440         }
 441
 442         /* xfer types must match, except that interrupt ~= bulk */
 443         if (ep->bmAttributes != desc->bmAttributes
 444                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 445                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 446                 DMSG("%s, %s type mismatch\n", __func__, _ep->name);
 447                 return -EINVAL;
 448         }
 449
 450         /* hardware _could_ do smaller, but driver doesn't */
 451         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 452                                 && usb_endpoint_maxp (desc)
 453                                                 != BULK_FIFO_SIZE)
 454                         || !desc->wMaxPacketSize) {
 455                 DMSG("%s, bad %s maxpacket\n", __func__, _ep->name);
 456                 return -ERANGE;
 457         }
 458
 459         dev = ep->dev;
 460         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 461                 DMSG("%s, bogus device state\n", __func__);
 462                 return -ESHUTDOWN;
 463         }
 464
 465         ep->ep.desc = desc;
 466         ep->stopped = 0;
 467         ep->pio_irqs = 0;
 468         ep->ep.maxpacket = usb_endpoint_maxp (desc);
 469
 470         /* flush fifo (mostly for OUT buffers) */
 471         pxa25x_ep_fifo_flush (_ep);
 472
 473         /* ... reset halt state too, if we could ... */
 474
 475         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 476         return 0;
 477 }
 478
 479 static int pxa25x_ep_disable (struct usb_ep *_ep)
 480 {
 481         struct pxa25x_ep        *ep;
 482         unsigned long           flags;
 483
 484         ep = container_of (_ep, struct pxa25x_ep, ep);
 485         if (!_ep || !ep->ep.desc) {
 486                 DMSG("%s, %s not enabled\n", __func__,
 487                         _ep ? ep->ep.name : NULL);
 488                 return -EINVAL;
 489         }
 490         local_irq_save(flags);
 491
 492         nuke (ep, -ESHUTDOWN);
 493
 494         /* flush fifo (mostly for IN buffers) */
 495         pxa25x_ep_fifo_flush (_ep);
 496
 497         ep->ep.desc = NULL;
 498         ep->stopped = 1;
 499
 500         local_irq_restore(flags);
 501         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 502         return 0;
 503 }
 504
 505 /*-------------------------------------------------------------------------*/
 506
 507 /* for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
 508  * must still pass correctly initialized endpoints, since other controller
 509  * drivers may care about how it's currently set up (dma issues etc).
 510  */
 511
 512 /*
 513  *      pxa25x_ep_alloc_request - allocate a request data structure
 514  */
 515 static struct usb_request *
 516 pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
 517 {
 518         struct pxa25x_request *req;
 519
 520         req = kzalloc(sizeof(*req), gfp_flags);
 521         if (!req)
 522                 return NULL;
 523
 524         INIT_LIST_HEAD (&req->queue);
 525         return &req->req;
 526 }
 527
 528
 529 /*
 530  *      pxa25x_ep_free_request - deallocate a request data structure
 531  */
 532 static void
 533 pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 534 {
 535         struct pxa25x_request   *req;
 536
 537         req = container_of (_req, struct pxa25x_request, req);
 538         WARN_ON(!list_empty (&req->queue));
 539         kfree(req);
 540 }
 541
 542 /*-------------------------------------------------------------------------*/
 543
 544 /*
 545  *      done - retire a request; caller blocked irqs
 546  */
 547 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
 548 {
 549         unsigned                stopped = ep->stopped;
 550
 551         list_del_init(&req->queue);
 552
 553         if (likely (req->req.status == -EINPROGRESS))
 554                 req->req.status = status;
 555         else
 556                 status = req->req.status;
 557
 558         if (status && status != -ESHUTDOWN)
 559                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 560                         ep->ep.name, &req->req, status,
 561                         req->req.actual, req->req.length);
 562
 563         /* don't modify queue heads during completion callback */
 564         ep->stopped = 1;
 565         usb_gadget_giveback_request(&ep->ep, &req->req);
 566         ep->stopped = stopped;
 567 }
 568
 569
 570 static inline void ep0_idle (struct pxa25x_udc *dev)
 571 {
 572         dev->ep0state = EP0_IDLE;
 573 }
 574
 575 static int
 576 write_packet(struct pxa25x_ep *ep, struct pxa25x_request *req, unsigned max)
 577 {
 578         u8              *buf;
 579         unsigned        length, count;
 580
 581         buf = req->req.buf + req->req.actual;
 582         prefetch(buf);
 583
 584         /* how big will this packet be? */
 585         length = min(req->req.length - req->req.actual, max);
 586         req->req.actual += length;
 587
 588         count = length;
 589         while (likely(count--))
 590                 udc_ep_set_UDDR(ep, *buf++);
 591
 592         return length;
 593 }
 594
 595 /*
 596  * write to an IN endpoint fifo, as many packets as possible.
 597  * irqs will use this to write the rest later.
 598  * caller guarantees at least one packet buffer is ready (or a zlp).
 599  */
 600 static int
 601 write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 602 {
 603         unsigned                max;
 604
 605         max = usb_endpoint_maxp(ep->ep.desc);
 606         do {
 607                 unsigned        count;
 608                 int             is_last, is_short;
 609
 610                 count = write_packet(ep, req, max);
 611
 612                 /* last packet is usually short (or a zlp) */
 613                 if (unlikely (count != max))
 614                         is_last = is_short = 1;
 615                 else {
 616                         if (likely(req->req.length != req->req.actual)
 617                                         || req->req.zero)
 618                                 is_last = 0;
 619                         else
 620                                 is_last = 1;
 621                         /* interrupt/iso maxpacket may not fill the fifo */
 622                         is_short = unlikely (max < ep->fifo_size);
 623                 }
 624
 625                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 626                         ep->ep.name, count,
 627                         is_last ? "/L" : "", is_short ? "/S" : "",
 628                         req->req.length - req->req.actual, req);
 629
 630                 /* let loose that packet. maybe try writing another one,
 631                  * double buffering might work.  TSP, TPC, and TFS
 632                  * bit values are the same for all normal IN endpoints.
 633                  */
 634                 udc_ep_set_UDCCS(ep, UDCCS_BI_TPC);
 635                 if (is_short)
 636                         udc_ep_set_UDCCS(ep, UDCCS_BI_TSP);
 637
 638                 /* requests complete when all IN data is in the FIFO */
 639                 if (is_last) {
 640                         done (ep, req, 0);
 641                         if (list_empty(&ep->queue))
 642                                 pio_irq_disable(ep);
 643                         return 1;
 644                 }
 645
 646                 // TODO experiment: how robust can fifo mode tweaking be?
 647                 // double buffering is off in the default fifo mode, which
 648                 // prevents TFS from being set here.
 649
 650         } while (udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS);
 651         return 0;
 652 }
 653
 654 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 655  * ep0 data stage.  these chips want very simple state transitions.
 656  */
 657 static inline
 658 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
 659 {
 660         udc_ep0_set_UDCCS(dev, flags|UDCCS0_SA|UDCCS0_OPR);
 661         udc_set_reg(dev, USIR0, USIR0_IR0);
 662         dev->req_pending = 0;
 663         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 664                 __func__, tag, udc_ep0_get_UDCCS(dev), flags);
 665 }
 666
 667 static int
 668 write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 669 {
 670         struct pxa25x_udc *dev = ep->dev;
 671         unsigned        count;
 672         int             is_short;
 673
 674         count = write_packet(&dev->ep[0], req, EP0_FIFO_SIZE);
 675         ep->dev->stats.write.bytes += count;
 676
 677         /* last packet "must be" short (or a zlp) */
 678         is_short = (count != EP0_FIFO_SIZE);
 679
 680         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 681                 req->req.length - req->req.actual, req);
 682
 683         if (unlikely (is_short)) {
 684                 if (ep->dev->req_pending)
 685                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 686                 else
 687                         udc_ep0_set_UDCCS(dev, UDCCS0_IPR);
 688
 689                 count = req->req.length;
 690                 done (ep, req, 0);
 691                 ep0_idle(ep->dev);
 692 #ifndef CONFIG_ARCH_IXP4XX
 693 #if 1
 694                 /* This seems to get rid of lost status irqs in some cases:
 695                  * host responds quickly, or next request involves config
 696                  * change automagic, or should have been hidden, or ...
 697                  *
 698                  * FIXME get rid of all udelays possible...
 699                  */
 700                 if (count >= EP0_FIFO_SIZE) {
 701                         count = 100;
 702                         do {
 703                                 if ((udc_ep0_get_UDCCS(dev) & UDCCS0_OPR) != 0) {
 704                                         /* clear OPR, generate ack */
 705                                         udc_ep0_set_UDCCS(dev, UDCCS0_OPR);
 706                                         break;
 707                                 }
 708                                 count--;
 709                                 udelay(1);
 710                         } while (count);
 711                 }
 712 #endif
 713 #endif
 714         } else if (ep->dev->req_pending)
 715                 ep0start(ep->dev, 0, "IN");
 716         return is_short;
 717 }
 718
 719
 720 /*
 721  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 722  * transfers and put them into the request.  caller should have made
 723  * sure there's at least one packet ready.
 724  *
 725  * returns true if the request completed because of short packet or the
 726  * request buffer having filled (and maybe overran till end-of-packet).
 727  */
 728 static int
 729 read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 730 {
 731         for (;;) {
 732                 u32             udccs;
 733                 u8              *buf;
 734                 unsigned        bufferspace, count, is_short;
 735
 736                 /* make sure there's a packet in the FIFO.
 737                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 738                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 739                  */
 740                 udccs = udc_ep_get_UDCCS(ep);
 741                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 742                         break;
 743                 buf = req->req.buf + req->req.actual;
 744                 prefetchw(buf);
 745                 bufferspace = req->req.length - req->req.actual;
 746
 747                 /* read all bytes from this packet */
 748                 if (likely (udccs & UDCCS_BO_RNE)) {
 749                         count = 1 + (0x0ff & udc_ep_get_UBCR(ep));
 750                         req->req.actual += min (count, bufferspace);
 751                 } else /* zlp */
 752                         count = 0;
 753                 is_short = (count < ep->ep.maxpacket);
 754                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 755                         ep->ep.name, udccs, count,
 756                         is_short ? "/S" : "",
 757                         req, req->req.actual, req->req.length);
 758                 while (likely (count-- != 0)) {
 759                         u8      byte = (u8) udc_ep_get_UDDR(ep);
 760
 761                         if (unlikely (bufferspace == 0)) {
 762                                 /* this happens when the driver's buffer
 763                                  * is smaller than what the host sent.
 764                                  * discard the extra data.
 765                                  */
 766                                 if (req->req.status != -EOVERFLOW)
 767                                         DMSG("%s overflow %d\n",
 768                                                 ep->ep.name, count);
 769                                 req->req.status = -EOVERFLOW;
 770                         } else {
 771                                 *buf++ = byte;
 772                                 bufferspace--;
 773                         }
 774                 }
 775                 udc_ep_set_UDCCS(ep, UDCCS_BO_RPC);
 776                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 777
 778                 /* iso is one request per packet */
 779                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 780                         if (udccs & UDCCS_IO_ROF)
 781                                 req->req.status = -EHOSTUNREACH;
 782                         /* more like "is_done" */
 783                         is_short = 1;
 784                 }
 785
 786                 /* completion */
 787                 if (is_short || req->req.actual == req->req.length) {
 788                         done (ep, req, 0);
 789                         if (list_empty(&ep->queue))
 790                                 pio_irq_disable(ep);
 791                         return 1;
 792                 }
 793
 794                 /* finished that packet.  the next one may be waiting... */
 795         }
 796         return 0;
 797 }
 798
 799 /*
 800  * special ep0 version of the above.  no UBCR0 or double buffering; status
 801  * handshaking is magic.  most device protocols don't need control-OUT.
 802  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 803  * protocols do use them.
 804  */
 805 static int
 806 read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
 807 {
 808         u8              *buf, byte;
 809         unsigned        bufferspace;
 810
 811         buf = req->req.buf + req->req.actual;
 812         bufferspace = req->req.length - req->req.actual;
 813
 814         while (udc_ep_get_UDCCS(ep) & UDCCS0_RNE) {
 815                 byte = (u8) UDDR0;
 816
 817                 if (unlikely (bufferspace == 0)) {
 818                         /* this happens when the driver's buffer
 819                          * is smaller than what the host sent.
 820                          * discard the extra data.
 821                          */
 822                         if (req->req.status != -EOVERFLOW)
 823                                 DMSG("%s overflow\n", ep->ep.name);
 824                         req->req.status = -EOVERFLOW;
 825                 } else {
 826                         *buf++ = byte;
 827                         req->req.actual++;
 828                         bufferspace--;
 829                 }
 830         }
 831
 832         udc_ep_set_UDCCS(ep, UDCCS0_OPR | UDCCS0_IPR);
 833
 834         /* completion */
 835         if (req->req.actual >= req->req.length)
 836                 return 1;
 837
 838         /* finished that packet.  the next one may be waiting... */
 839         return 0;
 840 }
 841
 842 /*-------------------------------------------------------------------------*/
 843
 844 static int
 845 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 846 {
 847         struct pxa25x_request   *req;
 848         struct pxa25x_ep        *ep;
 849         struct pxa25x_udc       *dev;
 850         unsigned long           flags;
 851
 852         req = container_of(_req, struct pxa25x_request, req);
 853         if (unlikely (!_req || !_req->complete || !_req->buf
 854                         || !list_empty(&req->queue))) {
 855                 DMSG("%s, bad params\n", __func__);
 856                 return -EINVAL;
 857         }
 858
 859         ep = container_of(_ep, struct pxa25x_ep, ep);
 860         if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
 861                 DMSG("%s, bad ep\n", __func__);
 862                 return -EINVAL;
 863         }
 864
 865         dev = ep->dev;
 866         if (unlikely (!dev->driver
 867                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 868                 DMSG("%s, bogus device state\n", __func__);
 869                 return -ESHUTDOWN;
 870         }
 871
 872         /* iso is always one packet per request, that's the only way
 873          * we can report per-packet status.  that also helps with dma.
 874          */
 875         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 876                         && req->req.length > usb_endpoint_maxp(ep->ep.desc)))
 877                 return -EMSGSIZE;
 878
 879         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 880                 _ep->name, _req, _req->length, _req->buf);
 881
 882         local_irq_save(flags);
 883
 884         _req->status = -EINPROGRESS;
 885         _req->actual = 0;
 886
 887         /* kickstart this i/o queue? */
 888         if (list_empty(&ep->queue) && !ep->stopped) {
 889                 if (ep->ep.desc == NULL/* ep0 */) {
 890                         unsigned        length = _req->length;
 891
 892                         switch (dev->ep0state) {
 893                         case EP0_IN_DATA_PHASE:
 894                                 dev->stats.write.ops++;
 895                                 if (write_ep0_fifo(ep, req))
 896                                         req = NULL;
 897                                 break;
 898
 899                         case EP0_OUT_DATA_PHASE:
 900                                 dev->stats.read.ops++;
 901                                 /* messy ... */
 902                                 if (dev->req_config) {
 903                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 904                                                 dev->has_cfr ?  "" : " raced");
 905                                         if (dev->has_cfr)
 906                                                 udc_set_reg(dev, UDCCFR, UDCCFR_AREN |
 907                                                             UDCCFR_ACM | UDCCFR_MB1);
 908                                         done(ep, req, 0);
 909                                         dev->ep0state = EP0_END_XFER;
 910                                         local_irq_restore (flags);
 911                                         return 0;
 912                                 }
 913                                 if (dev->req_pending)
 914                                         ep0start(dev, UDCCS0_IPR, "OUT");
 915                                 if (length == 0 || ((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0
 916                                                 && read_ep0_fifo(ep, req))) {
 917                                         ep0_idle(dev);
 918                                         done(ep, req, 0);
 919                                         req = NULL;
 920                                 }
 921                                 break;
 922
 923                         default:
 924                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 925                                 local_irq_restore (flags);
 926                                 return -EL2HLT;
 927                         }
 928                 /* can the FIFO can satisfy the request immediately? */
 929                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
 930                         if ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) != 0
 931                                         && write_fifo(ep, req))
 932                                 req = NULL;
 933                 } else if ((udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) != 0
 934                                 && read_fifo(ep, req)) {
 935                         req = NULL;
 936                 }
 937
 938                 if (likely(req && ep->ep.desc))
 939                         pio_irq_enable(ep);
 940         }
 941
 942         /* pio or dma irq handler advances the queue. */
 943         if (likely(req != NULL))
 944                 list_add_tail(&req->queue, &ep->queue);
 945         local_irq_restore(flags);
 946
 947         return 0;
 948 }
 949
 950
 951 /*
 952  *      nuke - dequeue ALL requests
 953  */
 954 static void nuke(struct pxa25x_ep *ep, int status)
 955 {
 956         struct pxa25x_request *req;
 957
 958         /* called with irqs blocked */
 959         while (!list_empty(&ep->queue)) {
 960                 req = list_entry(ep->queue.next,
 961                                 struct pxa25x_request,
 962                                 queue);
 963                 done(ep, req, status);
 964         }
 965         if (ep->ep.desc)
 966                 pio_irq_disable(ep);
 967 }
 968
 969
 970 /* dequeue JUST ONE request */
 971 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 972 {
 973         struct pxa25x_ep        *ep;
 974         struct pxa25x_request   *req;
 975         unsigned long           flags;
 976
 977         ep = container_of(_ep, struct pxa25x_ep, ep);
 978         if (!_ep || ep->ep.name == ep0name)
 979                 return -EINVAL;
 980
 981         local_irq_save(flags);
 982
 983         /* make sure it's actually queued on this endpoint */
 984         list_for_each_entry (req, &ep->queue, queue) {
 985                 if (&req->req == _req)
 986                         break;
 987         }
 988         if (&req->req != _req) {
 989                 local_irq_restore(flags);
 990                 return -EINVAL;
 991         }
 992
 993         done(ep, req, -ECONNRESET);
 994
 995         local_irq_restore(flags);
 996         return 0;
 997 }
 998
 999 /*-------------------------------------------------------------------------*/
1000
1001 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
1002 {
1003         struct pxa25x_ep        *ep;
1004         unsigned long           flags;
1005
1006         ep = container_of(_ep, struct pxa25x_ep, ep);
1007         if (unlikely (!_ep
1008                         || (!ep->ep.desc && ep->ep.name != ep0name))
1009                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1010                 DMSG("%s, bad ep\n", __func__);
1011                 return -EINVAL;
1012         }
1013         if (value == 0) {
1014                 /* this path (reset toggle+halt) is needed to implement
1015                  * SET_INTERFACE on normal hardware.  but it can't be
1016                  * done from software on the PXA UDC, and the hardware
1017                  * forgets to do it as part of SET_INTERFACE automagic.
1018                  */
1019                 DMSG("only host can clear %s halt\n", _ep->name);
1020                 return -EROFS;
1021         }
1022
1023         local_irq_save(flags);
1024
1025         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1026                         && ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) == 0
1027                            || !list_empty(&ep->queue))) {
1028                 local_irq_restore(flags);
1029                 return -EAGAIN;
1030         }
1031
1032         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1033         udc_ep_set_UDCCS(ep, UDCCS_BI_FST|UDCCS_BI_FTF);
1034
1035         /* ep0 needs special care */
1036         if (!ep->ep.desc) {
1037                 start_watchdog(ep->dev);
1038                 ep->dev->req_pending = 0;
1039                 ep->dev->ep0state = EP0_STALL;
1040
1041         /* and bulk/intr endpoints like dropping stalls too */
1042         } else {
1043                 unsigned i;
1044                 for (i = 0; i < 1000; i += 20) {
1045                         if (udc_ep_get_UDCCS(ep) & UDCCS_BI_SST)
1046                                 break;
1047                         udelay(20);
1048                 }
1049         }
1050         local_irq_restore(flags);
1051
1052         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1053         return 0;
1054 }
1055
1056 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
1057 {
1058         struct pxa25x_ep        *ep;
1059
1060         ep = container_of(_ep, struct pxa25x_ep, ep);
1061         if (!_ep) {
1062                 DMSG("%s, bad ep\n", __func__);
1063                 return -ENODEV;
1064         }
1065         /* pxa can't report unclaimed bytes from IN fifos */
1066         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1067                 return -EOPNOTSUPP;
1068         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1069                         || (udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) == 0)
1070                 return 0;
1071         else
1072                 return (udc_ep_get_UBCR(ep) & 0xfff) + 1;
1073 }
1074
1075 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
1076 {
1077         struct pxa25x_ep        *ep;
1078
1079         ep = container_of(_ep, struct pxa25x_ep, ep);
1080         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1081                 DMSG("%s, bad ep\n", __func__);
1082                 return;
1083         }
1084
1085         /* toggle and halt bits stay unchanged */
1086
1087         /* for OUT, just read and discard the FIFO contents. */
1088         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1089                 while (((udc_ep_get_UDCCS(ep)) & UDCCS_BO_RNE) != 0)
1090                         (void)udc_ep_get_UDDR(ep);
1091                 return;
1092         }
1093
1094         /* most IN status is the same, but ISO can't stall */
1095         udc_ep_set_UDCCS(ep, UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1096                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1097                         ? 0 : UDCCS_BI_SST));
1098 }
1099
1100
1101 static struct usb_ep_ops pxa25x_ep_ops = {
1102         .enable         = pxa25x_ep_enable,
1103         .disable        = pxa25x_ep_disable,
1104
1105         .alloc_request  = pxa25x_ep_alloc_request,
1106         .free_request   = pxa25x_ep_free_request,
1107
1108         .queue          = pxa25x_ep_queue,
1109         .dequeue        = pxa25x_ep_dequeue,
1110
1111         .set_halt       = pxa25x_ep_set_halt,
1112         .fifo_status    = pxa25x_ep_fifo_status,
1113         .fifo_flush     = pxa25x_ep_fifo_flush,
1114 };
1115
1116
1117 /* ---------------------------------------------------------------------------
1118  *      device-scoped parts of the api to the usb controller hardware
1119  * ---------------------------------------------------------------------------
1120  */
1121
1122 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1123 {
1124         struct pxa25x_udc       *dev;
1125
1126         dev = container_of(_gadget, struct pxa25x_udc, gadget);
1127         return ((udc_get_reg(dev, UFNRH) & 0x07) << 8) |
1128                 (udc_get_reg(dev, UFNRL) & 0xff);
1129 }
1130
1131 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1132 {
1133         struct pxa25x_udc       *udc;
1134
1135         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1136
1137         /* host may not have enabled remote wakeup */
1138         if ((udc_ep0_get_UDCCS(udc) & UDCCS0_DRWF) == 0)
1139                 return -EHOSTUNREACH;
1140         udc_set_mask_UDCCR(udc, UDCCR_RSM);
1141         return 0;
1142 }
1143
1144 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1145 static void udc_enable (struct pxa25x_udc *);
1146 static void udc_disable(struct pxa25x_udc *);
1147
1148 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1149  * in active use.
1150  */
1151 static int pullup(struct pxa25x_udc *udc)
1152 {
1153         int is_active = udc->vbus && udc->pullup && !udc->suspended;
1154         DMSG("%s\n", is_active ? "active" : "inactive");
1155         if (is_active) {
1156                 if (!udc->active) {
1157                         udc->active = 1;
1158                         /* Enable clock for USB device */
1159                         clk_enable(udc->clk);
1160                         udc_enable(udc);
1161                 }
1162         } else {
1163                 if (udc->active) {
1164                         if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1165                                 DMSG("disconnect %s\n", udc->driver
1166                                         ? udc->driver->driver.name
1167                                         : "(no driver)");
1168                                 stop_activity(udc, udc->driver);
1169                         }
1170                         udc_disable(udc);
1171                         /* Disable clock for USB device */
1172                         clk_disable(udc->clk);
1173                         udc->active = 0;
1174                 }
1175
1176         }
1177         return 0;
1178 }
1179
1180 /* VBUS reporting logically comes from a transceiver */
1181 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1182 {
1183         struct pxa25x_udc       *udc;
1184
1185         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1186         udc->vbus = is_active;
1187         DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
1188         pullup(udc);
1189         return 0;
1190 }
1191
1192 /* drivers may have software control over D+ pullup */
1193 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1194 {
1195         struct pxa25x_udc       *udc;
1196
1197         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1198
1199         /* not all boards support pullup control */
1200         if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
1201                 return -EOPNOTSUPP;
1202
1203         udc->pullup = (is_active != 0);
1204         pullup(udc);
1205         return 0;
1206 }
1207
1208 /* boards may consume current from VBUS, up to 100-500mA based on config.
1209  * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1210  * violate USB specs.
1211  */
1212 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1213 {
1214         struct pxa25x_udc       *udc;
1215
1216         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1217
1218         if (!IS_ERR_OR_NULL(udc->transceiver))
1219                 return usb_phy_set_power(udc->transceiver, mA);
1220         return -EOPNOTSUPP;
1221 }
1222
1223 static int pxa25x_udc_start(struct usb_gadget *g,
1224                 struct usb_gadget_driver *driver);
1225 static int pxa25x_udc_stop(struct usb_gadget *g);
1226
1227 static const struct usb_gadget_ops pxa25x_udc_ops = {
1228         .get_frame      = pxa25x_udc_get_frame,
1229         .wakeup         = pxa25x_udc_wakeup,
1230         .vbus_session   = pxa25x_udc_vbus_session,
1231         .pullup         = pxa25x_udc_pullup,
1232         .vbus_draw      = pxa25x_udc_vbus_draw,
1233         .udc_start      = pxa25x_udc_start,
1234         .udc_stop       = pxa25x_udc_stop,
1235 };
1236
1237 /*-------------------------------------------------------------------------*/
1238
1239 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1240
1241 static int
1242 udc_seq_show(struct seq_file *m, void *_d)
1243 {
1244         struct pxa25x_udc       *dev = m->private;
1245         unsigned long           flags;
1246         int                     i;
1247         u32                     tmp;
1248
1249         local_irq_save(flags);
1250
1251         /* basic device status */
1252         seq_printf(m, DRIVER_DESC "\n"
1253                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1254                 driver_name, DRIVER_VERSION SIZE_STR "(pio)",
1255                 dev->driver ? dev->driver->driver.name : "(none)",
1256                 dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected");
1257
1258         /* registers for device and ep0 */
1259         seq_printf(m,
1260                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1261                 udc_get_reg(dev, UICR1), udc_get_reg(dev, UICR0),
1262                 udc_get_reg(dev, USIR1), udc_get_reg(dev, USIR0),
1263                 udc_get_reg(dev, UFNRH), udc_get_reg(dev, UFNRL));
1264
1265         tmp = udc_get_reg(dev, UDCCR);
1266         seq_printf(m,
1267                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1268                 (tmp & UDCCR_REM) ? " rem" : "",
1269                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1270                 (tmp & UDCCR_SRM) ? " srm" : "",
1271                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1272                 (tmp & UDCCR_RESIR) ? " resir" : "",
1273                 (tmp & UDCCR_RSM) ? " rsm" : "",
1274                 (tmp & UDCCR_UDA) ? " uda" : "",
1275                 (tmp & UDCCR_UDE) ? " ude" : "");
1276
1277         tmp = udc_ep0_get_UDCCS(dev);
1278         seq_printf(m,
1279                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1280                 (tmp & UDCCS0_SA) ? " sa" : "",
1281                 (tmp & UDCCS0_RNE) ? " rne" : "",
1282                 (tmp & UDCCS0_FST) ? " fst" : "",
1283                 (tmp & UDCCS0_SST) ? " sst" : "",
1284                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1285                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1286                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1287                 (tmp & UDCCS0_OPR) ? " opr" : "");
1288
1289         if (dev->has_cfr) {
1290                 tmp = udc_get_reg(dev, UDCCFR);
1291                 seq_printf(m,
1292                         "udccfr %02X =%s%s\n", tmp,
1293                         (tmp & UDCCFR_AREN) ? " aren" : "",
1294                         (tmp & UDCCFR_ACM) ? " acm" : "");
1295         }
1296
1297         if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver)
1298                 goto done;
1299
1300         seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1301                 dev->stats.write.bytes, dev->stats.write.ops,
1302                 dev->stats.read.bytes, dev->stats.read.ops,
1303                 dev->stats.irqs);
1304
1305         /* dump endpoint queues */
1306         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1307                 struct pxa25x_ep        *ep = &dev->ep [i];
1308                 struct pxa25x_request   *req;
1309
1310                 if (i != 0) {
1311                         const struct usb_endpoint_descriptor    *desc;
1312
1313                         desc = ep->ep.desc;
1314                         if (!desc)
1315                                 continue;
1316                         tmp = udc_ep_get_UDCCS(&dev->ep[i]);
1317                         seq_printf(m,
1318                                 "%s max %d %s udccs %02x irqs %lu\n",
1319                                 ep->ep.name, usb_endpoint_maxp(desc),
1320                                 "pio", tmp, ep->pio_irqs);
1321                         /* TODO translate all five groups of udccs bits! */
1322
1323                 } else /* ep0 should only have one transfer queued */
1324                         seq_printf(m, "ep0 max 16 pio irqs %lu\n",
1325                                 ep->pio_irqs);
1326
1327                 if (list_empty(&ep->queue)) {
1328                         seq_printf(m, "\t(nothing queued)\n");
1329                         continue;
1330                 }
1331                 list_for_each_entry(req, &ep->queue, queue) {
1332                         seq_printf(m,
1333                                         "\treq %p len %d/%d buf %p\n",
1334                                         &req->req, req->req.actual,
1335                                         req->req.length, req->req.buf);
1336                 }
1337         }
1338
1339 done:
1340         local_irq_restore(flags);
1341         return 0;
1342 }
1343
1344 static int
1345 udc_debugfs_open(struct inode *inode, struct file *file)
1346 {
1347         return single_open(file, udc_seq_show, inode->i_private);
1348 }
1349
1350 static const struct file_operations debug_fops = {
1351         .open           = udc_debugfs_open,
1352         .read           = seq_read,
1353         .llseek         = seq_lseek,
1354         .release        = single_release,
1355         .owner          = THIS_MODULE,
1356 };
1357
1358 #define create_debug_files(dev) \
1359         do { \
1360                 dev->debugfs_udc = debugfs_create_file(dev->gadget.name, \
1361                         S_IRUGO, NULL, dev, &debug_fops); \
1362         } while (0)
1363 #define remove_debug_files(dev) debugfs_remove(dev->debugfs_udc)
1364
1365 #else   /* !CONFIG_USB_GADGET_DEBUG_FILES */
1366
1367 #define create_debug_files(dev) do {} while (0)
1368 #define remove_debug_files(dev) do {} while (0)
1369
1370 #endif  /* CONFIG_USB_GADGET_DEBUG_FILES */
1371
1372 /*-------------------------------------------------------------------------*/
1373
1374 /*
1375  *      udc_disable - disable USB device controller
1376  */
1377 static void udc_disable(struct pxa25x_udc *dev)
1378 {
1379         /* block all irqs */
1380         udc_set_mask_UDCCR(dev, UDCCR_SRM|UDCCR_REM);
1381         udc_set_reg(dev, UICR0, 0xff);
1382         udc_set_reg(dev, UICR1, 0xff);
1383         udc_set_reg(dev, UFNRH, UFNRH_SIM);
1384
1385         /* if hardware supports it, disconnect from usb */
1386         pullup_off();
1387
1388         udc_clear_mask_UDCCR(dev, UDCCR_UDE);
1389
1390         ep0_idle (dev);
1391         dev->gadget.speed = USB_SPEED_UNKNOWN;
1392 }
1393
1394
1395 /*
1396  *      udc_reinit - initialize software state
1397  */
1398 static void udc_reinit(struct pxa25x_udc *dev)
1399 {
1400         u32     i;
1401
1402         /* device/ep0 records init */
1403         INIT_LIST_HEAD (&dev->gadget.ep_list);
1404         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1405         dev->ep0state = EP0_IDLE;
1406         dev->gadget.quirk_altset_not_supp = 1;
1407
1408         /* basic endpoint records init */
1409         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1410                 struct pxa25x_ep *ep = &dev->ep[i];
1411
1412                 if (i != 0)
1413                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1414
1415                 ep->ep.desc = NULL;
1416                 ep->stopped = 0;
1417                 INIT_LIST_HEAD (&ep->queue);
1418                 ep->pio_irqs = 0;
1419                 usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
1420         }
1421
1422         /* the rest was statically initialized, and is read-only */
1423 }
1424
1425 /* until it's enabled, this UDC should be completely invisible
1426  * to any USB host.
1427  */
1428 static void udc_enable (struct pxa25x_udc *dev)
1429 {
1430         udc_clear_mask_UDCCR(dev, UDCCR_UDE);
1431
1432         /* try to clear these bits before we enable the udc */
1433         udc_ack_int_UDCCR(dev, UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1434
1435         ep0_idle(dev);
1436         dev->gadget.speed = USB_SPEED_UNKNOWN;
1437         dev->stats.irqs = 0;
1438
1439         /*
1440          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1441          * - enable UDC
1442          * - if RESET is already in progress, ack interrupt
1443          * - unmask reset interrupt
1444          */
1445         udc_set_mask_UDCCR(dev, UDCCR_UDE);
1446         if (!(udc_get_reg(dev, UDCCR) & UDCCR_UDA))
1447                 udc_ack_int_UDCCR(dev, UDCCR_RSTIR);
1448
1449         if (dev->has_cfr /* UDC_RES2 is defined */) {
1450                 /* pxa255 (a0+) can avoid a set_config race that could
1451                  * prevent gadget drivers from configuring correctly
1452                  */
1453                 udc_set_reg(dev, UDCCFR, UDCCFR_ACM | UDCCFR_MB1);
1454         } else {
1455                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1456                  * which could result in missing packets and interrupts.
1457                  * supposedly one bit per endpoint, controlling whether it
1458                  * double buffers or not; ACM/AREN bits fit into the holes.
1459                  * zero bits (like USIR0_IRx) disable double buffering.
1460                  */
1461                 udc_set_reg(dev, UDC_RES1, 0x00);
1462                 udc_set_reg(dev, UDC_RES2, 0x00);
1463         }
1464
1465         /* enable suspend/resume and reset irqs */
1466         udc_clear_mask_UDCCR(dev, UDCCR_SRM | UDCCR_REM);
1467
1468         /* enable ep0 irqs */
1469         udc_set_reg(dev, UICR0, udc_get_reg(dev, UICR0) & ~UICR0_IM0);
1470
1471         /* if hardware supports it, pullup D+ and wait for reset */
1472         pullup_on();
1473 }
1474
1475
1476 /* when a driver is successfully registered, it will receive
1477  * control requests including set_configuration(), which enables
1478  * non-control requests.  then usb traffic follows until a
1479  * disconnect is reported.  then a host may connect again, or
1480  * the driver might get unbound.
1481  */
1482 static int pxa25x_udc_start(struct usb_gadget *g,
1483                 struct usb_gadget_driver *driver)
1484 {
1485         struct pxa25x_udc       *dev = to_pxa25x(g);
1486         int                     retval;
1487
1488         /* first hook up the driver ... */
1489         dev->driver = driver;
1490         dev->pullup = 1;
1491
1492         /* ... then enable host detection and ep0; and we're ready
1493          * for set_configuration as well as eventual disconnect.
1494          */
1495         /* connect to bus through transceiver */
1496         if (!IS_ERR_OR_NULL(dev->transceiver)) {
1497                 retval = otg_set_peripheral(dev->transceiver->otg,
1498                                                 &dev->gadget);
1499                 if (retval)
1500                         goto bind_fail;
1501         }
1502
1503         dump_state(dev);
1504         return 0;
1505 bind_fail:
1506         return retval;
1507 }
1508
1509 static void
1510 reset_gadget(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1511 {
1512         int i;
1513
1514         /* don't disconnect drivers more than once */
1515         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1516                 driver = NULL;
1517         dev->gadget.speed = USB_SPEED_UNKNOWN;
1518
1519         /* prevent new request submissions, kill any outstanding requests  */
1520         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1521                 struct pxa25x_ep *ep = &dev->ep[i];
1522
1523                 ep->stopped = 1;
1524                 nuke(ep, -ESHUTDOWN);
1525         }
1526         del_timer_sync(&dev->timer);
1527
1528         /* report reset; the driver is already quiesced */
1529         if (driver)
1530                 usb_gadget_udc_reset(&dev->gadget, driver);
1531
1532         /* re-init driver-visible data structures */
1533         udc_reinit(dev);
1534 }
1535
1536 static void
1537 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1538 {
1539         int i;
1540
1541         /* don't disconnect drivers more than once */
1542         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1543                 driver = NULL;
1544         dev->gadget.speed = USB_SPEED_UNKNOWN;
1545
1546         /* prevent new request submissions, kill any outstanding requests  */
1547         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1548                 struct pxa25x_ep *ep = &dev->ep[i];
1549
1550                 ep->stopped = 1;
1551                 nuke(ep, -ESHUTDOWN);
1552         }
1553         del_timer_sync(&dev->timer);
1554
1555         /* report disconnect; the driver is already quiesced */
1556         if (driver)
1557                 driver->disconnect(&dev->gadget);
1558
1559         /* re-init driver-visible data structures */
1560         udc_reinit(dev);
1561 }
1562
1563 static int pxa25x_udc_stop(struct usb_gadget*g)
1564 {
1565         struct pxa25x_udc       *dev = to_pxa25x(g);
1566
1567         local_irq_disable();
1568         dev->pullup = 0;
1569         stop_activity(dev, NULL);
1570         local_irq_enable();
1571
1572         if (!IS_ERR_OR_NULL(dev->transceiver))
1573                 (void) otg_set_peripheral(dev->transceiver->otg, NULL);
1574
1575         dev->driver = NULL;
1576
1577         dump_state(dev);
1578
1579         return 0;
1580 }
1581
1582 /*-------------------------------------------------------------------------*/
1583
1584 #ifdef CONFIG_ARCH_LUBBOCK
1585
1586 /* Lubbock has separate connect and disconnect irqs.  More typical designs
1587  * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1588  */
1589
1590 static irqreturn_t
1591 lubbock_vbus_irq(int irq, void *_dev)
1592 {
1593         struct pxa25x_udc       *dev = _dev;
1594         int                     vbus;
1595
1596         dev->stats.irqs++;
1597         switch (irq) {
1598         case LUBBOCK_USB_IRQ:
1599                 vbus = 1;
1600                 disable_irq(LUBBOCK_USB_IRQ);
1601                 enable_irq(LUBBOCK_USB_DISC_IRQ);
1602                 break;
1603         case LUBBOCK_USB_DISC_IRQ:
1604                 vbus = 0;
1605                 disable_irq(LUBBOCK_USB_DISC_IRQ);
1606                 enable_irq(LUBBOCK_USB_IRQ);
1607                 break;
1608         default:
1609                 return IRQ_NONE;
1610         }
1611
1612         pxa25x_udc_vbus_session(&dev->gadget, vbus);
1613         return IRQ_HANDLED;
1614 }
1615
1616 #endif
1617
1618
1619 /*-------------------------------------------------------------------------*/
1620
1621 static inline void clear_ep_state (struct pxa25x_udc *dev)
1622 {
1623         unsigned i;
1624
1625         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1626          * fifos, and pending transactions mustn't be continued in any case.
1627          */
1628         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1629                 nuke(&dev->ep[i], -ECONNABORTED);
1630 }
1631
1632 static void udc_watchdog(unsigned long _dev)
1633 {
1634         struct pxa25x_udc       *dev = (void *)_dev;
1635
1636         local_irq_disable();
1637         if (dev->ep0state == EP0_STALL
1638                         && (udc_ep0_get_UDCCS(dev) & UDCCS0_FST) == 0
1639                         && (udc_ep0_get_UDCCS(dev) & UDCCS0_SST) == 0) {
1640                 udc_ep0_set_UDCCS(dev, UDCCS0_FST|UDCCS0_FTF);
1641                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1642                 start_watchdog(dev);
1643         }
1644         local_irq_enable();
1645 }
1646
1647 static void handle_ep0 (struct pxa25x_udc *dev)
1648 {
1649         u32                     udccs0 = udc_ep0_get_UDCCS(dev);
1650         struct pxa25x_ep        *ep = &dev->ep [0];
1651         struct pxa25x_request   *req;
1652         union {
1653                 struct usb_ctrlrequest  r;
1654                 u8                      raw [8];
1655                 u32                     word [2];
1656         } u;
1657
1658         if (list_empty(&ep->queue))
1659                 req = NULL;
1660         else
1661                 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1662
1663         /* clear stall status */
1664         if (udccs0 & UDCCS0_SST) {
1665                 nuke(ep, -EPIPE);
1666                 udc_ep0_set_UDCCS(dev, UDCCS0_SST);
1667                 del_timer(&dev->timer);
1668                 ep0_idle(dev);
1669         }
1670
1671         /* previous request unfinished?  non-error iff back-to-back ... */
1672         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1673                 nuke(ep, 0);
1674                 del_timer(&dev->timer);
1675                 ep0_idle(dev);
1676         }
1677
1678         switch (dev->ep0state) {
1679         case EP0_IDLE:
1680                 /* late-breaking status? */
1681                 udccs0 = udc_ep0_get_UDCCS(dev);
1682
1683                 /* start control request? */
1684                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1685                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1686                         int i;
1687
1688                         nuke (ep, -EPROTO);
1689
1690                         /* read SETUP packet */
1691                         for (i = 0; i < 8; i++) {
1692                                 if (unlikely(!(udc_ep0_get_UDCCS(dev) & UDCCS0_RNE))) {
1693 bad_setup:
1694                                         DMSG("SETUP %d!\n", i);
1695                                         goto stall;
1696                                 }
1697                                 u.raw [i] = (u8) UDDR0;
1698                         }
1699                         if (unlikely((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0))
1700                                 goto bad_setup;
1701
1702 got_setup:
1703                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1704                                 u.r.bRequestType, u.r.bRequest,
1705                                 le16_to_cpu(u.r.wValue),
1706                                 le16_to_cpu(u.r.wIndex),
1707                                 le16_to_cpu(u.r.wLength));
1708
1709                         /* cope with automagic for some standard requests. */
1710                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1711                                                 == USB_TYPE_STANDARD;
1712                         dev->req_config = 0;
1713                         dev->req_pending = 1;
1714                         switch (u.r.bRequest) {
1715                         /* hardware restricts gadget drivers here! */
1716                         case USB_REQ_SET_CONFIGURATION:
1717                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1718                                         /* reflect hardware's automagic
1719                                          * up to the gadget driver.
1720                                          */
1721 config_change:
1722                                         dev->req_config = 1;
1723                                         clear_ep_state(dev);
1724                                         /* if !has_cfr, there's no synch
1725                                          * else use AREN (later) not SA|OPR
1726                                          * USIR0_IR0 acts edge sensitive
1727                                          */
1728                                 }
1729                                 break;
1730                         /* ... and here, even more ... */
1731                         case USB_REQ_SET_INTERFACE:
1732                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1733                                         /* udc hardware is broken by design:
1734                                          *  - altsetting may only be zero;
1735                                          *  - hw resets all interfaces' eps;
1736                                          *  - ep reset doesn't include halt(?).
1737                                          */
1738                                         DMSG("broken set_interface (%d/%d)\n",
1739                                                 le16_to_cpu(u.r.wIndex),
1740                                                 le16_to_cpu(u.r.wValue));
1741                                         goto config_change;
1742                                 }
1743                                 break;
1744                         /* hardware was supposed to hide this */
1745                         case USB_REQ_SET_ADDRESS:
1746                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1747                                         ep0start(dev, 0, "address");
1748                                         return;
1749                                 }
1750                                 break;
1751                         }
1752
1753                         if (u.r.bRequestType & USB_DIR_IN)
1754                                 dev->ep0state = EP0_IN_DATA_PHASE;
1755                         else
1756                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1757
1758                         i = dev->driver->setup(&dev->gadget, &u.r);
1759                         if (i < 0) {
1760                                 /* hardware automagic preventing STALL... */
1761                                 if (dev->req_config) {
1762                                         /* hardware sometimes neglects to tell
1763                                          * tell us about config change events,
1764                                          * so later ones may fail...
1765                                          */
1766                                         WARNING("config change %02x fail %d?\n",
1767                                                 u.r.bRequest, i);
1768                                         return;
1769                                         /* TODO experiment:  if has_cfr,
1770                                          * hardware didn't ACK; maybe we
1771                                          * could actually STALL!
1772                                          */
1773                                 }
1774                                 DBG(DBG_VERBOSE, "protocol STALL, "
1775                                         "%02x err %d\n", udc_ep0_get_UDCCS(dev), i);
1776 stall:
1777                                 /* the watchdog timer helps deal with cases
1778                                  * where udc seems to clear FST wrongly, and
1779                                  * then NAKs instead of STALLing.
1780                                  */
1781                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1782                                 start_watchdog(dev);
1783                                 dev->ep0state = EP0_STALL;
1784
1785                         /* deferred i/o == no response yet */
1786                         } else if (dev->req_pending) {
1787                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1788                                                 || dev->req_std || u.r.wLength))
1789                                         ep0start(dev, 0, "defer");
1790                                 else
1791                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1792                         }
1793
1794                         /* expect at least one data or status stage irq */
1795                         return;
1796
1797                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1798                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1799                         unsigned i;
1800
1801                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1802                          * still observed on a pxa255 a0.
1803                          */
1804                         DBG(DBG_VERBOSE, "e131\n");
1805                         nuke(ep, -EPROTO);
1806
1807                         /* read SETUP data, but don't trust it too much */
1808                         for (i = 0; i < 8; i++)
1809                                 u.raw [i] = (u8) UDDR0;
1810                         if ((u.r.bRequestType & USB_RECIP_MASK)
1811                                         > USB_RECIP_OTHER)
1812                                 goto stall;
1813                         if (u.word [0] == 0 && u.word [1] == 0)
1814                                 goto stall;
1815                         goto got_setup;
1816                 } else {
1817                         /* some random early IRQ:
1818                          * - we acked FST
1819                          * - IPR cleared
1820                          * - OPR got set, without SA (likely status stage)
1821                          */
1822                         udc_ep0_set_UDCCS(dev, udccs0 & (UDCCS0_SA|UDCCS0_OPR));
1823                 }
1824                 break;
1825         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1826                 if (udccs0 & UDCCS0_OPR) {
1827                         udc_ep0_set_UDCCS(dev, UDCCS0_OPR|UDCCS0_FTF);
1828                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1829                         if (req)
1830                                 done(ep, req, 0);
1831                         ep0_idle(dev);
1832                 } else /* irq was IPR clearing */ {
1833                         if (req) {
1834                                 /* this IN packet might finish the request */
1835                                 (void) write_ep0_fifo(ep, req);
1836                         } /* else IN token before response was written */
1837                 }
1838                 break;
1839         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1840                 if (udccs0 & UDCCS0_OPR) {
1841                         if (req) {
1842                                 /* this OUT packet might finish the request */
1843                                 if (read_ep0_fifo(ep, req))
1844                                         done(ep, req, 0);
1845                                 /* else more OUT packets expected */
1846                         } /* else OUT token before read was issued */
1847                 } else /* irq was IPR clearing */ {
1848                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1849                         if (req)
1850                                 done(ep, req, 0);
1851                         ep0_idle(dev);
1852                 }
1853                 break;
1854         case EP0_END_XFER:
1855                 if (req)
1856                         done(ep, req, 0);
1857                 /* ack control-IN status (maybe in-zlp was skipped)
1858                  * also appears after some config change events.
1859                  */
1860                 if (udccs0 & UDCCS0_OPR)
1861                         udc_ep0_set_UDCCS(dev, UDCCS0_OPR);
1862                 ep0_idle(dev);
1863                 break;
1864         case EP0_STALL:
1865                 udc_ep0_set_UDCCS(dev, UDCCS0_FST);
1866                 break;
1867         }
1868         udc_set_reg(dev, USIR0, USIR0_IR0);
1869 }
1870
1871 static void handle_ep(struct pxa25x_ep *ep)
1872 {
1873         struct pxa25x_request   *req;
1874         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1875         int                     completed;
1876         u32                     udccs, tmp;
1877
1878         do {
1879                 completed = 0;
1880                 if (likely (!list_empty(&ep->queue)))
1881                         req = list_entry(ep->queue.next,
1882                                         struct pxa25x_request, queue);
1883                 else
1884                         req = NULL;
1885
1886                 // TODO check FST handling
1887
1888                 udccs = udc_ep_get_UDCCS(ep);
1889                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1890                         tmp = UDCCS_BI_TUR;
1891                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1892                                 tmp |= UDCCS_BI_SST;
1893                         tmp &= udccs;
1894                         if (likely (tmp))
1895                                 udc_ep_set_UDCCS(ep, tmp);
1896                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1897                                 completed = write_fifo(ep, req);
1898
1899                 } else {        /* irq from RPC (or for ISO, ROF) */
1900                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1901                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1902                         else
1903                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1904                         tmp &= udccs;
1905                         if (likely(tmp))
1906                                 udc_ep_set_UDCCS(ep, tmp);
1907
1908                         /* fifos can hold packets, ready for reading... */
1909                         if (likely(req)) {
1910                                 completed = read_fifo(ep, req);
1911                         } else
1912                                 pio_irq_disable(ep);
1913                 }
1914                 ep->pio_irqs++;
1915         } while (completed);
1916 }
1917
1918 /*
1919  *      pxa25x_udc_irq - interrupt handler
1920  *
1921  * avoid delays in ep0 processing. the control handshaking isn't always
1922  * under software control (pxa250c0 and the pxa255 are better), and delays
1923  * could cause usb protocol errors.
1924  */
1925 static irqreturn_t
1926 pxa25x_udc_irq(int irq, void *_dev)
1927 {
1928         struct pxa25x_udc       *dev = _dev;
1929         int                     handled;
1930
1931         dev->stats.irqs++;
1932         do {
1933                 u32             udccr = udc_get_reg(dev, UDCCR);
1934
1935                 handled = 0;
1936
1937                 /* SUSpend Interrupt Request */
1938                 if (unlikely(udccr & UDCCR_SUSIR)) {
1939                         udc_ack_int_UDCCR(dev, UDCCR_SUSIR);
1940                         handled = 1;
1941                         DBG(DBG_VERBOSE, "USB suspend\n");
1942
1943                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1944                                         && dev->driver
1945                                         && dev->driver->suspend)
1946                                 dev->driver->suspend(&dev->gadget);
1947                         ep0_idle (dev);
1948                 }
1949
1950                 /* RESume Interrupt Request */
1951                 if (unlikely(udccr & UDCCR_RESIR)) {
1952                         udc_ack_int_UDCCR(dev, UDCCR_RESIR);
1953                         handled = 1;
1954                         DBG(DBG_VERBOSE, "USB resume\n");
1955
1956                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1957                                         && dev->driver
1958                                         && dev->driver->resume)
1959                                 dev->driver->resume(&dev->gadget);
1960                 }
1961
1962                 /* ReSeT Interrupt Request - USB reset */
1963                 if (unlikely(udccr & UDCCR_RSTIR)) {
1964                         udc_ack_int_UDCCR(dev, UDCCR_RSTIR);
1965                         handled = 1;
1966
1967                         if ((udc_get_reg(dev, UDCCR) & UDCCR_UDA) == 0) {
1968                                 DBG(DBG_VERBOSE, "USB reset start\n");
1969
1970                                 /* reset driver and endpoints,
1971                                  * in case that's not yet done
1972                                  */
1973                                 reset_gadget(dev, dev->driver);
1974
1975                         } else {
1976                                 DBG(DBG_VERBOSE, "USB reset end\n");
1977                                 dev->gadget.speed = USB_SPEED_FULL;
1978                                 memset(&dev->stats, 0, sizeof dev->stats);
1979                                 /* driver and endpoints are still reset */
1980                         }
1981
1982                 } else {
1983                         u32     usir0 = udc_get_reg(dev, USIR0) &
1984                                         ~udc_get_reg(dev, UICR0);
1985                         u32     usir1 = udc_get_reg(dev, USIR1) &
1986                                         ~udc_get_reg(dev, UICR1);
1987                         int     i;
1988
1989                         if (unlikely (!usir0 && !usir1))
1990                                 continue;
1991
1992                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
1993
1994                         /* control traffic */
1995                         if (usir0 & USIR0_IR0) {
1996                                 dev->ep[0].pio_irqs++;
1997                                 handle_ep0(dev);
1998                                 handled = 1;
1999                         }
2000
2001                         /* endpoint data transfers */
2002                         for (i = 0; i < 8; i++) {
2003                                 u32     tmp = 1 << i;
2004
2005                                 if (i && (usir0 & tmp)) {
2006                                         handle_ep(&dev->ep[i]);
2007                                         udc_set_reg(dev, USIR0,
2008                                                 udc_get_reg(dev, USIR0) | tmp);
2009                                         handled = 1;
2010                                 }
2011 #ifndef CONFIG_USB_PXA25X_SMALL
2012                                 if (usir1 & tmp) {
2013                                         handle_ep(&dev->ep[i+8]);
2014                                         udc_set_reg(dev, USIR1,
2015                                                 udc_get_reg(dev, USIR1) | tmp);
2016                                         handled = 1;
2017                                 }
2018 #endif
2019                         }
2020                 }
2021
2022                 /* we could also ask for 1 msec SOF (SIR) interrupts */
2023
2024         } while (handled);
2025         return IRQ_HANDLED;
2026 }
2027
2028 /*-------------------------------------------------------------------------*/
2029
2030 static void nop_release (struct device *dev)
2031 {
2032         DMSG("%s %s\n", __func__, dev_name(dev));
2033 }
2034
2035 /* this uses load-time allocation and initialization (instead of
2036  * doing it at run-time) to save code, eliminate fault paths, and
2037  * be more obviously correct.
2038  */
2039 static struct pxa25x_udc memory = {
2040         .gadget = {
2041                 .ops            = &pxa25x_udc_ops,
2042                 .ep0            = &memory.ep[0].ep,
2043                 .name           = driver_name,
2044                 .dev = {
2045                         .init_name      = "gadget",
2046                         .release        = nop_release,
2047                 },
2048         },
2049
2050         /* control endpoint */
2051         .ep[0] = {
2052                 .ep = {
2053                         .name           = ep0name,
2054                         .ops            = &pxa25x_ep_ops,
2055                         .maxpacket      = EP0_FIFO_SIZE,
2056                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2057                                                 USB_EP_CAPS_DIR_ALL),
2058                 },
2059                 .dev            = &memory,
2060                 .regoff_udccs   = UDCCS0,
2061                 .regoff_uddr    = UDDR0,
2062         },
2063
2064         /* first group of endpoints */
2065         .ep[1] = {
2066                 .ep = {
2067                         .name           = "ep1in-bulk",
2068                         .ops            = &pxa25x_ep_ops,
2069                         .maxpacket      = BULK_FIFO_SIZE,
2070                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2071                                                 USB_EP_CAPS_DIR_IN),
2072                 },
2073                 .dev            = &memory,
2074                 .fifo_size      = BULK_FIFO_SIZE,
2075                 .bEndpointAddress = USB_DIR_IN | 1,
2076                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2077                 .regoff_udccs   = UDCCS1,
2078                 .regoff_uddr    = UDDR1,
2079         },
2080         .ep[2] = {
2081                 .ep = {
2082                         .name           = "ep2out-bulk",
2083                         .ops            = &pxa25x_ep_ops,
2084                         .maxpacket      = BULK_FIFO_SIZE,
2085                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2086                                                 USB_EP_CAPS_DIR_OUT),
2087                 },
2088                 .dev            = &memory,
2089                 .fifo_size      = BULK_FIFO_SIZE,
2090                 .bEndpointAddress = 2,
2091                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2092                 .regoff_udccs   = UDCCS2,
2093                 .regoff_ubcr    = UBCR2,
2094                 .regoff_uddr    = UDDR2,
2095         },
2096 #ifndef CONFIG_USB_PXA25X_SMALL
2097         .ep[3] = {
2098                 .ep = {
2099                         .name           = "ep3in-iso",
2100                         .ops            = &pxa25x_ep_ops,
2101                         .maxpacket      = ISO_FIFO_SIZE,
2102                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2103                                                 USB_EP_CAPS_DIR_IN),
2104                 },
2105                 .dev            = &memory,
2106                 .fifo_size      = ISO_FIFO_SIZE,
2107                 .bEndpointAddress = USB_DIR_IN | 3,
2108                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2109                 .regoff_udccs   = UDCCS3,
2110                 .regoff_uddr    = UDDR3,
2111         },
2112         .ep[4] = {
2113                 .ep = {
2114                         .name           = "ep4out-iso",
2115                         .ops            = &pxa25x_ep_ops,
2116                         .maxpacket      = ISO_FIFO_SIZE,
2117                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2118                                                 USB_EP_CAPS_DIR_OUT),
2119                 },
2120                 .dev            = &memory,
2121                 .fifo_size      = ISO_FIFO_SIZE,
2122                 .bEndpointAddress = 4,
2123                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2124                 .regoff_udccs   = UDCCS4,
2125                 .regoff_ubcr    = UBCR4,
2126                 .regoff_uddr    = UDDR4,
2127         },
2128         .ep[5] = {
2129                 .ep = {
2130                         .name           = "ep5in-int",
2131                         .ops            = &pxa25x_ep_ops,
2132                         .maxpacket      = INT_FIFO_SIZE,
2133                         .caps           = USB_EP_CAPS(0, 0),
2134                 },
2135                 .dev            = &memory,
2136                 .fifo_size      = INT_FIFO_SIZE,
2137                 .bEndpointAddress = USB_DIR_IN | 5,
2138                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2139                 .regoff_udccs   = UDCCS5,
2140                 .regoff_uddr    = UDDR5,
2141         },
2142
2143         /* second group of endpoints */
2144         .ep[6] = {
2145                 .ep = {
2146                         .name           = "ep6in-bulk",
2147                         .ops            = &pxa25x_ep_ops,
2148                         .maxpacket      = BULK_FIFO_SIZE,
2149                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2150                                                 USB_EP_CAPS_DIR_IN),
2151                 },
2152                 .dev            = &memory,
2153                 .fifo_size      = BULK_FIFO_SIZE,
2154                 .bEndpointAddress = USB_DIR_IN | 6,
2155                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2156                 .regoff_udccs   = UDCCS6,
2157                 .regoff_uddr    = UDDR6,
2158         },
2159         .ep[7] = {
2160                 .ep = {
2161                         .name           = "ep7out-bulk",
2162                         .ops            = &pxa25x_ep_ops,
2163                         .maxpacket      = BULK_FIFO_SIZE,
2164                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2165                                                 USB_EP_CAPS_DIR_OUT),
2166                 },
2167                 .dev            = &memory,
2168                 .fifo_size      = BULK_FIFO_SIZE,
2169                 .bEndpointAddress = 7,
2170                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2171                 .regoff_udccs   = UDCCS7,
2172                 .regoff_ubcr    = UBCR7,
2173                 .regoff_uddr    = UDDR7,
2174         },
2175         .ep[8] = {
2176                 .ep = {
2177                         .name           = "ep8in-iso",
2178                         .ops            = &pxa25x_ep_ops,
2179                         .maxpacket      = ISO_FIFO_SIZE,
2180                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2181                                                 USB_EP_CAPS_DIR_IN),
2182                 },
2183                 .dev            = &memory,
2184                 .fifo_size      = ISO_FIFO_SIZE,
2185                 .bEndpointAddress = USB_DIR_IN | 8,
2186                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2187                 .regoff_udccs   = UDCCS8,
2188                 .regoff_uddr    = UDDR8,
2189         },
2190         .ep[9] = {
2191                 .ep = {
2192                         .name           = "ep9out-iso",
2193                         .ops            = &pxa25x_ep_ops,
2194                         .maxpacket      = ISO_FIFO_SIZE,
2195                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2196                                                 USB_EP_CAPS_DIR_OUT),
2197                 },
2198                 .dev            = &memory,
2199                 .fifo_size      = ISO_FIFO_SIZE,
2200                 .bEndpointAddress = 9,
2201                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2202                 .regoff_udccs   = UDCCS9,
2203                 .regoff_ubcr    = UBCR9,
2204                 .regoff_uddr    = UDDR9,
2205         },
2206         .ep[10] = {
2207                 .ep = {
2208                         .name           = "ep10in-int",
2209                         .ops            = &pxa25x_ep_ops,
2210                         .maxpacket      = INT_FIFO_SIZE,
2211                         .caps           = USB_EP_CAPS(0, 0),
2212                 },
2213                 .dev            = &memory,
2214                 .fifo_size      = INT_FIFO_SIZE,
2215                 .bEndpointAddress = USB_DIR_IN | 10,
2216                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2217                 .regoff_udccs   = UDCCS10,
2218                 .regoff_uddr    = UDDR10,
2219         },
2220
2221         /* third group of endpoints */
2222         .ep[11] = {
2223                 .ep = {
2224                         .name           = "ep11in-bulk",
2225                         .ops            = &pxa25x_ep_ops,
2226                         .maxpacket      = BULK_FIFO_SIZE,
2227                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2228                                                 USB_EP_CAPS_DIR_IN),
2229                 },
2230                 .dev            = &memory,
2231                 .fifo_size      = BULK_FIFO_SIZE,
2232                 .bEndpointAddress = USB_DIR_IN | 11,
2233                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2234                 .regoff_udccs   = UDCCS11,
2235                 .regoff_uddr    = UDDR11,
2236         },
2237         .ep[12] = {
2238                 .ep = {
2239                         .name           = "ep12out-bulk",
2240                         .ops            = &pxa25x_ep_ops,
2241                         .maxpacket      = BULK_FIFO_SIZE,
2242                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2243                                                 USB_EP_CAPS_DIR_OUT),
2244                 },
2245                 .dev            = &memory,
2246                 .fifo_size      = BULK_FIFO_SIZE,
2247                 .bEndpointAddress = 12,
2248                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2249                 .regoff_udccs   = UDCCS12,
2250                 .regoff_ubcr    = UBCR12,
2251                 .regoff_uddr    = UDDR12,
2252         },
2253         .ep[13] = {
2254                 .ep = {
2255                         .name           = "ep13in-iso",
2256                         .ops            = &pxa25x_ep_ops,
2257                         .maxpacket      = ISO_FIFO_SIZE,
2258                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2259                                                 USB_EP_CAPS_DIR_IN),
2260                 },
2261                 .dev            = &memory,
2262                 .fifo_size      = ISO_FIFO_SIZE,
2263                 .bEndpointAddress = USB_DIR_IN | 13,
2264                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2265                 .regoff_udccs   = UDCCS13,
2266                 .regoff_uddr    = UDDR13,
2267         },
2268         .ep[14] = {
2269                 .ep = {
2270                         .name           = "ep14out-iso",
2271                         .ops            = &pxa25x_ep_ops,
2272                         .maxpacket      = ISO_FIFO_SIZE,
2273                         .caps           = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2274                                                 USB_EP_CAPS_DIR_OUT),
2275                 },
2276                 .dev            = &memory,
2277                 .fifo_size      = ISO_FIFO_SIZE,
2278                 .bEndpointAddress = 14,
2279                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2280                 .regoff_udccs   = UDCCS14,
2281                 .regoff_ubcr    = UBCR14,
2282                 .regoff_uddr    = UDDR14,
2283         },
2284         .ep[15] = {
2285                 .ep = {
2286                         .name           = "ep15in-int",
2287                         .ops            = &pxa25x_ep_ops,
2288                         .maxpacket      = INT_FIFO_SIZE,
2289                         .caps           = USB_EP_CAPS(0, 0),
2290                 },
2291                 .dev            = &memory,
2292                 .fifo_size      = INT_FIFO_SIZE,
2293                 .bEndpointAddress = USB_DIR_IN | 15,
2294                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2295                 .regoff_udccs   = UDCCS15,
2296                 .regoff_uddr    = UDDR15,
2297         },
2298 #endif /* !CONFIG_USB_PXA25X_SMALL */
2299 };
2300
2301 #define CP15R0_VENDOR_MASK      0xffffe000
2302
2303 #if     defined(CONFIG_ARCH_PXA)
2304 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2305
2306 #elif   defined(CONFIG_ARCH_IXP4XX)
2307 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2308
2309 #endif
2310
2311 #define CP15R0_PROD_MASK        0x000003f0
2312 #define PXA25x                  0x00000100      /* and PXA26x */
2313 #define PXA210                  0x00000120
2314
2315 #define CP15R0_REV_MASK         0x0000000f
2316
2317 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2318
2319 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2320 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2321 #define PXA250_B2               0x00000104
2322 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2323 #define PXA250_B0               0x00000102
2324 #define PXA250_A1               0x00000101
2325 #define PXA250_A0               0x00000100
2326
2327 #define PXA210_C0               0x00000125
2328 #define PXA210_B2               0x00000124
2329 #define PXA210_B1               0x00000123
2330 #define PXA210_B0               0x00000122
2331 #define IXP425_A0               0x000001c1
2332 #define IXP425_B0               0x000001f1
2333 #define IXP465_AD               0x00000200
2334
2335 /*
2336  *      probe - binds to the platform device
2337  */
2338 static int pxa25x_udc_probe(struct platform_device *pdev)
2339 {
2340         struct pxa25x_udc *dev = &memory;
2341         int retval, irq;
2342         u32 chiprev;
2343         struct resource *res;
2344
2345         pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
2346
2347         /* insist on Intel/ARM/XScale */
2348         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2349         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2350                 pr_err("%s: not XScale!\n", driver_name);
2351                 return -ENODEV;
2352         }
2353
2354         /* trigger chiprev-specific logic */
2355         switch (chiprev & CP15R0_PRODREV_MASK) {
2356 #if     defined(CONFIG_ARCH_PXA)
2357         case PXA255_A0:
2358                 dev->has_cfr = 1;
2359                 break;
2360         case PXA250_A0:
2361         case PXA250_A1:
2362                 /* A0/A1 "not released"; ep 13, 15 unusable */
2363                 /* fall through */
2364         case PXA250_B2: case PXA210_B2:
2365         case PXA250_B1: case PXA210_B1:
2366         case PXA250_B0: case PXA210_B0:
2367                 /* OUT-DMA is broken ... */
2368                 /* fall through */
2369         case PXA250_C0: case PXA210_C0:
2370                 break;
2371 #elif   defined(CONFIG_ARCH_IXP4XX)
2372         case IXP425_A0:
2373         case IXP425_B0:
2374         case IXP465_AD:
2375                 dev->has_cfr = 1;
2376                 break;
2377 #endif
2378         default:
2379                 pr_err("%s: unrecognized processor: %08x\n",
2380                         driver_name, chiprev);
2381                 /* iop3xx, ixp4xx, ... */
2382                 return -ENODEV;
2383         }
2384
2385         irq = platform_get_irq(pdev, 0);
2386         if (irq < 0)
2387                 return -ENODEV;
2388
2389         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2390         dev->regs = devm_ioremap_resource(&pdev->dev, res);
2391         if (IS_ERR(dev->regs))
2392                 return PTR_ERR(dev->regs);
2393
2394         dev->clk = devm_clk_get(&pdev->dev, NULL);
2395         if (IS_ERR(dev->clk))
2396                 return PTR_ERR(dev->clk);
2397
2398         pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2399                 dev->has_cfr ? "" : " (!cfr)",
2400                 SIZE_STR "(pio)"
2401                 );
2402
2403         /* other non-static parts of init */
2404         dev->dev = &pdev->dev;
2405         dev->mach = dev_get_platdata(&pdev->dev);
2406
2407         dev->transceiver = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
2408
2409         if (gpio_is_valid(dev->mach->gpio_pullup)) {
2410                 retval = devm_gpio_request(&pdev->dev, dev->mach->gpio_pullup,
2411                                            "pca25x_udc GPIO PULLUP");
2412                 if (retval) {
2413                         dev_dbg(&pdev->dev,
2414                                 "can't get pullup gpio %d, err: %d\n",
2415                                 dev->mach->gpio_pullup, retval);
2416                         goto err;
2417                 }
2418                 gpio_direction_output(dev->mach->gpio_pullup, 0);
2419         }
2420
2421         setup_timer(&dev->timer, udc_watchdog, (unsigned long)dev);
2422
2423         the_controller = dev;
2424         platform_set_drvdata(pdev, dev);
2425
2426         udc_disable(dev);
2427         udc_reinit(dev);
2428
2429         dev->vbus = 0;
2430
2431         /* irq setup after old hardware state is cleaned up */
2432         retval = devm_request_irq(&pdev->dev, irq, pxa25x_udc_irq, 0,
2433                                   driver_name, dev);
2434         if (retval != 0) {
2435                 pr_err("%s: can't get irq %d, err %d\n",
2436                         driver_name, irq, retval);
2437                 goto err;
2438         }
2439         dev->got_irq = 1;
2440
2441 #ifdef CONFIG_ARCH_LUBBOCK
2442         if (machine_is_lubbock()) {
2443                 retval = devm_request_irq(&pdev->dev, LUBBOCK_USB_DISC_IRQ,
2444                                           lubbock_vbus_irq, 0, driver_name,
2445                                           dev);
2446                 if (retval != 0) {
2447                         pr_err("%s: can't get irq %i, err %d\n",
2448                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2449                         goto err;
2450                 }
2451                 retval = devm_request_irq(&pdev->dev, LUBBOCK_USB_IRQ,
2452                                           lubbock_vbus_irq, 0, driver_name,
2453                                           dev);
2454                 if (retval != 0) {
2455                         pr_err("%s: can't get irq %i, err %d\n",
2456                                 driver_name, LUBBOCK_USB_IRQ, retval);
2457                         goto err;
2458                 }
2459         } else
2460 #endif
2461         create_debug_files(dev);
2462
2463         retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
2464         if (!retval)
2465                 return retval;
2466
2467         remove_debug_files(dev);
2468  err:
2469         if (!IS_ERR_OR_NULL(dev->transceiver))
2470                 dev->transceiver = NULL;
2471         return retval;
2472 }
2473
2474 static void pxa25x_udc_shutdown(struct platform_device *_dev)
2475 {
2476         pullup_off();
2477 }
2478
2479 static int pxa25x_udc_remove(struct platform_device *pdev)
2480 {
2481         struct pxa25x_udc *dev = platform_get_drvdata(pdev);
2482
2483         if (dev->driver)
2484                 return -EBUSY;
2485
2486         usb_del_gadget_udc(&dev->gadget);
2487         dev->pullup = 0;
2488         pullup(dev);
2489
2490         remove_debug_files(dev);
2491
2492         if (!IS_ERR_OR_NULL(dev->transceiver))
2493                 dev->transceiver = NULL;
2494
2495         the_controller = NULL;
2496         return 0;
2497 }
2498
2499 /*-------------------------------------------------------------------------*/
2500
2501 #ifdef  CONFIG_PM
2502
2503 /* USB suspend (controlled by the host) and system suspend (controlled
2504  * by the PXA) don't necessarily work well together.  If USB is active,
2505  * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2506  * mode, or any deeper PM saving state.
2507  *
2508  * For now, we punt and forcibly disconnect from the USB host when PXA
2509  * enters any suspend state.  While we're disconnected, we always disable
2510  * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2511  * Boards without software pullup control shouldn't use those states.
2512  * VBUS IRQs should probably be ignored so that the PXA device just acts
2513  * "dead" to USB hosts until system resume.
2514  */
2515 static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state)
2516 {
2517         struct pxa25x_udc       *udc = platform_get_drvdata(dev);
2518         unsigned long flags;
2519
2520         if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
2521                 WARNING("USB host won't detect disconnect!\n");
2522         udc->suspended = 1;
2523
2524         local_irq_save(flags);
2525         pullup(udc);
2526         local_irq_restore(flags);
2527
2528         return 0;
2529 }
2530
2531 static int pxa25x_udc_resume(struct platform_device *dev)
2532 {
2533         struct pxa25x_udc       *udc = platform_get_drvdata(dev);
2534         unsigned long flags;
2535
2536         udc->suspended = 0;
2537         local_irq_save(flags);
2538         pullup(udc);
2539         local_irq_restore(flags);
2540
2541         return 0;
2542 }
2543
2544 #else
2545 #define pxa25x_udc_suspend      NULL
2546 #define pxa25x_udc_resume       NULL
2547 #endif
2548
2549 /*-------------------------------------------------------------------------*/
2550
2551 static struct platform_driver udc_driver = {
2552         .shutdown       = pxa25x_udc_shutdown,
2553         .probe          = pxa25x_udc_probe,
2554         .remove         = pxa25x_udc_remove,
2555         .suspend        = pxa25x_udc_suspend,
2556         .resume         = pxa25x_udc_resume,
2557         .driver         = {
2558                 .name   = "pxa25x-udc",
2559         },
2560 };
2561
2562 module_platform_driver(udc_driver);
2563
2564 MODULE_DESCRIPTION(DRIVER_DESC);
2565 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2566 MODULE_LICENSE("GPL");
2567 MODULE_ALIAS("platform:pxa25x-udc");