1 // SPDX-License-Identifier: GPL-2.0
3 * Toshiba TC86C001 ("Goku-S") USB Device Controller driver
5 * Copyright (C) 2000-2002 Lineo
6 * by Stuart Lynne, Tom Rushworth, and Bruce Balden
7 * Copyright (C) 2002 Toshiba Corporation
8 * Copyright (C) 2003 MontaVista Software (source@mvista.com)
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
16 * PCI BAR 0 points to these registers.
18 struct goku_udc_regs {
20 u32 int_status; /* 0x000 */
22 #define INT_SUSPEND 0x00001 /* or resume */
23 #define INT_USBRESET 0x00002
24 #define INT_ENDPOINT0 0x00004
25 #define INT_SETUP 0x00008
26 #define INT_STATUS 0x00010
27 #define INT_STATUSNAK 0x00020
28 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
29 # define INT_EP1DATASET 0x00040
30 # define INT_EP2DATASET 0x00080
31 # define INT_EP3DATASET 0x00100
32 #define INT_EPnNAK(n) (0x00100 < (n)) /* 0 < n < 4 */
33 # define INT_EP1NAK 0x00200
34 # define INT_EP2NAK 0x00400
35 # define INT_EP3NAK 0x00800
36 #define INT_SOF 0x01000
37 #define INT_ERR 0x02000
38 #define INT_MSTWRSET 0x04000
39 #define INT_MSTWREND 0x08000
40 #define INT_MSTWRTMOUT 0x10000
41 #define INT_MSTRDEND 0x20000
42 #define INT_SYSERROR 0x40000
43 #define INT_PWRDETECT 0x80000
46 (INT_PWRDETECT|INT_SYSERROR/*|INT_ERR*/|INT_USBRESET|INT_SUSPEND)
48 (INT_SETUP|INT_ENDPOINT0/*|INT_STATUS*/|INT_STATUSNAK)
51 #define MST_EOPB_DIS 0x0800
52 #define MST_EOPB_ENA 0x0400
53 #define MST_TIMEOUT_DIS 0x0200
54 #define MST_TIMEOUT_ENA 0x0100
55 #define MST_RD_EOPB 0x0080 /* write-only */
56 #define MST_RD_RESET 0x0040
57 #define MST_WR_RESET 0x0020
58 #define MST_RD_ENA 0x0004 /* 1:start, 0:ignore */
59 #define MST_WR_ENA 0x0002 /* 1:start, 0:ignore */
60 #define MST_CONNECTION 0x0001 /* 0 for ep1out/ep2in */
62 #define MST_R_BITS (MST_EOPB_DIS|MST_EOPB_ENA \
63 |MST_RD_ENA|MST_RD_RESET)
64 #define MST_W_BITS (MST_TIMEOUT_DIS|MST_TIMEOUT_ENA \
65 |MST_WR_ENA|MST_WR_RESET)
66 #define MST_RW_BITS (MST_R_BITS|MST_W_BITS \
69 /* these values assume (dma_master & MST_CONNECTION) == 0 */
70 #define UDC_MSTWR_ENDPOINT 1
71 #define UDC_MSTRD_ENDPOINT 2
73 /* dma master write */
84 #define PW_DETECT 0x04
85 #define PW_RESETB 0x02
86 #define PW_PULLUP 0x01
88 u8 _reserved0 [0x1d8];
90 /* endpoint registers */
91 u32 ep_fifo [4]; /* 0x200 */
93 u32 ep_mode [4]; /* only 1-3 valid */
97 #define EPxSTATUS_TOGGLE 0x40
98 #define EPxSTATUS_SUSPEND 0x20
99 #define EPxSTATUS_EP_MASK (0x07<<2)
100 # define EPxSTATUS_EP_READY (0<<2)
101 # define EPxSTATUS_EP_DATAIN (1<<2)
102 # define EPxSTATUS_EP_FULL (2<<2)
103 # define EPxSTATUS_EP_TX_ERR (3<<2)
104 # define EPxSTATUS_EP_RX_ERR (4<<2)
105 # define EPxSTATUS_EP_BUSY (5<<2)
106 # define EPxSTATUS_EP_STALL (6<<2)
107 # define EPxSTATUS_EP_INVALID (7<<2)
108 #define EPxSTATUS_FIFO_DISABLE 0x02
109 #define EPxSTATUS_STAGE_ERROR 0x01
111 u8 _reserved3 [0x10];
113 #define PACKET_ACTIVE (1<<7)
114 #define DATASIZE 0x7f
115 u8 _reserved3a [0x10];
116 u32 EPxSizeLB[4]; /* only 1,2 valid */
117 u8 _reserved3b [0x10];
118 u32 EPxSizeHA[4]; /* only 1-3 valid */
119 u8 _reserved3c [0x10];
120 u32 EPxSizeHB[4]; /* only 1,2 valid */
123 /* SETUP packet contents */
124 u32 bRequestType; /* 0x300 */
133 /* command interaction/handshaking */
134 u32 SetupRecv; /* 0x320 */
139 #define DATASET_A(epnum) (1<<(2*(epnum)))
140 #define DATASET_B(epnum) (2<<(2*(epnum)))
141 #define DATASET_AB(epnum) (3<<(2*(epnum)))
145 #define USBSTATE_CONFIGURED 0x04
146 #define USBSTATE_ADDRESSED 0x02
147 #define USBSTATE_DEFAULT 0x01
151 u32 Command; /* 0x340 */
152 #define COMMAND_SETDATA0 2
153 #define COMMAND_RESET 3
154 #define COMMAND_STALL 4
155 #define COMMAND_INVALID 5
156 #define COMMAND_FIFO_DISABLE 7
157 #define COMMAND_FIFO_ENABLE 8
158 #define COMMAND_INIT_DESCRIPTOR 9
159 #define COMMAND_FIFO_CLEAR 10 /* also stall */
160 #define COMMAND_STALL_CLEAR 11
161 #define COMMAND_EP(n) ((n) << 4)
168 #define ICONTROL_STATUSNAK 1
171 u32 reqmode; // 0x360 standard request mode, low 8 bits
172 #define G_REQMODE_SET_INTF (1<<7)
173 #define G_REQMODE_GET_INTF (1<<6)
174 #define G_REQMODE_SET_CONF (1<<5)
175 #define G_REQMODE_GET_CONF (1<<4)
176 #define G_REQMODE_GET_DESC (1<<3)
177 #define G_REQMODE_SET_FEAT (1<<2)
178 #define G_REQMODE_CLEAR_FEAT (1<<1)
179 #define G_REQMODE_GET_STATUS (1<<0)
183 u32 PortStatus; /* 0x380 */
190 u32 SetDescStall; /* 0x3a0 */
191 u8 _reserved13[0x45c];
193 /* hardware could handle limited GET_DESCRIPTOR duties */
194 #define DESC_LEN 0x80
195 u32 descriptors[DESC_LEN]; /* 0x800 */
196 u8 _reserved14[0x600];
198 } __attribute__ ((packed));
200 #define MAX_FIFO_SIZE 64
201 #define MAX_EP0_SIZE 8 /* ep0 fifo is bigger, though */
204 /*-------------------------------------------------------------------------*/
206 /* DRIVER DATA STRUCTURES and UTILITIES */
210 struct goku_udc *dev;
218 /* analogous to a host-side qh */
219 struct list_head queue;
221 u32 __iomem *reg_fifo;
222 u32 __iomem *reg_mode;
223 u32 __iomem *reg_status;
226 struct goku_request {
227 struct usb_request req;
228 struct list_head queue;
234 EP0_DISCONNECT, /* no host */
235 EP0_IDLE, /* between STATUS ack and SETUP report */
236 EP0_IN, EP0_OUT, /* data stage */
237 EP0_STATUS, /* status stage */
238 EP0_STALL, /* data or status stages */
239 EP0_SUSPEND, /* usb suspend */
243 /* each pci device provides one gadget, several endpoints */
244 struct usb_gadget gadget;
246 struct goku_ep ep[4];
247 struct usb_gadget_driver *driver;
249 enum ep0state ep0state;
256 /* pci state used to access those endpoints */
257 struct pci_dev *pdev;
258 struct goku_udc_regs __iomem *regs;
264 #define to_goku_udc(g) (container_of((g), struct goku_udc, gadget))
266 /*-------------------------------------------------------------------------*/
268 #define xprintk(dev,level,fmt,args...) \
269 printk(level "%s %s: " fmt , driver_name , \
270 pci_name(dev->pdev) , ## args)
273 #define DBG(dev,fmt,args...) \
274 xprintk(dev , KERN_DEBUG , fmt , ## args)
276 #define DBG(dev,fmt,args...) \
283 #define VDBG(dev,fmt,args...) \
287 #define ERROR(dev,fmt,args...) \
288 xprintk(dev , KERN_ERR , fmt , ## args)
289 #define WARNING(dev,fmt,args...) \
290 xprintk(dev , KERN_WARNING , fmt , ## args)
291 #define INFO(dev,fmt,args...) \
292 xprintk(dev , KERN_INFO , fmt , ## args)