1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004,2012 Freescale Semiconductor, Inc
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Freescale USB device/endpoint management registers
13 #ifndef __FSL_USB2_UDC_H
14 #define __FSL_USB2_UDC_H
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
19 /* ### define USB registers here
21 #define USB_MAX_CTRL_PAYLOAD 64
22 #define USB_DR_SYS_OFFSET 0x400
24 /* USB DR device mode registers (Little Endian) */
25 struct usb_dr_device {
26 /* Capability register */
28 u16 caplength; /* Capability Register Length */
29 u16 hciversion; /* Host Controller Interface Version */
30 u32 hcsparams; /* Host Controller Structural Parameters */
31 u32 hccparams; /* Host Controller Capability Parameters */
33 u32 dciversion; /* Device Controller Interface Version */
34 u32 dccparams; /* Device Controller Capability Parameters */
36 /* Operation register */
37 u32 usbcmd; /* USB Command Register */
38 u32 usbsts; /* USB Status Register */
39 u32 usbintr; /* USB Interrupt Enable Register */
40 u32 frindex; /* Frame Index Register */
42 u32 deviceaddr; /* Device Address */
43 u32 endpointlistaddr; /* Endpoint List Address Register */
45 u32 burstsize; /* Master Interface Data Burst Size Register */
46 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
48 u32 configflag; /* Configure Flag Register */
49 u32 portsc1; /* Port 1 Status and Control Register */
51 u32 otgsc; /* On-The-Go Status and Control */
52 u32 usbmode; /* USB Mode Register */
53 u32 endptsetupstat; /* Endpoint Setup Status Register */
54 u32 endpointprime; /* Endpoint Initialization Register */
55 u32 endptflush; /* Endpoint Flush Register */
56 u32 endptstatus; /* Endpoint Status Register */
57 u32 endptcomplete; /* Endpoint Complete Register */
58 u32 endptctrl[6]; /* Endpoint Control Registers */
61 /* USB DR host mode registers (Little Endian) */
63 /* Capability register */
65 u16 caplength; /* Capability Register Length */
66 u16 hciversion; /* Host Controller Interface Version */
67 u32 hcsparams; /* Host Controller Structural Parameters */
68 u32 hccparams; /* Host Controller Capability Parameters */
70 u32 dciversion; /* Device Controller Interface Version */
71 u32 dccparams; /* Device Controller Capability Parameters */
73 /* Operation register */
74 u32 usbcmd; /* USB Command Register */
75 u32 usbsts; /* USB Status Register */
76 u32 usbintr; /* USB Interrupt Enable Register */
77 u32 frindex; /* Frame Index Register */
79 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
80 u32 asynclistaddr; /* Current Asynchronous List Address Register */
82 u32 burstsize; /* Master Interface Data Burst Size Register */
83 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
85 u32 configflag; /* Configure Flag Register */
86 u32 portsc1; /* Port 1 Status and Control Register */
88 u32 otgsc; /* On-The-Go Status and Control */
89 u32 usbmode; /* USB Mode Register */
90 u32 endptsetupstat; /* Endpoint Setup Status Register */
91 u32 endpointprime; /* Endpoint Initialization Register */
92 u32 endptflush; /* Endpoint Flush Register */
93 u32 endptstatus; /* Endpoint Status Register */
94 u32 endptcomplete; /* Endpoint Complete Register */
95 u32 endptctrl[6]; /* Endpoint Control Registers */
98 /* non-EHCI USB system interface registers (Big Endian) */
99 struct usb_sys_interface {
102 u32 age_cnt_thresh; /* Age Count Threshold Register */
103 u32 pri_ctrl; /* Priority Control Register */
104 u32 si_ctrl; /* System Interface Control Register */
106 u32 control; /* General Purpose Control Register */
109 /* ep0 transfer state */
110 #define WAIT_FOR_SETUP 0
111 #define DATA_STATE_XMIT 1
112 #define DATA_STATE_NEED_ZLP 2
113 #define WAIT_FOR_OUT_STATUS 3
114 #define DATA_STATE_RECV 4
116 /* Device Controller Capability Parameter register */
117 #define DCCPARAMS_DC 0x00000080
118 #define DCCPARAMS_DEN_MASK 0x0000001f
120 /* Frame Index Register Bit Masks */
121 #define USB_FRINDEX_MASKS 0x3fff
122 /* USB CMD Register Bit Masks */
123 #define USB_CMD_RUN_STOP 0x00000001
124 #define USB_CMD_CTRL_RESET 0x00000002
125 #define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
126 #define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
127 #define USB_CMD_INT_AA_DOORBELL 0x00000040
128 #define USB_CMD_ASP 0x00000300
129 #define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
130 #define USB_CMD_SUTW 0x00002000
131 #define USB_CMD_ATDTW 0x00004000
132 #define USB_CMD_ITC 0x00FF0000
134 /* bit 15,3,2 are frame list size */
135 #define USB_CMD_FRAME_SIZE_1024 0x00000000
136 #define USB_CMD_FRAME_SIZE_512 0x00000004
137 #define USB_CMD_FRAME_SIZE_256 0x00000008
138 #define USB_CMD_FRAME_SIZE_128 0x0000000C
139 #define USB_CMD_FRAME_SIZE_64 0x00008000
140 #define USB_CMD_FRAME_SIZE_32 0x00008004
141 #define USB_CMD_FRAME_SIZE_16 0x00008008
142 #define USB_CMD_FRAME_SIZE_8 0x0000800C
144 /* bit 9-8 are async schedule park mode count */
145 #define USB_CMD_ASP_00 0x00000000
146 #define USB_CMD_ASP_01 0x00000100
147 #define USB_CMD_ASP_10 0x00000200
148 #define USB_CMD_ASP_11 0x00000300
149 #define USB_CMD_ASP_BIT_POS 8
151 /* bit 23-16 are interrupt threshold control */
152 #define USB_CMD_ITC_NO_THRESHOLD 0x00000000
153 #define USB_CMD_ITC_1_MICRO_FRM 0x00010000
154 #define USB_CMD_ITC_2_MICRO_FRM 0x00020000
155 #define USB_CMD_ITC_4_MICRO_FRM 0x00040000
156 #define USB_CMD_ITC_8_MICRO_FRM 0x00080000
157 #define USB_CMD_ITC_16_MICRO_FRM 0x00100000
158 #define USB_CMD_ITC_32_MICRO_FRM 0x00200000
159 #define USB_CMD_ITC_64_MICRO_FRM 0x00400000
160 #define USB_CMD_ITC_BIT_POS 16
162 /* USB STS Register Bit Masks */
163 #define USB_STS_INT 0x00000001
164 #define USB_STS_ERR 0x00000002
165 #define USB_STS_PORT_CHANGE 0x00000004
166 #define USB_STS_FRM_LST_ROLL 0x00000008
167 #define USB_STS_SYS_ERR 0x00000010
168 #define USB_STS_IAA 0x00000020
169 #define USB_STS_RESET 0x00000040
170 #define USB_STS_SOF 0x00000080
171 #define USB_STS_SUSPEND 0x00000100
172 #define USB_STS_HC_HALTED 0x00001000
173 #define USB_STS_RCL 0x00002000
174 #define USB_STS_PERIODIC_SCHEDULE 0x00004000
175 #define USB_STS_ASYNC_SCHEDULE 0x00008000
177 /* USB INTR Register Bit Masks */
178 #define USB_INTR_INT_EN 0x00000001
179 #define USB_INTR_ERR_INT_EN 0x00000002
180 #define USB_INTR_PTC_DETECT_EN 0x00000004
181 #define USB_INTR_FRM_LST_ROLL_EN 0x00000008
182 #define USB_INTR_SYS_ERR_EN 0x00000010
183 #define USB_INTR_ASYN_ADV_EN 0x00000020
184 #define USB_INTR_RESET_EN 0x00000040
185 #define USB_INTR_SOF_EN 0x00000080
186 #define USB_INTR_DEVICE_SUSPEND 0x00000100
188 /* Device Address bit masks */
189 #define USB_DEVICE_ADDRESS_MASK 0xFE000000
190 #define USB_DEVICE_ADDRESS_BIT_POS 25
192 /* endpoint list address bit masks */
193 #define USB_EP_LIST_ADDRESS_MASK 0xfffff800
195 /* PORTSCX Register Bit Masks */
196 #define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001
197 #define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002
198 #define PORTSCX_PORT_ENABLE 0x00000004
199 #define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008
200 #define PORTSCX_OVER_CURRENT_ACT 0x00000010
201 #define PORTSCX_OVER_CURRENT_CHG 0x00000020
202 #define PORTSCX_PORT_FORCE_RESUME 0x00000040
203 #define PORTSCX_PORT_SUSPEND 0x00000080
204 #define PORTSCX_PORT_RESET 0x00000100
205 #define PORTSCX_LINE_STATUS_BITS 0x00000C00
206 #define PORTSCX_PORT_POWER 0x00001000
207 #define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000
208 #define PORTSCX_PORT_TEST_CTRL 0x000F0000
209 #define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000
210 #define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000
211 #define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000
212 #define PORTSCX_PHY_LOW_POWER_SPD 0x00800000
213 #define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000
214 #define PORTSCX_PORT_SPEED_MASK 0x0C000000
215 #define PORTSCX_PORT_WIDTH 0x10000000
216 #define PORTSCX_PHY_TYPE_SEL 0xC0000000
218 /* bit 11-10 are line status */
219 #define PORTSCX_LINE_STATUS_SE0 0x00000000
220 #define PORTSCX_LINE_STATUS_JSTATE 0x00000400
221 #define PORTSCX_LINE_STATUS_KSTATE 0x00000800
222 #define PORTSCX_LINE_STATUS_UNDEF 0x00000C00
223 #define PORTSCX_LINE_STATUS_BIT_POS 10
225 /* bit 15-14 are port indicator control */
226 #define PORTSCX_PIC_OFF 0x00000000
227 #define PORTSCX_PIC_AMBER 0x00004000
228 #define PORTSCX_PIC_GREEN 0x00008000
229 #define PORTSCX_PIC_UNDEF 0x0000C000
230 #define PORTSCX_PIC_BIT_POS 14
232 /* bit 19-16 are port test control */
233 #define PORTSCX_PTC_DISABLE 0x00000000
234 #define PORTSCX_PTC_JSTATE 0x00010000
235 #define PORTSCX_PTC_KSTATE 0x00020000
236 #define PORTSCX_PTC_SEQNAK 0x00030000
237 #define PORTSCX_PTC_PACKET 0x00040000
238 #define PORTSCX_PTC_FORCE_EN 0x00050000
239 #define PORTSCX_PTC_BIT_POS 16
241 /* bit 27-26 are port speed */
242 #define PORTSCX_PORT_SPEED_FULL 0x00000000
243 #define PORTSCX_PORT_SPEED_LOW 0x04000000
244 #define PORTSCX_PORT_SPEED_HIGH 0x08000000
245 #define PORTSCX_PORT_SPEED_UNDEF 0x0C000000
246 #define PORTSCX_SPEED_BIT_POS 26
248 /* bit 28 is parallel transceiver width for UTMI interface */
249 #define PORTSCX_PTW 0x10000000
250 #define PORTSCX_PTW_8BIT 0x00000000
251 #define PORTSCX_PTW_16BIT 0x10000000
253 /* bit 31-30 are port transceiver select */
254 #define PORTSCX_PTS_UTMI 0x00000000
255 #define PORTSCX_PTS_ULPI 0x80000000
256 #define PORTSCX_PTS_FSLS 0xC0000000
257 #define PORTSCX_PTS_BIT_POS 30
259 /* otgsc Register Bit Masks */
260 #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
261 #define OTGSC_CTRL_VUSB_CHARGE 0x00000002
262 #define OTGSC_CTRL_OTG_TERM 0x00000008
263 #define OTGSC_CTRL_DATA_PULSING 0x00000010
264 #define OTGSC_STS_USB_ID 0x00000100
265 #define OTGSC_STS_A_VBUS_VALID 0x00000200
266 #define OTGSC_STS_A_SESSION_VALID 0x00000400
267 #define OTGSC_STS_B_SESSION_VALID 0x00000800
268 #define OTGSC_STS_B_SESSION_END 0x00001000
269 #define OTGSC_STS_1MS_TOGGLE 0x00002000
270 #define OTGSC_STS_DATA_PULSING 0x00004000
271 #define OTGSC_INTSTS_USB_ID 0x00010000
272 #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
273 #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
274 #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
275 #define OTGSC_INTSTS_B_SESSION_END 0x00100000
276 #define OTGSC_INTSTS_1MS 0x00200000
277 #define OTGSC_INTSTS_DATA_PULSING 0x00400000
278 #define OTGSC_INTR_USB_ID 0x01000000
279 #define OTGSC_INTR_A_VBUS_VALID 0x02000000
280 #define OTGSC_INTR_A_SESSION_VALID 0x04000000
281 #define OTGSC_INTR_B_SESSION_VALID 0x08000000
282 #define OTGSC_INTR_B_SESSION_END 0x10000000
283 #define OTGSC_INTR_1MS_TIMER 0x20000000
284 #define OTGSC_INTR_DATA_PULSING 0x40000000
286 /* USB MODE Register Bit Masks */
287 #define USB_MODE_CTRL_MODE_IDLE 0x00000000
288 #define USB_MODE_CTRL_MODE_DEVICE 0x00000002
289 #define USB_MODE_CTRL_MODE_HOST 0x00000003
290 #define USB_MODE_CTRL_MODE_MASK 0x00000003
291 #define USB_MODE_CTRL_MODE_RSV 0x00000001
292 #define USB_MODE_ES 0x00000004 /* Endian Select */
293 #define USB_MODE_SETUP_LOCK_OFF 0x00000008
294 #define USB_MODE_STREAM_DISABLE 0x00000010
295 /* Endpoint Flush Register */
296 #define EPFLUSH_TX_OFFSET 0x00010000
297 #define EPFLUSH_RX_OFFSET 0x00000000
299 /* Endpoint Setup Status bit masks */
300 #define EP_SETUP_STATUS_MASK 0x0000003F
301 #define EP_SETUP_STATUS_EP0 0x00000001
303 /* ENDPOINTCTRLx Register Bit Masks */
304 #define EPCTRL_TX_ENABLE 0x00800000
305 #define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
306 #define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
307 #define EPCTRL_TX_TYPE 0x000C0000
308 #define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
309 #define EPCTRL_TX_EP_STALL 0x00010000
310 #define EPCTRL_RX_ENABLE 0x00000080
311 #define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
312 #define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
313 #define EPCTRL_RX_TYPE 0x0000000C
314 #define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
315 #define EPCTRL_RX_EP_STALL 0x00000001
317 /* bit 19-18 and 3-2 are endpoint type */
318 #define EPCTRL_EP_TYPE_CONTROL 0
319 #define EPCTRL_EP_TYPE_ISO 1
320 #define EPCTRL_EP_TYPE_BULK 2
321 #define EPCTRL_EP_TYPE_INTERRUPT 3
322 #define EPCTRL_TX_EP_TYPE_SHIFT 18
323 #define EPCTRL_RX_EP_TYPE_SHIFT 2
325 /* SNOOPn Register Bit Masks */
326 #define SNOOP_ADDRESS_MASK 0xFFFFF000
327 #define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
328 #define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
329 #define SNOOP_SIZE_8KB 0x0C
330 #define SNOOP_SIZE_16KB 0x0D
331 #define SNOOP_SIZE_32KB 0x0E
332 #define SNOOP_SIZE_64KB 0x0F
333 #define SNOOP_SIZE_128KB 0x10
334 #define SNOOP_SIZE_256KB 0x11
335 #define SNOOP_SIZE_512KB 0x12
336 #define SNOOP_SIZE_1MB 0x13
337 #define SNOOP_SIZE_2MB 0x14
338 #define SNOOP_SIZE_4MB 0x15
339 #define SNOOP_SIZE_8MB 0x16
340 #define SNOOP_SIZE_16MB 0x17
341 #define SNOOP_SIZE_32MB 0x18
342 #define SNOOP_SIZE_64MB 0x19
343 #define SNOOP_SIZE_128MB 0x1A
344 #define SNOOP_SIZE_256MB 0x1B
345 #define SNOOP_SIZE_512MB 0x1C
346 #define SNOOP_SIZE_1GB 0x1D
347 #define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
349 /* pri_ctrl Register Bit Masks */
350 #define PRI_CTRL_PRI_LVL1 0x0000000C
351 #define PRI_CTRL_PRI_LVL0 0x00000003
353 /* si_ctrl Register Bit Masks */
354 #define SI_CTRL_ERR_DISABLE 0x00000010
355 #define SI_CTRL_IDRC_DISABLE 0x00000008
356 #define SI_CTRL_RD_SAFE_EN 0x00000004
357 #define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
358 #define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
360 /* control Register Bit Masks */
361 #define USB_CTRL_IOENB 0x00000004
362 #define USB_CTRL_ULPI_INT0EN 0x00000001
363 #define USB_CTRL_UTMI_PHY_EN 0x00000200
364 #define USB_CTRL_USB_EN 0x00000004
365 #define USB_CTRL_ULPI_PHY_CLK_SEL 0x00000400
367 /* Endpoint Queue Head data struct
368 * Rem: all the variables of qh are LittleEndian Mode
369 * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr
371 struct ep_queue_head {
372 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
374 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */
375 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */
376 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15),
377 MultO(11-10), STS (7-0) */
378 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */
379 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */
380 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */
381 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */
382 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */
384 u8 setup_buffer[8]; /* Setup data 8 bytes */
388 /* Endpoint Queue Head Bit Masks */
389 #define EP_QUEUE_HEAD_MULT_POS 30
390 #define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
391 #define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16
392 #define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
393 #define EP_QUEUE_HEAD_IOS 0x00008000
394 #define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
395 #define EP_QUEUE_HEAD_IOC 0x00008000
396 #define EP_QUEUE_HEAD_MULTO 0x00000C00
397 #define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
398 #define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
399 #define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
400 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
401 #define EP_QUEUE_FRINDEX_MASK 0x000007FF
402 #define EP_MAX_LENGTH_TRANSFER 0x4000
404 /* Endpoint Transfer Descriptor data struct */
405 /* Rem: all the variables of td are LittleEndian Mode */
406 struct ep_td_struct {
407 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set
409 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15),
410 MultO(11-10), STS (7-0) */
411 u32 buff_ptr0; /* Buffer pointer Page 0 */
412 u32 buff_ptr1; /* Buffer pointer Page 1 */
413 u32 buff_ptr2; /* Buffer pointer Page 2 */
414 u32 buff_ptr3; /* Buffer pointer Page 3 */
415 u32 buff_ptr4; /* Buffer pointer Page 4 */
418 dma_addr_t td_dma; /* dma address for this td */
419 /* virtual address of next td specified in next_td_ptr */
420 struct ep_td_struct *next_td_virt;
423 /* Endpoint Transfer Descriptor bit Masks */
424 #define DTD_NEXT_TERMINATE 0x00000001
425 #define DTD_IOC 0x00008000
426 #define DTD_STATUS_ACTIVE 0x00000080
427 #define DTD_STATUS_HALTED 0x00000040
428 #define DTD_STATUS_DATA_BUFF_ERR 0x00000020
429 #define DTD_STATUS_TRANSACTION_ERR 0x00000008
430 #define DTD_RESERVED_FIELDS 0x80007300
431 #define DTD_ADDR_MASK 0xFFFFFFE0
432 #define DTD_PACKET_SIZE 0x7FFF0000
433 #define DTD_LENGTH_BIT_POS 16
434 #define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
435 DTD_STATUS_DATA_BUFF_ERR | \
436 DTD_STATUS_TRANSACTION_ERR)
437 /* Alignment requirements; must be a power of two */
438 #define DTD_ALIGNMENT 0x20
439 #define QH_ALIGNMENT 2048
441 /* Controller dma boundary */
442 #define UDC_DMA_BOUNDARY 0x1000
444 /*-------------------------------------------------------------------------*/
446 /* ### driver private data
449 struct usb_request req;
450 struct list_head queue;
451 /* ep_queue() func will add
452 a request->queue into a udc_ep->queue 'd tail */
456 struct ep_td_struct *head, *tail; /* For dTD List
457 cpu endian Virtual addr */
458 unsigned int dtd_count;
461 #define REQ_UNCOMPLETE 1
465 struct list_head queue;
467 struct ep_queue_head *qh;
468 struct usb_gadget *gadget;
478 struct usb_gadget gadget;
479 struct usb_gadget_driver *driver;
480 struct fsl_usb2_platform_data *pdata;
481 struct completion *done; /* to make sure release() is done */
486 struct usb_ctrlrequest local_setup_buff;
488 struct usb_phy *transceiver;
489 unsigned softconnect:1;
490 unsigned vbus_active:1;
492 unsigned remote_wakeup:1;
493 unsigned already_stopped:1;
494 unsigned big_endian_desc:1;
496 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
497 struct fsl_req *status_req; /* ep0 status request */
498 struct dma_pool *td_pool; /* dma pool for DTD */
499 enum fsl_usb2_phy_modes phy_mode;
501 size_t ep_qh_size; /* size after alignment adjustment*/
502 dma_addr_t ep_qh_dma; /* dma address of QH */
504 u32 max_pipes; /* Device max pipes */
505 u32 bus_reset; /* Device is bus resetting */
506 u32 resume_state; /* USB state to resume */
507 u32 usb_state; /* USB current state */
508 u32 ep0_state; /* Endpoint zero state */
509 u32 ep0_dir; /* Endpoint zero direction: can be
510 USB_DIR_IN or USB_DIR_OUT */
511 u8 device_address; /* Device USB address */
514 /*-------------------------------------------------------------------------*/
517 #define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \
520 #define DBG(fmt, args...) do{}while(0)
524 static void dump_msg(const char *label, const u8 * buf, unsigned int length)
526 unsigned int start, num, i;
531 DBG("%s, length %u:\n", label, length);
534 num = min(length, 16u);
536 for (i = 0; i < num; ++i) {
539 sprintf(p, " %02x", buf[i]);
543 printk(KERN_DEBUG "%6x: %s\n", start, line);
554 #define VDBG(stuff...) do{}while(0)
557 #define ERR(stuff...) pr_err("udc: " stuff)
558 #define WARNING(stuff...) pr_warn("udc: " stuff)
559 #define INFO(stuff...) pr_info("udc: " stuff)
561 /*-------------------------------------------------------------------------*/
563 /* ### Add board specific defines here
567 * ### pipe direction macro from device view
569 #define USB_RECV 0 /* OUT EP */
570 #define USB_SEND 1 /* IN EP */
573 * ### internal used help routines.
575 #define ep_index(EP) ((EP)->ep.desc->bEndpointAddress&0xF)
576 #define ep_maxpacket(EP) ((EP)->ep.maxpacket)
577 #define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
578 USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \
579 & USB_DIR_IN)==USB_DIR_IN)
580 #define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \
582 #define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \
583 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
584 #define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
586 static inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep)
588 /* we only have one ep0 structure but two queue heads */
589 if (ep_index(ep) != 0)
592 return &ep->udc->ep_qh[(ep->udc->ep0_dir ==
593 USB_DIR_IN) ? 1 : 0];
596 struct platform_device;
597 #ifdef CONFIG_ARCH_MXC
598 int fsl_udc_clk_init(struct platform_device *pdev);
599 int fsl_udc_clk_finalize(struct platform_device *pdev);
600 void fsl_udc_clk_release(void);
602 static inline int fsl_udc_clk_init(struct platform_device *pdev)
606 static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
610 static inline void fsl_udc_clk_release(void)