drivers/usb/gadget/udc/fsl_udc_core.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
   4  * All rights reserved.
   5  *
   6  * Author: Li Yang <leoli@freescale.com>
   7  *         Jiang Bo <tanya.jiang@freescale.com>
   8  *
   9  * Description:
  10  * Freescale high-speed USB SOC DR module device controller driver.
  11  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  12  * The driver is previously named as mpc_udc.  Based on bare board
  13  * code from Dave Liu and Shlomi Gridish.
  14  */
  15
  16 #define pr_fmt(x) "udc: " x
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/err.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/mm.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/device.h>
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38 #include <linux/dmapool.h>
  39
  40 #include <asm/byteorder.h>
  41 #include <asm/io.h>
  42 #include <asm/unaligned.h>
  43 #include <asm/dma.h>
  44
  45 #include "fsl_usb2_udc.h"
  46
  47 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  48 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  49 #define DRIVER_VERSION  "Apr 20, 2007"
  50
  51 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  52
  53 static const char driver_name[] = "fsl-usb2-udc";
  54
  55 static struct usb_dr_device __iomem *dr_regs;
  56
  57 static struct usb_sys_interface __iomem *usb_sys_regs;
  58
  59 /* it is initialized in probe()  */
  60 static struct fsl_udc *udc_controller = NULL;
  61
  62 static const struct usb_endpoint_descriptor
  63 fsl_ep0_desc = {
  64         .bLength =              USB_DT_ENDPOINT_SIZE,
  65         .bDescriptorType =      USB_DT_ENDPOINT,
  66         .bEndpointAddress =     0,
  67         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  68         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  69 };
  70
  71 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  72
  73 #ifdef CONFIG_PPC32
  74 /*
  75  * On some SoCs, the USB controller registers can be big or little endian,
  76  * depending on the version of the chip. In order to be able to run the
  77  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  78  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  79  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  80  * call through those pointers. Platform code for SoCs that have BE USB
  81  * registers should set pdata->big_endian_mmio flag.
  82  *
  83  * This also applies to controller-to-cpu accessors for the USB descriptors,
  84  * since their endianness is also SoC dependant. Platform code for SoCs that
  85  * have BE USB descriptors should set pdata->big_endian_desc flag.
  86  */
  87 static u32 _fsl_readl_be(const unsigned __iomem *p)
  88 {
  89         return in_be32(p);
  90 }
  91
  92 static u32 _fsl_readl_le(const unsigned __iomem *p)
  93 {
  94         return in_le32(p);
  95 }
  96
  97 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
  98 {
  99         out_be32(p, v);
 100 }
 101
 102 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 103 {
 104         out_le32(p, v);
 105 }
 106
 107 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 108 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 109
 110 #define fsl_readl(p)            (*_fsl_readl)((p))
 111 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 112
 113 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 114 {
 115         if (pdata->big_endian_mmio) {
 116                 _fsl_readl = _fsl_readl_be;
 117                 _fsl_writel = _fsl_writel_be;
 118         } else {
 119                 _fsl_readl = _fsl_readl_le;
 120                 _fsl_writel = _fsl_writel_le;
 121         }
 122 }
 123
 124 static inline u32 cpu_to_hc32(const u32 x)
 125 {
 126         return udc_controller->pdata->big_endian_desc
 127                 ? (__force u32)cpu_to_be32(x)
 128                 : (__force u32)cpu_to_le32(x);
 129 }
 130
 131 static inline u32 hc32_to_cpu(const u32 x)
 132 {
 133         return udc_controller->pdata->big_endian_desc
 134                 ? be32_to_cpu((__force __be32)x)
 135                 : le32_to_cpu((__force __le32)x);
 136 }
 137 #else /* !CONFIG_PPC32 */
 138 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 139
 140 #define fsl_readl(addr)         readl(addr)
 141 #define fsl_writel(val32, addr) writel(val32, addr)
 142 #define cpu_to_hc32(x)          cpu_to_le32(x)
 143 #define hc32_to_cpu(x)          le32_to_cpu(x)
 144 #endif /* CONFIG_PPC32 */
 145
 146 /********************************************************************
 147  *      Internal Used Function
 148 ********************************************************************/
 149 /*-----------------------------------------------------------------
 150  * done() - retire a request; caller blocked irqs
 151  * @status : request status to be set, only works when
 152  *      request is still in progress.
 153  *--------------------------------------------------------------*/
 154 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 155 __releases(ep->udc->lock)
 156 __acquires(ep->udc->lock)
 157 {
 158         struct fsl_udc *udc = NULL;
 159         unsigned char stopped = ep->stopped;
 160         struct ep_td_struct *curr_td, *next_td;
 161         int j;
 162
 163         udc = (struct fsl_udc *)ep->udc;
 164         /* Removed the req from fsl_ep->queue */
 165         list_del_init(&req->queue);
 166
 167         /* req.status should be set as -EINPROGRESS in ep_queue() */
 168         if (req->req.status == -EINPROGRESS)
 169                 req->req.status = status;
 170         else
 171                 status = req->req.status;
 172
 173         /* Free dtd for the request */
 174         next_td = req->head;
 175         for (j = 0; j < req->dtd_count; j++) {
 176                 curr_td = next_td;
 177                 if (j != req->dtd_count - 1) {
 178                         next_td = curr_td->next_td_virt;
 179                 }
 180                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 181         }
 182
 183         usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 184
 185         if (status && (status != -ESHUTDOWN))
 186                 dev_vdbg(&udc->gadget.dev, "complete %s req %p stat %d len %u/%u\n",
 187                          ep->ep.name, &req->req, status,
 188                          req->req.actual, req->req.length);
 189
 190         ep->stopped = 1;
 191
 192         spin_unlock(&ep->udc->lock);
 193
 194         usb_gadget_giveback_request(&ep->ep, &req->req);
 195
 196         spin_lock(&ep->udc->lock);
 197         ep->stopped = stopped;
 198 }
 199
 200 /*-----------------------------------------------------------------
 201  * nuke(): delete all requests related to this ep
 202  * called with spinlock held
 203  *--------------------------------------------------------------*/
 204 static void nuke(struct fsl_ep *ep, int status)
 205 {
 206         ep->stopped = 1;
 207
 208         /* Flush fifo */
 209         fsl_ep_fifo_flush(&ep->ep);
 210
 211         /* Whether this eq has request linked */
 212         while (!list_empty(&ep->queue)) {
 213                 struct fsl_req *req = NULL;
 214
 215                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 216                 done(ep, req, status);
 217         }
 218 }
 219
 220 /*------------------------------------------------------------------
 221         Internal Hardware related function
 222  ------------------------------------------------------------------*/
 223
 224 static int dr_controller_setup(struct fsl_udc *udc)
 225 {
 226         unsigned int tmp, portctrl, ep_num;
 227         unsigned int max_no_of_ep;
 228         unsigned int ctrl;
 229         unsigned long timeout;
 230
 231 #define FSL_UDC_RESET_TIMEOUT 1000
 232
 233         /* Config PHY interface */
 234         portctrl = fsl_readl(&dr_regs->portsc1);
 235         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 236         switch (udc->phy_mode) {
 237         case FSL_USB2_PHY_ULPI:
 238                 if (udc->pdata->have_sysif_regs) {
 239                         if (udc->pdata->controller_ver) {
 240                                 /* controller version 1.6 or above */
 241                                 ctrl = __raw_readl(&usb_sys_regs->control);
 242                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
 243                                 ctrl |= USB_CTRL_USB_EN;
 244                                 __raw_writel(ctrl, &usb_sys_regs->control);
 245                         }
 246                 }
 247                 portctrl |= PORTSCX_PTS_ULPI;
 248                 break;
 249         case FSL_USB2_PHY_UTMI_WIDE:
 250                 portctrl |= PORTSCX_PTW_16BIT;
 251                 fallthrough;
 252         case FSL_USB2_PHY_UTMI:
 253         case FSL_USB2_PHY_UTMI_DUAL:
 254                 if (udc->pdata->have_sysif_regs) {
 255                         if (udc->pdata->controller_ver) {
 256                                 /* controller version 1.6 or above */
 257                                 ctrl = __raw_readl(&usb_sys_regs->control);
 258                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
 259                                         USB_CTRL_USB_EN);
 260                                 __raw_writel(ctrl, &usb_sys_regs->control);
 261                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
 262                                         PHY CLK to become stable - 10ms*/
 263                         }
 264                 }
 265                 portctrl |= PORTSCX_PTS_UTMI;
 266                 break;
 267         case FSL_USB2_PHY_SERIAL:
 268                 portctrl |= PORTSCX_PTS_FSLS;
 269                 break;
 270         default:
 271                 return -EINVAL;
 272         }
 273         fsl_writel(portctrl, &dr_regs->portsc1);
 274
 275         /* Stop and reset the usb controller */
 276         tmp = fsl_readl(&dr_regs->usbcmd);
 277         tmp &= ~USB_CMD_RUN_STOP;
 278         fsl_writel(tmp, &dr_regs->usbcmd);
 279
 280         tmp = fsl_readl(&dr_regs->usbcmd);
 281         tmp |= USB_CMD_CTRL_RESET;
 282         fsl_writel(tmp, &dr_regs->usbcmd);
 283
 284         /* Wait for reset to complete */
 285         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 286         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 287                 if (time_after(jiffies, timeout)) {
 288                         dev_err(&udc->gadget.dev, "udc reset timeout!\n");
 289                         return -ETIMEDOUT;
 290                 }
 291                 cpu_relax();
 292         }
 293
 294         /* Set the controller as device mode */
 295         tmp = fsl_readl(&dr_regs->usbmode);
 296         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 297         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 298         /* Disable Setup Lockout */
 299         tmp |= USB_MODE_SETUP_LOCK_OFF;
 300         if (udc->pdata->es)
 301                 tmp |= USB_MODE_ES;
 302         fsl_writel(tmp, &dr_regs->usbmode);
 303
 304         /* Clear the setup status */
 305         fsl_writel(0, &dr_regs->usbsts);
 306
 307         tmp = udc->ep_qh_dma;
 308         tmp &= USB_EP_LIST_ADDRESS_MASK;
 309         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 310
 311         dev_vdbg(&udc->gadget.dev,
 312                  "vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x\n",
 313                  udc->ep_qh, (int)tmp,
 314                  fsl_readl(&dr_regs->endpointlistaddr));
 315
 316         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 317         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 318                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 319                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 320                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 321                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 322                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 323         }
 324         /* Config control enable i/o output, cpu endian register */
 325         if (udc->pdata->have_sysif_regs) {
 326                 ctrl = __raw_readl(&usb_sys_regs->control);
 327                 ctrl |= USB_CTRL_IOENB;
 328                 __raw_writel(ctrl, &usb_sys_regs->control);
 329         }
 330
 331 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 332         /* Turn on cache snooping hardware, since some PowerPC platforms
 333          * wholly rely on hardware to deal with cache coherent. */
 334
 335         if (udc->pdata->have_sysif_regs) {
 336                 /* Setup Snooping for all the 4GB space */
 337                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 338                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 339                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 340                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 341         }
 342 #endif
 343
 344         return 0;
 345 }
 346
 347 /* Enable DR irq and set controller to run state */
 348 static void dr_controller_run(struct fsl_udc *udc)
 349 {
 350         u32 temp;
 351
 352         /* Enable DR irq reg */
 353         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 354                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 355                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 356
 357         fsl_writel(temp, &dr_regs->usbintr);
 358
 359         /* Clear stopped bit */
 360         udc->stopped = 0;
 361
 362         /* Set the controller as device mode */
 363         temp = fsl_readl(&dr_regs->usbmode);
 364         temp |= USB_MODE_CTRL_MODE_DEVICE;
 365         fsl_writel(temp, &dr_regs->usbmode);
 366
 367         /* Set controller to Run */
 368         temp = fsl_readl(&dr_regs->usbcmd);
 369         temp |= USB_CMD_RUN_STOP;
 370         fsl_writel(temp, &dr_regs->usbcmd);
 371 }
 372
 373 static void dr_controller_stop(struct fsl_udc *udc)
 374 {
 375         unsigned int tmp;
 376
 377         pr_debug("%s\n", __func__);
 378
 379         /* if we're in OTG mode, and the Host is currently using the port,
 380          * stop now and don't rip the controller out from under the
 381          * ehci driver
 382          */
 383         if (udc->gadget.is_otg) {
 384                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 385                         pr_debug("udc: Leaving early\n");
 386                         return;
 387                 }
 388         }
 389
 390         /* disable all INTR */
 391         fsl_writel(0, &dr_regs->usbintr);
 392
 393         /* Set stopped bit for isr */
 394         udc->stopped = 1;
 395
 396         /* disable IO output */
 397 /*      usb_sys_regs->control = 0; */
 398
 399         /* set controller to Stop */
 400         tmp = fsl_readl(&dr_regs->usbcmd);
 401         tmp &= ~USB_CMD_RUN_STOP;
 402         fsl_writel(tmp, &dr_regs->usbcmd);
 403 }
 404
 405 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 406                         unsigned char ep_type)
 407 {
 408         unsigned int tmp_epctrl = 0;
 409
 410         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 411         if (dir) {
 412                 if (ep_num)
 413                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 414                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 415                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 416                 tmp_epctrl |= ((unsigned int)(ep_type)
 417                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 418         } else {
 419                 if (ep_num)
 420                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 421                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 422                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 423                 tmp_epctrl |= ((unsigned int)(ep_type)
 424                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 425         }
 426
 427         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 428 }
 429
 430 static void
 431 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 432 {
 433         u32 tmp_epctrl = 0;
 434
 435         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 436
 437         if (value) {
 438                 /* set the stall bit */
 439                 if (dir)
 440                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 441                 else
 442                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 443         } else {
 444                 /* clear the stall bit and reset data toggle */
 445                 if (dir) {
 446                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 447                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 448                 } else {
 449                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 450                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 451                 }
 452         }
 453         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 454 }
 455
 456 /* Get stall status of a specific ep
 457    Return: 0: not stalled; 1:stalled */
 458 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 459 {
 460         u32 epctrl;
 461
 462         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 463         if (dir)
 464                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 465         else
 466                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 467 }
 468
 469 /********************************************************************
 470         Internal Structure Build up functions
 471 ********************************************************************/
 472
 473 /*------------------------------------------------------------------
 474 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 475  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 476  * @mult: Mult field
 477  ------------------------------------------------------------------*/
 478 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 479                 unsigned char dir, unsigned char ep_type,
 480                 unsigned int max_pkt_len,
 481                 unsigned int zlt, unsigned char mult)
 482 {
 483         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 484         unsigned int tmp = 0;
 485
 486         /* set the Endpoint Capabilites in QH */
 487         switch (ep_type) {
 488         case USB_ENDPOINT_XFER_CONTROL:
 489                 /* Interrupt On Setup (IOS). for control ep  */
 490                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 491                         | EP_QUEUE_HEAD_IOS;
 492                 break;
 493         case USB_ENDPOINT_XFER_ISOC:
 494                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 495                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 496                 break;
 497         case USB_ENDPOINT_XFER_BULK:
 498         case USB_ENDPOINT_XFER_INT:
 499                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 500                 break;
 501         default:
 502                 dev_vdbg(&udc->gadget.dev, "error ep type is %d\n", ep_type);
 503                 return;
 504         }
 505         if (zlt)
 506                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 507
 508         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 509         p_QH->next_dtd_ptr = 1;
 510         p_QH->size_ioc_int_sts = 0;
 511 }
 512
 513 /* Setup qh structure and ep register for ep0. */
 514 static void ep0_setup(struct fsl_udc *udc)
 515 {
 516         /* the initialization of an ep includes: fields in QH, Regs,
 517          * fsl_ep struct */
 518         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 519                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 520         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 521                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 522         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 523         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 524
 525         return;
 526
 527 }
 528
 529 /***********************************************************************
 530                 Endpoint Management Functions
 531 ***********************************************************************/
 532
 533 /*-------------------------------------------------------------------------
 534  * when configurations are set, or when interface settings change
 535  * for example the do_set_interface() in gadget layer,
 536  * the driver will enable or disable the relevant endpoints
 537  * ep0 doesn't use this routine. It is always enabled.
 538 -------------------------------------------------------------------------*/
 539 static int fsl_ep_enable(struct usb_ep *_ep,
 540                 const struct usb_endpoint_descriptor *desc)
 541 {
 542         struct fsl_udc *udc = NULL;
 543         struct fsl_ep *ep = NULL;
 544         unsigned short max = 0;
 545         unsigned char mult = 0, zlt;
 546         int retval = -EINVAL;
 547         unsigned long flags;
 548
 549         ep = container_of(_ep, struct fsl_ep, ep);
 550
 551         /* catch various bogus parameters */
 552         if (!_ep || !desc
 553                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 554                 return -EINVAL;
 555
 556         udc = ep->udc;
 557
 558         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 559                 return -ESHUTDOWN;
 560
 561         max = usb_endpoint_maxp(desc);
 562
 563         /* Disable automatic zlp generation.  Driver is responsible to indicate
 564          * explicitly through req->req.zero.  This is needed to enable multi-td
 565          * request. */
 566         zlt = 1;
 567
 568         /* Assume the max packet size from gadget is always correct */
 569         switch (desc->bmAttributes & 0x03) {
 570         case USB_ENDPOINT_XFER_CONTROL:
 571         case USB_ENDPOINT_XFER_BULK:
 572         case USB_ENDPOINT_XFER_INT:
 573                 /* mult = 0.  Execute N Transactions as demonstrated by
 574                  * the USB variable length packet protocol where N is
 575                  * computed using the Maximum Packet Length (dQH) and
 576                  * the Total Bytes field (dTD) */
 577                 mult = 0;
 578                 break;
 579         case USB_ENDPOINT_XFER_ISOC:
 580                 /* Calculate transactions needed for high bandwidth iso */
 581                 mult = usb_endpoint_maxp_mult(desc);
 582                 /* 3 transactions at most */
 583                 if (mult > 3)
 584                         goto en_done;
 585                 break;
 586         default:
 587                 goto en_done;
 588         }
 589
 590         spin_lock_irqsave(&udc->lock, flags);
 591         ep->ep.maxpacket = max;
 592         ep->ep.desc = desc;
 593         ep->stopped = 0;
 594
 595         /* Controller related setup */
 596         /* Init EPx Queue Head (Ep Capabilites field in QH
 597          * according to max, zlt, mult) */
 598         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 599                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 600                                         ?  USB_SEND : USB_RECV),
 601                         (unsigned char) (desc->bmAttributes
 602                                         & USB_ENDPOINT_XFERTYPE_MASK),
 603                         max, zlt, mult);
 604
 605         /* Init endpoint ctrl register */
 606         dr_ep_setup((unsigned char) ep_index(ep),
 607                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 608                                         ? USB_SEND : USB_RECV),
 609                         (unsigned char) (desc->bmAttributes
 610                                         & USB_ENDPOINT_XFERTYPE_MASK));
 611
 612         spin_unlock_irqrestore(&udc->lock, flags);
 613         retval = 0;
 614
 615         dev_vdbg(&udc->gadget.dev, "enabled %s (ep%d%s) maxpacket %d\n",
 616                  ep->ep.name, ep->ep.desc->bEndpointAddress & 0x0f,
 617                  (desc->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
 618                  max);
 619 en_done:
 620         return retval;
 621 }
 622
 623 /*---------------------------------------------------------------------
 624  * @ep : the ep being unconfigured. May not be ep0
 625  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 626 *---------------------------------------------------------------------*/
 627 static int fsl_ep_disable(struct usb_ep *_ep)
 628 {
 629         struct fsl_udc *udc = NULL;
 630         struct fsl_ep *ep = NULL;
 631         unsigned long flags;
 632         u32 epctrl;
 633         int ep_num;
 634
 635         ep = container_of(_ep, struct fsl_ep, ep);
 636         if (!_ep || !ep->ep.desc) {
 637                 /*
 638                  * dev_vdbg(&udc->gadget.dev, "%s not enabled\n",
 639                  *       _ep ? ep->ep.name : NULL);
 640                  */
 641                 return -EINVAL;
 642         }
 643
 644         /* disable ep on controller */
 645         ep_num = ep_index(ep);
 646         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 647         if (ep_is_in(ep)) {
 648                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 649                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 650         } else {
 651                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 652                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 653         }
 654         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 655
 656         udc = (struct fsl_udc *)ep->udc;
 657         spin_lock_irqsave(&udc->lock, flags);
 658
 659         /* nuke all pending requests (does flush) */
 660         nuke(ep, -ESHUTDOWN);
 661
 662         ep->ep.desc = NULL;
 663         ep->stopped = 1;
 664         spin_unlock_irqrestore(&udc->lock, flags);
 665
 666         dev_vdbg(&udc->gadget.dev, "disabled %s OK\n", _ep->name);
 667         return 0;
 668 }
 669
 670 /*---------------------------------------------------------------------
 671  * allocate a request object used by this endpoint
 672  * the main operation is to insert the req->queue to the eq->queue
 673  * Returns the request, or null if one could not be allocated
 674 *---------------------------------------------------------------------*/
 675 static struct usb_request *
 676 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 677 {
 678         struct fsl_req *req;
 679
 680         req = kzalloc(sizeof *req, gfp_flags);
 681         if (!req)
 682                 return NULL;
 683
 684         req->req.dma = DMA_ADDR_INVALID;
 685         INIT_LIST_HEAD(&req->queue);
 686
 687         return &req->req;
 688 }
 689
 690 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 691 {
 692         struct fsl_req *req = NULL;
 693
 694         req = container_of(_req, struct fsl_req, req);
 695
 696         if (_req)
 697                 kfree(req);
 698 }
 699
 700 /* Actually add a dTD chain to an empty dQH and let go */
 701 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 702 {
 703         struct ep_queue_head *qh = get_qh_by_ep(ep);
 704
 705         /* Write dQH next pointer and terminate bit to 0 */
 706         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 707                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 708
 709         /* Clear active and halt bit */
 710         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 711                                         | EP_QUEUE_HEAD_STATUS_HALT));
 712
 713         /* Ensure that updates to the QH will occur before priming. */
 714         wmb();
 715
 716         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 717         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 718                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 719 }
 720
 721 /* Add dTD chain to the dQH of an EP */
 722 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 723 {
 724         u32 temp, bitmask, tmp_stat;
 725
 726         /* dev_vdbg(&udc->gadget.dev, "QH addr Register 0x%8x\n", dr_regs->endpointlistaddr);
 727         dev_vdbg(&udc->gadget.dev, "ep_qh[%d] addr is 0x%8x\n", i, (u32)&(ep->udc->ep_qh[i])); */
 728
 729         bitmask = ep_is_in(ep)
 730                 ? (1 << (ep_index(ep) + 16))
 731                 : (1 << (ep_index(ep)));
 732
 733         /* check if the pipe is empty */
 734         if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
 735                 /* Add td to the end */
 736                 struct fsl_req *lastreq;
 737                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 738                 lastreq->tail->next_td_ptr =
 739                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 740                 /* Ensure dTD's next dtd pointer to be updated */
 741                 wmb();
 742                 /* Read prime bit, if 1 goto done */
 743                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 744                         return;
 745
 746                 do {
 747                         /* Set ATDTW bit in USBCMD */
 748                         temp = fsl_readl(&dr_regs->usbcmd);
 749                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 750
 751                         /* Read correct status bit */
 752                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 753
 754                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 755
 756                 /* Write ATDTW bit to 0 */
 757                 temp = fsl_readl(&dr_regs->usbcmd);
 758                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 759
 760                 if (tmp_stat)
 761                         return;
 762         }
 763
 764         fsl_prime_ep(ep, req->head);
 765 }
 766
 767 /* Fill in the dTD structure
 768  * @req: request that the transfer belongs to
 769  * @length: return actually data length of the dTD
 770  * @dma: return dma address of the dTD
 771  * @is_last: return flag if it is the last dTD of the request
 772  * return: pointer to the built dTD */
 773 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 774                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 775 {
 776         u32 swap_temp;
 777         struct ep_td_struct *dtd;
 778
 779         /* how big will this transfer be? */
 780         *length = min(req->req.length - req->req.actual,
 781                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 782
 783         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 784         if (dtd == NULL)
 785                 return dtd;
 786
 787         dtd->td_dma = *dma;
 788         /* Clear reserved field */
 789         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 790         swap_temp &= ~DTD_RESERVED_FIELDS;
 791         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 792
 793         /* Init all of buffer page pointers */
 794         swap_temp = (u32) (req->req.dma + req->req.actual);
 795         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 796         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 797         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 798         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 799         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 800
 801         req->req.actual += *length;
 802
 803         /* zlp is needed if req->req.zero is set */
 804         if (req->req.zero) {
 805                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 806                         *is_last = 1;
 807                 else
 808                         *is_last = 0;
 809         } else if (req->req.length == req->req.actual)
 810                 *is_last = 1;
 811         else
 812                 *is_last = 0;
 813
 814         if ((*is_last) == 0)
 815                 dev_vdbg(&udc_controller->gadget.dev, "multi-dtd request!\n");
 816         /* Fill in the transfer size; set active bit */
 817         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 818
 819         /* Enable interrupt for the last dtd of a request */
 820         if (*is_last && !req->req.no_interrupt)
 821                 swap_temp |= DTD_IOC;
 822
 823         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 824
 825         mb();
 826
 827         dev_vdbg(&udc_controller->gadget.dev, "length = %d address= 0x%x\n", *length, (int)*dma);
 828
 829         return dtd;
 830 }
 831
 832 /* Generate dtd chain for a request */
 833 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 834 {
 835         unsigned        count;
 836         int             is_last;
 837         int             is_first =1;
 838         struct ep_td_struct     *last_dtd = NULL, *dtd;
 839         dma_addr_t dma;
 840
 841         do {
 842                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 843                 if (dtd == NULL)
 844                         return -ENOMEM;
 845
 846                 if (is_first) {
 847                         is_first = 0;
 848                         req->head = dtd;
 849                 } else {
 850                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 851                         last_dtd->next_td_virt = dtd;
 852                 }
 853                 last_dtd = dtd;
 854
 855                 req->dtd_count++;
 856         } while (!is_last);
 857
 858         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 859
 860         req->tail = dtd;
 861
 862         return 0;
 863 }
 864
 865 /* queues (submits) an I/O request to an endpoint */
 866 static int
 867 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 868 {
 869         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 870         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 871         struct fsl_udc *udc;
 872         unsigned long flags;
 873         int ret;
 874
 875         /* catch various bogus parameters */
 876         if (!_req || !req->req.complete || !req->req.buf
 877                         || !list_empty(&req->queue)) {
 878                 dev_vdbg(&udc->gadget.dev, "%s, bad params\n", __func__);
 879                 return -EINVAL;
 880         }
 881         if (unlikely(!_ep || !ep->ep.desc)) {
 882                 dev_vdbg(&udc->gadget.dev, "%s, bad ep\n", __func__);
 883                 return -EINVAL;
 884         }
 885         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
 886                 if (req->req.length > ep->ep.maxpacket)
 887                         return -EMSGSIZE;
 888         }
 889
 890         udc = ep->udc;
 891         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 892                 return -ESHUTDOWN;
 893
 894         req->ep = ep;
 895
 896         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 897         if (ret)
 898                 return ret;
 899
 900         req->req.status = -EINPROGRESS;
 901         req->req.actual = 0;
 902         req->dtd_count = 0;
 903
 904         /* build dtds and push them to device queue */
 905         if (!fsl_req_to_dtd(req, gfp_flags)) {
 906                 spin_lock_irqsave(&udc->lock, flags);
 907                 fsl_queue_td(ep, req);
 908         } else {
 909                 return -ENOMEM;
 910         }
 911
 912         /* irq handler advances the queue */
 913         if (req != NULL)
 914                 list_add_tail(&req->queue, &ep->queue);
 915         spin_unlock_irqrestore(&udc->lock, flags);
 916
 917         return 0;
 918 }
 919
 920 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 921 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 922 {
 923         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 924         struct fsl_req *req = NULL;
 925         struct fsl_req *iter;
 926         unsigned long flags;
 927         int ep_num, stopped, ret = 0;
 928         u32 epctrl;
 929
 930         if (!_ep || !_req)
 931                 return -EINVAL;
 932
 933         spin_lock_irqsave(&ep->udc->lock, flags);
 934         stopped = ep->stopped;
 935
 936         /* Stop the ep before we deal with the queue */
 937         ep->stopped = 1;
 938         ep_num = ep_index(ep);
 939         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 940         if (ep_is_in(ep))
 941                 epctrl &= ~EPCTRL_TX_ENABLE;
 942         else
 943                 epctrl &= ~EPCTRL_RX_ENABLE;
 944         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 945
 946         /* make sure it's actually queued on this endpoint */
 947         list_for_each_entry(iter, &ep->queue, queue) {
 948                 if (&iter->req != _req)
 949                         continue;
 950                 req = iter;
 951                 break;
 952         }
 953         if (!req) {
 954                 ret = -EINVAL;
 955                 goto out;
 956         }
 957
 958         /* The request is in progress, or completed but not dequeued */
 959         if (ep->queue.next == &req->queue) {
 960                 _req->status = -ECONNRESET;
 961                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 962
 963                 /* The request isn't the last request in this ep queue */
 964                 if (req->queue.next != &ep->queue) {
 965                         struct fsl_req *next_req;
 966
 967                         next_req = list_entry(req->queue.next, struct fsl_req,
 968                                         queue);
 969
 970                         /* prime with dTD of next request */
 971                         fsl_prime_ep(ep, next_req->head);
 972                 }
 973         /* The request hasn't been processed, patch up the TD chain */
 974         } else {
 975                 struct fsl_req *prev_req;
 976
 977                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 978                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 979         }
 980
 981         done(ep, req, -ECONNRESET);
 982
 983         /* Enable EP */
 984 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 985         if (ep_is_in(ep))
 986                 epctrl |= EPCTRL_TX_ENABLE;
 987         else
 988                 epctrl |= EPCTRL_RX_ENABLE;
 989         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 990         ep->stopped = stopped;
 991
 992         spin_unlock_irqrestore(&ep->udc->lock, flags);
 993         return ret;
 994 }
 995
 996 /*-------------------------------------------------------------------------*/
 997
 998 /*-----------------------------------------------------------------
 999  * modify the endpoint halt feature
1000  * @ep: the non-isochronous endpoint being stalled
1001  * @value: 1--set halt  0--clear halt
1002  * Returns zero, or a negative error code.
1003 *----------------------------------------------------------------*/
1004 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1005 {
1006         struct fsl_ep *ep = NULL;
1007         unsigned long flags;
1008         int status = -EOPNOTSUPP;       /* operation not supported */
1009         unsigned char ep_dir = 0, ep_num = 0;
1010         struct fsl_udc *udc = NULL;
1011
1012         ep = container_of(_ep, struct fsl_ep, ep);
1013         udc = ep->udc;
1014         if (!_ep || !ep->ep.desc) {
1015                 status = -EINVAL;
1016                 goto out;
1017         }
1018
1019         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1020                 status = -EOPNOTSUPP;
1021                 goto out;
1022         }
1023
1024         /* Attempt to halt IN ep will fail if any transfer requests
1025          * are still queue */
1026         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1027                 status = -EAGAIN;
1028                 goto out;
1029         }
1030
1031         status = 0;
1032         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1033         ep_num = (unsigned char)(ep_index(ep));
1034         spin_lock_irqsave(&ep->udc->lock, flags);
1035         dr_ep_change_stall(ep_num, ep_dir, value);
1036         spin_unlock_irqrestore(&ep->udc->lock, flags);
1037
1038         if (ep_index(ep) == 0) {
1039                 udc->ep0_state = WAIT_FOR_SETUP;
1040                 udc->ep0_dir = 0;
1041         }
1042 out:
1043         dev_vdbg(&udc->gadget.dev, "%s %s halt stat %d\n", ep->ep.name,
1044                  value ?  "set" : "clear", status);
1045
1046         return status;
1047 }
1048
1049 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1050 {
1051         struct fsl_ep *ep;
1052         struct fsl_udc *udc;
1053         int size = 0;
1054         u32 bitmask;
1055         struct ep_queue_head *qh;
1056
1057         if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1058                 return -ENODEV;
1059
1060         ep = container_of(_ep, struct fsl_ep, ep);
1061
1062         udc = (struct fsl_udc *)ep->udc;
1063
1064         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1065                 return -ESHUTDOWN;
1066
1067         qh = get_qh_by_ep(ep);
1068
1069         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1070             (1 << (ep_index(ep)));
1071
1072         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1073                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1074                     >> DTD_LENGTH_BIT_POS;
1075
1076         pr_debug("%s %u\n", __func__, size);
1077         return size;
1078 }
1079
1080 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1081 {
1082         struct fsl_ep *ep;
1083         int ep_num, ep_dir;
1084         u32 bits;
1085         unsigned long timeout;
1086 #define FSL_UDC_FLUSH_TIMEOUT 1000
1087
1088         if (!_ep) {
1089                 return;
1090         } else {
1091                 ep = container_of(_ep, struct fsl_ep, ep);
1092                 if (!ep->ep.desc)
1093                         return;
1094         }
1095         ep_num = ep_index(ep);
1096         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1097
1098         if (ep_num == 0)
1099                 bits = (1 << 16) | 1;
1100         else if (ep_dir == USB_SEND)
1101                 bits = 1 << (16 + ep_num);
1102         else
1103                 bits = 1 << ep_num;
1104
1105         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1106         do {
1107                 fsl_writel(bits, &dr_regs->endptflush);
1108
1109                 /* Wait until flush complete */
1110                 while (fsl_readl(&dr_regs->endptflush)) {
1111                         if (time_after(jiffies, timeout)) {
1112                                 dev_err(&udc_controller->gadget.dev,
1113                                         "ep flush timeout\n");
1114                                 return;
1115                         }
1116                         cpu_relax();
1117                 }
1118                 /* See if we need to flush again */
1119         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1120 }
1121
1122 static const struct usb_ep_ops fsl_ep_ops = {
1123         .enable = fsl_ep_enable,
1124         .disable = fsl_ep_disable,
1125
1126         .alloc_request = fsl_alloc_request,
1127         .free_request = fsl_free_request,
1128
1129         .queue = fsl_ep_queue,
1130         .dequeue = fsl_ep_dequeue,
1131
1132         .set_halt = fsl_ep_set_halt,
1133         .fifo_status = fsl_ep_fifo_status,
1134         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1135 };
1136
1137 /*-------------------------------------------------------------------------
1138                 Gadget Driver Layer Operations
1139 -------------------------------------------------------------------------*/
1140
1141 /*----------------------------------------------------------------------
1142  * Get the current frame number (from DR frame_index Reg )
1143  *----------------------------------------------------------------------*/
1144 static int fsl_get_frame(struct usb_gadget *gadget)
1145 {
1146         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1147 }
1148
1149 /*-----------------------------------------------------------------------
1150  * Tries to wake up the host connected to this gadget
1151  -----------------------------------------------------------------------*/
1152 static int fsl_wakeup(struct usb_gadget *gadget)
1153 {
1154         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1155         u32 portsc;
1156
1157         /* Remote wakeup feature not enabled by host */
1158         if (!udc->remote_wakeup)
1159                 return -ENOTSUPP;
1160
1161         portsc = fsl_readl(&dr_regs->portsc1);
1162         /* not suspended? */
1163         if (!(portsc & PORTSCX_PORT_SUSPEND))
1164                 return 0;
1165         /* trigger force resume */
1166         portsc |= PORTSCX_PORT_FORCE_RESUME;
1167         fsl_writel(portsc, &dr_regs->portsc1);
1168         return 0;
1169 }
1170
1171 static int can_pullup(struct fsl_udc *udc)
1172 {
1173         return udc->driver && udc->softconnect && udc->vbus_active;
1174 }
1175
1176 /* Notify controller that VBUS is powered, Called by whatever
1177    detects VBUS sessions */
1178 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1179 {
1180         struct fsl_udc  *udc;
1181         unsigned long   flags;
1182
1183         udc = container_of(gadget, struct fsl_udc, gadget);
1184         spin_lock_irqsave(&udc->lock, flags);
1185         dev_vdbg(&gadget->dev, "VBUS %s\n", is_active ? "on" : "off");
1186         udc->vbus_active = (is_active != 0);
1187         if (can_pullup(udc))
1188                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1189                                 &dr_regs->usbcmd);
1190         else
1191                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1192                                 &dr_regs->usbcmd);
1193         spin_unlock_irqrestore(&udc->lock, flags);
1194         return 0;
1195 }
1196
1197 /* constrain controller's VBUS power usage
1198  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1199  * reporting how much power the device may consume.  For example, this
1200  * could affect how quickly batteries are recharged.
1201  *
1202  * Returns zero on success, else negative errno.
1203  */
1204 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1205 {
1206         struct fsl_udc *udc;
1207
1208         udc = container_of(gadget, struct fsl_udc, gadget);
1209         if (!IS_ERR_OR_NULL(udc->transceiver))
1210                 return usb_phy_set_power(udc->transceiver, mA);
1211         return -ENOTSUPP;
1212 }
1213
1214 /* Change Data+ pullup status
1215  * this func is used by usb_gadget_connect/disconnect
1216  */
1217 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1218 {
1219         struct fsl_udc *udc;
1220
1221         udc = container_of(gadget, struct fsl_udc, gadget);
1222
1223         if (!udc->vbus_active)
1224                 return -EOPNOTSUPP;
1225
1226         udc->softconnect = (is_on != 0);
1227         if (can_pullup(udc))
1228                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1229                                 &dr_regs->usbcmd);
1230         else
1231                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1232                                 &dr_regs->usbcmd);
1233
1234         return 0;
1235 }
1236
1237 static int fsl_udc_start(struct usb_gadget *g,
1238                 struct usb_gadget_driver *driver);
1239 static int fsl_udc_stop(struct usb_gadget *g);
1240
1241 static const struct usb_gadget_ops fsl_gadget_ops = {
1242         .get_frame = fsl_get_frame,
1243         .wakeup = fsl_wakeup,
1244 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1245         .vbus_session = fsl_vbus_session,
1246         .vbus_draw = fsl_vbus_draw,
1247         .pullup = fsl_pullup,
1248         .udc_start = fsl_udc_start,
1249         .udc_stop = fsl_udc_stop,
1250 };
1251
1252 /*
1253  * Empty complete function used by this driver to fill in the req->complete
1254  * field when creating a request since the complete field is mandatory.
1255  */
1256 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1257
1258 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1259    on new transaction */
1260 static void ep0stall(struct fsl_udc *udc)
1261 {
1262         u32 tmp;
1263
1264         /* must set tx and rx to stall at the same time */
1265         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1266         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1267         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1268         udc->ep0_state = WAIT_FOR_SETUP;
1269         udc->ep0_dir = 0;
1270 }
1271
1272 /* Prime a status phase for ep0 */
1273 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1274 {
1275         struct fsl_req *req = udc->status_req;
1276         struct fsl_ep *ep;
1277         int ret;
1278
1279         if (direction == EP_DIR_IN)
1280                 udc->ep0_dir = USB_DIR_IN;
1281         else
1282                 udc->ep0_dir = USB_DIR_OUT;
1283
1284         ep = &udc->eps[0];
1285         if (udc->ep0_state != DATA_STATE_XMIT)
1286                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1287
1288         req->ep = ep;
1289         req->req.length = 0;
1290         req->req.status = -EINPROGRESS;
1291         req->req.actual = 0;
1292         req->req.complete = fsl_noop_complete;
1293         req->dtd_count = 0;
1294
1295         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1296         if (ret)
1297                 return ret;
1298
1299         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1300                 fsl_queue_td(ep, req);
1301         else
1302                 return -ENOMEM;
1303
1304         list_add_tail(&req->queue, &ep->queue);
1305
1306         return 0;
1307 }
1308
1309 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1310 {
1311         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1312
1313         if (ep->ep.name)
1314                 nuke(ep, -ESHUTDOWN);
1315 }
1316
1317 /*
1318  * ch9 Set address
1319  */
1320 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1321 {
1322         /* Save the new address to device struct */
1323         udc->device_address = (u8) value;
1324         /* Update usb state */
1325         udc->usb_state = USB_STATE_ADDRESS;
1326         /* Status phase */
1327         if (ep0_prime_status(udc, EP_DIR_IN))
1328                 ep0stall(udc);
1329 }
1330
1331 /*
1332  * ch9 Get status
1333  */
1334 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1335                 u16 index, u16 length)
1336 {
1337         u16 tmp = 0;            /* Status, cpu endian */
1338         struct fsl_req *req;
1339         struct fsl_ep *ep;
1340         int ret;
1341
1342         ep = &udc->eps[0];
1343
1344         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1345                 /* Get device status */
1346                 tmp = udc->gadget.is_selfpowered;
1347                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1348         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1349                 /* Get interface status */
1350                 /* We don't have interface information in udc driver */
1351                 tmp = 0;
1352         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1353                 /* Get endpoint status */
1354                 struct fsl_ep *target_ep;
1355
1356                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1357
1358                 /* stall if endpoint doesn't exist */
1359                 if (!target_ep->ep.desc)
1360                         goto stall;
1361                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1362                                 << USB_ENDPOINT_HALT;
1363         }
1364
1365         udc->ep0_dir = USB_DIR_IN;
1366         /* Borrow the per device status_req */
1367         req = udc->status_req;
1368         /* Fill in the request structure */
1369         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1370
1371         req->ep = ep;
1372         req->req.length = 2;
1373         req->req.status = -EINPROGRESS;
1374         req->req.actual = 0;
1375         req->req.complete = fsl_noop_complete;
1376         req->dtd_count = 0;
1377
1378         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1379         if (ret)
1380                 goto stall;
1381
1382         /* prime the data phase */
1383         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1384                 fsl_queue_td(ep, req);
1385         else                    /* no mem */
1386                 goto stall;
1387
1388         list_add_tail(&req->queue, &ep->queue);
1389         udc->ep0_state = DATA_STATE_XMIT;
1390         if (ep0_prime_status(udc, EP_DIR_OUT))
1391                 ep0stall(udc);
1392
1393         return;
1394 stall:
1395         ep0stall(udc);
1396 }
1397
1398 static void setup_received_irq(struct fsl_udc *udc,
1399                 struct usb_ctrlrequest *setup)
1400 __releases(udc->lock)
1401 __acquires(udc->lock)
1402 {
1403         u16 wValue = le16_to_cpu(setup->wValue);
1404         u16 wIndex = le16_to_cpu(setup->wIndex);
1405         u16 wLength = le16_to_cpu(setup->wLength);
1406
1407         udc_reset_ep_queue(udc, 0);
1408
1409         /* We process some stardard setup requests here */
1410         switch (setup->bRequest) {
1411         case USB_REQ_GET_STATUS:
1412                 /* Data+Status phase from udc */
1413                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1414                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1415                         break;
1416                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1417                 return;
1418
1419         case USB_REQ_SET_ADDRESS:
1420                 /* Status phase from udc */
1421                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1422                                                 | USB_RECIP_DEVICE))
1423                         break;
1424                 ch9setaddress(udc, wValue, wIndex, wLength);
1425                 return;
1426
1427         case USB_REQ_CLEAR_FEATURE:
1428         case USB_REQ_SET_FEATURE:
1429                 /* Status phase from udc */
1430         {
1431                 int rc = -EOPNOTSUPP;
1432                 u16 ptc = 0;
1433
1434                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1435                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1436                         int pipe = get_pipe_by_windex(wIndex);
1437                         struct fsl_ep *ep;
1438
1439                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1440                                 break;
1441                         ep = get_ep_by_pipe(udc, pipe);
1442
1443                         spin_unlock(&udc->lock);
1444                         rc = fsl_ep_set_halt(&ep->ep,
1445                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1446                                                 ? 1 : 0);
1447                         spin_lock(&udc->lock);
1448
1449                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1450                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1451                                 | USB_TYPE_STANDARD)) {
1452                         /* Note: The driver has not include OTG support yet.
1453                          * This will be set when OTG support is added */
1454                         if (wValue == USB_DEVICE_TEST_MODE)
1455                                 ptc = wIndex >> 8;
1456                         else if (gadget_is_otg(&udc->gadget)) {
1457                                 if (setup->bRequest ==
1458                                     USB_DEVICE_B_HNP_ENABLE)
1459                                         udc->gadget.b_hnp_enable = 1;
1460                                 else if (setup->bRequest ==
1461                                          USB_DEVICE_A_HNP_SUPPORT)
1462                                         udc->gadget.a_hnp_support = 1;
1463                                 else if (setup->bRequest ==
1464                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1465                                         udc->gadget.a_alt_hnp_support = 1;
1466                         }
1467                         rc = 0;
1468                 } else
1469                         break;
1470
1471                 if (rc == 0) {
1472                         if (ep0_prime_status(udc, EP_DIR_IN))
1473                                 ep0stall(udc);
1474                 }
1475                 if (ptc) {
1476                         u32 tmp;
1477
1478                         mdelay(10);
1479                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1480                         fsl_writel(tmp, &dr_regs->portsc1);
1481                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1482                 }
1483
1484                 return;
1485         }
1486
1487         default:
1488                 break;
1489         }
1490
1491         /* Requests handled by gadget */
1492         if (wLength) {
1493                 /* Data phase from gadget, status phase from udc */
1494                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1495                                 ?  USB_DIR_IN : USB_DIR_OUT;
1496                 spin_unlock(&udc->lock);
1497                 if (udc->driver->setup(&udc->gadget,
1498                                 &udc->local_setup_buff) < 0)
1499                         ep0stall(udc);
1500                 spin_lock(&udc->lock);
1501                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1502                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1503                 /*
1504                  * If the data stage is IN, send status prime immediately.
1505                  * See 2.0 Spec chapter 8.5.3.3 for detail.
1506                  */
1507                 if (udc->ep0_state == DATA_STATE_XMIT)
1508                         if (ep0_prime_status(udc, EP_DIR_OUT))
1509                                 ep0stall(udc);
1510
1511         } else {
1512                 /* No data phase, IN status from gadget */
1513                 udc->ep0_dir = USB_DIR_IN;
1514                 spin_unlock(&udc->lock);
1515                 if (udc->driver->setup(&udc->gadget,
1516                                 &udc->local_setup_buff) < 0)
1517                         ep0stall(udc);
1518                 spin_lock(&udc->lock);
1519                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1520         }
1521 }
1522
1523 /* Process request for Data or Status phase of ep0
1524  * prime status phase if needed */
1525 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1526                 struct fsl_req *req)
1527 {
1528         if (udc->usb_state == USB_STATE_ADDRESS) {
1529                 /* Set the new address */
1530                 u32 new_address = (u32) udc->device_address;
1531                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1532                                 &dr_regs->deviceaddr);
1533         }
1534
1535         done(ep0, req, 0);
1536
1537         switch (udc->ep0_state) {
1538         case DATA_STATE_XMIT:
1539                 /* already primed at setup_received_irq */
1540                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1541                 break;
1542         case DATA_STATE_RECV:
1543                 /* send status phase */
1544                 if (ep0_prime_status(udc, EP_DIR_IN))
1545                         ep0stall(udc);
1546                 break;
1547         case WAIT_FOR_OUT_STATUS:
1548                 udc->ep0_state = WAIT_FOR_SETUP;
1549                 break;
1550         case WAIT_FOR_SETUP:
1551                 dev_err(&udc->gadget.dev, "Unexpected ep0 packets\n");
1552                 break;
1553         default:
1554                 ep0stall(udc);
1555                 break;
1556         }
1557 }
1558
1559 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1560  * being corrupted by another incoming setup packet */
1561 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1562 {
1563         u32 temp;
1564         struct ep_queue_head *qh;
1565         struct fsl_usb2_platform_data *pdata = udc->pdata;
1566
1567         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1568
1569         /* Clear bit in ENDPTSETUPSTAT */
1570         temp = fsl_readl(&dr_regs->endptsetupstat);
1571         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1572
1573         /* while a hazard exists when setup package arrives */
1574         do {
1575                 /* Set Setup Tripwire */
1576                 temp = fsl_readl(&dr_regs->usbcmd);
1577                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1578
1579                 /* Copy the setup packet to local buffer */
1580                 if (pdata->le_setup_buf) {
1581                         u32 *p = (u32 *)buffer_ptr;
1582                         u32 *s = (u32 *)qh->setup_buffer;
1583
1584                         /* Convert little endian setup buffer to CPU endian */
1585                         *p++ = le32_to_cpu(*s++);
1586                         *p = le32_to_cpu(*s);
1587                 } else {
1588                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1589                 }
1590         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1591
1592         /* Clear Setup Tripwire */
1593         temp = fsl_readl(&dr_regs->usbcmd);
1594         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1595 }
1596
1597 /* process-ep_req(): free the completed Tds for this req */
1598 static int process_ep_req(struct fsl_udc *udc, int pipe,
1599                 struct fsl_req *curr_req)
1600 {
1601         struct ep_td_struct *curr_td;
1602         int     actual, remaining_length, j, tmp;
1603         int     status = 0;
1604         int     errors = 0;
1605         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1606         int direction = pipe % 2;
1607
1608         curr_td = curr_req->head;
1609         actual = curr_req->req.length;
1610
1611         for (j = 0; j < curr_req->dtd_count; j++) {
1612                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1613                                         & DTD_PACKET_SIZE)
1614                                 >> DTD_LENGTH_BIT_POS;
1615                 actual -= remaining_length;
1616
1617                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1618                 if (errors & DTD_ERROR_MASK) {
1619                         if (errors & DTD_STATUS_HALTED) {
1620                                 dev_err(&udc->gadget.dev, "dTD error %08x QH=%d\n", errors, pipe);
1621                                 /* Clear the errors and Halt condition */
1622                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1623                                 tmp &= ~errors;
1624                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1625                                 status = -EPIPE;
1626                                 /* FIXME: continue with next queued TD? */
1627
1628                                 break;
1629                         }
1630                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1631                                 dev_vdbg(&udc->gadget.dev, "Transfer overflow\n");
1632                                 status = -EPROTO;
1633                                 break;
1634                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1635                                 dev_vdbg(&udc->gadget.dev, "ISO error\n");
1636                                 status = -EILSEQ;
1637                                 break;
1638                         } else
1639                                 dev_err(&udc->gadget.dev,
1640                                         "Unknown error has occurred (0x%x)!\n",
1641                                         errors);
1642
1643                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1644                                 & DTD_STATUS_ACTIVE) {
1645                         dev_vdbg(&udc->gadget.dev, "Request not complete\n");
1646                         status = REQ_UNCOMPLETE;
1647                         return status;
1648                 } else if (remaining_length) {
1649                         if (direction) {
1650                                 dev_vdbg(&udc->gadget.dev,
1651                                          "Transmit dTD remaining length not zero\n");
1652                                 status = -EPROTO;
1653                                 break;
1654                         } else {
1655                                 break;
1656                         }
1657                 } else {
1658                         dev_vdbg(&udc->gadget.dev,
1659                                  "dTD transmitted successful\n");
1660                 }
1661
1662                 if (j != curr_req->dtd_count - 1)
1663                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1664         }
1665
1666         if (status)
1667                 return status;
1668
1669         curr_req->req.actual = actual;
1670
1671         return 0;
1672 }
1673
1674 /* Process a DTD completion interrupt */
1675 static void dtd_complete_irq(struct fsl_udc *udc)
1676 {
1677         u32 bit_pos;
1678         int i, ep_num, direction, bit_mask, status;
1679         struct fsl_ep *curr_ep;
1680         struct fsl_req *curr_req, *temp_req;
1681
1682         /* Clear the bits in the register */
1683         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1684         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1685
1686         if (!bit_pos)
1687                 return;
1688
1689         for (i = 0; i < udc->max_ep; i++) {
1690                 ep_num = i >> 1;
1691                 direction = i % 2;
1692
1693                 bit_mask = 1 << (ep_num + 16 * direction);
1694
1695                 if (!(bit_pos & bit_mask))
1696                         continue;
1697
1698                 curr_ep = get_ep_by_pipe(udc, i);
1699
1700                 /* If the ep is configured */
1701                 if (!curr_ep->ep.name) {
1702                         dev_warn(&udc->gadget.dev, "Invalid EP?\n");
1703                         continue;
1704                 }
1705
1706                 /* process the req queue until an uncomplete request */
1707                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1708                                 queue) {
1709                         status = process_ep_req(udc, i, curr_req);
1710
1711                         dev_vdbg(&udc->gadget.dev,
1712                                  "status of process_ep_req= %d, ep = %d\n",
1713                                  status, ep_num);
1714                         if (status == REQ_UNCOMPLETE)
1715                                 break;
1716                         /* write back status to req */
1717                         curr_req->req.status = status;
1718
1719                         if (ep_num == 0) {
1720                                 ep0_req_complete(udc, curr_ep, curr_req);
1721                                 break;
1722                         } else
1723                                 done(curr_ep, curr_req, status);
1724                 }
1725         }
1726 }
1727
1728 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1729 {
1730         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1731         case PORTSCX_PORT_SPEED_HIGH:
1732                 return USB_SPEED_HIGH;
1733         case PORTSCX_PORT_SPEED_FULL:
1734                 return USB_SPEED_FULL;
1735         case PORTSCX_PORT_SPEED_LOW:
1736                 return USB_SPEED_LOW;
1737         default:
1738                 return USB_SPEED_UNKNOWN;
1739         }
1740 }
1741
1742 /* Process a port change interrupt */
1743 static void port_change_irq(struct fsl_udc *udc)
1744 {
1745         if (udc->bus_reset)
1746                 udc->bus_reset = 0;
1747
1748         /* Bus resetting is finished */
1749         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1750                 /* Get the speed */
1751                 udc->gadget.speed =
1752                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1753
1754         /* Update USB state */
1755         if (!udc->resume_state)
1756                 udc->usb_state = USB_STATE_DEFAULT;
1757 }
1758
1759 /* Process suspend interrupt */
1760 static void suspend_irq(struct fsl_udc *udc)
1761 {
1762         udc->resume_state = udc->usb_state;
1763         udc->usb_state = USB_STATE_SUSPENDED;
1764
1765         /* report suspend to the driver, serial.c does not support this */
1766         if (udc->driver->suspend)
1767                 udc->driver->suspend(&udc->gadget);
1768 }
1769
1770 static void bus_resume(struct fsl_udc *udc)
1771 {
1772         udc->usb_state = udc->resume_state;
1773         udc->resume_state = 0;
1774
1775         /* report resume to the driver, serial.c does not support this */
1776         if (udc->driver->resume)
1777                 udc->driver->resume(&udc->gadget);
1778 }
1779
1780 /* Clear up all ep queues */
1781 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1782 {
1783         u8 pipe;
1784
1785         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1786                 udc_reset_ep_queue(udc, pipe);
1787
1788         /* report disconnect; the driver is already quiesced */
1789         spin_unlock(&udc->lock);
1790         if (bus_reset)
1791                 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1792         else
1793                 udc->driver->disconnect(&udc->gadget);
1794         spin_lock(&udc->lock);
1795
1796         return 0;
1797 }
1798
1799 /* Process reset interrupt */
1800 static void reset_irq(struct fsl_udc *udc)
1801 {
1802         u32 temp;
1803         unsigned long timeout;
1804
1805         /* Clear the device address */
1806         temp = fsl_readl(&dr_regs->deviceaddr);
1807         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1808
1809         udc->device_address = 0;
1810
1811         /* Clear usb state */
1812         udc->resume_state = 0;
1813         udc->ep0_dir = 0;
1814         udc->ep0_state = WAIT_FOR_SETUP;
1815         udc->remote_wakeup = 0; /* default to 0 on reset */
1816         udc->gadget.b_hnp_enable = 0;
1817         udc->gadget.a_hnp_support = 0;
1818         udc->gadget.a_alt_hnp_support = 0;
1819
1820         /* Clear all the setup token semaphores */
1821         temp = fsl_readl(&dr_regs->endptsetupstat);
1822         fsl_writel(temp, &dr_regs->endptsetupstat);
1823
1824         /* Clear all the endpoint complete status bits */
1825         temp = fsl_readl(&dr_regs->endptcomplete);
1826         fsl_writel(temp, &dr_regs->endptcomplete);
1827
1828         timeout = jiffies + 100;
1829         while (fsl_readl(&dr_regs->endpointprime)) {
1830                 /* Wait until all endptprime bits cleared */
1831                 if (time_after(jiffies, timeout)) {
1832                         dev_err(&udc->gadget.dev, "Timeout for reset\n");
1833                         break;
1834                 }
1835                 cpu_relax();
1836         }
1837
1838         /* Write 1s to the flush register */
1839         fsl_writel(0xffffffff, &dr_regs->endptflush);
1840
1841         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1842                 dev_vdbg(&udc->gadget.dev, "Bus reset\n");
1843                 /* Bus is reseting */
1844                 udc->bus_reset = 1;
1845                 /* Reset all the queues, include XD, dTD, EP queue
1846                  * head and TR Queue */
1847                 reset_queues(udc, true);
1848                 udc->usb_state = USB_STATE_DEFAULT;
1849         } else {
1850                 dev_vdbg(&udc->gadget.dev, "Controller reset\n");
1851                 /* initialize usb hw reg except for regs for EP, not
1852                  * touch usbintr reg */
1853                 dr_controller_setup(udc);
1854
1855                 /* Reset all internal used Queues */
1856                 reset_queues(udc, false);
1857
1858                 ep0_setup(udc);
1859
1860                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1861                 dr_controller_run(udc);
1862                 udc->usb_state = USB_STATE_ATTACHED;
1863         }
1864 }
1865
1866 /*
1867  * USB device controller interrupt handler
1868  */
1869 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1870 {
1871         struct fsl_udc *udc = _udc;
1872         u32 irq_src;
1873         irqreturn_t status = IRQ_NONE;
1874         unsigned long flags;
1875
1876         /* Disable ISR for OTG host mode */
1877         if (udc->stopped)
1878                 return IRQ_NONE;
1879         spin_lock_irqsave(&udc->lock, flags);
1880         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1881         /* Clear notification bits */
1882         fsl_writel(irq_src, &dr_regs->usbsts);
1883
1884         /* dev_vdbg(&udc->gadget.dev, "irq_src [0x%8x]", irq_src); */
1885
1886         /* Need to resume? */
1887         if (udc->usb_state == USB_STATE_SUSPENDED)
1888                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1889                         bus_resume(udc);
1890
1891         /* USB Interrupt */
1892         if (irq_src & USB_STS_INT) {
1893                 dev_vdbg(&udc->gadget.dev, "Packet int\n");
1894                 /* Setup package, we only support ep0 as control ep */
1895                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1896                         tripwire_handler(udc, 0,
1897                                         (u8 *) (&udc->local_setup_buff));
1898                         setup_received_irq(udc, &udc->local_setup_buff);
1899                         status = IRQ_HANDLED;
1900                 }
1901
1902                 /* completion of dtd */
1903                 if (fsl_readl(&dr_regs->endptcomplete)) {
1904                         dtd_complete_irq(udc);
1905                         status = IRQ_HANDLED;
1906                 }
1907         }
1908
1909         /* SOF (for ISO transfer) */
1910         if (irq_src & USB_STS_SOF) {
1911                 status = IRQ_HANDLED;
1912         }
1913
1914         /* Port Change */
1915         if (irq_src & USB_STS_PORT_CHANGE) {
1916                 port_change_irq(udc);
1917                 status = IRQ_HANDLED;
1918         }
1919
1920         /* Reset Received */
1921         if (irq_src & USB_STS_RESET) {
1922                 dev_vdbg(&udc->gadget.dev, "reset int\n");
1923                 reset_irq(udc);
1924                 status = IRQ_HANDLED;
1925         }
1926
1927         /* Sleep Enable (Suspend) */
1928         if (irq_src & USB_STS_SUSPEND) {
1929                 suspend_irq(udc);
1930                 status = IRQ_HANDLED;
1931         }
1932
1933         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1934                 dev_vdbg(&udc->gadget.dev, "Error IRQ %x\n", irq_src);
1935         }
1936
1937         spin_unlock_irqrestore(&udc->lock, flags);
1938         return status;
1939 }
1940
1941 /*----------------------------------------------------------------*
1942  * Hook to gadget drivers
1943  * Called by initialization code of gadget drivers
1944 *----------------------------------------------------------------*/
1945 static int fsl_udc_start(struct usb_gadget *g,
1946                 struct usb_gadget_driver *driver)
1947 {
1948         int retval = 0;
1949         unsigned long flags;
1950
1951         /* lock is needed but whether should use this lock or another */
1952         spin_lock_irqsave(&udc_controller->lock, flags);
1953
1954         /* hook up the driver */
1955         udc_controller->driver = driver;
1956         spin_unlock_irqrestore(&udc_controller->lock, flags);
1957         g->is_selfpowered = 1;
1958
1959         if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1960                 /* Suspend the controller until OTG enable it */
1961                 udc_controller->stopped = 1;
1962                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1963
1964                 /* connect to bus through transceiver */
1965                 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1966                         retval = otg_set_peripheral(
1967                                         udc_controller->transceiver->otg,
1968                                                     &udc_controller->gadget);
1969                         if (retval < 0) {
1970                                 dev_err(&udc_controller->gadget.dev, "can't bind to transceiver\n");
1971                                 udc_controller->driver = NULL;
1972                                 return retval;
1973                         }
1974                 }
1975         } else {
1976                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1977                 dr_controller_run(udc_controller);
1978                 udc_controller->usb_state = USB_STATE_ATTACHED;
1979                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1980                 udc_controller->ep0_dir = 0;
1981         }
1982
1983         return retval;
1984 }
1985
1986 /* Disconnect from gadget driver */
1987 static int fsl_udc_stop(struct usb_gadget *g)
1988 {
1989         struct fsl_ep *loop_ep;
1990         unsigned long flags;
1991
1992         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1993                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1994
1995         /* stop DR, disable intr */
1996         dr_controller_stop(udc_controller);
1997
1998         /* in fact, no needed */
1999         udc_controller->usb_state = USB_STATE_ATTACHED;
2000         udc_controller->ep0_state = WAIT_FOR_SETUP;
2001         udc_controller->ep0_dir = 0;
2002
2003         /* stand operation */
2004         spin_lock_irqsave(&udc_controller->lock, flags);
2005         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2006         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2007         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2008                         ep.ep_list)
2009                 nuke(loop_ep, -ESHUTDOWN);
2010         spin_unlock_irqrestore(&udc_controller->lock, flags);
2011
2012         udc_controller->driver = NULL;
2013
2014         return 0;
2015 }
2016
2017 /*-------------------------------------------------------------------------
2018                 PROC File System Support
2019 -------------------------------------------------------------------------*/
2020 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2021
2022 #include <linux/seq_file.h>
2023
2024 static const char proc_filename[] = "driver/fsl_usb2_udc";
2025
2026 static int fsl_proc_read(struct seq_file *m, void *v)
2027 {
2028         unsigned long flags;
2029         int i;
2030         u32 tmp_reg;
2031         struct fsl_ep *ep = NULL;
2032         struct fsl_req *req;
2033
2034         struct fsl_udc *udc = udc_controller;
2035
2036         spin_lock_irqsave(&udc->lock, flags);
2037
2038         /* ------basic driver information ---- */
2039         seq_printf(m,
2040                         DRIVER_DESC "\n"
2041                         "%s version: %s\n"
2042                         "Gadget driver: %s\n\n",
2043                         driver_name, DRIVER_VERSION,
2044                         udc->driver ? udc->driver->driver.name : "(none)");
2045
2046         /* ------ DR Registers ----- */
2047         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2048         seq_printf(m,
2049                         "USBCMD reg:\n"
2050                         "SetupTW: %d\n"
2051                         "Run/Stop: %s\n\n",
2052                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2053                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2054
2055         tmp_reg = fsl_readl(&dr_regs->usbsts);
2056         seq_printf(m,
2057                         "USB Status Reg:\n"
2058                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2059                         "USB Error Interrupt: %s\n\n",
2060                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2061                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2062                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2063                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2064
2065         tmp_reg = fsl_readl(&dr_regs->usbintr);
2066         seq_printf(m,
2067                         "USB Interrupt Enable Reg:\n"
2068                         "Sleep Enable: %d SOF Received Enable: %d "
2069                         "Reset Enable: %d\n"
2070                         "System Error Enable: %d "
2071                         "Port Change Detected Enable: %d\n"
2072                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2073                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2074                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2075                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2076                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2077                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2078                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2079                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2080
2081         tmp_reg = fsl_readl(&dr_regs->frindex);
2082         seq_printf(m,
2083                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2084                         (tmp_reg & USB_FRINDEX_MASKS));
2085
2086         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2087         seq_printf(m,
2088                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2089                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2090
2091         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2092         seq_printf(m,
2093                         "USB Endpoint List Address Reg: "
2094                         "Device Addr is 0x%x\n\n",
2095                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2096
2097         tmp_reg = fsl_readl(&dr_regs->portsc1);
2098         seq_printf(m,
2099                 "USB Port Status&Control Reg:\n"
2100                 "Port Transceiver Type : %s Port Speed: %s\n"
2101                 "PHY Low Power Suspend: %s Port Reset: %s "
2102                 "Port Suspend Mode: %s\n"
2103                 "Over-current Change: %s "
2104                 "Port Enable/Disable Change: %s\n"
2105                 "Port Enabled/Disabled: %s "
2106                 "Current Connect Status: %s\n\n", ( {
2107                         const char *s;
2108                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2109                         case PORTSCX_PTS_UTMI:
2110                                 s = "UTMI"; break;
2111                         case PORTSCX_PTS_ULPI:
2112                                 s = "ULPI "; break;
2113                         case PORTSCX_PTS_FSLS:
2114                                 s = "FS/LS Serial"; break;
2115                         default:
2116                                 s = "None"; break;
2117                         }
2118                         s;} ),
2119                 usb_speed_string(portscx_device_speed(tmp_reg)),
2120                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2121                 "Normal PHY mode" : "Low power mode",
2122                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2123                 "Not in Reset",
2124                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2125                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2126                 "No",
2127                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2128                 "Not change",
2129                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2130                 "Not correct",
2131                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2132                 "Attached" : "Not-Att");
2133
2134         tmp_reg = fsl_readl(&dr_regs->usbmode);
2135         seq_printf(m,
2136                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2137                                 const char *s;
2138                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2139                                 case USB_MODE_CTRL_MODE_IDLE:
2140                                         s = "Idle"; break;
2141                                 case USB_MODE_CTRL_MODE_DEVICE:
2142                                         s = "Device Controller"; break;
2143                                 case USB_MODE_CTRL_MODE_HOST:
2144                                         s = "Host Controller"; break;
2145                                 default:
2146                                         s = "None"; break;
2147                                 }
2148                                 s;
2149                         } ));
2150
2151         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2152         seq_printf(m,
2153                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2154                         (tmp_reg & EP_SETUP_STATUS_MASK));
2155
2156         for (i = 0; i < udc->max_ep / 2; i++) {
2157                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2158                 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2159         }
2160         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2161         seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2162
2163         if (udc->pdata->have_sysif_regs) {
2164                 tmp_reg = usb_sys_regs->snoop1;
2165                 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2166
2167                 tmp_reg = usb_sys_regs->control;
2168                 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2169         }
2170
2171         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2172         ep = &udc->eps[0];
2173         seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2174                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2175
2176         if (list_empty(&ep->queue)) {
2177                 seq_puts(m, "its req queue is empty\n\n");
2178         } else {
2179                 list_for_each_entry(req, &ep->queue, queue) {
2180                         seq_printf(m,
2181                                 "req %p actual 0x%x length 0x%x buf %p\n",
2182                                 &req->req, req->req.actual,
2183                                 req->req.length, req->req.buf);
2184                 }
2185         }
2186         /* other gadget->eplist ep */
2187         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2188                 if (ep->ep.desc) {
2189                         seq_printf(m,
2190                                         "\nFor %s Maxpkt is 0x%x "
2191                                         "index is 0x%x\n",
2192                                         ep->ep.name, ep_maxpacket(ep),
2193                                         ep_index(ep));
2194
2195                         if (list_empty(&ep->queue)) {
2196                                 seq_puts(m, "its req queue is empty\n\n");
2197                         } else {
2198                                 list_for_each_entry(req, &ep->queue, queue) {
2199                                         seq_printf(m,
2200                                                 "req %p actual 0x%x length "
2201                                                 "0x%x  buf %p\n",
2202                                                 &req->req, req->req.actual,
2203                                                 req->req.length, req->req.buf);
2204                                 }       /* end for each_entry of ep req */
2205                         }       /* end for else */
2206                 }       /* end for if(ep->queue) */
2207         }       /* end (ep->desc) */
2208
2209         spin_unlock_irqrestore(&udc->lock, flags);
2210         return 0;
2211 }
2212
2213 #define create_proc_file() \
2214         proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2215 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2216
2217 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2218
2219 #define create_proc_file()      do {} while (0)
2220 #define remove_proc_file()      do {} while (0)
2221
2222 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2223
2224 /*-------------------------------------------------------------------------*/
2225
2226 /* Release udc structures */
2227 static void fsl_udc_release(struct device *dev)
2228 {
2229         complete(udc_controller->done);
2230         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2231                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2232         kfree(udc_controller);
2233 }
2234
2235 /******************************************************************
2236         Internal structure setup functions
2237 *******************************************************************/
2238 /*------------------------------------------------------------------
2239  * init resource for global controller called by fsl_udc_probe()
2240  * On success the udc handle is initialized, on failure it is
2241  * unchanged (reset).
2242  * Return 0 on success and -1 on allocation failure
2243  ------------------------------------------------------------------*/
2244 static int struct_udc_setup(struct fsl_udc *udc,
2245                 struct platform_device *pdev)
2246 {
2247         struct fsl_usb2_platform_data *pdata;
2248         size_t size;
2249
2250         pdata = dev_get_platdata(&pdev->dev);
2251         udc->phy_mode = pdata->phy_mode;
2252
2253         udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2254         if (!udc->eps) {
2255                 dev_err(&udc->gadget.dev, "kmalloc udc endpoint status failed\n");
2256                 goto eps_alloc_failed;
2257         }
2258
2259         /* initialized QHs, take care of alignment */
2260         size = udc->max_ep * sizeof(struct ep_queue_head);
2261         if (size < QH_ALIGNMENT)
2262                 size = QH_ALIGNMENT;
2263         else if ((size % QH_ALIGNMENT) != 0) {
2264                 size += QH_ALIGNMENT + 1;
2265                 size &= ~(QH_ALIGNMENT - 1);
2266         }
2267         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2268                                         &udc->ep_qh_dma, GFP_KERNEL);
2269         if (!udc->ep_qh) {
2270                 dev_err(&udc->gadget.dev, "malloc QHs for udc failed\n");
2271                 goto ep_queue_alloc_failed;
2272         }
2273
2274         udc->ep_qh_size = size;
2275
2276         /* Initialize ep0 status request structure */
2277         /* FIXME: fsl_alloc_request() ignores ep argument */
2278         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2279                         struct fsl_req, req);
2280         if (!udc->status_req) {
2281                 dev_err(&udc->gadget.dev, "kzalloc for udc status request failed\n");
2282                 goto udc_status_alloc_failed;
2283         }
2284
2285         /* allocate a small amount of memory to get valid address */
2286         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2287         if (!udc->status_req->req.buf) {
2288                 dev_err(&udc->gadget.dev, "kzalloc for udc request buffer failed\n");
2289                 goto udc_req_buf_alloc_failed;
2290         }
2291
2292         udc->resume_state = USB_STATE_NOTATTACHED;
2293         udc->usb_state = USB_STATE_POWERED;
2294         udc->ep0_dir = 0;
2295         udc->remote_wakeup = 0; /* default to 0 on reset */
2296
2297         return 0;
2298
2299 udc_req_buf_alloc_failed:
2300         kfree(udc->status_req);
2301 udc_status_alloc_failed:
2302         kfree(udc->ep_qh);
2303         udc->ep_qh_size = 0;
2304 ep_queue_alloc_failed:
2305         kfree(udc->eps);
2306 eps_alloc_failed:
2307         udc->phy_mode = 0;
2308         return -1;
2309
2310 }
2311
2312 /*----------------------------------------------------------------
2313  * Setup the fsl_ep struct for eps
2314  * Link fsl_ep->ep to gadget->ep_list
2315  * ep0out is not used so do nothing here
2316  * ep0in should be taken care
2317  *--------------------------------------------------------------*/
2318 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2319                 char *name, int link)
2320 {
2321         struct fsl_ep *ep = &udc->eps[index];
2322
2323         ep->udc = udc;
2324         strcpy(ep->name, name);
2325         ep->ep.name = ep->name;
2326
2327         ep->ep.ops = &fsl_ep_ops;
2328         ep->stopped = 0;
2329
2330         if (index == 0) {
2331                 ep->ep.caps.type_control = true;
2332         } else {
2333                 ep->ep.caps.type_iso = true;
2334                 ep->ep.caps.type_bulk = true;
2335                 ep->ep.caps.type_int = true;
2336         }
2337
2338         if (index & 1)
2339                 ep->ep.caps.dir_in = true;
2340         else
2341                 ep->ep.caps.dir_out = true;
2342
2343         /* for ep0: maxP defined in desc
2344          * for other eps, maxP is set by epautoconfig() called by gadget layer
2345          */
2346         usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2347
2348         /* the queue lists any req for this ep */
2349         INIT_LIST_HEAD(&ep->queue);
2350
2351         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2352         if (link)
2353                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2354         ep->gadget = &udc->gadget;
2355         ep->qh = &udc->ep_qh[index];
2356
2357         return 0;
2358 }
2359
2360 /* Driver probe function
2361  * all initialization operations implemented here except enabling usb_intr reg
2362  * board setup should have been done in the platform code
2363  */
2364 static int fsl_udc_probe(struct platform_device *pdev)
2365 {
2366         struct fsl_usb2_platform_data *pdata;
2367         struct resource *res;
2368         int ret = -ENODEV;
2369         unsigned int i;
2370         u32 dccparams;
2371
2372         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2373         if (udc_controller == NULL)
2374                 return -ENOMEM;
2375
2376         pdata = dev_get_platdata(&pdev->dev);
2377         udc_controller->pdata = pdata;
2378         spin_lock_init(&udc_controller->lock);
2379         udc_controller->stopped = 1;
2380
2381 #ifdef CONFIG_USB_OTG
2382         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2383                 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2384                 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2385                         dev_err(&udc_controller->gadget.dev, "Can't find OTG driver!\n");
2386                         ret = -ENODEV;
2387                         goto err_kfree;
2388                 }
2389         }
2390 #endif
2391
2392         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2393         if (!res) {
2394                 ret = -ENXIO;
2395                 goto err_kfree;
2396         }
2397
2398         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2399                 if (!request_mem_region(res->start, resource_size(res),
2400                                         driver_name)) {
2401                         dev_err(&udc_controller->gadget.dev, "request mem region for %s failed\n", pdev->name);
2402                         ret = -EBUSY;
2403                         goto err_kfree;
2404                 }
2405         }
2406
2407         dr_regs = ioremap(res->start, resource_size(res));
2408         if (!dr_regs) {
2409                 ret = -ENOMEM;
2410                 goto err_release_mem_region;
2411         }
2412
2413         pdata->regs = (void __iomem *)dr_regs;
2414
2415         /*
2416          * do platform specific init: check the clock, grab/config pins, etc.
2417          */
2418         if (pdata->init && pdata->init(pdev)) {
2419                 ret = -ENODEV;
2420                 goto err_iounmap;
2421         }
2422
2423         /* Set accessors only after pdata->init() ! */
2424         fsl_set_accessors(pdata);
2425
2426         if (pdata->have_sysif_regs)
2427                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2428
2429         /* Read Device Controller Capability Parameters register */
2430         dccparams = fsl_readl(&dr_regs->dccparams);
2431         if (!(dccparams & DCCPARAMS_DC)) {
2432                 dev_err(&udc_controller->gadget.dev, "This SOC doesn't support device role\n");
2433                 ret = -ENODEV;
2434                 goto err_exit;
2435         }
2436         /* Get max device endpoints */
2437         /* DEN is bidirectional ep number, max_ep doubles the number */
2438         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2439
2440         ret = platform_get_irq(pdev, 0);
2441         if (ret <= 0) {
2442                 ret = ret ? : -ENODEV;
2443                 goto err_exit;
2444         }
2445         udc_controller->irq = ret;
2446
2447         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2448                         driver_name, udc_controller);
2449         if (ret != 0) {
2450                 dev_err(&udc_controller->gadget.dev, "cannot request irq %d err %d\n",
2451                                 udc_controller->irq, ret);
2452                 goto err_exit;
2453         }
2454
2455         /* Initialize the udc structure including QH member and other member */
2456         if (struct_udc_setup(udc_controller, pdev)) {
2457                 dev_err(&udc_controller->gadget.dev, "Can't initialize udc data structure\n");
2458                 ret = -ENOMEM;
2459                 goto err_free_irq;
2460         }
2461
2462         if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2463                 /* initialize usb hw reg except for regs for EP,
2464                  * leave usbintr reg untouched */
2465                 dr_controller_setup(udc_controller);
2466         }
2467
2468         /* Setup gadget structure */
2469         udc_controller->gadget.ops = &fsl_gadget_ops;
2470         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2471         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2472         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2473         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2474         udc_controller->gadget.name = driver_name;
2475
2476         /* Setup gadget.dev and register with kernel */
2477         dev_set_name(&udc_controller->gadget.dev, "gadget");
2478         udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2479
2480         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2481                 udc_controller->gadget.is_otg = 1;
2482
2483         /* setup QH and epctrl for ep0 */
2484         ep0_setup(udc_controller);
2485
2486         /* setup udc->eps[] for ep0 */
2487         struct_ep_setup(udc_controller, 0, "ep0", 0);
2488         /* for ep0: the desc defined here;
2489          * for other eps, gadget layer called ep_enable with defined desc
2490          */
2491         udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2492         usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2493                                    USB_MAX_CTRL_PAYLOAD);
2494
2495         /* setup the udc->eps[] for non-control endpoints and link
2496          * to gadget.ep_list */
2497         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2498                 char name[16];
2499
2500                 sprintf(name, "ep%dout", i);
2501                 struct_ep_setup(udc_controller, i * 2, name, 1);
2502                 sprintf(name, "ep%din", i);
2503                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2504         }
2505
2506         /* use dma_pool for TD management */
2507         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2508                         sizeof(struct ep_td_struct),
2509                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2510         if (udc_controller->td_pool == NULL) {
2511                 ret = -ENOMEM;
2512                 goto err_free_irq;
2513         }
2514
2515         ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2516                         fsl_udc_release);
2517         if (ret)
2518                 goto err_del_udc;
2519
2520         create_proc_file();
2521         return 0;
2522
2523 err_del_udc:
2524         dma_pool_destroy(udc_controller->td_pool);
2525 err_free_irq:
2526         free_irq(udc_controller->irq, udc_controller);
2527 err_exit:
2528         if (pdata->exit)
2529                 pdata->exit(pdev);
2530 err_iounmap:
2531         iounmap(dr_regs);
2532 err_release_mem_region:
2533         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2534                 release_mem_region(res->start, resource_size(res));
2535 err_kfree:
2536         kfree(udc_controller);
2537         udc_controller = NULL;
2538         return ret;
2539 }
2540
2541 /* Driver removal function
2542  * Free resources and finish pending transactions
2543  */
2544 static void fsl_udc_remove(struct platform_device *pdev)
2545 {
2546         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2547         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2548
2549         DECLARE_COMPLETION_ONSTACK(done);
2550
2551         if (!udc_controller) {
2552                 dev_err(&pdev->dev,
2553                         "Driver still in use but removing anyhow\n");
2554                 return;
2555         }
2556
2557         udc_controller->done = &done;
2558         usb_del_gadget_udc(&udc_controller->gadget);
2559
2560         /* DR has been stopped in usb_gadget_unregister_driver() */
2561         remove_proc_file();
2562
2563         /* Free allocated memory */
2564         kfree(udc_controller->status_req->req.buf);
2565         kfree(udc_controller->status_req);
2566         kfree(udc_controller->eps);
2567
2568         dma_pool_destroy(udc_controller->td_pool);
2569         free_irq(udc_controller->irq, udc_controller);
2570         iounmap(dr_regs);
2571         if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2572                 release_mem_region(res->start, resource_size(res));
2573
2574         /* free udc --wait for the release() finished */
2575         wait_for_completion(&done);
2576
2577         /*
2578          * do platform specific un-initialization:
2579          * release iomux pins, etc.
2580          */
2581         if (pdata->exit)
2582                 pdata->exit(pdev);
2583 }
2584
2585 /*-----------------------------------------------------------------
2586  * Modify Power management attributes
2587  * Used by OTG statemachine to disable gadget temporarily
2588  -----------------------------------------------------------------*/
2589 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2590 {
2591         dr_controller_stop(udc_controller);
2592         return 0;
2593 }
2594
2595 /*-----------------------------------------------------------------
2596  * Invoked on USB resume. May be called in_interrupt.
2597  * Here we start the DR controller and enable the irq
2598  *-----------------------------------------------------------------*/
2599 static int fsl_udc_resume(struct platform_device *pdev)
2600 {
2601         /* Enable DR irq reg and set controller Run */
2602         if (udc_controller->stopped) {
2603                 dr_controller_setup(udc_controller);
2604                 dr_controller_run(udc_controller);
2605         }
2606         udc_controller->usb_state = USB_STATE_ATTACHED;
2607         udc_controller->ep0_state = WAIT_FOR_SETUP;
2608         udc_controller->ep0_dir = 0;
2609         return 0;
2610 }
2611
2612 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2613 {
2614         struct fsl_udc *udc = udc_controller;
2615         u32 mode, usbcmd;
2616
2617         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2618
2619         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2620
2621         /*
2622          * If the controller is already stopped, then this must be a
2623          * PM suspend.  Remember this fact, so that we will leave the
2624          * controller stopped at PM resume time.
2625          */
2626         if (udc->stopped) {
2627                 pr_debug("gadget already stopped, leaving early\n");
2628                 udc->already_stopped = 1;
2629                 return 0;
2630         }
2631
2632         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2633                 pr_debug("gadget not in device mode, leaving early\n");
2634                 return 0;
2635         }
2636
2637         /* stop the controller */
2638         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2639         fsl_writel(usbcmd, &dr_regs->usbcmd);
2640
2641         udc->stopped = 1;
2642
2643         pr_info("USB Gadget suspended\n");
2644
2645         return 0;
2646 }
2647
2648 static int fsl_udc_otg_resume(struct device *dev)
2649 {
2650         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2651                  udc_controller->stopped, udc_controller->already_stopped);
2652
2653         /*
2654          * If the controller was stopped at suspend time, then
2655          * don't resume it now.
2656          */
2657         if (udc_controller->already_stopped) {
2658                 udc_controller->already_stopped = 0;
2659                 pr_debug("gadget was already stopped, leaving early\n");
2660                 return 0;
2661         }
2662
2663         pr_info("USB Gadget resume\n");
2664
2665         return fsl_udc_resume(NULL);
2666 }
2667 /*-------------------------------------------------------------------------
2668         Register entry point for the peripheral controller driver
2669 --------------------------------------------------------------------------*/
2670 static const struct platform_device_id fsl_udc_devtype[] = {
2671         {
2672                 .name = "fsl-usb2-udc",
2673         }, {
2674                 /* sentinel */
2675         }
2676 };
2677 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2678
2679 static const struct of_device_id fsl_udc_dt_ids[] = {
2680         { .compatible = "fsl-usb2-dr" },
2681         { .compatible = "fsl-usb2-mph" },
2682         { .compatible = "fsl,mpc5121-usb2-dr" },
2683         { /* sentinel */ }
2684 };
2685 MODULE_DEVICE_TABLE(of, fsl_udc_dt_ids);
2686
2687 static struct platform_driver udc_driver = {
2688         .probe          = fsl_udc_probe,
2689         .remove_new     = fsl_udc_remove,
2690         .id_table       = fsl_udc_devtype,
2691         /* these suspend and resume are not usb suspend and resume */
2692         .suspend        = fsl_udc_suspend,
2693         .resume         = fsl_udc_resume,
2694         .driver         = {
2695                         .name = driver_name,
2696                         .of_match_table = fsl_udc_dt_ids,
2697                         /* udc suspend/resume called from OTG driver */
2698                         .suspend = fsl_udc_otg_suspend,
2699                         .resume  = fsl_udc_otg_resume,
2700         },
2701 };
2702
2703 module_platform_driver(udc_driver);
2704
2705 MODULE_DESCRIPTION(DRIVER_DESC);
2706 MODULE_AUTHOR(DRIVER_AUTHOR);
2707 MODULE_LICENSE("GPL");
2708 MODULE_ALIAS("platform:fsl-usb2-udc");