1 #include <linux/module.h>
3 #include <linux/dma-mapping.h>
4 #include <linux/dmapool.h>
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/ioport.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/timer.h>
13 #include <linux/list.h>
14 #include <linux/interrupt.h>
15 #include <linux/moduleparam.h>
16 #include <linux/device.h>
17 #include <linux/usb/ch9.h>
18 #include <linux/usb/gadget.h>
19 #include <linux/usb/otg.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
25 #include <asm/system.h>
26 #include <asm/unaligned.h>
30 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
31 #define DRIVER_VERSION "8 Nov 2010"
33 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
34 ((ep)->udc->ep0_dir) : ((ep)->direction))
36 /* timeout value -- usec */
37 #define RESET_TIMEOUT 10000
38 #define FLUSH_TIMEOUT 10000
39 #define EPSTATUS_TIMEOUT 10000
40 #define PRIME_TIMEOUT 10000
41 #define READSAFE_TIMEOUT 1000
42 #define DTD_TIMEOUT 1000
44 #define LOOPS_USEC_SHIFT 4
45 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
46 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
48 static const char driver_name[] = "mv_udc";
49 static const char driver_desc[] = DRIVER_DESC;
51 /* controller device global variable */
52 static struct mv_udc *the_controller;
55 static void nuke(struct mv_ep *ep, int status);
57 /* for endpoint 0 operations */
58 static const struct usb_endpoint_descriptor mv_ep0_desc = {
59 .bLength = USB_DT_ENDPOINT_SIZE,
60 .bDescriptorType = USB_DT_ENDPOINT,
61 .bEndpointAddress = 0,
62 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
63 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
66 static void ep0_reset(struct mv_udc *udc)
73 for (i = 0; i < 2; i++) {
78 ep->dqh = &udc->ep_dqh[i];
80 /* configure ep0 endpoint capabilities in dQH */
81 ep->dqh->max_packet_length =
82 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
85 epctrlx = readl(&udc->op_regs->epctrlx[0]);
87 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
88 | (USB_ENDPOINT_XFER_CONTROL
89 << EPCTRL_TX_EP_TYPE_SHIFT);
92 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
93 | (USB_ENDPOINT_XFER_CONTROL
94 << EPCTRL_RX_EP_TYPE_SHIFT);
97 writel(epctrlx, &udc->op_regs->epctrlx[0]);
101 /* protocol ep0 stall, will automatically be cleared on new transaction */
102 static void ep0_stall(struct mv_udc *udc)
106 /* set TX and RX to stall */
107 epctrlx = readl(&udc->op_regs->epctrlx[0]);
108 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
109 writel(epctrlx, &udc->op_regs->epctrlx[0]);
111 /* update ep0 state */
112 udc->ep0_state = WAIT_FOR_SETUP;
113 udc->ep0_dir = EP_DIR_OUT;
116 static int process_ep_req(struct mv_udc *udc, int index,
117 struct mv_req *curr_req)
119 struct mv_dtd *curr_dtd;
120 struct mv_dqh *curr_dqh;
121 int td_complete, actual, remaining_length;
126 curr_dqh = &udc->ep_dqh[index];
127 direction = index % 2;
129 curr_dtd = curr_req->head;
131 actual = curr_req->req.length;
133 for (i = 0; i < curr_req->dtd_count; i++) {
134 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
135 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
136 udc->eps[index].name);
140 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
143 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
144 >> DTD_LENGTH_BIT_POS;
145 actual -= remaining_length;
147 dev_info(&udc->dev->dev,
148 "complete_tr error: ep=%d %s: error = 0x%x\n",
149 index >> 1, direction ? "SEND" : "RECV",
151 if (errors & DTD_STATUS_HALTED) {
152 /* Clear the errors and Halt condition */
153 curr_dqh->size_ioc_int_sts &= ~errors;
155 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
157 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
161 if (i != curr_req->dtd_count - 1)
162 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
167 curr_req->req.actual = actual;
173 * done() - retire a request; caller blocked irqs
174 * @status : request status to be set, only works when
175 * request is still in progress.
177 static void done(struct mv_ep *ep, struct mv_req *req, int status)
179 struct mv_udc *udc = NULL;
180 unsigned char stopped = ep->stopped;
181 struct mv_dtd *curr_td, *next_td;
184 udc = (struct mv_udc *)ep->udc;
185 /* Removed the req from fsl_ep->queue */
186 list_del_init(&req->queue);
188 /* req.status should be set as -EINPROGRESS in ep_queue() */
189 if (req->req.status == -EINPROGRESS)
190 req->req.status = status;
192 status = req->req.status;
194 /* Free dtd for the request */
196 for (j = 0; j < req->dtd_count; j++) {
198 if (j != req->dtd_count - 1)
199 next_td = curr_td->next_dtd_virt;
200 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
204 dma_unmap_single(ep->udc->gadget.dev.parent,
205 req->req.dma, req->req.length,
206 ((ep_dir(ep) == EP_DIR_IN) ?
207 DMA_TO_DEVICE : DMA_FROM_DEVICE));
208 req->req.dma = DMA_ADDR_INVALID;
211 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
212 req->req.dma, req->req.length,
213 ((ep_dir(ep) == EP_DIR_IN) ?
214 DMA_TO_DEVICE : DMA_FROM_DEVICE));
216 if (status && (status != -ESHUTDOWN))
217 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
218 ep->ep.name, &req->req, status,
219 req->req.actual, req->req.length);
223 spin_unlock(&ep->udc->lock);
225 * complete() is from gadget layer,
226 * eg fsg->bulk_in_complete()
228 if (req->req.complete)
229 req->req.complete(&ep->ep, &req->req);
231 spin_lock(&ep->udc->lock);
232 ep->stopped = stopped;
235 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
237 u32 tmp, epstatus, bit_pos, direction;
241 int readsafe, retval = 0;
244 direction = ep_dir(ep);
245 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
246 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
248 /* check if the pipe is empty */
249 if (!(list_empty(&ep->queue))) {
250 struct mv_req *lastreq;
251 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
252 lastreq->tail->dtd_next =
253 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
254 if (readl(&udc->op_regs->epprime) & bit_pos) {
255 loops = LOOPS(PRIME_TIMEOUT);
256 while (readl(&udc->op_regs->epprime) & bit_pos) {
264 if (readl(&udc->op_regs->epstatus) & bit_pos)
268 loops = LOOPS(READSAFE_TIMEOUT);
269 while (readsafe == 0) {
274 /* start with setting the semaphores */
275 tmp = readl(&udc->op_regs->usbcmd);
276 tmp |= USBCMD_ATDTW_TRIPWIRE_SET;
277 writel(tmp, &udc->op_regs->usbcmd);
279 /* read the endpoint status */
280 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
283 * Reread the ATDTW semaphore bit to check if it is
284 * cleared. When hardware see a hazard, it will clear
285 * the bit or else we remain set to 1 and we can
286 * proceed with priming of endpoint if not already
289 if (readl(&udc->op_regs->usbcmd)
290 & USBCMD_ATDTW_TRIPWIRE_SET) {
297 /* Clear the semaphore */
298 tmp = readl(&udc->op_regs->usbcmd);
299 tmp &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
300 writel(tmp, &udc->op_regs->usbcmd);
302 /* If endpoint is not active, we activate it now. */
304 if (direction == EP_DIR_IN) {
305 struct mv_dtd *curr_dtd = dma_to_virt(
306 &udc->dev->dev, dqh->curr_dtd_ptr);
308 loops = LOOPS(DTD_TIMEOUT);
309 while (curr_dtd->size_ioc_sts
310 & DTD_STATUS_ACTIVE) {
319 /* No other transfers on the queue */
321 /* Write dQH next pointer and terminate bit to 0 */
322 dqh->next_dtd_ptr = req->head->td_dma
323 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
324 dqh->size_ioc_int_sts = 0;
327 * Ensure that updates to the QH will
328 * occur before priming.
332 /* Prime the Endpoint */
333 writel(bit_pos, &udc->op_regs->epprime);
336 /* Write dQH next pointer and terminate bit to 0 */
337 dqh->next_dtd_ptr = req->head->td_dma
338 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;;
339 dqh->size_ioc_int_sts = 0;
341 /* Ensure that updates to the QH will occur before priming. */
344 /* Prime the Endpoint */
345 writel(bit_pos, &udc->op_regs->epprime);
347 if (direction == EP_DIR_IN) {
348 /* FIXME add status check after prime the IN ep */
350 u32 curr_dtd_ptr = dqh->curr_dtd_ptr;
352 loops = LOOPS(DTD_TIMEOUT);
354 while ((curr_dtd_ptr != req->head->td_dma)) {
355 curr_dtd_ptr = dqh->curr_dtd_ptr;
357 dev_err(&udc->dev->dev,
358 "failed to prime %s\n",
366 if (loops == (LOOPS(DTD_TIMEOUT) >> 2)) {
369 dev_info(&udc->dev->dev,
372 &udc->op_regs->epprime);
382 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
383 dma_addr_t *dma, int *is_last)
389 /* how big will this transfer be? */
390 *length = min(req->req.length - req->req.actual,
391 (unsigned)EP_MAX_LENGTH_TRANSFER);
396 * Be careful that no _GFP_HIGHMEM is set,
397 * or we can not use dma_to_virt
399 dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
404 /* initialize buffer page pointers */
405 temp = (u32)(req->req.dma + req->req.actual);
406 dtd->buff_ptr0 = cpu_to_le32(temp);
408 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
409 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
410 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
411 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
413 req->req.actual += *length;
415 /* zlp is needed if req->req.zero is set */
417 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
421 } else if (req->req.length == req->req.actual)
426 /* Fill in the transfer size; set active bit */
427 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
429 /* Enable interrupt for the last dtd of a request */
430 if (*is_last && !req->req.no_interrupt)
433 dtd->size_ioc_sts = temp;
440 /* generate dTD linked list for a request */
441 static int req_to_dtd(struct mv_req *req)
444 int is_last, is_first = 1;
445 struct mv_dtd *dtd, *last_dtd = NULL;
452 dtd = build_dtd(req, &count, &dma, &is_last);
460 last_dtd->dtd_next = dma;
461 last_dtd->next_dtd_virt = dtd;
467 /* set terminate bit to 1 for the last dTD */
468 dtd->dtd_next = DTD_NEXT_TERMINATE;
475 static int mv_ep_enable(struct usb_ep *_ep,
476 const struct usb_endpoint_descriptor *desc)
482 u32 bit_pos, epctrlx, direction;
483 unsigned char zlt = 0, ios = 0, mult = 0;
485 ep = container_of(_ep, struct mv_ep, ep);
488 if (!_ep || !desc || ep->desc
489 || desc->bDescriptorType != USB_DT_ENDPOINT)
492 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
495 direction = ep_dir(ep);
496 max = usb_endpoint_maxp(desc);
499 * disable HW zero length termination select
500 * driver handles zero length packet through req->req.zero
504 /* Get the endpoint queue head address */
505 dqh = (struct mv_dqh *)ep->dqh;
507 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
509 /* Check if the Endpoint is Primed */
510 if ((readl(&udc->op_regs->epprime) & bit_pos)
511 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
512 dev_info(&udc->dev->dev,
513 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
514 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
515 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
516 (unsigned)readl(&udc->op_regs->epprime),
517 (unsigned)readl(&udc->op_regs->epstatus),
521 /* Set the max packet length, interrupt on Setup and Mult fields */
522 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
523 case USB_ENDPOINT_XFER_BULK:
527 case USB_ENDPOINT_XFER_CONTROL:
529 case USB_ENDPOINT_XFER_INT:
532 case USB_ENDPOINT_XFER_ISOC:
533 /* Calculate transactions needed for high bandwidth iso */
534 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
535 max = max & 0x8ff; /* bit 0~10 */
536 /* 3 transactions at most */
543 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
544 | (mult << EP_QUEUE_HEAD_MULT_POS)
545 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
546 | (ios ? EP_QUEUE_HEAD_IOS : 0);
547 dqh->next_dtd_ptr = 1;
548 dqh->size_ioc_int_sts = 0;
550 ep->ep.maxpacket = max;
554 /* Enable the endpoint for Rx or Tx and set the endpoint type */
555 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
556 if (direction == EP_DIR_IN) {
557 epctrlx &= ~EPCTRL_TX_ALL_MASK;
558 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
559 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
560 << EPCTRL_TX_EP_TYPE_SHIFT);
562 epctrlx &= ~EPCTRL_RX_ALL_MASK;
563 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
564 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
565 << EPCTRL_RX_EP_TYPE_SHIFT);
567 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
570 * Implement Guideline (GL# USB-7) The unused endpoint type must
571 * be programmed to bulk.
573 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
574 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
575 epctrlx |= ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
576 << EPCTRL_RX_EP_TYPE_SHIFT);
577 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
580 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
581 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
582 epctrlx |= ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
583 << EPCTRL_TX_EP_TYPE_SHIFT);
584 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
592 static int mv_ep_disable(struct usb_ep *_ep)
597 u32 bit_pos, epctrlx, direction;
599 ep = container_of(_ep, struct mv_ep, ep);
600 if ((_ep == NULL) || !ep->desc)
605 /* Get the endpoint queue head address */
608 direction = ep_dir(ep);
609 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
611 /* Reset the max packet length and the interrupt on Setup */
612 dqh->max_packet_length = 0;
614 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
615 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
616 epctrlx &= ~((direction == EP_DIR_IN)
617 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
618 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
619 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
621 /* nuke all pending requests (does flush) */
622 nuke(ep, -ESHUTDOWN);
629 static struct usb_request *
630 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
632 struct mv_req *req = NULL;
634 req = kzalloc(sizeof *req, gfp_flags);
638 req->req.dma = DMA_ADDR_INVALID;
639 INIT_LIST_HEAD(&req->queue);
644 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
646 struct mv_req *req = NULL;
648 req = container_of(_req, struct mv_req, req);
654 static void mv_ep_fifo_flush(struct usb_ep *_ep)
657 u32 bit_pos, direction;
658 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
662 direction = ep_dir(ep);
663 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
665 * Flushing will halt the pipe
666 * Write 1 to the Flush register
668 writel(bit_pos, &udc->op_regs->epflush);
670 /* Wait until flushing completed */
671 loops = LOOPS(FLUSH_TIMEOUT);
672 while (readl(&udc->op_regs->epflush) & bit_pos) {
674 * ENDPTFLUSH bit should be cleared to indicate this
675 * operation is complete
678 dev_err(&udc->dev->dev,
679 "TIMEOUT for ENDPTFLUSH=0x%x, bit_pos=0x%x\n",
680 (unsigned)readl(&udc->op_regs->epflush),
687 loops = LOOPS(EPSTATUS_TIMEOUT);
688 while (readl(&udc->op_regs->epstatus) & bit_pos) {
689 unsigned int inter_loops;
692 dev_err(&udc->dev->dev,
693 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
694 (unsigned)readl(&udc->op_regs->epstatus),
698 /* Write 1 to the Flush register */
699 writel(bit_pos, &udc->op_regs->epflush);
701 /* Wait until flushing completed */
702 inter_loops = LOOPS(FLUSH_TIMEOUT);
703 while (readl(&udc->op_regs->epflush) & bit_pos) {
705 * ENDPTFLUSH bit should be cleared to indicate this
706 * operation is complete
708 if (inter_loops == 0) {
709 dev_err(&udc->dev->dev,
710 "TIMEOUT for ENDPTFLUSH=0x%x,"
712 (unsigned)readl(&udc->op_regs->epflush),
723 /* queues (submits) an I/O request to an endpoint */
725 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
727 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
728 struct mv_req *req = container_of(_req, struct mv_req, req);
729 struct mv_udc *udc = ep->udc;
732 /* catch various bogus parameters */
733 if (!_req || !req->req.complete || !req->req.buf
734 || !list_empty(&req->queue)) {
735 dev_err(&udc->dev->dev, "%s, bad params", __func__);
738 if (unlikely(!_ep || !ep->desc)) {
739 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
742 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
743 if (req->req.length > ep->ep.maxpacket)
748 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
753 /* map virtual address to hardware */
754 if (req->req.dma == DMA_ADDR_INVALID) {
755 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
757 req->req.length, ep_dir(ep)
762 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
763 req->req.dma, req->req.length,
770 req->req.status = -EINPROGRESS;
774 spin_lock_irqsave(&udc->lock, flags);
776 /* build dtds and push them to device queue */
777 if (!req_to_dtd(req)) {
779 retval = queue_dtd(ep, req);
781 spin_unlock_irqrestore(&udc->lock, flags);
785 spin_unlock_irqrestore(&udc->lock, flags);
789 /* Update ep0 state */
791 udc->ep0_state = DATA_STATE_XMIT;
793 /* irq handler advances the queue */
795 list_add_tail(&req->queue, &ep->queue);
796 spin_unlock_irqrestore(&udc->lock, flags);
801 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
802 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
804 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
806 struct mv_udc *udc = ep->udc;
808 int stopped, ret = 0;
814 spin_lock_irqsave(&ep->udc->lock, flags);
815 stopped = ep->stopped;
817 /* Stop the ep before we deal with the queue */
819 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
820 if (ep_dir(ep) == EP_DIR_IN)
821 epctrlx &= ~EPCTRL_TX_ENABLE;
823 epctrlx &= ~EPCTRL_RX_ENABLE;
824 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
826 /* make sure it's actually queued on this endpoint */
827 list_for_each_entry(req, &ep->queue, queue) {
828 if (&req->req == _req)
831 if (&req->req != _req) {
836 /* The request is in progress, or completed but not dequeued */
837 if (ep->queue.next == &req->queue) {
838 _req->status = -ECONNRESET;
839 mv_ep_fifo_flush(_ep); /* flush current transfer */
841 /* The request isn't the last request in this ep queue */
842 if (req->queue.next != &ep->queue) {
844 struct mv_req *next_req;
847 next_req = list_entry(req->queue.next, struct mv_req,
850 /* Point the QH to the first TD of next request */
851 writel((u32) next_req->head, &qh->curr_dtd_ptr);
856 qh->next_dtd_ptr = 1;
857 qh->size_ioc_int_sts = 0;
860 /* The request hasn't been processed, patch up the TD chain */
862 struct mv_req *prev_req;
864 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
865 writel(readl(&req->tail->dtd_next),
866 &prev_req->tail->dtd_next);
870 done(ep, req, -ECONNRESET);
874 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
875 if (ep_dir(ep) == EP_DIR_IN)
876 epctrlx |= EPCTRL_TX_ENABLE;
878 epctrlx |= EPCTRL_RX_ENABLE;
879 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
880 ep->stopped = stopped;
882 spin_unlock_irqrestore(&ep->udc->lock, flags);
886 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
890 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
893 if (direction == EP_DIR_IN)
894 epctrlx |= EPCTRL_TX_EP_STALL;
896 epctrlx |= EPCTRL_RX_EP_STALL;
898 if (direction == EP_DIR_IN) {
899 epctrlx &= ~EPCTRL_TX_EP_STALL;
900 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
902 epctrlx &= ~EPCTRL_RX_EP_STALL;
903 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
906 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
909 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
913 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
915 if (direction == EP_DIR_OUT)
916 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
918 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
921 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
924 unsigned long flags = 0;
928 ep = container_of(_ep, struct mv_ep, ep);
930 if (!_ep || !ep->desc) {
935 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
936 status = -EOPNOTSUPP;
941 * Attempt to halt IN ep will fail if any transfer requests
944 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
949 spin_lock_irqsave(&ep->udc->lock, flags);
950 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
955 spin_unlock_irqrestore(&ep->udc->lock, flags);
957 if (ep->ep_num == 0) {
958 udc->ep0_state = WAIT_FOR_SETUP;
959 udc->ep0_dir = EP_DIR_OUT;
965 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
967 return mv_ep_set_halt_wedge(_ep, halt, 0);
970 static int mv_ep_set_wedge(struct usb_ep *_ep)
972 return mv_ep_set_halt_wedge(_ep, 1, 1);
975 static struct usb_ep_ops mv_ep_ops = {
976 .enable = mv_ep_enable,
977 .disable = mv_ep_disable,
979 .alloc_request = mv_alloc_request,
980 .free_request = mv_free_request,
982 .queue = mv_ep_queue,
983 .dequeue = mv_ep_dequeue,
985 .set_wedge = mv_ep_set_wedge,
986 .set_halt = mv_ep_set_halt,
987 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
990 static void udc_stop(struct mv_udc *udc)
994 /* Disable interrupts */
995 tmp = readl(&udc->op_regs->usbintr);
996 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
997 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
998 writel(tmp, &udc->op_regs->usbintr);
1000 /* Reset the Run the bit in the command register to stop VUSB */
1001 tmp = readl(&udc->op_regs->usbcmd);
1002 tmp &= ~USBCMD_RUN_STOP;
1003 writel(tmp, &udc->op_regs->usbcmd);
1006 static void udc_start(struct mv_udc *udc)
1010 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1011 | USBINTR_PORT_CHANGE_DETECT_EN
1012 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1013 /* Enable interrupts */
1014 writel(usbintr, &udc->op_regs->usbintr);
1016 /* Set the Run bit in the command register */
1017 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1020 static int udc_reset(struct mv_udc *udc)
1025 /* Stop the controller */
1026 tmp = readl(&udc->op_regs->usbcmd);
1027 tmp &= ~USBCMD_RUN_STOP;
1028 writel(tmp, &udc->op_regs->usbcmd);
1030 /* Reset the controller to get default values */
1031 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1033 /* wait for reset to complete */
1034 loops = LOOPS(RESET_TIMEOUT);
1035 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1037 dev_err(&udc->dev->dev,
1038 "Wait for RESET completed TIMEOUT\n");
1045 /* set controller to device mode */
1046 tmp = readl(&udc->op_regs->usbmode);
1047 tmp |= USBMODE_CTRL_MODE_DEVICE;
1049 /* turn setup lockout off, require setup tripwire in usbcmd */
1050 tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1052 writel(tmp, &udc->op_regs->usbmode);
1054 writel(0x0, &udc->op_regs->epsetupstat);
1056 /* Configure the Endpoint List Address */
1057 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1058 &udc->op_regs->eplistaddr);
1060 portsc = readl(&udc->op_regs->portsc[0]);
1061 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1062 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1065 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1067 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1069 writel(portsc, &udc->op_regs->portsc[0]);
1071 tmp = readl(&udc->op_regs->epctrlx[0]);
1072 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1073 writel(tmp, &udc->op_regs->epctrlx[0]);
1078 static int mv_udc_get_frame(struct usb_gadget *gadget)
1086 udc = container_of(gadget, struct mv_udc, gadget);
1088 retval = readl(udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1093 /* Tries to wake up the host connected to this gadget */
1094 static int mv_udc_wakeup(struct usb_gadget *gadget)
1096 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1099 /* Remote wakeup feature not enabled by host */
1100 if (!udc->remote_wakeup)
1103 portsc = readl(&udc->op_regs->portsc);
1104 /* not suspended? */
1105 if (!(portsc & PORTSCX_PORT_SUSPEND))
1107 /* trigger force resume */
1108 portsc |= PORTSCX_PORT_FORCE_RESUME;
1109 writel(portsc, &udc->op_regs->portsc[0]);
1113 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1116 unsigned long flags;
1118 udc = container_of(gadget, struct mv_udc, gadget);
1119 spin_lock_irqsave(&udc->lock, flags);
1121 udc->softconnect = (is_on != 0);
1122 if (udc->driver && udc->softconnect)
1127 spin_unlock_irqrestore(&udc->lock, flags);
1131 static int mv_udc_start(struct usb_gadget_driver *driver,
1132 int (*bind)(struct usb_gadget *));
1133 static int mv_udc_stop(struct usb_gadget_driver *driver);
1134 /* device controller usb_gadget_ops structure */
1135 static const struct usb_gadget_ops mv_ops = {
1137 /* returns the current frame number */
1138 .get_frame = mv_udc_get_frame,
1140 /* tries to wake up the host connected to this gadget */
1141 .wakeup = mv_udc_wakeup,
1143 /* D+ pullup, software-controlled connect/disconnect to USB host */
1144 .pullup = mv_udc_pullup,
1145 .start = mv_udc_start,
1146 .stop = mv_udc_stop,
1149 static void mv_udc_testmode(struct mv_udc *udc, u16 index, bool enter)
1151 dev_info(&udc->dev->dev, "Test Mode is not support yet\n");
1154 static int eps_init(struct mv_udc *udc)
1160 /* initialize ep0 */
1163 strncpy(ep->name, "ep0", sizeof(ep->name));
1164 ep->ep.name = ep->name;
1165 ep->ep.ops = &mv_ep_ops;
1168 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1170 ep->desc = &mv_ep0_desc;
1171 INIT_LIST_HEAD(&ep->queue);
1173 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1175 /* initialize other endpoints */
1176 for (i = 2; i < udc->max_eps * 2; i++) {
1179 snprintf(name, sizeof(name), "ep%din", i / 2);
1180 ep->direction = EP_DIR_IN;
1182 snprintf(name, sizeof(name), "ep%dout", i / 2);
1183 ep->direction = EP_DIR_OUT;
1186 strncpy(ep->name, name, sizeof(ep->name));
1187 ep->ep.name = ep->name;
1189 ep->ep.ops = &mv_ep_ops;
1191 ep->ep.maxpacket = (unsigned short) ~0;
1194 INIT_LIST_HEAD(&ep->queue);
1195 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1197 ep->dqh = &udc->ep_dqh[i];
1203 /* delete all endpoint requests, called with spinlock held */
1204 static void nuke(struct mv_ep *ep, int status)
1206 /* called with spinlock held */
1209 /* endpoint fifo flush */
1210 mv_ep_fifo_flush(&ep->ep);
1212 while (!list_empty(&ep->queue)) {
1213 struct mv_req *req = NULL;
1214 req = list_entry(ep->queue.next, struct mv_req, queue);
1215 done(ep, req, status);
1219 /* stop all USB activities */
1220 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1224 nuke(&udc->eps[0], -ESHUTDOWN);
1226 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1227 nuke(ep, -ESHUTDOWN);
1230 /* report disconnect; the driver is already quiesced */
1232 spin_unlock(&udc->lock);
1233 driver->disconnect(&udc->gadget);
1234 spin_lock(&udc->lock);
1238 static int mv_udc_start(struct usb_gadget_driver *driver,
1239 int (*bind)(struct usb_gadget *))
1241 struct mv_udc *udc = the_controller;
1243 unsigned long flags;
1251 spin_lock_irqsave(&udc->lock, flags);
1253 /* hook up the driver ... */
1254 driver->driver.bus = NULL;
1255 udc->driver = driver;
1256 udc->gadget.dev.driver = &driver->driver;
1258 udc->usb_state = USB_STATE_ATTACHED;
1259 udc->ep0_state = WAIT_FOR_SETUP;
1260 udc->ep0_dir = USB_DIR_OUT;
1262 spin_unlock_irqrestore(&udc->lock, flags);
1264 retval = bind(&udc->gadget);
1266 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1267 driver->driver.name, retval);
1269 udc->gadget.dev.driver = NULL;
1279 static int mv_udc_stop(struct usb_gadget_driver *driver)
1281 struct mv_udc *udc = the_controller;
1282 unsigned long flags;
1289 spin_lock_irqsave(&udc->lock, flags);
1291 /* stop all usb activities */
1292 udc->gadget.speed = USB_SPEED_UNKNOWN;
1293 stop_activity(udc, driver);
1294 spin_unlock_irqrestore(&udc->lock, flags);
1296 /* unbind gadget driver */
1297 driver->unbind(&udc->gadget);
1298 udc->gadget.dev.driver = NULL;
1305 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1312 udc->ep0_dir = direction;
1314 req = udc->status_req;
1316 /* fill in the reqest structure */
1317 if (empty == false) {
1318 *((u16 *) req->req.buf) = cpu_to_le16(status);
1319 req->req.length = 2;
1321 req->req.length = 0;
1324 req->req.status = -EINPROGRESS;
1325 req->req.actual = 0;
1326 req->req.complete = NULL;
1329 /* prime the data phase */
1330 if (!req_to_dtd(req))
1331 retval = queue_dtd(ep, req);
1338 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1342 list_add_tail(&req->queue, &ep->queue);
1349 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1351 udc->dev_addr = (u8)setup->wValue;
1353 /* update usb state */
1354 udc->usb_state = USB_STATE_ADDRESS;
1356 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1360 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1361 struct usb_ctrlrequest *setup)
1366 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1367 != (USB_DIR_IN | USB_TYPE_STANDARD))
1370 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1371 status = 1 << USB_DEVICE_SELF_POWERED;
1372 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1373 } else if ((setup->bRequestType & USB_RECIP_MASK)
1374 == USB_RECIP_INTERFACE) {
1375 /* get interface status */
1377 } else if ((setup->bRequestType & USB_RECIP_MASK)
1378 == USB_RECIP_ENDPOINT) {
1379 u8 ep_num, direction;
1381 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1382 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1383 ? EP_DIR_IN : EP_DIR_OUT;
1384 status = ep_is_stall(udc, ep_num, direction)
1385 << USB_ENDPOINT_HALT;
1388 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1393 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1399 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1400 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1401 switch (setup->wValue) {
1402 case USB_DEVICE_REMOTE_WAKEUP:
1403 udc->remote_wakeup = 0;
1405 case USB_DEVICE_TEST_MODE:
1406 mv_udc_testmode(udc, 0, false);
1411 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1412 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1413 switch (setup->wValue) {
1414 case USB_ENDPOINT_HALT:
1415 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1416 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1417 ? EP_DIR_IN : EP_DIR_OUT;
1418 if (setup->wValue != 0 || setup->wLength != 0
1419 || ep_num > udc->max_eps)
1421 ep = &udc->eps[ep_num * 2 + direction];
1424 spin_unlock(&udc->lock);
1425 ep_set_stall(udc, ep_num, direction, 0);
1426 spin_lock(&udc->lock);
1434 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1437 udc->ep0_state = DATA_STATE_XMIT;
1442 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1447 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1448 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1449 switch (setup->wValue) {
1450 case USB_DEVICE_REMOTE_WAKEUP:
1451 udc->remote_wakeup = 1;
1453 case USB_DEVICE_TEST_MODE:
1454 if (setup->wIndex & 0xFF
1455 && udc->gadget.speed != USB_SPEED_HIGH)
1457 if (udc->usb_state == USB_STATE_CONFIGURED
1458 || udc->usb_state == USB_STATE_ADDRESS
1459 || udc->usb_state == USB_STATE_DEFAULT)
1460 mv_udc_testmode(udc,
1461 setup->wIndex & 0xFF00, true);
1468 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1469 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1470 switch (setup->wValue) {
1471 case USB_ENDPOINT_HALT:
1472 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1473 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1474 ? EP_DIR_IN : EP_DIR_OUT;
1475 if (setup->wValue != 0 || setup->wLength != 0
1476 || ep_num > udc->max_eps)
1478 spin_unlock(&udc->lock);
1479 ep_set_stall(udc, ep_num, direction, 1);
1480 spin_lock(&udc->lock);
1488 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1494 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1495 struct usb_ctrlrequest *setup)
1497 bool delegate = false;
1499 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1501 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1502 setup->bRequestType, setup->bRequest,
1503 setup->wValue, setup->wIndex, setup->wLength);
1504 /* We process some stardard setup requests here */
1505 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1506 switch (setup->bRequest) {
1507 case USB_REQ_GET_STATUS:
1508 ch9getstatus(udc, ep_num, setup);
1511 case USB_REQ_SET_ADDRESS:
1512 ch9setaddress(udc, setup);
1515 case USB_REQ_CLEAR_FEATURE:
1516 ch9clearfeature(udc, setup);
1519 case USB_REQ_SET_FEATURE:
1520 ch9setfeature(udc, setup);
1529 /* delegate USB standard requests to the gadget driver */
1530 if (delegate == true) {
1531 /* USB requests handled by gadget */
1532 if (setup->wLength) {
1533 /* DATA phase from gadget, STATUS phase from udc */
1534 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1535 ? EP_DIR_IN : EP_DIR_OUT;
1536 spin_unlock(&udc->lock);
1537 if (udc->driver->setup(&udc->gadget,
1538 &udc->local_setup_buff) < 0)
1540 spin_lock(&udc->lock);
1541 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1542 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1544 /* no DATA phase, IN STATUS phase from gadget */
1545 udc->ep0_dir = EP_DIR_IN;
1546 spin_unlock(&udc->lock);
1547 if (udc->driver->setup(&udc->gadget,
1548 &udc->local_setup_buff) < 0)
1550 spin_lock(&udc->lock);
1551 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1556 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1557 static void ep0_req_complete(struct mv_udc *udc,
1558 struct mv_ep *ep0, struct mv_req *req)
1562 if (udc->usb_state == USB_STATE_ADDRESS) {
1563 /* set the new address */
1564 new_addr = (u32)udc->dev_addr;
1565 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1566 &udc->op_regs->deviceaddr);
1571 switch (udc->ep0_state) {
1572 case DATA_STATE_XMIT:
1573 /* receive status phase */
1574 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1577 case DATA_STATE_RECV:
1578 /* send status phase */
1579 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1582 case WAIT_FOR_OUT_STATUS:
1583 udc->ep0_state = WAIT_FOR_SETUP;
1585 case WAIT_FOR_SETUP:
1586 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1594 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1599 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1601 /* Clear bit in ENDPTSETUPSTAT */
1602 temp = readl(&udc->op_regs->epsetupstat);
1603 writel(temp | (1 << ep_num), &udc->op_regs->epsetupstat);
1605 /* while a hazard exists when setup package arrives */
1607 /* Set Setup Tripwire */
1608 temp = readl(&udc->op_regs->usbcmd);
1609 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1611 /* Copy the setup packet to local buffer */
1612 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1613 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1615 /* Clear Setup Tripwire */
1616 temp = readl(&udc->op_regs->usbcmd);
1617 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1620 static void irq_process_tr_complete(struct mv_udc *udc)
1623 int i, ep_num = 0, direction = 0;
1624 struct mv_ep *curr_ep;
1625 struct mv_req *curr_req, *temp_req;
1629 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1630 * because the setup packets are to be read ASAP
1633 /* Process all Setup packet received interrupts */
1634 tmp = readl(&udc->op_regs->epsetupstat);
1637 for (i = 0; i < udc->max_eps; i++) {
1638 if (tmp & (1 << i)) {
1639 get_setup_data(udc, i,
1640 (u8 *)(&udc->local_setup_buff));
1641 handle_setup_packet(udc, i,
1642 &udc->local_setup_buff);
1647 /* Don't clear the endpoint setup status register here.
1648 * It is cleared as a setup packet is read out of the buffer
1651 /* Process non-setup transaction complete interrupts */
1652 tmp = readl(&udc->op_regs->epcomplete);
1657 writel(tmp, &udc->op_regs->epcomplete);
1659 for (i = 0; i < udc->max_eps * 2; i++) {
1663 bit_pos = 1 << (ep_num + 16 * direction);
1665 if (!(bit_pos & tmp))
1669 curr_ep = &udc->eps[0];
1671 curr_ep = &udc->eps[i];
1672 /* process the req queue until an uncomplete request */
1673 list_for_each_entry_safe(curr_req, temp_req,
1674 &curr_ep->queue, queue) {
1675 status = process_ep_req(udc, i, curr_req);
1679 /* write back status to req */
1680 curr_req->req.status = status;
1682 /* ep0 request completion */
1684 ep0_req_complete(udc, curr_ep, curr_req);
1687 done(curr_ep, curr_req, status);
1693 void irq_process_reset(struct mv_udc *udc)
1698 udc->ep0_dir = EP_DIR_OUT;
1699 udc->ep0_state = WAIT_FOR_SETUP;
1700 udc->remote_wakeup = 0; /* default to 0 on reset */
1702 /* The address bits are past bit 25-31. Set the address */
1703 tmp = readl(&udc->op_regs->deviceaddr);
1704 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1705 writel(tmp, &udc->op_regs->deviceaddr);
1707 /* Clear all the setup token semaphores */
1708 tmp = readl(&udc->op_regs->epsetupstat);
1709 writel(tmp, &udc->op_regs->epsetupstat);
1711 /* Clear all the endpoint complete status bits */
1712 tmp = readl(&udc->op_regs->epcomplete);
1713 writel(tmp, &udc->op_regs->epcomplete);
1715 /* wait until all endptprime bits cleared */
1716 loops = LOOPS(PRIME_TIMEOUT);
1717 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1719 dev_err(&udc->dev->dev,
1720 "Timeout for ENDPTPRIME = 0x%x\n",
1721 readl(&udc->op_regs->epprime));
1728 /* Write 1s to the Flush register */
1729 writel((u32)~0, &udc->op_regs->epflush);
1731 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1732 dev_info(&udc->dev->dev, "usb bus reset\n");
1733 udc->usb_state = USB_STATE_DEFAULT;
1734 /* reset all the queues, stop all USB activities */
1735 stop_activity(udc, udc->driver);
1737 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1738 readl(&udc->op_regs->portsc));
1746 /* reset all the queues, stop all USB activities */
1747 stop_activity(udc, udc->driver);
1749 /* reset ep0 dQH and endptctrl */
1752 /* enable interrupt and set controller to run state */
1755 udc->usb_state = USB_STATE_ATTACHED;
1759 static void handle_bus_resume(struct mv_udc *udc)
1761 udc->usb_state = udc->resume_state;
1762 udc->resume_state = 0;
1764 /* report resume to the driver */
1766 if (udc->driver->resume) {
1767 spin_unlock(&udc->lock);
1768 udc->driver->resume(&udc->gadget);
1769 spin_lock(&udc->lock);
1774 static void irq_process_suspend(struct mv_udc *udc)
1776 udc->resume_state = udc->usb_state;
1777 udc->usb_state = USB_STATE_SUSPENDED;
1779 if (udc->driver->suspend) {
1780 spin_unlock(&udc->lock);
1781 udc->driver->suspend(&udc->gadget);
1782 spin_lock(&udc->lock);
1786 static void irq_process_port_change(struct mv_udc *udc)
1790 portsc = readl(&udc->op_regs->portsc[0]);
1791 if (!(portsc & PORTSCX_PORT_RESET)) {
1793 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1795 case PORTSCX_PORT_SPEED_HIGH:
1796 udc->gadget.speed = USB_SPEED_HIGH;
1798 case PORTSCX_PORT_SPEED_FULL:
1799 udc->gadget.speed = USB_SPEED_FULL;
1801 case PORTSCX_PORT_SPEED_LOW:
1802 udc->gadget.speed = USB_SPEED_LOW;
1805 udc->gadget.speed = USB_SPEED_UNKNOWN;
1810 if (portsc & PORTSCX_PORT_SUSPEND) {
1811 udc->resume_state = udc->usb_state;
1812 udc->usb_state = USB_STATE_SUSPENDED;
1813 if (udc->driver->suspend) {
1814 spin_unlock(&udc->lock);
1815 udc->driver->suspend(&udc->gadget);
1816 spin_lock(&udc->lock);
1820 if (!(portsc & PORTSCX_PORT_SUSPEND)
1821 && udc->usb_state == USB_STATE_SUSPENDED) {
1822 handle_bus_resume(udc);
1825 if (!udc->resume_state)
1826 udc->usb_state = USB_STATE_DEFAULT;
1829 static void irq_process_error(struct mv_udc *udc)
1831 /* Increment the error count */
1835 static irqreturn_t mv_udc_irq(int irq, void *dev)
1837 struct mv_udc *udc = (struct mv_udc *)dev;
1840 spin_lock(&udc->lock);
1842 status = readl(&udc->op_regs->usbsts);
1843 intr = readl(&udc->op_regs->usbintr);
1847 spin_unlock(&udc->lock);
1851 /* Clear all the interrupts occurred */
1852 writel(status, &udc->op_regs->usbsts);
1854 if (status & USBSTS_ERR)
1855 irq_process_error(udc);
1857 if (status & USBSTS_RESET)
1858 irq_process_reset(udc);
1860 if (status & USBSTS_PORT_CHANGE)
1861 irq_process_port_change(udc);
1863 if (status & USBSTS_INT)
1864 irq_process_tr_complete(udc);
1866 if (status & USBSTS_SUSPEND)
1867 irq_process_suspend(udc);
1869 spin_unlock(&udc->lock);
1874 /* release device structure */
1875 static void gadget_release(struct device *_dev)
1877 struct mv_udc *udc = the_controller;
1879 complete(udc->done);
1883 static int mv_udc_remove(struct platform_device *dev)
1885 struct mv_udc *udc = the_controller;
1886 DECLARE_COMPLETION(done);
1888 usb_del_gadget_udc(&udc->gadget);
1892 /* free memory allocated in probe */
1894 dma_pool_destroy(udc->dtd_pool);
1897 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
1898 udc->ep_dqh, udc->ep_dqh_dma);
1903 free_irq(udc->irq, &dev->dev);
1906 iounmap(udc->cap_regs);
1907 udc->cap_regs = NULL;
1910 iounmap((void *)udc->phy_regs);
1913 if (udc->status_req) {
1914 kfree(udc->status_req->req.buf);
1915 kfree(udc->status_req);
1918 device_unregister(&udc->gadget.dev);
1920 /* free dev, wait for the release() finished */
1921 wait_for_completion(&done);
1923 the_controller = NULL;
1928 int mv_udc_probe(struct platform_device *dev)
1935 udc = kzalloc(sizeof *udc, GFP_KERNEL);
1937 dev_err(&dev->dev, "failed to allocate memory for udc\n");
1942 spin_lock_init(&udc->lock);
1946 udc->clk = clk_get(&dev->dev, "U2OCLK");
1947 if (IS_ERR(udc->clk)) {
1948 retval = PTR_ERR(udc->clk);
1952 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "u2o");
1954 dev_err(&dev->dev, "no I/O memory resource defined\n");
1959 udc->cap_regs = (struct mv_cap_regs __iomem *)
1960 ioremap(r->start, resource_size(r));
1961 if (udc->cap_regs == NULL) {
1962 dev_err(&dev->dev, "failed to map I/O memory\n");
1967 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "u2ophy");
1969 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
1974 udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
1975 if (udc->phy_regs == 0) {
1976 dev_err(&dev->dev, "failed to map phy I/O memory\n");
1981 /* we will acces controller register, so enable the clk */
1982 clk_enable(udc->clk);
1983 retval = mv_udc_phy_init(udc->phy_regs);
1985 dev_err(&dev->dev, "phy initialization error %d\n", retval);
1989 udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
1990 + (readl(&udc->cap_regs->caplength_hciversion)
1992 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
1994 size = udc->max_eps * sizeof(struct mv_dqh) *2;
1995 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
1996 udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
1997 &udc->ep_dqh_dma, GFP_KERNEL);
1999 if (udc->ep_dqh == NULL) {
2000 dev_err(&dev->dev, "allocate dQH memory failed\n");
2004 udc->ep_dqh_size = size;
2006 /* create dTD dma_pool resource */
2007 udc->dtd_pool = dma_pool_create("mv_dtd",
2009 sizeof(struct mv_dtd),
2013 if (!udc->dtd_pool) {
2018 size = udc->max_eps * sizeof(struct mv_ep) *2;
2019 udc->eps = kzalloc(size, GFP_KERNEL);
2020 if (udc->eps == NULL) {
2021 dev_err(&dev->dev, "allocate ep memory failed\n");
2026 /* initialize ep0 status request structure */
2027 udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2028 if (!udc->status_req) {
2029 dev_err(&dev->dev, "allocate status_req memory failed\n");
2033 INIT_LIST_HEAD(&udc->status_req->queue);
2035 /* allocate a small amount of memory to get valid address */
2036 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2037 udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2039 udc->resume_state = USB_STATE_NOTATTACHED;
2040 udc->usb_state = USB_STATE_POWERED;
2041 udc->ep0_dir = EP_DIR_OUT;
2042 udc->remote_wakeup = 0;
2044 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2046 dev_err(&dev->dev, "no IRQ resource defined\n");
2050 udc->irq = r->start;
2051 if (request_irq(udc->irq, mv_udc_irq,
2052 IRQF_DISABLED | IRQF_SHARED, driver_name, udc)) {
2053 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2059 /* initialize gadget structure */
2060 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2061 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2062 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2063 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2064 udc->gadget.is_dualspeed = 1; /* support dual speed */
2066 /* the "gadget" abstracts/virtualizes the controller */
2067 dev_set_name(&udc->gadget.dev, "gadget");
2068 udc->gadget.dev.parent = &dev->dev;
2069 udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2070 udc->gadget.dev.release = gadget_release;
2071 udc->gadget.name = driver_name; /* gadget name */
2073 retval = device_register(&udc->gadget.dev);
2079 the_controller = udc;
2081 retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
2086 mv_udc_remove(udc->dev);
2091 static int mv_udc_suspend(struct device *_dev)
2093 struct mv_udc *udc = the_controller;
2100 static int mv_udc_resume(struct device *_dev)
2102 struct mv_udc *udc = the_controller;
2105 retval = mv_udc_phy_init(udc->phy_regs);
2107 dev_err(_dev, "phy initialization error %d\n", retval);
2117 static const struct dev_pm_ops mv_udc_pm_ops = {
2118 .suspend = mv_udc_suspend,
2119 .resume = mv_udc_resume,
2123 static struct platform_driver udc_driver = {
2124 .probe = mv_udc_probe,
2125 .remove = __exit_p(mv_udc_remove),
2127 .owner = THIS_MODULE,
2130 .pm = &mv_udc_pm_ops,
2134 MODULE_ALIAS("platform:pxa-u2o");
2136 MODULE_DESCRIPTION(DRIVER_DESC);
2137 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2138 MODULE_VERSION(DRIVER_VERSION);
2139 MODULE_LICENSE("GPL");
2142 static int __init init(void)
2144 return platform_driver_register(&udc_driver);
2149 static void __exit cleanup(void)
2151 platform_driver_unregister(&udc_driver);
2153 module_exit(cleanup);