2 * USB Gadget driver for LPC32xx
5 * Kevin Wells <kevin.wells@nxp.com>
7 * Roland Stigge <stigge@antcom.de>
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
13 * Note: This driver is based on original work done by Mike James for
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/init.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/proc_fs.h>
42 #include <linux/clk.h>
43 #include <linux/usb/ch9.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/i2c.h>
46 #include <linux/kthread.h>
47 #include <linux/freezer.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/dmapool.h>
50 #include <linux/workqueue.h>
52 #include <linux/usb/isp1301.h>
54 #include <asm/byteorder.h>
55 #include <mach/hardware.h>
58 #include <asm/system.h>
60 #include <mach/platform.h>
61 #include <mach/irqs.h>
62 #include <mach/board.h>
63 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
64 #include <linux/debugfs.h>
65 #include <linux/seq_file.h>
69 * USB device configuration structure
71 typedef void (*usc_chg_event)(int);
72 struct lpc32xx_usbd_cfg {
73 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
74 usc_chg_event conn_chgb; /* Connection change event (optional) */
75 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
76 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
80 * controller driver data structures
83 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
84 #define NUM_ENDPOINTS 16
87 * IRQ indices make reading the code a little easier
91 #define IRQ_USB_DEVDMA 2
94 #define EP_OUT 0 /* RX (from host) */
95 #define EP_IN 1 /* TX (to host) */
97 /* Returns the interrupt mask for the selected hardware endpoint */
98 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
100 #define EP_INT_TYPE 0
101 #define EP_ISO_TYPE 1
102 #define EP_BLK_TYPE 2
103 #define EP_CTL_TYPE 3
106 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
107 #define DATA_IN 1 /* Expect dev->host transfer */
108 #define DATA_OUT 2 /* Expect host->dev transfer */
110 /* DD (DMA Descriptor) structure, requires word alignment, this is already
111 * defined in the LPC32XX USB device header file, but this version is slightly
112 * modified to tag some work data with each DMA descriptor. */
113 struct lpc32xx_usbd_dd_gad {
118 u32 dd_iso_ps_mem_addr;
120 u32 iso_status[6]; /* 5 spare */
125 * Logical endpoint structure
129 struct list_head queue;
130 struct lpc32xx_udc *udc;
132 u32 hwep_num_base; /* Physical hardware EP */
133 u32 hwep_num; /* Maps to hardware endpoint */
147 * Common UDC structure
150 struct usb_gadget gadget;
151 struct usb_gadget_driver *driver;
152 struct platform_device *pdev;
156 struct i2c_client *isp1301_i2c_client;
158 /* Board and device specific */
159 struct lpc32xx_usbd_cfg *board;
162 void __iomem *udp_baseaddr;
164 struct clk *usb_pll_clk;
165 struct clk *usb_slv_clk;
166 struct clk *usb_otg_clk;
171 struct dma_pool *dd_cache;
173 /* Common EP and control data */
175 u32 enabled_hwepints;
179 /* VBUS detection, pullup, and power flags */
185 /* Work queues related to I2C support */
186 struct work_struct pullup_job;
187 struct work_struct vbus_job;
188 struct work_struct power_job;
190 /* USB device peripheral - various */
191 struct lpc32xx_ep ep[NUM_ENDPOINTS];
197 atomic_t enabled_ep_cnt;
198 wait_queue_head_t ep_disable_wait_queue;
204 struct lpc32xx_request {
205 struct usb_request req;
206 struct list_head queue;
207 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
212 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
214 return container_of(g, struct lpc32xx_udc, gadget);
217 #define ep_dbg(epp, fmt, arg...) \
218 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
219 #define ep_err(epp, fmt, arg...) \
220 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
221 #define ep_info(epp, fmt, arg...) \
222 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
223 #define ep_warn(epp, fmt, arg...) \
224 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
226 #define UDCA_BUFF_SIZE (128)
228 /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
229 * be replaced with an inremap()ed pointer
231 #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
233 /* USB_CTRL bit defines */
234 #define USB_SLAVE_HCLK_EN (1 << 24)
235 #define USB_HOST_NEED_CLK_EN (1 << 21)
236 #define USB_DEV_NEED_CLK_EN (1 << 22)
238 /**********************************************************************
239 * USB device controller register offsets
240 **********************************************************************/
242 #define USBD_DEVINTST(x) ((x) + 0x200)
243 #define USBD_DEVINTEN(x) ((x) + 0x204)
244 #define USBD_DEVINTCLR(x) ((x) + 0x208)
245 #define USBD_DEVINTSET(x) ((x) + 0x20C)
246 #define USBD_CMDCODE(x) ((x) + 0x210)
247 #define USBD_CMDDATA(x) ((x) + 0x214)
248 #define USBD_RXDATA(x) ((x) + 0x218)
249 #define USBD_TXDATA(x) ((x) + 0x21C)
250 #define USBD_RXPLEN(x) ((x) + 0x220)
251 #define USBD_TXPLEN(x) ((x) + 0x224)
252 #define USBD_CTRL(x) ((x) + 0x228)
253 #define USBD_DEVINTPRI(x) ((x) + 0x22C)
254 #define USBD_EPINTST(x) ((x) + 0x230)
255 #define USBD_EPINTEN(x) ((x) + 0x234)
256 #define USBD_EPINTCLR(x) ((x) + 0x238)
257 #define USBD_EPINTSET(x) ((x) + 0x23C)
258 #define USBD_EPINTPRI(x) ((x) + 0x240)
259 #define USBD_REEP(x) ((x) + 0x244)
260 #define USBD_EPIND(x) ((x) + 0x248)
261 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
262 /* DMA support registers only below */
263 /* Set, clear, or get enabled state of the DMA request status. If
264 * enabled, an IN or OUT token will start a DMA transfer for the EP */
265 #define USBD_DMARST(x) ((x) + 0x250)
266 #define USBD_DMARCLR(x) ((x) + 0x254)
267 #define USBD_DMARSET(x) ((x) + 0x258)
268 /* DMA UDCA head pointer */
269 #define USBD_UDCAH(x) ((x) + 0x280)
270 /* EP DMA status, enable, and disable. This is used to specifically
271 * enabled or disable DMA for a specific EP */
272 #define USBD_EPDMAST(x) ((x) + 0x284)
273 #define USBD_EPDMAEN(x) ((x) + 0x288)
274 #define USBD_EPDMADIS(x) ((x) + 0x28C)
275 /* DMA master interrupts enable and pending interrupts */
276 #define USBD_DMAINTST(x) ((x) + 0x290)
277 #define USBD_DMAINTEN(x) ((x) + 0x294)
278 /* DMA end of transfer interrupt enable, disable, status */
279 #define USBD_EOTINTST(x) ((x) + 0x2A0)
280 #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
281 #define USBD_EOTINTSET(x) ((x) + 0x2A8)
282 /* New DD request interrupt enable, disable, status */
283 #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
284 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
285 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
286 /* DMA error interrupt enable, disable, status */
287 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
288 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
289 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
291 /**********************************************************************
292 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
293 * USBD_DEVINTPRI register definitions
294 **********************************************************************/
295 #define USBD_ERR_INT (1 << 9)
296 #define USBD_EP_RLZED (1 << 8)
297 #define USBD_TXENDPKT (1 << 7)
298 #define USBD_RXENDPKT (1 << 6)
299 #define USBD_CDFULL (1 << 5)
300 #define USBD_CCEMPTY (1 << 4)
301 #define USBD_DEV_STAT (1 << 3)
302 #define USBD_EP_SLOW (1 << 2)
303 #define USBD_EP_FAST (1 << 1)
304 #define USBD_FRAME (1 << 0)
306 /**********************************************************************
307 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
308 * USBD_EPINTPRI register definitions
309 **********************************************************************/
310 /* End point selection macro (RX) */
311 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
313 /* End point selection macro (TX) */
314 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
316 /**********************************************************************
317 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
318 * USBD_EPDMAEN/USBD_EPDMADIS/
319 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
320 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
321 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
322 * register definitions
323 **********************************************************************/
324 /* Endpoint selection macro */
325 #define USBD_EP_SEL(e) (1 << (e))
327 /**********************************************************************
328 * SBD_DMAINTST/USBD_DMAINTEN
329 **********************************************************************/
330 #define USBD_SYS_ERR_INT (1 << 2)
331 #define USBD_NEW_DD_INT (1 << 1)
332 #define USBD_EOT_INT (1 << 0)
334 /**********************************************************************
335 * USBD_RXPLEN register definitions
336 **********************************************************************/
337 #define USBD_PKT_RDY (1 << 11)
338 #define USBD_DV (1 << 10)
339 #define USBD_PK_LEN_MASK 0x3FF
341 /**********************************************************************
342 * USBD_CTRL register definitions
343 **********************************************************************/
344 #define USBD_LOG_ENDPOINT(e) ((e) << 2)
345 #define USBD_WR_EN (1 << 1)
346 #define USBD_RD_EN (1 << 0)
348 /**********************************************************************
349 * USBD_CMDCODE register definitions
350 **********************************************************************/
351 #define USBD_CMD_CODE(c) ((c) << 16)
352 #define USBD_CMD_PHASE(p) ((p) << 8)
354 /**********************************************************************
355 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
356 **********************************************************************/
357 #define USBD_DMAEP(e) (1 << (e))
359 /* DD (DMA Descriptor) structure, requires word alignment */
360 struct lpc32xx_usbd_dd {
365 u32 dd_iso_ps_mem_addr;
368 /* dd_setup bit defines */
369 #define DD_SETUP_ATLE_DMA_MODE 0x01
370 #define DD_SETUP_NEXT_DD_VALID 0x04
371 #define DD_SETUP_ISO_EP 0x10
372 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
373 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
375 /* dd_status bit defines */
376 #define DD_STATUS_DD_RETIRED 0x01
377 #define DD_STATUS_STS_MASK 0x1E
378 #define DD_STATUS_STS_NS 0x00 /* Not serviced */
379 #define DD_STATUS_STS_BS 0x02 /* Being serviced */
380 #define DD_STATUS_STS_NC 0x04 /* Normal completion */
381 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
382 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
383 #define DD_STATUS_STS_SE 0x12 /* System error */
384 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
385 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
386 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
387 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
388 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
392 * Protocol engine bits below
395 /* Device Interrupt Bit Definitions */
396 #define FRAME_INT 0x00000001
397 #define EP_FAST_INT 0x00000002
398 #define EP_SLOW_INT 0x00000004
399 #define DEV_STAT_INT 0x00000008
400 #define CCEMTY_INT 0x00000010
401 #define CDFULL_INT 0x00000020
402 #define RxENDPKT_INT 0x00000040
403 #define TxENDPKT_INT 0x00000080
404 #define EP_RLZED_INT 0x00000100
405 #define ERR_INT 0x00000200
407 /* Rx & Tx Packet Length Definitions */
408 #define PKT_LNGTH_MASK 0x000003FF
409 #define PKT_DV 0x00000400
410 #define PKT_RDY 0x00000800
412 /* USB Control Definitions */
413 #define CTRL_RD_EN 0x00000001
414 #define CTRL_WR_EN 0x00000002
417 #define CMD_SET_ADDR 0x00D00500
418 #define CMD_CFG_DEV 0x00D80500
419 #define CMD_SET_MODE 0x00F30500
420 #define CMD_RD_FRAME 0x00F50500
421 #define DAT_RD_FRAME 0x00F50200
422 #define CMD_RD_TEST 0x00FD0500
423 #define DAT_RD_TEST 0x00FD0200
424 #define CMD_SET_DEV_STAT 0x00FE0500
425 #define CMD_GET_DEV_STAT 0x00FE0500
426 #define DAT_GET_DEV_STAT 0x00FE0200
427 #define CMD_GET_ERR_CODE 0x00FF0500
428 #define DAT_GET_ERR_CODE 0x00FF0200
429 #define CMD_RD_ERR_STAT 0x00FB0500
430 #define DAT_RD_ERR_STAT 0x00FB0200
431 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
432 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
433 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
434 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
435 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
436 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
437 #define CMD_CLR_BUF 0x00F20500
438 #define DAT_CLR_BUF 0x00F20200
439 #define CMD_VALID_BUF 0x00FA0500
441 /* Device Address Register Definitions */
442 #define DEV_ADDR_MASK 0x7F
445 /* Device Configure Register Definitions */
446 #define CONF_DVICE 0x01
448 /* Device Mode Register Definitions */
457 /* Device Status Register Definitions */
459 #define DEV_CON_CH 0x02
461 #define DEV_SUS_CH 0x08
464 /* Error Code Register Definitions */
465 #define ERR_EC_MASK 0x0F
468 /* Error Status Register Definitions */
470 #define ERR_UEPKT 0x02
471 #define ERR_DCRC 0x04
472 #define ERR_TIMOUT 0x08
474 #define ERR_B_OVRN 0x20
475 #define ERR_BTSTF 0x40
478 /* Endpoint Select Register Definitions */
479 #define EP_SEL_F 0x01
480 #define EP_SEL_ST 0x02
481 #define EP_SEL_STP 0x04
482 #define EP_SEL_PO 0x08
483 #define EP_SEL_EPN 0x10
484 #define EP_SEL_B_1_FULL 0x20
485 #define EP_SEL_B_2_FULL 0x40
487 /* Endpoint Status Register Definitions */
488 #define EP_STAT_ST 0x01
489 #define EP_STAT_DA 0x20
490 #define EP_STAT_RF_MO 0x40
491 #define EP_STAT_CND_ST 0x80
493 /* Clear Buffer Register Definitions */
494 #define CLR_BUF_PO 0x01
496 /* DMA Interrupt Bit Definitions */
498 #define NDD_REQ_INT 0x02
499 #define SYS_ERR_INT 0x04
501 #define DRIVER_VERSION "1.03"
502 static const char driver_name[] = "lpc32xx_udc";
506 * proc interface support
509 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
510 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
511 static const char debug_filename[] = "driver/udc";
513 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
515 struct lpc32xx_request *req;
518 seq_printf(s, "%12s, maxpacket %4d %3s",
519 ep->ep.name, ep->ep.maxpacket,
520 ep->is_in ? "in" : "out");
521 seq_printf(s, " type %4s", epnames[ep->eptype]);
522 seq_printf(s, " ints: %12d", ep->totalints);
524 if (list_empty(&ep->queue))
525 seq_printf(s, "\t(queue empty)\n");
527 list_for_each_entry(req, &ep->queue, queue) {
528 u32 length = req->req.actual;
530 seq_printf(s, "\treq %p len %d/%d buf %p\n",
532 req->req.length, req->req.buf);
537 static int proc_udc_show(struct seq_file *s, void *unused)
539 struct lpc32xx_udc *udc = s->private;
540 struct lpc32xx_ep *ep;
543 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
545 spin_lock_irqsave(&udc->lock, flags);
547 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
548 udc->vbus ? "present" : "off",
549 udc->enabled ? (udc->vbus ? "active" : "enabled") :
551 udc->selfpowered ? "self" : "VBUS",
552 udc->suspended ? ", suspended" : "",
553 udc->driver ? udc->driver->driver.name : "(none)");
555 if (udc->enabled && udc->vbus) {
556 proc_ep_show(s, &udc->ep[0]);
557 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
561 spin_unlock_irqrestore(&udc->lock, flags);
566 static int proc_udc_open(struct inode *inode, struct file *file)
568 return single_open(file, proc_udc_show, PDE(inode)->data);
571 static const struct file_operations proc_ops = {
572 .owner = THIS_MODULE,
573 .open = proc_udc_open,
576 .release = single_release,
579 static void create_debug_file(struct lpc32xx_udc *udc)
581 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
584 static void remove_debug_file(struct lpc32xx_udc *udc)
587 debugfs_remove(udc->pde);
591 static inline void create_debug_file(struct lpc32xx_udc *udc) {}
592 static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
595 /* Primary initialization sequence for the ISP1301 transceiver */
596 static void isp1301_udc_configure(struct lpc32xx_udc *udc)
598 /* LPC32XX only supports DAT_SE0 USB mode */
599 /* This sequence is important */
601 /* Disable transparent UART mode first */
602 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
603 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
606 /* Set full speed and SE0 mode */
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
609 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
610 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
613 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
615 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
616 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
617 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
618 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
620 /* Driver VBUS_DRV high or low depending on board setup */
621 if (udc->board->vbus_drv_pol != 0)
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
625 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
626 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
629 /* Bi-directional mode with suspend control
630 * Enable both pulldowns for now - the pullup will be enable when VBUS
632 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
633 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
634 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
635 ISP1301_I2C_OTG_CONTROL_1,
636 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
638 /* Discharge VBUS (just in case) */
639 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
640 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
642 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
643 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
646 /* Clear and enable VBUS high edge interrupt */
647 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
648 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
649 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
650 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
651 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
652 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
653 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
654 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
655 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
656 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
658 /* Enable usb_need_clk clock after transceiver is initialized */
659 writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL);
661 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
662 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
663 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
664 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
665 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
666 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
669 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
670 static void isp1301_pullup_set(struct lpc32xx_udc *udc)
673 /* Enable pullup for bus signalling */
674 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
675 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
677 /* Enable pullup for bus signalling */
678 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
679 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
683 static void pullup_work(struct work_struct *work)
685 struct lpc32xx_udc *udc =
686 container_of(work, struct lpc32xx_udc, pullup_job);
688 isp1301_pullup_set(udc);
691 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
694 if (en_pullup == udc->pullup)
697 udc->pullup = en_pullup;
699 isp1301_pullup_set(udc);
701 /* defer slow i2c pull up setting */
702 schedule_work(&udc->pullup_job);
706 /* Powers up or down the ISP1301 transceiver */
707 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
710 /* Power up ISP1301 - this ISP1301 will automatically wakeup
711 when VBUS is detected */
712 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
713 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
716 /* Power down ISP1301 */
717 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
718 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
721 static void power_work(struct work_struct *work)
723 struct lpc32xx_udc *udc =
724 container_of(work, struct lpc32xx_udc, power_job);
726 isp1301_set_powerstate(udc, udc->poweron);
732 * USB protocol engine command/data read/write helper functions
735 /* Issues a single command to the USB device state machine */
736 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
741 /* EP may lock on CLRI if this read isn't done */
742 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
746 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
748 /* Write command code */
749 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
751 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
752 USBD_CCEMPTY) == 0) && (to > 0)) {
763 /* Issues 2 commands (or command and data) to the USB device state machine */
764 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
767 udc_protocol_cmd_w(udc, cmd);
768 udc_protocol_cmd_w(udc, data);
771 /* Issues a single command to the USB device state machine and reads
773 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
778 /* Write a command and read data from the protocol engine */
779 writel((USBD_CDFULL | USBD_CCEMPTY),
780 USBD_DEVINTCLR(udc->udp_baseaddr));
782 /* Write command code */
783 udc_protocol_cmd_w(udc, cmd);
785 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
786 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
791 "Protocol engine didn't receive response (CDFULL)\n");
793 return readl(USBD_CMDDATA(udc->udp_baseaddr));
798 * USB device interrupt mask support functions
801 /* Enable one or more USB device interrupts */
802 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
804 udc->enabled_devints |= devmask;
805 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
808 /* Disable one or more USB device interrupts */
809 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
811 udc->enabled_devints &= ~mask;
812 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
815 /* Clear one or more USB device interrupts */
816 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
818 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
823 * Endpoint interrupt disable/enable functions
826 /* Enable one or more USB endpoint interrupts */
827 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
829 udc->enabled_hwepints |= (1 << hwep);
830 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
833 /* Disable one or more USB endpoint interrupts */
834 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
836 udc->enabled_hwepints &= ~(1 << hwep);
837 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
840 /* Clear one or more USB endpoint interrupts */
841 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
843 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
846 /* Enable DMA for the HW channel */
847 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
849 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
852 /* Disable DMA for the HW channel */
853 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
855 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
860 * Endpoint realize/unrealize functions
863 /* Before an endpoint can be used, it needs to be realized
864 * in the USB protocol engine - this realizes the endpoint.
865 * The interrupt (FIFO or DMA) is not enabled with this function */
866 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
871 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
872 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
873 udc->realized_eps |= (1 << hwep);
874 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
875 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
877 /* Wait until endpoint is realized in hardware */
878 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
879 USBD_EP_RLZED)) && (to > 0))
882 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
884 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
887 /* Unrealize an EP */
888 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
890 udc->realized_eps &= ~(1 << hwep);
891 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
896 * Endpoint support functions
899 /* Select and clear endpoint interrupt */
900 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
902 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
903 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
906 /* Disables the endpoint in the USB protocol engine */
907 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
909 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
910 DAT_WR_BYTE(EP_STAT_DA));
913 /* Stalls the endpoint - endpoint will return STALL */
914 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
916 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
917 DAT_WR_BYTE(EP_STAT_ST));
920 /* Clear stall or reset endpoint */
921 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
923 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
927 /* Select an endpoint for endpoint status, clear, validate */
928 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
930 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
935 * Endpoint buffer management functions
938 /* Clear the current endpoint's buffer */
939 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
941 udc_select_hwep(udc, hwep);
942 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
945 /* Validate the current endpoint's buffer */
946 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
948 udc_select_hwep(udc, hwep);
949 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
952 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
954 /* Clear EP interrupt */
955 uda_clear_hwepint(udc, hwep);
956 return udc_selep_clrint(udc, hwep);
964 /* Allocate a DMA Descriptor */
965 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
968 struct lpc32xx_usbd_dd_gad *dd;
970 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
971 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
978 /* Free a DMA Descriptor */
979 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
981 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
986 * USB setup and shutdown functions
989 /* Enables or disables most of the USB system clocks when low power mode is
990 * needed. Clocks are typically started on a connection event, and disabled
991 * when a cable is disconnected */
992 static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
1001 clk_enable(udc->usb_pll_clk);
1003 /* Enable the USB device clock */
1004 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
1007 clk_enable(udc->usb_otg_clk);
1014 /* Never disable the USB_HCLK during normal operation */
1016 /* 48MHz PLL dpwn */
1017 clk_disable(udc->usb_pll_clk);
1019 /* Disable the USB device clock */
1020 writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
1023 clk_disable(udc->usb_otg_clk);
1027 /* Set/reset USB device address */
1028 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
1030 /* Address will be latched at the end of the status phase, or
1031 latched immediately if function is called twice */
1032 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
1033 DAT_WR_BYTE(DEV_EN | addr));
1036 /* Setup up a IN request for DMA transfer - this consists of determining the
1037 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1038 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1039 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1041 struct lpc32xx_request *req;
1042 u32 hwep = ep->hwep_num;
1044 ep->req_pending = 1;
1046 /* There will always be a request waiting here */
1047 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1049 /* Place the DD Descriptor into the UDCA */
1050 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1052 /* Enable DMA and interrupt for the HW EP */
1053 udc_ep_dma_enable(udc, hwep);
1055 /* Clear ZLP if last packet is not of MAXP size */
1056 if (req->req.length % ep->ep.maxpacket)
1062 /* Setup up a OUT request for DMA transfer - this consists of determining the
1063 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1064 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1065 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1067 struct lpc32xx_request *req;
1068 u32 hwep = ep->hwep_num;
1070 ep->req_pending = 1;
1072 /* There will always be a request waiting here */
1073 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1075 /* Place the DD Descriptor into the UDCA */
1076 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1078 /* Enable DMA and interrupt for the HW EP */
1079 udc_ep_dma_enable(udc, hwep);
1083 static void udc_disable(struct lpc32xx_udc *udc)
1087 /* Disable device */
1088 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1089 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1091 /* Disable all device interrupts (including EP0) */
1092 uda_disable_devint(udc, 0x3FF);
1094 /* Disable and reset all endpoint interrupts */
1095 for (i = 0; i < 32; i++) {
1096 uda_disable_hwepint(udc, i);
1097 uda_clear_hwepint(udc, i);
1098 udc_disable_hwep(udc, i);
1099 udc_unrealize_hwep(udc, i);
1100 udc->udca_v_base[i] = 0;
1102 /* Disable and clear all interrupts and DMA */
1103 udc_ep_dma_disable(udc, i);
1104 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1105 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1106 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1107 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1110 /* Disable DMA interrupts */
1111 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1113 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1116 static void udc_enable(struct lpc32xx_udc *udc)
1119 struct lpc32xx_ep *ep = &udc->ep[0];
1121 /* Start with known state */
1125 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1127 /* EP interrupts on high priority, FRAME interrupt on low priority */
1128 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1129 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1131 /* Clear any pending device interrupts */
1132 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1134 /* Setup UDCA - not yet used (DMA) */
1135 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1137 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1138 for (i = 0; i <= 1; i++) {
1139 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1140 uda_enable_hwepint(udc, i);
1141 udc_select_hwep(udc, i);
1142 udc_clrstall_hwep(udc, i);
1143 udc_clr_buffer_hwep(udc, i);
1146 /* Device interrupt setup */
1147 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1149 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1152 /* Set device address to 0 - called twice to force a latch in the USB
1153 engine without the need of a setup packet status closure */
1154 udc_set_address(udc, 0);
1155 udc_set_address(udc, 0);
1157 /* Enable master DMA interrupts */
1158 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1159 USBD_DMAINTEN(udc->udp_baseaddr));
1161 udc->dev_status = 0;
1166 * USB device board specific events handled via callbacks
1169 /* Connection change event - notify board function of change */
1170 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1172 /* Just notify of a connection change event (optional) */
1173 if (udc->board->conn_chgb != NULL)
1174 udc->board->conn_chgb(conn);
1177 /* Suspend/resume event - notify board function of change */
1178 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1180 /* Just notify of a Suspend/resume change event (optional) */
1181 if (udc->board->susp_chgb != NULL)
1182 udc->board->susp_chgb(conn);
1190 /* Remote wakeup enable/disable - notify board function of change */
1191 static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1193 if (udc->board->rmwk_chgb != NULL)
1194 udc->board->rmwk_chgb(udc->dev_status &
1195 (1 << USB_DEVICE_REMOTE_WAKEUP));
1198 /* Reads data from FIFO, adjusts for alignment and data size */
1199 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1203 u32 *p32, tmp, cbytes;
1205 /* Use optimal data transfer method based on source address and size */
1206 switch (((u32) data) & 0x3) {
1207 case 0: /* 32-bit aligned */
1209 cbytes = (bytes & ~0x3);
1211 /* Copy 32-bit aligned data first */
1212 for (n = 0; n < cbytes; n += 4)
1213 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1215 /* Handle any remaining bytes */
1216 bl = bytes - cbytes;
1218 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1219 for (n = 0; n < bl; n++)
1220 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1225 case 1: /* 8-bit aligned */
1227 /* Each byte has to be handled independently */
1228 for (n = 0; n < bytes; n += 4) {
1229 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1235 for (i = 0; i < bl; i++)
1236 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1240 case 2: /* 16-bit aligned */
1242 cbytes = (bytes & ~0x3);
1244 /* Copy 32-bit sized objects first with 16-bit alignment */
1245 for (n = 0; n < cbytes; n += 4) {
1246 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1247 *p16++ = (u16)(tmp & 0xFFFF);
1248 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1251 /* Handle any remaining bytes */
1252 bl = bytes - cbytes;
1254 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1255 for (n = 0; n < bl; n++)
1256 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1262 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1263 * as EP0) that don't use DMA. This function should only be called if a packet
1264 * is known to be ready to read for the endpoint. Note that the endpoint must
1265 * be selected in the protocol engine prior to this call. */
1266 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1271 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1273 /* Setup read of endpoint */
1274 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1276 /* Wait until packet is ready */
1277 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1278 PKT_RDY) == 0) && (to > 0))
1281 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1283 /* Mask out count */
1284 tmp = tmpv & PKT_LNGTH_MASK;
1288 if ((tmp > 0) && (data != NULL))
1289 udc_pop_fifo(udc, (u8 *) data, tmp);
1291 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1293 /* Clear the buffer */
1294 udc_clr_buffer_hwep(udc, hwep);
1299 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1300 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1304 u32 *p32, tmp, cbytes;
1306 /* Use optimal data transfer method based on source address and size */
1307 switch (((u32) data) & 0x3) {
1308 case 0: /* 32-bit aligned */
1310 cbytes = (bytes & ~0x3);
1312 /* Copy 32-bit aligned data first */
1313 for (n = 0; n < cbytes; n += 4)
1314 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1316 /* Handle any remaining bytes */
1317 bl = bytes - cbytes;
1320 for (n = 0; n < bl; n++)
1321 tmp |= data[cbytes + n] << (n * 8);
1323 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1327 case 1: /* 8-bit aligned */
1329 /* Each byte has to be handled independently */
1330 for (n = 0; n < bytes; n += 4) {
1336 for (i = 0; i < bl; i++)
1337 tmp |= data[n + i] << (i * 8);
1339 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1343 case 2: /* 16-bit aligned */
1345 cbytes = (bytes & ~0x3);
1347 /* Copy 32-bit aligned data first */
1348 for (n = 0; n < cbytes; n += 4) {
1349 tmp = *p16++ & 0xFFFF;
1350 tmp |= (*p16++ & 0xFFFF) << 16;
1351 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1354 /* Handle any remaining bytes */
1355 bl = bytes - cbytes;
1358 for (n = 0; n < bl; n++)
1359 tmp |= data[cbytes + n] << (n * 8);
1361 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1367 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1368 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1369 * protocol engine prior to this call. */
1370 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1373 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1375 if ((bytes > 0) && (data == NULL))
1378 /* Setup write of endpoint */
1379 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1381 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1383 /* Need at least 1 byte to trigger TX */
1385 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1387 udc_stuff_fifo(udc, (u8 *) data, bytes);
1389 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1391 udc_val_buffer_hwep(udc, hwep);
1394 /* USB device reset - resets USB to a default state with just EP0
1396 static void uda_usb_reset(struct lpc32xx_udc *udc)
1399 /* Re-init device controller and EP0 */
1401 udc->gadget.speed = USB_SPEED_FULL;
1403 for (i = 1; i < NUM_ENDPOINTS; i++) {
1404 struct lpc32xx_ep *ep = &udc->ep[i];
1405 ep->req_pending = 0;
1409 /* Send a ZLP on EP0 */
1410 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1412 udc_write_hwep(udc, EP_IN, NULL, 0);
1415 /* Get current frame number */
1416 static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1420 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1421 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1422 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1424 return (fhi << 8) | flo;
1427 /* Set the device as configured - enables all endpoints */
1428 static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1430 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1433 /* Set the device as unconfigured - disables all endpoints */
1434 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1436 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1439 /* reinit == restore initial software state */
1440 static void udc_reinit(struct lpc32xx_udc *udc)
1444 INIT_LIST_HEAD(&udc->gadget.ep_list);
1445 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1447 for (i = 0; i < NUM_ENDPOINTS; i++) {
1448 struct lpc32xx_ep *ep = &udc->ep[i];
1451 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1452 ep->ep.maxpacket = ep->maxpacket;
1453 INIT_LIST_HEAD(&ep->queue);
1454 ep->req_pending = 0;
1457 udc->ep0state = WAIT_FOR_SETUP;
1460 /* Must be called with lock */
1461 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1463 struct lpc32xx_udc *udc = ep->udc;
1465 list_del_init(&req->queue);
1466 if (req->req.status == -EINPROGRESS)
1467 req->req.status = status;
1469 status = req->req.status;
1472 enum dma_data_direction direction;
1475 direction = DMA_TO_DEVICE;
1477 direction = DMA_FROM_DEVICE;
1480 dma_unmap_single(ep->udc->gadget.dev.parent,
1481 req->req.dma, req->req.length,
1486 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
1487 req->req.dma, req->req.length,
1491 udc_dd_free(udc, req->dd_desc_ptr);
1494 if (status && status != -ESHUTDOWN)
1495 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1497 ep->req_pending = 0;
1498 spin_unlock(&udc->lock);
1499 req->req.complete(&ep->ep, &req->req);
1500 spin_lock(&udc->lock);
1503 /* Must be called with lock */
1504 static void nuke(struct lpc32xx_ep *ep, int status)
1506 struct lpc32xx_request *req;
1508 while (!list_empty(&ep->queue)) {
1509 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1510 done(ep, req, status);
1513 if (status == -ESHUTDOWN) {
1514 uda_disable_hwepint(ep->udc, ep->hwep_num);
1515 udc_disable_hwep(ep->udc, ep->hwep_num);
1519 /* IN endpoint 0 transfer */
1520 static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1522 struct lpc32xx_request *req;
1523 struct lpc32xx_ep *ep0 = &udc->ep[0];
1526 if (list_empty(&ep0->queue))
1527 /* Nothing to send */
1530 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1533 tsend = ts = req->req.length - req->req.actual;
1536 udc_ep0_send_zlp(udc);
1539 } else if (ts > ep0->ep.maxpacket)
1540 ts = ep0->ep.maxpacket; /* Just send what we can */
1542 /* Write data to the EP0 FIFO and start transfer */
1543 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1545 /* Increment data pointer */
1546 req->req.actual += ts;
1548 if (tsend >= ep0->ep.maxpacket)
1549 return 0; /* Stay in data transfer state */
1551 /* Transfer request is complete */
1552 udc->ep0state = WAIT_FOR_SETUP;
1557 /* OUT endpoint 0 transfer */
1558 static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1560 struct lpc32xx_request *req;
1561 struct lpc32xx_ep *ep0 = &udc->ep[0];
1562 u32 tr, bufferspace;
1564 if (list_empty(&ep0->queue))
1567 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1571 if (req->req.length == 0) {
1572 /* Just dequeue request */
1574 udc->ep0state = WAIT_FOR_SETUP;
1578 /* Get data from FIFO */
1579 bufferspace = req->req.length - req->req.actual;
1580 if (bufferspace > ep0->ep.maxpacket)
1581 bufferspace = ep0->ep.maxpacket;
1583 /* Copy data to buffer */
1584 prefetchw(req->req.buf + req->req.actual);
1585 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1587 req->req.actual += bufferspace;
1589 if (tr < ep0->ep.maxpacket) {
1590 /* This is the last packet */
1592 udc->ep0state = WAIT_FOR_SETUP;
1600 /* Must be called with lock */
1601 static void stop_activity(struct lpc32xx_udc *udc)
1603 struct usb_gadget_driver *driver = udc->driver;
1606 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1609 udc->gadget.speed = USB_SPEED_UNKNOWN;
1612 for (i = 0; i < NUM_ENDPOINTS; i++) {
1613 struct lpc32xx_ep *ep = &udc->ep[i];
1614 nuke(ep, -ESHUTDOWN);
1617 spin_unlock(&udc->lock);
1618 driver->disconnect(&udc->gadget);
1619 spin_lock(&udc->lock);
1622 isp1301_pullup_enable(udc, 0, 0);
1628 * Activate or kill host pullup
1629 * Can be called with or without lock
1631 static void pullup(struct lpc32xx_udc *udc, int is_on)
1636 if (!udc->enabled || !udc->vbus)
1639 if (is_on != udc->pullup)
1640 isp1301_pullup_enable(udc, is_on, 0);
1643 /* Must be called without lock */
1644 static int lpc32xx_ep_disable(struct usb_ep *_ep)
1646 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1647 struct lpc32xx_udc *udc = ep->udc;
1648 unsigned long flags;
1650 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1652 spin_lock_irqsave(&udc->lock, flags);
1654 nuke(ep, -ESHUTDOWN);
1656 /* Clear all DMA statuses for this EP */
1657 udc_ep_dma_disable(udc, ep->hwep_num);
1658 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1659 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1660 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1661 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1663 /* Remove the DD pointer in the UDCA */
1664 udc->udca_v_base[ep->hwep_num] = 0;
1666 /* Disable and reset endpoint and interrupt */
1667 uda_clear_hwepint(udc, ep->hwep_num);
1668 udc_unrealize_hwep(udc, ep->hwep_num);
1672 spin_unlock_irqrestore(&udc->lock, flags);
1674 atomic_dec(&udc->enabled_ep_cnt);
1675 wake_up(&udc->ep_disable_wait_queue);
1680 /* Must be called without lock */
1681 static int lpc32xx_ep_enable(struct usb_ep *_ep,
1682 const struct usb_endpoint_descriptor *desc)
1684 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1685 struct lpc32xx_udc *udc = ep->udc;
1688 unsigned long flags;
1690 /* Verify EP data */
1691 if ((!_ep) || (!ep) || (!desc) ||
1692 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1693 dev_dbg(udc->dev, "bad ep or descriptor\n");
1696 maxpacket = usb_endpoint_maxp(desc);
1697 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1698 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1702 /* Don't touch EP0 */
1703 if (ep->hwep_num_base == 0) {
1704 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1708 /* Is driver ready? */
1709 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1710 dev_dbg(udc->dev, "bogus device state\n");
1714 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1716 case USB_ENDPOINT_XFER_CONTROL:
1719 case USB_ENDPOINT_XFER_INT:
1720 if (maxpacket > ep->maxpacket) {
1722 "Bad INT endpoint maxpacket %d\n", maxpacket);
1727 case USB_ENDPOINT_XFER_BULK:
1728 switch (maxpacket) {
1737 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1742 case USB_ENDPOINT_XFER_ISOC:
1745 spin_lock_irqsave(&udc->lock, flags);
1747 /* Initialize endpoint to match the selected descriptor */
1748 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1749 ep->ep.maxpacket = maxpacket;
1751 /* Map hardware endpoint from base and direction */
1753 /* IN endpoints are offset 1 from the OUT endpoint */
1754 ep->hwep_num = ep->hwep_num_base + EP_IN;
1756 ep->hwep_num = ep->hwep_num_base;
1758 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1759 ep->hwep_num, maxpacket, (ep->is_in == 1));
1761 /* Realize the endpoint, interrupt is enabled later when
1762 * buffers are queued, IN EPs will NAK until buffers are ready */
1763 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1764 udc_clr_buffer_hwep(udc, ep->hwep_num);
1765 uda_disable_hwepint(udc, ep->hwep_num);
1766 udc_clrstall_hwep(udc, ep->hwep_num);
1768 /* Clear all DMA statuses for this EP */
1769 udc_ep_dma_disable(udc, ep->hwep_num);
1770 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1771 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1772 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1773 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1775 spin_unlock_irqrestore(&udc->lock, flags);
1777 atomic_inc(&udc->enabled_ep_cnt);
1782 * Allocate a USB request list
1783 * Can be called with or without lock
1785 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1788 struct lpc32xx_request *req;
1790 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1794 INIT_LIST_HEAD(&req->queue);
1799 * De-allocate a USB request list
1800 * Can be called with or without lock
1802 static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1803 struct usb_request *_req)
1805 struct lpc32xx_request *req;
1807 req = container_of(_req, struct lpc32xx_request, req);
1808 BUG_ON(!list_empty(&req->queue));
1812 /* Must be called without lock */
1813 static int lpc32xx_ep_queue(struct usb_ep *_ep,
1814 struct usb_request *_req, gfp_t gfp_flags)
1816 struct lpc32xx_request *req;
1817 struct lpc32xx_ep *ep;
1818 struct lpc32xx_udc *udc;
1819 unsigned long flags;
1822 req = container_of(_req, struct lpc32xx_request, req);
1823 ep = container_of(_ep, struct lpc32xx_ep, ep);
1825 if (!_req || !_req->complete || !_req->buf ||
1826 !list_empty(&req->queue))
1832 dev_dbg(udc->dev, "invalid ep\n");
1837 if ((!udc) || (!udc->driver) ||
1838 (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1839 dev_dbg(udc->dev, "invalid device\n");
1844 enum dma_data_direction direction;
1845 struct lpc32xx_usbd_dd_gad *dd;
1847 /* Map DMA pointer */
1849 direction = DMA_TO_DEVICE;
1851 direction = DMA_FROM_DEVICE;
1853 if (req->req.dma == 0) {
1854 req->req.dma = dma_map_single(
1855 ep->udc->gadget.dev.parent,
1856 req->req.buf, req->req.length, direction);
1859 dma_sync_single_for_device(
1860 ep->udc->gadget.dev.parent, req->req.dma,
1861 req->req.length, direction);
1865 /* For the request, build a list of DDs */
1866 dd = udc_dd_alloc(udc);
1868 /* Error allocating DD */
1871 req->dd_desc_ptr = dd;
1873 /* Setup the DMA descriptor */
1874 dd->dd_next_phy = dd->dd_next_v = 0;
1875 dd->dd_buffer_addr = req->req.dma;
1878 /* Special handling for ISO EPs */
1879 if (ep->eptype == EP_ISO_TYPE) {
1880 dd->dd_setup = DD_SETUP_ISO_EP |
1881 DD_SETUP_PACKETLEN(0) |
1882 DD_SETUP_DMALENBYTES(1);
1883 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1885 dd->iso_status[0] = req->req.length;
1887 dd->iso_status[0] = 0;
1889 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1890 DD_SETUP_DMALENBYTES(req->req.length);
1893 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1894 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1896 spin_lock_irqsave(&udc->lock, flags);
1898 _req->status = -EINPROGRESS;
1900 req->send_zlp = _req->zero;
1902 /* Kickstart empty queues */
1903 if (list_empty(&ep->queue)) {
1904 list_add_tail(&req->queue, &ep->queue);
1906 if (ep->hwep_num_base == 0) {
1907 /* Handle expected data direction */
1909 /* IN packet to host */
1910 udc->ep0state = DATA_IN;
1911 status = udc_ep0_in_req(udc);
1913 /* OUT packet from host */
1914 udc->ep0state = DATA_OUT;
1915 status = udc_ep0_out_req(udc);
1917 } else if (ep->is_in) {
1918 /* IN packet to host and kick off transfer */
1919 if (!ep->req_pending)
1920 udc_ep_in_req_dma(udc, ep);
1922 /* OUT packet from host and kick off list */
1923 if (!ep->req_pending)
1924 udc_ep_out_req_dma(udc, ep);
1926 list_add_tail(&req->queue, &ep->queue);
1928 spin_unlock_irqrestore(&udc->lock, flags);
1930 return (status < 0) ? status : 0;
1933 /* Must be called without lock */
1934 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1936 struct lpc32xx_ep *ep;
1937 struct lpc32xx_request *req;
1938 unsigned long flags;
1940 ep = container_of(_ep, struct lpc32xx_ep, ep);
1941 if (!_ep || ep->hwep_num_base == 0)
1944 spin_lock_irqsave(&ep->udc->lock, flags);
1946 /* make sure it's actually queued on this endpoint */
1947 list_for_each_entry(req, &ep->queue, queue) {
1948 if (&req->req == _req)
1951 if (&req->req != _req) {
1952 spin_unlock_irqrestore(&ep->udc->lock, flags);
1956 done(ep, req, -ECONNRESET);
1958 spin_unlock_irqrestore(&ep->udc->lock, flags);
1963 /* Must be called without lock */
1964 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1966 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1967 struct lpc32xx_udc *udc = ep->udc;
1968 unsigned long flags;
1970 if ((!ep) || (ep->hwep_num <= 1))
1973 /* Don't halt an IN EP */
1977 spin_lock_irqsave(&udc->lock, flags);
1981 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1982 DAT_WR_BYTE(EP_STAT_ST));
1986 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1990 spin_unlock_irqrestore(&udc->lock, flags);
1995 /* set the halt feature and ignores clear requests */
1996 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1998 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
2000 if (!_ep || !ep->udc)
2005 return usb_ep_set_halt(_ep);
2008 static const struct usb_ep_ops lpc32xx_ep_ops = {
2009 .enable = lpc32xx_ep_enable,
2010 .disable = lpc32xx_ep_disable,
2011 .alloc_request = lpc32xx_ep_alloc_request,
2012 .free_request = lpc32xx_ep_free_request,
2013 .queue = lpc32xx_ep_queue,
2014 .dequeue = lpc32xx_ep_dequeue,
2015 .set_halt = lpc32xx_ep_set_halt,
2016 .set_wedge = lpc32xx_ep_set_wedge,
2019 /* Send a ZLP on a non-0 IN EP */
2020 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2022 /* Clear EP status */
2023 udc_clearep_getsts(udc, ep->hwep_num);
2025 /* Send ZLP via FIFO mechanism */
2026 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
2030 * Handle EP completion for ZLP
2031 * This function will only be called when a delayed ZLP needs to be sent out
2032 * after a DMA transfer has filled both buffers.
2034 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2037 struct lpc32xx_request *req;
2039 if (ep->hwep_num <= 0)
2042 uda_clear_hwepint(udc, ep->hwep_num);
2044 /* If this interrupt isn't enabled, return now */
2045 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
2048 /* Get endpoint status */
2049 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2052 * This should never happen, but protect against writing to the
2055 if (epstatus & EP_SEL_F)
2059 udc_send_in_zlp(udc, ep);
2060 uda_disable_hwepint(udc, ep->hwep_num);
2064 /* If there isn't a request waiting, something went wrong */
2065 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2069 /* Start another request if ready */
2070 if (!list_empty(&ep->queue)) {
2072 udc_ep_in_req_dma(udc, ep);
2074 udc_ep_out_req_dma(udc, ep);
2076 ep->req_pending = 0;
2081 /* DMA end of transfer completion */
2082 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2084 u32 status, epstatus;
2085 struct lpc32xx_request *req;
2086 struct lpc32xx_usbd_dd_gad *dd;
2088 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2092 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2094 ep_err(ep, "DMA interrupt on no req!\n");
2097 dd = req->dd_desc_ptr;
2099 /* DMA descriptor should always be retired for this call */
2100 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2101 ep_warn(ep, "DMA descriptor did not retire\n");
2104 udc_ep_dma_disable(udc, ep->hwep_num);
2105 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2106 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2109 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2110 (1 << ep->hwep_num)) {
2111 writel((1 << ep->hwep_num),
2112 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2113 ep_err(ep, "AHB critical error!\n");
2114 ep->req_pending = 0;
2116 /* The error could have occurred on a packet of a multipacket
2117 * transfer, so recovering the transfer is not possible. Close
2118 * the request with an error */
2119 done(ep, req, -ECONNABORTED);
2123 /* Handle the current DD's status */
2124 status = dd->dd_status;
2125 switch (status & DD_STATUS_STS_MASK) {
2126 case DD_STATUS_STS_NS:
2127 /* DD not serviced? This shouldn't happen! */
2128 ep->req_pending = 0;
2129 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2132 done(ep, req, -ECONNABORTED);
2135 case DD_STATUS_STS_BS:
2136 /* Interrupt only fires on EOT - This shouldn't happen! */
2137 ep->req_pending = 0;
2138 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2140 done(ep, req, -ECONNABORTED);
2143 case DD_STATUS_STS_NC:
2144 case DD_STATUS_STS_DUR:
2145 /* Really just a short packet, not an underrun */
2146 /* This is a good status and what we expect */
2150 /* Data overrun, system error, or unknown */
2151 ep->req_pending = 0;
2152 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2154 done(ep, req, -ECONNABORTED);
2158 /* ISO endpoints are handled differently */
2159 if (ep->eptype == EP_ISO_TYPE) {
2161 req->req.actual = req->req.length;
2163 req->req.actual = dd->iso_status[0] & 0xFFFF;
2165 req->req.actual += DD_STATUS_CURDMACNT(status);
2167 /* Send a ZLP if necessary. This will be done for non-int
2168 * packets which have a size that is a divisor of MAXP */
2169 if (req->send_zlp) {
2171 * If at least 1 buffer is available, send the ZLP now.
2172 * Otherwise, the ZLP send needs to be deferred until a
2173 * buffer is available.
2175 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2176 udc_clearep_getsts(udc, ep->hwep_num);
2177 uda_enable_hwepint(udc, ep->hwep_num);
2178 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2180 /* Let the EP interrupt handle the ZLP */
2183 udc_send_in_zlp(udc, ep);
2186 /* Transfer request is complete */
2189 /* Start another request if ready */
2190 udc_clearep_getsts(udc, ep->hwep_num);
2191 if (!list_empty((&ep->queue))) {
2193 udc_ep_in_req_dma(udc, ep);
2195 udc_ep_out_req_dma(udc, ep);
2197 ep->req_pending = 0;
2203 * Endpoint 0 functions
2206 static void udc_handle_dev(struct lpc32xx_udc *udc)
2210 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2211 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2215 else if (tmp & DEV_CON_CH)
2216 uda_power_event(udc, (tmp & DEV_CON));
2217 else if (tmp & DEV_SUS_CH) {
2218 if (tmp & DEV_SUS) {
2221 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2223 /* Power down transceiver */
2225 schedule_work(&udc->pullup_job);
2226 uda_resm_susp_event(udc, 1);
2228 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2229 udc->driver && udc->vbus) {
2230 uda_resm_susp_event(udc, 0);
2231 /* Power up transceiver */
2233 schedule_work(&udc->pullup_job);
2238 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2240 struct lpc32xx_ep *ep;
2241 u32 ep0buff = 0, tmp;
2243 switch (reqtype & USB_RECIP_MASK) {
2244 case USB_RECIP_INTERFACE:
2245 break; /* Not supported */
2247 case USB_RECIP_DEVICE:
2248 ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
2249 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2250 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2253 case USB_RECIP_ENDPOINT:
2254 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2256 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2259 if (wIndex & USB_DIR_IN) {
2261 return -EOPNOTSUPP; /* Something's wrong */
2262 } else if (ep->is_in)
2263 return -EOPNOTSUPP; /* Not an IN endpoint */
2265 /* Get status of the endpoint */
2266 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2267 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2269 if (tmp & EP_SEL_ST)
2270 ep0buff = (1 << USB_ENDPOINT_HALT);
2280 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2285 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2287 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2288 struct usb_ctrlrequest ctrlpkt;
2290 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2292 /* Nuke previous transfers */
2295 /* Get setup packet */
2296 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2298 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2303 /* Native endianness */
2304 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2305 wValue = le16_to_cpu(ctrlpkt.wValue);
2306 wLength = le16_to_cpu(ctrlpkt.wLength);
2307 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2309 /* Set direction of EP0 */
2310 if (likely(reqtype & USB_DIR_IN))
2315 /* Handle SETUP packet */
2316 req = le16_to_cpu(ctrlpkt.bRequest);
2318 case USB_REQ_CLEAR_FEATURE:
2319 case USB_REQ_SET_FEATURE:
2321 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2322 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2323 goto stall; /* Nothing else handled */
2325 /* Tell board about event */
2326 if (req == USB_REQ_CLEAR_FEATURE)
2328 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2331 (1 << USB_DEVICE_REMOTE_WAKEUP);
2332 uda_remwkp_cgh(udc);
2335 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2336 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2337 if ((wValue != USB_ENDPOINT_HALT) ||
2338 (tmp >= NUM_ENDPOINTS))
2341 /* Find hardware endpoint from logical endpoint */
2347 if (req == USB_REQ_SET_FEATURE)
2348 udc_stall_hwep(udc, tmp);
2349 else if (!ep->wedge)
2350 udc_clrstall_hwep(udc, tmp);
2359 case USB_REQ_SET_ADDRESS:
2360 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2361 udc_set_address(udc, wValue);
2366 case USB_REQ_GET_STATUS:
2367 udc_get_status(udc, reqtype, wIndex);
2371 break; /* Let GadgetFS handle the descriptor instead */
2374 if (likely(udc->driver)) {
2375 /* device-2-host (IN) or no data setup command, process
2377 spin_unlock(&udc->lock);
2378 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2380 spin_lock(&udc->lock);
2381 if (req == USB_REQ_SET_CONFIGURATION) {
2382 /* Configuration is set after endpoints are realized */
2384 /* Set configuration */
2385 udc_set_device_configured(udc);
2387 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2388 DAT_WR_BYTE(AP_CLK |
2389 INAK_BI | INAK_II));
2391 /* Clear configuration */
2392 udc_set_device_unconfigured(udc);
2394 /* Disable NAK interrupts */
2395 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2396 DAT_WR_BYTE(AP_CLK));
2401 /* setup processing failed, force stall */
2403 "req %02x.%02x protocol STALL; stat %d\n",
2405 udc->ep0state = WAIT_FOR_SETUP;
2411 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2416 udc_stall_hwep(udc, EP_IN);
2420 udc_ep0_send_zlp(udc);
2424 /* IN endpoint 0 transfer */
2425 static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2427 struct lpc32xx_ep *ep0 = &udc->ep[0];
2430 /* Clear EP interrupt */
2431 epstatus = udc_clearep_getsts(udc, EP_IN);
2433 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2437 /* Stalled? Clear stall and reset buffers */
2438 if (epstatus & EP_SEL_ST) {
2439 udc_clrstall_hwep(udc, EP_IN);
2440 nuke(ep0, -ECONNABORTED);
2441 udc->ep0state = WAIT_FOR_SETUP;
2445 /* Is a buffer available? */
2446 if (!(epstatus & EP_SEL_F)) {
2447 /* Handle based on current state */
2448 if (udc->ep0state == DATA_IN)
2449 udc_ep0_in_req(udc);
2451 /* Unknown state for EP0 oe end of DATA IN phase */
2452 nuke(ep0, -ECONNABORTED);
2453 udc->ep0state = WAIT_FOR_SETUP;
2458 /* OUT endpoint 0 transfer */
2459 static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2461 struct lpc32xx_ep *ep0 = &udc->ep[0];
2464 /* Clear EP interrupt */
2465 epstatus = udc_clearep_getsts(udc, EP_OUT);
2468 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2473 if (epstatus & EP_SEL_ST) {
2474 udc_clrstall_hwep(udc, EP_OUT);
2475 nuke(ep0, -ECONNABORTED);
2476 udc->ep0state = WAIT_FOR_SETUP;
2480 /* A NAK may occur if a packet couldn't be received yet */
2481 if (epstatus & EP_SEL_EPN)
2483 /* Setup packet incoming? */
2484 if (epstatus & EP_SEL_STP) {
2486 udc->ep0state = WAIT_FOR_SETUP;
2489 /* Data available? */
2490 if (epstatus & EP_SEL_F)
2491 /* Handle based on current state */
2492 switch (udc->ep0state) {
2493 case WAIT_FOR_SETUP:
2494 udc_handle_ep0_setup(udc);
2498 udc_ep0_out_req(udc);
2502 /* Unknown state for EP0 */
2503 nuke(ep0, -ECONNABORTED);
2504 udc->ep0state = WAIT_FOR_SETUP;
2508 /* Must be called without lock */
2509 static int lpc32xx_get_frame(struct usb_gadget *gadget)
2512 unsigned long flags;
2513 struct lpc32xx_udc *udc = to_udc(gadget);
2518 spin_lock_irqsave(&udc->lock, flags);
2520 frame = (int) udc_get_current_frame(udc);
2522 spin_unlock_irqrestore(&udc->lock, flags);
2527 static int lpc32xx_wakeup(struct usb_gadget *gadget)
2532 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2534 struct lpc32xx_udc *udc = to_udc(gadget);
2536 /* Always self-powered */
2537 udc->selfpowered = (is_on != 0);
2543 * vbus is here! turn everything on that's ready
2544 * Must be called without lock
2546 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2548 unsigned long flags;
2549 struct lpc32xx_udc *udc = to_udc(gadget);
2551 spin_lock_irqsave(&udc->lock, flags);
2553 /* Doesn't need lock */
2555 udc_clk_set(udc, 1);
2557 pullup(udc, is_active);
2562 spin_unlock_irqrestore(&udc->lock, flags);
2564 * Wait for all the endpoints to disable,
2565 * before disabling clocks. Don't wait if
2566 * endpoints are not enabled.
2568 if (atomic_read(&udc->enabled_ep_cnt))
2569 wait_event_interruptible(udc->ep_disable_wait_queue,
2570 (atomic_read(&udc->enabled_ep_cnt) == 0));
2572 spin_lock_irqsave(&udc->lock, flags);
2574 udc_clk_set(udc, 0);
2577 spin_unlock_irqrestore(&udc->lock, flags);
2582 /* Can be called with or without lock */
2583 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2585 struct lpc32xx_udc *udc = to_udc(gadget);
2587 /* Doesn't need lock */
2593 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2594 static int lpc32xx_stop(struct usb_gadget *, struct usb_gadget_driver *);
2596 static const struct usb_gadget_ops lpc32xx_udc_ops = {
2597 .get_frame = lpc32xx_get_frame,
2598 .wakeup = lpc32xx_wakeup,
2599 .set_selfpowered = lpc32xx_set_selfpowered,
2600 .vbus_session = lpc32xx_vbus_session,
2601 .pullup = lpc32xx_pullup,
2602 .udc_start = lpc32xx_start,
2603 .udc_stop = lpc32xx_stop,
2606 static void nop_release(struct device *dev)
2608 /* nothing to free */
2611 static const struct lpc32xx_udc controller_template = {
2613 .ops = &lpc32xx_udc_ops,
2614 .name = driver_name,
2616 .init_name = "gadget",
2617 .release = nop_release,
2623 .ops = &lpc32xx_ep_ops,
2627 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2629 .eptype = EP_CTL_TYPE,
2634 .ops = &lpc32xx_ep_ops,
2638 .hwep_num = 0, /* 2 or 3, will be set later */
2640 .eptype = EP_INT_TYPE,
2645 .ops = &lpc32xx_ep_ops,
2649 .hwep_num = 0, /* 4 or 5, will be set later */
2651 .eptype = EP_BLK_TYPE,
2656 .ops = &lpc32xx_ep_ops,
2660 .hwep_num = 0, /* 6 or 7, will be set later */
2662 .eptype = EP_ISO_TYPE,
2667 .ops = &lpc32xx_ep_ops,
2671 .hwep_num = 0, /* 8 or 9, will be set later */
2673 .eptype = EP_INT_TYPE,
2678 .ops = &lpc32xx_ep_ops,
2681 .hwep_num_base = 10,
2682 .hwep_num = 0, /* 10 or 11, will be set later */
2684 .eptype = EP_BLK_TYPE,
2689 .ops = &lpc32xx_ep_ops,
2692 .hwep_num_base = 12,
2693 .hwep_num = 0, /* 12 or 13, will be set later */
2695 .eptype = EP_ISO_TYPE,
2700 .ops = &lpc32xx_ep_ops,
2703 .hwep_num_base = 14,
2706 .eptype = EP_INT_TYPE,
2711 .ops = &lpc32xx_ep_ops,
2714 .hwep_num_base = 16,
2717 .eptype = EP_BLK_TYPE,
2722 .ops = &lpc32xx_ep_ops,
2725 .hwep_num_base = 18,
2728 .eptype = EP_ISO_TYPE,
2733 .ops = &lpc32xx_ep_ops,
2736 .hwep_num_base = 20,
2739 .eptype = EP_INT_TYPE,
2743 .name = "ep11-bulk",
2744 .ops = &lpc32xx_ep_ops,
2747 .hwep_num_base = 22,
2750 .eptype = EP_BLK_TYPE,
2755 .ops = &lpc32xx_ep_ops,
2758 .hwep_num_base = 24,
2761 .eptype = EP_ISO_TYPE,
2766 .ops = &lpc32xx_ep_ops,
2769 .hwep_num_base = 26,
2772 .eptype = EP_INT_TYPE,
2776 .name = "ep14-bulk",
2777 .ops = &lpc32xx_ep_ops,
2780 .hwep_num_base = 28,
2783 .eptype = EP_BLK_TYPE,
2787 .name = "ep15-bulk",
2788 .ops = &lpc32xx_ep_ops,
2791 .hwep_num_base = 30,
2794 .eptype = EP_BLK_TYPE,
2798 /* ISO and status interrupts */
2799 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2802 struct lpc32xx_udc *udc = _udc;
2804 spin_lock(&udc->lock);
2806 /* Read the device status register */
2807 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2809 devstat &= ~USBD_EP_FAST;
2810 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2811 devstat = devstat & udc->enabled_devints;
2813 /* Device specific handling needed? */
2814 if (devstat & USBD_DEV_STAT)
2815 udc_handle_dev(udc);
2817 /* Start of frame? (devstat & FRAME_INT):
2818 * The frame interrupt isn't really needed for ISO support,
2819 * as the driver will queue the necessary packets */
2822 if (devstat & ERR_INT) {
2823 /* All types of errors, from cable removal during transfer to
2824 * misc protocol and bit errors. These are mostly for just info,
2825 * as the USB hardware will work around these. If these errors
2826 * happen alot, something is wrong. */
2827 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2828 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2829 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2832 spin_unlock(&udc->lock);
2838 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2841 struct lpc32xx_udc *udc = _udc;
2843 spin_lock(&udc->lock);
2845 /* Read the device status register */
2846 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2849 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2851 /* Special handling for EP0 */
2852 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2854 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2855 udc_handle_ep0_in(udc);
2857 /* Handle EP0 OUT */
2858 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2859 udc_handle_ep0_out(udc);
2863 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2866 /* Handle other EP interrupts */
2867 for (i = 1; i < NUM_ENDPOINTS; i++) {
2868 if (tmp & (1 << udc->ep[i].hwep_num))
2869 udc_handle_eps(udc, &udc->ep[i]);
2873 spin_unlock(&udc->lock);
2878 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2880 struct lpc32xx_udc *udc = _udc;
2885 spin_lock(&udc->lock);
2887 /* Handle EP DMA EOT interrupts */
2888 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2889 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2890 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2891 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2892 for (i = 1; i < NUM_ENDPOINTS; i++) {
2893 if (tmp & (1 << udc->ep[i].hwep_num))
2894 udc_handle_dma_ep(udc, &udc->ep[i]);
2897 spin_unlock(&udc->lock);
2904 * VBUS detection, pullup handler, and Gadget cable state notification
2907 static void vbus_work(struct work_struct *work)
2910 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2913 if (udc->enabled != 0) {
2914 /* Discharge VBUS real quick */
2915 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2916 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2918 /* Give VBUS some time (100mS) to discharge */
2921 /* Disable VBUS discharge resistor */
2922 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2923 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2926 /* Clear interrupt */
2927 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2928 ISP1301_I2C_INTERRUPT_LATCH |
2929 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2931 /* Get the VBUS status from the transceiver */
2932 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2933 ISP1301_I2C_INTERRUPT_SOURCE);
2935 /* VBUS on or off? */
2936 if (value & INT_SESS_VLD)
2942 if (udc->last_vbus != udc->vbus) {
2943 udc->last_vbus = udc->vbus;
2944 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2948 /* Re-enable after completion */
2949 enable_irq(udc->udp_irq[IRQ_USB_ATX]);
2952 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2954 struct lpc32xx_udc *udc = _udc;
2956 /* Defer handling of VBUS IRQ to work queue */
2957 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
2958 schedule_work(&udc->vbus_job);
2963 static int lpc32xx_start(struct usb_gadget *gadget,
2964 struct usb_gadget_driver *driver)
2966 struct lpc32xx_udc *udc = to_udc(gadget);
2969 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2970 dev_err(udc->dev, "bad parameter.\n");
2975 dev_err(udc->dev, "UDC already has a gadget driver\n");
2979 udc->driver = driver;
2980 udc->gadget.dev.driver = &driver->driver;
2981 udc->gadget.dev.of_node = udc->dev->of_node;
2983 udc->selfpowered = 1;
2986 /* Force VBUS process once to check for cable insertion */
2987 udc->last_vbus = udc->vbus = 0;
2988 schedule_work(&udc->vbus_job);
2990 /* Do not re-enable ATX IRQ (3) */
2991 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
2992 enable_irq(udc->udp_irq[i]);
2997 static int lpc32xx_stop(struct usb_gadget *gadget,
2998 struct usb_gadget_driver *driver)
3001 struct lpc32xx_udc *udc = to_udc(gadget);
3003 if (!driver || driver != udc->driver)
3006 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3007 disable_irq(udc->udp_irq[i]);
3010 spin_lock(&udc->lock);
3012 spin_unlock(&udc->lock);
3015 * Wait for all the endpoints to disable,
3016 * before disabling clocks. Don't wait if
3017 * endpoints are not enabled.
3019 if (atomic_read(&udc->enabled_ep_cnt))
3020 wait_event_interruptible(udc->ep_disable_wait_queue,
3021 (atomic_read(&udc->enabled_ep_cnt) == 0));
3023 spin_lock(&udc->lock);
3024 udc_clk_set(udc, 0);
3025 spin_unlock(&udc->lock);
3029 udc->gadget.dev.driver = NULL;
3035 static void lpc32xx_udc_shutdown(struct platform_device *dev)
3037 /* Force disconnect on reboot */
3038 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
3044 * Callbacks to be overridden by options passed via OF (TODO)
3047 static void lpc32xx_usbd_conn_chg(int conn)
3049 /* Do nothing, it might be nice to enable an LED
3050 * based on conn state being !0 */
3053 static void lpc32xx_usbd_susp_chg(int susp)
3055 /* Device suspend if susp != 0 */
3058 static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
3060 /* Enable or disable USB remote wakeup */
3063 struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
3065 .conn_chgb = &lpc32xx_usbd_conn_chg,
3066 .susp_chgb = &lpc32xx_usbd_susp_chg,
3067 .rmwk_chgb = &lpc32xx_rmwkup_chg,
3071 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3073 static int __init lpc32xx_udc_probe(struct platform_device *pdev)
3075 struct device *dev = &pdev->dev;
3076 struct lpc32xx_udc *udc;
3078 struct resource *res;
3079 dma_addr_t dma_handle;
3080 struct device_node *isp1301_node;
3082 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
3086 memcpy(udc, &controller_template, sizeof(*udc));
3087 for (i = 0; i <= 15; i++)
3088 udc->ep[i].udc = udc;
3089 udc->gadget.ep0 = &udc->ep[0].ep;
3091 /* init software state */
3092 udc->gadget.dev.parent = dev;
3094 udc->dev = &pdev->dev;
3097 if (pdev->dev.of_node) {
3098 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3101 isp1301_node = NULL;
3104 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3105 if (!udc->isp1301_i2c_client) {
3106 retval = -EPROBE_DEFER;
3110 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3111 udc->isp1301_i2c_client->addr);
3113 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3114 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3116 udc->board = &lpc32xx_usbddata;
3119 * Resources are mapped as follows:
3120 * IORESOURCE_MEM, base address and size of USB space
3121 * IORESOURCE_IRQ, USB device low priority interrupt number
3122 * IORESOURCE_IRQ, USB device high priority interrupt number
3123 * IORESOURCE_IRQ, USB device interrupt number
3124 * IORESOURCE_IRQ, USB transceiver interrupt number
3126 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3132 spin_lock_init(&udc->lock);
3135 for (i = 0; i < 4; i++) {
3136 udc->udp_irq[i] = platform_get_irq(pdev, i);
3137 if (udc->udp_irq[i] < 0) {
3139 "irq resource %d not available!\n", i);
3140 retval = udc->udp_irq[i];
3145 udc->io_p_start = res->start;
3146 udc->io_p_size = resource_size(res);
3147 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3148 dev_err(udc->dev, "someone's using UDC memory\n");
3150 goto request_mem_region_fail;
3153 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3154 if (!udc->udp_baseaddr) {
3156 dev_err(udc->dev, "IO map failure\n");
3160 /* Enable AHB slave USB clock, needed for further USB clock control */
3161 writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
3163 /* Get required clocks */
3164 udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
3165 if (IS_ERR(udc->usb_pll_clk)) {
3166 dev_err(udc->dev, "failed to acquire USB PLL\n");
3167 retval = PTR_ERR(udc->usb_pll_clk);
3170 udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
3171 if (IS_ERR(udc->usb_slv_clk)) {
3172 dev_err(udc->dev, "failed to acquire USB device clock\n");
3173 retval = PTR_ERR(udc->usb_slv_clk);
3174 goto usb_clk_get_fail;
3176 udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg");
3177 if (IS_ERR(udc->usb_otg_clk)) {
3178 dev_err(udc->dev, "failed to acquire USB otg clock\n");
3179 retval = PTR_ERR(udc->usb_otg_clk);
3180 goto usb_otg_clk_get_fail;
3183 /* Setup PLL clock to 48MHz */
3184 retval = clk_enable(udc->usb_pll_clk);
3186 dev_err(udc->dev, "failed to start USB PLL\n");
3187 goto pll_enable_fail;
3190 retval = clk_set_rate(udc->usb_pll_clk, 48000);
3192 dev_err(udc->dev, "failed to set USB clock rate\n");
3196 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
3198 /* Enable USB device clock */
3199 retval = clk_enable(udc->usb_slv_clk);
3201 dev_err(udc->dev, "failed to start USB device clock\n");
3202 goto usb_clk_enable_fail;
3205 /* Enable USB OTG clock */
3206 retval = clk_enable(udc->usb_otg_clk);
3208 dev_err(udc->dev, "failed to start USB otg clock\n");
3209 goto usb_otg_clk_enable_fail;
3212 /* Setup deferred workqueue data */
3213 udc->poweron = udc->pullup = 0;
3214 INIT_WORK(&udc->pullup_job, pullup_work);
3215 INIT_WORK(&udc->vbus_job, vbus_work);
3217 INIT_WORK(&udc->power_job, power_work);
3220 /* All clocks are now on */
3223 isp1301_udc_configure(udc);
3224 /* Allocate memory for the UDCA */
3225 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3227 (GFP_KERNEL | GFP_DMA));
3228 if (!udc->udca_v_base) {
3229 dev_err(udc->dev, "error getting UDCA region\n");
3233 udc->udca_p_base = dma_handle;
3234 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3235 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3237 /* Setup the DD DMA memory pool */
3238 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3239 sizeof(struct lpc32xx_usbd_dd_gad),
3241 if (!udc->dd_cache) {
3242 dev_err(udc->dev, "error getting DD DMA region\n");
3244 goto dma_alloc_fail;
3247 /* Clear USB peripheral and initialize gadget endpoints */
3251 retval = device_register(&udc->gadget.dev);
3253 dev_err(udc->dev, "Device registration failure\n");
3254 goto dev_register_fail;
3257 /* Request IRQs - low and high priority USB device IRQs are routed to
3258 * the same handler, while the DMA interrupt is routed elsewhere */
3259 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3262 dev_err(udc->dev, "LP request irq %d failed\n",
3263 udc->udp_irq[IRQ_USB_LP]);
3266 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3269 dev_err(udc->dev, "HP request irq %d failed\n",
3270 udc->udp_irq[IRQ_USB_HP]);
3274 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3275 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3277 dev_err(udc->dev, "DEV request irq %d failed\n",
3278 udc->udp_irq[IRQ_USB_DEVDMA]);
3282 /* The transceiver interrupt is used for VBUS detection and will
3283 kick off the VBUS handler function */
3284 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3287 dev_err(udc->dev, "VBUS request irq %d failed\n",
3288 udc->udp_irq[IRQ_USB_ATX]);
3292 /* Initialize wait queue */
3293 init_waitqueue_head(&udc->ep_disable_wait_queue);
3294 atomic_set(&udc->enabled_ep_cnt, 0);
3296 /* Keep all IRQs disabled until GadgetFS starts up */
3297 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3298 disable_irq(udc->udp_irq[i]);
3300 retval = usb_add_gadget_udc(dev, &udc->gadget);
3302 goto add_gadget_fail;
3304 dev_set_drvdata(dev, udc);
3305 device_init_wakeup(dev, 1);
3306 create_debug_file(udc);
3308 /* Disable clocks for now */
3309 udc_clk_set(udc, 0);
3311 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3315 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3317 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3319 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3321 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3323 device_unregister(&udc->gadget.dev);
3325 dma_pool_destroy(udc->dd_cache);
3327 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3328 udc->udca_v_base, udc->udca_p_base);
3330 clk_disable(udc->usb_otg_clk);
3331 usb_otg_clk_enable_fail:
3332 clk_disable(udc->usb_slv_clk);
3333 usb_clk_enable_fail:
3335 clk_disable(udc->usb_pll_clk);
3337 clk_put(udc->usb_slv_clk);
3338 usb_otg_clk_get_fail:
3339 clk_put(udc->usb_otg_clk);
3341 clk_put(udc->usb_pll_clk);
3343 iounmap(udc->udp_baseaddr);
3345 release_mem_region(udc->io_p_start, udc->io_p_size);
3346 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3347 request_mem_region_fail:
3355 static int __devexit lpc32xx_udc_remove(struct platform_device *pdev)
3357 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3359 usb_del_gadget_udc(&udc->gadget);
3363 udc_clk_set(udc, 1);
3367 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3369 device_init_wakeup(&pdev->dev, 0);
3370 remove_debug_file(udc);
3372 dma_pool_destroy(udc->dd_cache);
3373 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3374 udc->udca_v_base, udc->udca_p_base);
3375 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3376 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3377 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3379 device_unregister(&udc->gadget.dev);
3381 clk_disable(udc->usb_otg_clk);
3382 clk_put(udc->usb_otg_clk);
3383 clk_disable(udc->usb_slv_clk);
3384 clk_put(udc->usb_slv_clk);
3385 clk_disable(udc->usb_pll_clk);
3386 clk_put(udc->usb_pll_clk);
3387 iounmap(udc->udp_baseaddr);
3388 release_mem_region(udc->io_p_start, udc->io_p_size);
3395 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3397 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3400 /* Power down ISP */
3402 isp1301_set_powerstate(udc, 0);
3404 /* Disable clocking */
3405 udc_clk_set(udc, 0);
3407 /* Keep clock flag on, so we know to re-enable clocks
3411 /* Kill global USB clock */
3412 clk_disable(udc->usb_slv_clk);
3418 static int lpc32xx_udc_resume(struct platform_device *pdev)
3420 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3423 /* Enable global USB clock */
3424 clk_enable(udc->usb_slv_clk);
3426 /* Enable clocking */
3427 udc_clk_set(udc, 1);
3429 /* ISP back to normal power mode */
3431 isp1301_set_powerstate(udc, 1);
3437 #define lpc32xx_udc_suspend NULL
3438 #define lpc32xx_udc_resume NULL
3442 static struct of_device_id lpc32xx_udc_of_match[] = {
3443 { .compatible = "nxp,lpc3220-udc", },
3446 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3449 static struct platform_driver lpc32xx_udc_driver = {
3450 .remove = lpc32xx_udc_remove,
3451 .shutdown = lpc32xx_udc_shutdown,
3452 .suspend = lpc32xx_udc_suspend,
3453 .resume = lpc32xx_udc_resume,
3455 .name = (char *) driver_name,
3456 .owner = THIS_MODULE,
3457 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3461 static int __init udc_init_module(void)
3463 return platform_driver_probe(&lpc32xx_udc_driver, lpc32xx_udc_probe);
3465 module_init(udc_init_module);
3467 static void __exit udc_exit_module(void)
3469 platform_driver_unregister(&lpc32xx_udc_driver);
3471 module_exit(udc_exit_module);
3473 MODULE_DESCRIPTION("LPC32XX udc driver");
3474 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3475 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3476 MODULE_LICENSE("GPL");
3477 MODULE_ALIAS("platform:lpc32xx_udc");