drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  58
  59 /**
  60  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  61  * @dwc: pointer to our context structure
  62  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  63  *
  64  * Caller should take care of locking. This function will
  65  * return 0 on success or -EINVAL if wrong Test Selector
  66  * is passed
  67  */
  68 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  69 {
  70         u32             reg;
  71
  72         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  73         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  74
  75         switch (mode) {
  76         case TEST_J:
  77         case TEST_K:
  78         case TEST_SE0_NAK:
  79         case TEST_PACKET:
  80         case TEST_FORCE_EN:
  81                 reg |= mode << 1;
  82                 break;
  83         default:
  84                 return -EINVAL;
  85         }
  86
  87         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  88
  89         return 0;
  90 }
  91
  92 /**
  93  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  94  * @dwc: pointer to our context structure
  95  * @state: the state to put link into
  96  *
  97  * Caller should take care of locking. This function will
  98  * return 0 on success or -EINVAL.
  99  */
 100 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
 101 {
 102         int             retries = 100;
 103         u32             reg;
 104
 105         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 106         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 107
 108         /* set requested state */
 109         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 110         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 111
 112         /* wait for a change in DSTS */
 113         while (--retries) {
 114                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 115
 116                 /* in HS, means ON */
 117                 if (DWC3_DSTS_USBLNKST(reg) == state)
 118                         return 0;
 119
 120                 udelay(500);
 121         }
 122
 123         dev_vdbg(dwc->dev, "link state change request timed out\n");
 124
 125         return -ETIMEDOUT;
 126 }
 127
 128 /**
 129  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 130  * @dwc: pointer to our context structure
 131  *
 132  * This function will a best effort FIFO allocation in order
 133  * to improve FIFO usage and throughput, while still allowing
 134  * us to enable as many endpoints as possible.
 135  *
 136  * Keep in mind that this operation will be highly dependent
 137  * on the configured size for RAM1 - which contains TxFifo -,
 138  * the amount of endpoints enabled on coreConsultant tool, and
 139  * the width of the Master Bus.
 140  *
 141  * In the ideal world, we would always be able to satisfy the
 142  * following equation:
 143  *
 144  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 145  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 146  *
 147  * Unfortunately, due to many variables that's not always the case.
 148  */
 149 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 150 {
 151         int             last_fifo_depth = 0;
 152         int             ram1_depth;
 153         int             fifo_size;
 154         int             mdwidth;
 155         int             num;
 156
 157         if (!dwc->needs_fifo_resize)
 158                 return 0;
 159
 160         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 161         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 162
 163         /* MDWIDTH is represented in bits, we need it in bytes */
 164         mdwidth >>= 3;
 165
 166         /*
 167          * FIXME For now we will only allocate 1 wMaxPacketSize space
 168          * for each enabled endpoint, later patches will come to
 169          * improve this algorithm so that we better use the internal
 170          * FIFO space
 171          */
 172         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 173                 struct dwc3_ep  *dep = dwc->eps[num];
 174                 int             fifo_number = dep->number >> 1;
 175                 int             mult = 1;
 176                 int             tmp;
 177
 178                 if (!(dep->number & 1))
 179                         continue;
 180
 181                 if (!(dep->flags & DWC3_EP_ENABLED))
 182                         continue;
 183
 184                 if (usb_endpoint_xfer_bulk(dep->desc)
 185                                 || usb_endpoint_xfer_isoc(dep->desc))
 186                         mult = 3;
 187
 188                 /*
 189                  * REVISIT: the following assumes we will always have enough
 190                  * space available on the FIFO RAM for all possible use cases.
 191                  * Make sure that's true somehow and change FIFO allocation
 192                  * accordingly.
 193                  *
 194                  * If we have Bulk or Isochronous endpoints, we want
 195                  * them to be able to be very, very fast. So we're giving
 196                  * those endpoints a fifo_size which is enough for 3 full
 197                  * packets
 198                  */
 199                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 200                 tmp += mdwidth;
 201
 202                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 203
 204                 fifo_size |= (last_fifo_depth << 16);
 205
 206                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 207                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 208
 209                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 210                                 fifo_size);
 211
 212                 last_fifo_depth += (fifo_size & 0xffff);
 213         }
 214
 215         return 0;
 216 }
 217
 218 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
 219 {
 220         struct dwc3                     *dwc = req->dep->dwc;
 221
 222         if (req->request.length == 0) {
 223                 /* req->request.dma = dwc->setup_buf_addr; */
 224                 return;
 225         }
 226
 227         if (req->request.num_sgs) {
 228                 int     mapped;
 229
 230                 mapped = dma_map_sg(dwc->dev, req->request.sg,
 231                                 req->request.num_sgs,
 232                                 req->direction ? DMA_TO_DEVICE
 233                                 : DMA_FROM_DEVICE);
 234                 if (mapped < 0) {
 235                         dev_err(dwc->dev, "failed to map SGs\n");
 236                         return;
 237                 }
 238
 239                 req->request.num_mapped_sgs = mapped;
 240                 return;
 241         }
 242
 243         if (req->request.dma == DMA_ADDR_INVALID) {
 244                 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
 245                                 req->request.length, req->direction
 246                                 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 247                 req->mapped = true;
 248         }
 249 }
 250
 251 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
 252 {
 253         struct dwc3                     *dwc = req->dep->dwc;
 254
 255         if (req->request.length == 0) {
 256                 req->request.dma = DMA_ADDR_INVALID;
 257                 return;
 258         }
 259
 260         if (req->request.num_mapped_sgs) {
 261                 req->request.dma = DMA_ADDR_INVALID;
 262                 dma_unmap_sg(dwc->dev, req->request.sg,
 263                                 req->request.num_mapped_sgs,
 264                                 req->direction ? DMA_TO_DEVICE
 265                                 : DMA_FROM_DEVICE);
 266
 267                 req->request.num_mapped_sgs = 0;
 268                 return;
 269         }
 270
 271         if (req->mapped) {
 272                 dma_unmap_single(dwc->dev, req->request.dma,
 273                                 req->request.length, req->direction
 274                                 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 275                 req->mapped = 0;
 276                 req->request.dma = DMA_ADDR_INVALID;
 277         }
 278 }
 279
 280 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 281                 int status)
 282 {
 283         struct dwc3                     *dwc = dep->dwc;
 284
 285         if (req->queued) {
 286                 if (req->request.num_mapped_sgs)
 287                         dep->busy_slot += req->request.num_mapped_sgs;
 288                 else
 289                         dep->busy_slot++;
 290
 291                 /*
 292                  * Skip LINK TRB. We can't use req->trb and check for
 293                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
 294                  * completed (not the LINK TRB).
 295                  */
 296                 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 297                                 usb_endpoint_xfer_isoc(dep->desc))
 298                         dep->busy_slot++;
 299         }
 300         list_del(&req->list);
 301         req->trb = NULL;
 302
 303         if (req->request.status == -EINPROGRESS)
 304                 req->request.status = status;
 305
 306         dwc3_unmap_buffer_from_dma(req);
 307
 308         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 309                         req, dep->name, req->request.actual,
 310                         req->request.length, status);
 311
 312         spin_unlock(&dwc->lock);
 313         req->request.complete(&req->dep->endpoint, &req->request);
 314         spin_lock(&dwc->lock);
 315 }
 316
 317 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 318 {
 319         switch (cmd) {
 320         case DWC3_DEPCMD_DEPSTARTCFG:
 321                 return "Start New Configuration";
 322         case DWC3_DEPCMD_ENDTRANSFER:
 323                 return "End Transfer";
 324         case DWC3_DEPCMD_UPDATETRANSFER:
 325                 return "Update Transfer";
 326         case DWC3_DEPCMD_STARTTRANSFER:
 327                 return "Start Transfer";
 328         case DWC3_DEPCMD_CLEARSTALL:
 329                 return "Clear Stall";
 330         case DWC3_DEPCMD_SETSTALL:
 331                 return "Set Stall";
 332         case DWC3_DEPCMD_GETSEQNUMBER:
 333                 return "Get Data Sequence Number";
 334         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 335                 return "Set Endpoint Transfer Resource";
 336         case DWC3_DEPCMD_SETEPCONFIG:
 337                 return "Set Endpoint Configuration";
 338         default:
 339                 return "UNKNOWN command";
 340         }
 341 }
 342
 343 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 344                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 345 {
 346         struct dwc3_ep          *dep = dwc->eps[ep];
 347         u32                     timeout = 500;
 348         u32                     reg;
 349
 350         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 351                         dep->name,
 352                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 353                         params->param1, params->param2);
 354
 355         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 356         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 357         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 358
 359         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 360         do {
 361                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 362                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 363                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 364                                         DWC3_DEPCMD_STATUS(reg));
 365                         return 0;
 366                 }
 367
 368                 /*
 369                  * We can't sleep here, because it is also called from
 370                  * interrupt context.
 371                  */
 372                 timeout--;
 373                 if (!timeout)
 374                         return -ETIMEDOUT;
 375
 376                 udelay(1);
 377         } while (1);
 378 }
 379
 380 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 381                 struct dwc3_trb *trb)
 382 {
 383         u32             offset = (char *) trb - (char *) dep->trb_pool;
 384
 385         return dep->trb_pool_dma + offset;
 386 }
 387
 388 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 389 {
 390         struct dwc3             *dwc = dep->dwc;
 391
 392         if (dep->trb_pool)
 393                 return 0;
 394
 395         if (dep->number == 0 || dep->number == 1)
 396                 return 0;
 397
 398         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 399                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 400                         &dep->trb_pool_dma, GFP_KERNEL);
 401         if (!dep->trb_pool) {
 402                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 403                                 dep->name);
 404                 return -ENOMEM;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 411 {
 412         struct dwc3             *dwc = dep->dwc;
 413
 414         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 415                         dep->trb_pool, dep->trb_pool_dma);
 416
 417         dep->trb_pool = NULL;
 418         dep->trb_pool_dma = 0;
 419 }
 420
 421 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 422 {
 423         struct dwc3_gadget_ep_cmd_params params;
 424         u32                     cmd;
 425
 426         memset(&params, 0x00, sizeof(params));
 427
 428         if (dep->number != 1) {
 429                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 430                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 431                 if (dep->number > 1) {
 432                         if (dwc->start_config_issued)
 433                                 return 0;
 434                         dwc->start_config_issued = true;
 435                         cmd |= DWC3_DEPCMD_PARAM(2);
 436                 }
 437
 438                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 439         }
 440
 441         return 0;
 442 }
 443
 444 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 445                 const struct usb_endpoint_descriptor *desc,
 446                 const struct usb_ss_ep_comp_descriptor *comp_desc)
 447 {
 448         struct dwc3_gadget_ep_cmd_params params;
 449
 450         memset(&params, 0x00, sizeof(params));
 451
 452         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 453                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
 454                 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
 455
 456         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 457                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 458
 459         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 460                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 461                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 462                 dep->stream_capable = true;
 463         }
 464
 465         if (usb_endpoint_xfer_isoc(desc))
 466                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 467
 468         /*
 469          * We are doing 1:1 mapping for endpoints, meaning
 470          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 471          * so on. We consider the direction bit as part of the physical
 472          * endpoint number. So USB endpoint 0x81 is 0x03.
 473          */
 474         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 475
 476         /*
 477          * We must use the lower 16 TX FIFOs even though
 478          * HW might have more
 479          */
 480         if (dep->direction)
 481                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 482
 483         if (desc->bInterval) {
 484                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 485                 dep->interval = 1 << (desc->bInterval - 1);
 486         }
 487
 488         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 489                         DWC3_DEPCMD_SETEPCONFIG, &params);
 490 }
 491
 492 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 493 {
 494         struct dwc3_gadget_ep_cmd_params params;
 495
 496         memset(&params, 0x00, sizeof(params));
 497
 498         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 499
 500         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 501                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 502 }
 503
 504 /**
 505  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 506  * @dep: endpoint to be initialized
 507  * @desc: USB Endpoint Descriptor
 508  *
 509  * Caller should take care of locking
 510  */
 511 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 512                 const struct usb_endpoint_descriptor *desc,
 513                 const struct usb_ss_ep_comp_descriptor *comp_desc)
 514 {
 515         struct dwc3             *dwc = dep->dwc;
 516         u32                     reg;
 517         int                     ret = -ENOMEM;
 518
 519         if (!(dep->flags & DWC3_EP_ENABLED)) {
 520                 ret = dwc3_gadget_start_config(dwc, dep);
 521                 if (ret)
 522                         return ret;
 523         }
 524
 525         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
 526         if (ret)
 527                 return ret;
 528
 529         if (!(dep->flags & DWC3_EP_ENABLED)) {
 530                 struct dwc3_trb *trb_st_hw;
 531                 struct dwc3_trb *trb_link;
 532
 533                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 534                 if (ret)
 535                         return ret;
 536
 537                 dep->desc = desc;
 538                 dep->comp_desc = comp_desc;
 539                 dep->type = usb_endpoint_type(desc);
 540                 dep->flags |= DWC3_EP_ENABLED;
 541
 542                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 543                 reg |= DWC3_DALEPENA_EP(dep->number);
 544                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 545
 546                 if (!usb_endpoint_xfer_isoc(desc))
 547                         return 0;
 548
 549                 memset(&trb_link, 0, sizeof(trb_link));
 550
 551                 /* Link TRB for ISOC. The HWO but is never reset */
 552                 trb_st_hw = &dep->trb_pool[0];
 553
 554                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 555
 556                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 557                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 558                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 559                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 560         }
 561
 562         return 0;
 563 }
 564
 565 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 566 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 567 {
 568         struct dwc3_request             *req;
 569
 570         if (!list_empty(&dep->req_queued))
 571                 dwc3_stop_active_transfer(dwc, dep->number);
 572
 573         while (!list_empty(&dep->request_list)) {
 574                 req = next_request(&dep->request_list);
 575
 576                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 577         }
 578 }
 579
 580 /**
 581  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 582  * @dep: the endpoint to disable
 583  *
 584  * This function also removes requests which are currently processed ny the
 585  * hardware and those which are not yet scheduled.
 586  * Caller should take care of locking.
 587  */
 588 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 589 {
 590         struct dwc3             *dwc = dep->dwc;
 591         u32                     reg;
 592
 593         dwc3_remove_requests(dwc, dep);
 594
 595         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 596         reg &= ~DWC3_DALEPENA_EP(dep->number);
 597         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 598
 599         dep->stream_capable = false;
 600         dep->desc = NULL;
 601         dep->comp_desc = NULL;
 602         dep->type = 0;
 603         dep->flags = 0;
 604
 605         return 0;
 606 }
 607
 608 /* -------------------------------------------------------------------------- */
 609
 610 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 611                 const struct usb_endpoint_descriptor *desc)
 612 {
 613         return -EINVAL;
 614 }
 615
 616 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 617 {
 618         return -EINVAL;
 619 }
 620
 621 /* -------------------------------------------------------------------------- */
 622
 623 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 624                 const struct usb_endpoint_descriptor *desc)
 625 {
 626         struct dwc3_ep                  *dep;
 627         struct dwc3                     *dwc;
 628         unsigned long                   flags;
 629         int                             ret;
 630
 631         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 632                 pr_debug("dwc3: invalid parameters\n");
 633                 return -EINVAL;
 634         }
 635
 636         if (!desc->wMaxPacketSize) {
 637                 pr_debug("dwc3: missing wMaxPacketSize\n");
 638                 return -EINVAL;
 639         }
 640
 641         dep = to_dwc3_ep(ep);
 642         dwc = dep->dwc;
 643
 644         switch (usb_endpoint_type(desc)) {
 645         case USB_ENDPOINT_XFER_CONTROL:
 646                 strncat(dep->name, "-control", sizeof(dep->name));
 647                 break;
 648         case USB_ENDPOINT_XFER_ISOC:
 649                 strncat(dep->name, "-isoc", sizeof(dep->name));
 650                 break;
 651         case USB_ENDPOINT_XFER_BULK:
 652                 strncat(dep->name, "-bulk", sizeof(dep->name));
 653                 break;
 654         case USB_ENDPOINT_XFER_INT:
 655                 strncat(dep->name, "-int", sizeof(dep->name));
 656                 break;
 657         default:
 658                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 659         }
 660
 661         if (dep->flags & DWC3_EP_ENABLED) {
 662                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 663                                 dep->name);
 664                 return 0;
 665         }
 666
 667         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 668
 669         spin_lock_irqsave(&dwc->lock, flags);
 670         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
 671         spin_unlock_irqrestore(&dwc->lock, flags);
 672
 673         return ret;
 674 }
 675
 676 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 677 {
 678         struct dwc3_ep                  *dep;
 679         struct dwc3                     *dwc;
 680         unsigned long                   flags;
 681         int                             ret;
 682
 683         if (!ep) {
 684                 pr_debug("dwc3: invalid parameters\n");
 685                 return -EINVAL;
 686         }
 687
 688         dep = to_dwc3_ep(ep);
 689         dwc = dep->dwc;
 690
 691         if (!(dep->flags & DWC3_EP_ENABLED)) {
 692                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 693                                 dep->name);
 694                 return 0;
 695         }
 696
 697         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 698                         dep->number >> 1,
 699                         (dep->number & 1) ? "in" : "out");
 700
 701         spin_lock_irqsave(&dwc->lock, flags);
 702         ret = __dwc3_gadget_ep_disable(dep);
 703         spin_unlock_irqrestore(&dwc->lock, flags);
 704
 705         return ret;
 706 }
 707
 708 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 709         gfp_t gfp_flags)
 710 {
 711         struct dwc3_request             *req;
 712         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 713         struct dwc3                     *dwc = dep->dwc;
 714
 715         req = kzalloc(sizeof(*req), gfp_flags);
 716         if (!req) {
 717                 dev_err(dwc->dev, "not enough memory\n");
 718                 return NULL;
 719         }
 720
 721         req->epnum      = dep->number;
 722         req->dep        = dep;
 723         req->request.dma = DMA_ADDR_INVALID;
 724
 725         return &req->request;
 726 }
 727
 728 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 729                 struct usb_request *request)
 730 {
 731         struct dwc3_request             *req = to_dwc3_request(request);
 732
 733         kfree(req);
 734 }
 735
 736 /**
 737  * dwc3_prepare_one_trb - setup one TRB from one request
 738  * @dep: endpoint for which this request is prepared
 739  * @req: dwc3_request pointer
 740  */
 741 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 742                 struct dwc3_request *req, dma_addr_t dma,
 743                 unsigned length, unsigned last, unsigned chain)
 744 {
 745         struct dwc3             *dwc = dep->dwc;
 746         struct dwc3_trb         *trb;
 747
 748         unsigned int            cur_slot;
 749
 750         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 751                         dep->name, req, (unsigned long long) dma,
 752                         length, last ? " last" : "",
 753                         chain ? " chain" : "");
 754
 755         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 756         cur_slot = dep->free_slot;
 757         dep->free_slot++;
 758
 759         /* Skip the LINK-TRB on ISOC */
 760         if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 761                         usb_endpoint_xfer_isoc(dep->desc))
 762                 return;
 763
 764         if (!req->trb) {
 765                 dwc3_gadget_move_request_queued(req);
 766                 req->trb = trb;
 767                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 768         }
 769
 770         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 771         trb->bpl = lower_32_bits(dma);
 772         trb->bph = upper_32_bits(dma);
 773
 774         switch (usb_endpoint_type(dep->desc)) {
 775         case USB_ENDPOINT_XFER_CONTROL:
 776                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 777                 break;
 778
 779         case USB_ENDPOINT_XFER_ISOC:
 780                 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 781
 782                 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
 783                 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
 784                         trb->ctrl |= DWC3_TRB_CTRL_IOC;
 785                 break;
 786
 787         case USB_ENDPOINT_XFER_BULK:
 788         case USB_ENDPOINT_XFER_INT:
 789                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 790                 break;
 791         default:
 792                 /*
 793                  * This is only possible with faulty memory because we
 794                  * checked it already :)
 795                  */
 796                 BUG();
 797         }
 798
 799         if (usb_endpoint_xfer_isoc(dep->desc)) {
 800                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 801                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 802         } else {
 803                 if (chain)
 804                         trb->ctrl |= DWC3_TRB_CTRL_CHN;
 805
 806                 if (last)
 807                         trb->ctrl |= DWC3_TRB_CTRL_LST;
 808         }
 809
 810         if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
 811                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 812
 813         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 814 }
 815
 816 /*
 817  * dwc3_prepare_trbs - setup TRBs from requests
 818  * @dep: endpoint for which requests are being prepared
 819  * @starting: true if the endpoint is idle and no requests are queued.
 820  *
 821  * The functions goes through the requests list and setups TRBs for the
 822  * transfers. The functions returns once there are not more TRBs available or
 823  * it run out of requests.
 824  */
 825 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 826 {
 827         struct dwc3_request     *req, *n;
 828         u32                     trbs_left;
 829         unsigned int            last_one = 0;
 830
 831         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 832
 833         /* the first request must not be queued */
 834         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 835
 836         /*
 837          * if busy & slot are equal than it is either full or empty. If we are
 838          * starting to proceed requests then we are empty. Otherwise we ar
 839          * full and don't do anything
 840          */
 841         if (!trbs_left) {
 842                 if (!starting)
 843                         return;
 844                 trbs_left = DWC3_TRB_NUM;
 845                 /*
 846                  * In case we start from scratch, we queue the ISOC requests
 847                  * starting from slot 1. This is done because we use ring
 848                  * buffer and have no LST bit to stop us. Instead, we place
 849                  * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
 850                  * after the first request so we start at slot 1 and have
 851                  * 7 requests proceed before we hit the first IOC.
 852                  * Other transfer types don't use the ring buffer and are
 853                  * processed from the first TRB until the last one. Since we
 854                  * don't wrap around we have to start at the beginning.
 855                  */
 856                 if (usb_endpoint_xfer_isoc(dep->desc)) {
 857                         dep->busy_slot = 1;
 858                         dep->free_slot = 1;
 859                 } else {
 860                         dep->busy_slot = 0;
 861                         dep->free_slot = 0;
 862                 }
 863         }
 864
 865         /* The last TRB is a link TRB, not used for xfer */
 866         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
 867                 return;
 868
 869         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 870                 unsigned        length;
 871                 dma_addr_t      dma;
 872
 873                 if (req->request.num_mapped_sgs > 0) {
 874                         struct usb_request *request = &req->request;
 875                         struct scatterlist *sg = request->sg;
 876                         struct scatterlist *s;
 877                         int             i;
 878
 879                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 880                                 unsigned chain = true;
 881
 882                                 length = sg_dma_len(s);
 883                                 dma = sg_dma_address(s);
 884
 885                                 if (i == (request->num_mapped_sgs - 1)
 886                                                 || sg_is_last(s)) {
 887                                         last_one = true;
 888                                         chain = false;
 889                                 }
 890
 891                                 trbs_left--;
 892                                 if (!trbs_left)
 893                                         last_one = true;
 894
 895                                 if (last_one)
 896                                         chain = false;
 897
 898                                 dwc3_prepare_one_trb(dep, req, dma, length,
 899                                                 last_one, chain);
 900
 901                                 if (last_one)
 902                                         break;
 903                         }
 904                 } else {
 905                         dma = req->request.dma;
 906                         length = req->request.length;
 907                         trbs_left--;
 908
 909                         if (!trbs_left)
 910                                 last_one = 1;
 911
 912                         /* Is this the last request? */
 913                         if (list_is_last(&req->list, &dep->request_list))
 914                                 last_one = 1;
 915
 916                         dwc3_prepare_one_trb(dep, req, dma, length,
 917                                         last_one, false);
 918
 919                         if (last_one)
 920                                 break;
 921                 }
 922         }
 923 }
 924
 925 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 926                 int start_new)
 927 {
 928         struct dwc3_gadget_ep_cmd_params params;
 929         struct dwc3_request             *req;
 930         struct dwc3                     *dwc = dep->dwc;
 931         int                             ret;
 932         u32                             cmd;
 933
 934         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 935                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 936                 return -EBUSY;
 937         }
 938         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 939
 940         /*
 941          * If we are getting here after a short-out-packet we don't enqueue any
 942          * new requests as we try to set the IOC bit only on the last request.
 943          */
 944         if (start_new) {
 945                 if (list_empty(&dep->req_queued))
 946                         dwc3_prepare_trbs(dep, start_new);
 947
 948                 /* req points to the first request which will be sent */
 949                 req = next_request(&dep->req_queued);
 950         } else {
 951                 dwc3_prepare_trbs(dep, start_new);
 952
 953                 /*
 954                  * req points to the first request where HWO changed
 955                  * from 0 to 1
 956                  */
 957                 req = next_request(&dep->req_queued);
 958         }
 959         if (!req) {
 960                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 961                 return 0;
 962         }
 963
 964         memset(&params, 0, sizeof(params));
 965         params.param0 = upper_32_bits(req->trb_dma);
 966         params.param1 = lower_32_bits(req->trb_dma);
 967
 968         if (start_new)
 969                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 970         else
 971                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 972
 973         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 974         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 975         if (ret < 0) {
 976                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 977
 978                 /*
 979                  * FIXME we need to iterate over the list of requests
 980                  * here and stop, unmap, free and del each of the linked
 981                  * requests instead of we do now.
 982                  */
 983                 dwc3_unmap_buffer_from_dma(req);
 984                 list_del(&req->list);
 985                 return ret;
 986         }
 987
 988         dep->flags |= DWC3_EP_BUSY;
 989         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 990                         dep->number);
 991
 992         WARN_ON_ONCE(!dep->res_trans_idx);
 993
 994         return 0;
 995 }
 996
 997 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 998 {
 999         req->request.actual     = 0;
1000         req->request.status     = -EINPROGRESS;
1001         req->direction          = dep->direction;
1002         req->epnum              = dep->number;
1003
1004         /*
1005          * We only add to our list of requests now and
1006          * start consuming the list once we get XferNotReady
1007          * IRQ.
1008          *
1009          * That way, we avoid doing anything that we don't need
1010          * to do now and defer it until the point we receive a
1011          * particular token from the Host side.
1012          *
1013          * This will also avoid Host cancelling URBs due to too
1014          * many NACKs.
1015          */
1016         dwc3_map_buffer_to_dma(req);
1017         list_add_tail(&req->list, &dep->request_list);
1018
1019         /*
1020          * There is one special case: XferNotReady with
1021          * empty list of requests. We need to kick the
1022          * transfer here in that situation, otherwise
1023          * we will be NAKing forever.
1024          *
1025          * If we get XferNotReady before gadget driver
1026          * has a chance to queue a request, we will ACK
1027          * the IRQ but won't be able to receive the data
1028          * until the next request is queued. The following
1029          * code is handling exactly that.
1030          */
1031         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1032                 int ret;
1033                 int start_trans;
1034
1035                 start_trans = 1;
1036                 if (usb_endpoint_xfer_isoc(dep->desc) &&
1037                                 dep->flags & DWC3_EP_BUSY)
1038                         start_trans = 0;
1039
1040                 ret =  __dwc3_gadget_kick_transfer(dep, 0, start_trans);
1041                 if (ret && ret != -EBUSY) {
1042                         struct dwc3     *dwc = dep->dwc;
1043
1044                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1045                                         dep->name);
1046                 }
1047         };
1048
1049         return 0;
1050 }
1051
1052 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1053         gfp_t gfp_flags)
1054 {
1055         struct dwc3_request             *req = to_dwc3_request(request);
1056         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1057         struct dwc3                     *dwc = dep->dwc;
1058
1059         unsigned long                   flags;
1060
1061         int                             ret;
1062
1063         if (!dep->desc) {
1064                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1065                                 request, ep->name);
1066                 return -ESHUTDOWN;
1067         }
1068
1069         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1070                         request, ep->name, request->length);
1071
1072         spin_lock_irqsave(&dwc->lock, flags);
1073         ret = __dwc3_gadget_ep_queue(dep, req);
1074         spin_unlock_irqrestore(&dwc->lock, flags);
1075
1076         return ret;
1077 }
1078
1079 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1080                 struct usb_request *request)
1081 {
1082         struct dwc3_request             *req = to_dwc3_request(request);
1083         struct dwc3_request             *r = NULL;
1084
1085         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1086         struct dwc3                     *dwc = dep->dwc;
1087
1088         unsigned long                   flags;
1089         int                             ret = 0;
1090
1091         spin_lock_irqsave(&dwc->lock, flags);
1092
1093         list_for_each_entry(r, &dep->request_list, list) {
1094                 if (r == req)
1095                         break;
1096         }
1097
1098         if (r != req) {
1099                 list_for_each_entry(r, &dep->req_queued, list) {
1100                         if (r == req)
1101                                 break;
1102                 }
1103                 if (r == req) {
1104                         /* wait until it is processed */
1105                         dwc3_stop_active_transfer(dwc, dep->number);
1106                         goto out0;
1107                 }
1108                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1109                                 request, ep->name);
1110                 ret = -EINVAL;
1111                 goto out0;
1112         }
1113
1114         /* giveback the request */
1115         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1116
1117 out0:
1118         spin_unlock_irqrestore(&dwc->lock, flags);
1119
1120         return ret;
1121 }
1122
1123 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1124 {
1125         struct dwc3_gadget_ep_cmd_params        params;
1126         struct dwc3                             *dwc = dep->dwc;
1127         int                                     ret;
1128
1129         memset(&params, 0x00, sizeof(params));
1130
1131         if (value) {
1132                 if (dep->number == 0 || dep->number == 1) {
1133                         /*
1134                          * Whenever EP0 is stalled, we will restart
1135                          * the state machine, thus moving back to
1136                          * Setup Phase
1137                          */
1138                         dwc->ep0state = EP0_SETUP_PHASE;
1139                 }
1140
1141                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1142                         DWC3_DEPCMD_SETSTALL, &params);
1143                 if (ret)
1144                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1145                                         value ? "set" : "clear",
1146                                         dep->name);
1147                 else
1148                         dep->flags |= DWC3_EP_STALL;
1149         } else {
1150                 if (dep->flags & DWC3_EP_WEDGE)
1151                         return 0;
1152
1153                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1154                         DWC3_DEPCMD_CLEARSTALL, &params);
1155                 if (ret)
1156                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1157                                         value ? "set" : "clear",
1158                                         dep->name);
1159                 else
1160                         dep->flags &= ~DWC3_EP_STALL;
1161         }
1162
1163         return ret;
1164 }
1165
1166 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1167 {
1168         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1169         struct dwc3                     *dwc = dep->dwc;
1170
1171         unsigned long                   flags;
1172
1173         int                             ret;
1174
1175         spin_lock_irqsave(&dwc->lock, flags);
1176
1177         if (usb_endpoint_xfer_isoc(dep->desc)) {
1178                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1179                 ret = -EINVAL;
1180                 goto out;
1181         }
1182
1183         ret = __dwc3_gadget_ep_set_halt(dep, value);
1184 out:
1185         spin_unlock_irqrestore(&dwc->lock, flags);
1186
1187         return ret;
1188 }
1189
1190 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1191 {
1192         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1193
1194         dep->flags |= DWC3_EP_WEDGE;
1195
1196         return dwc3_gadget_ep_set_halt(ep, 1);
1197 }
1198
1199 /* -------------------------------------------------------------------------- */
1200
1201 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1202         .bLength        = USB_DT_ENDPOINT_SIZE,
1203         .bDescriptorType = USB_DT_ENDPOINT,
1204         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1205 };
1206
1207 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1208         .enable         = dwc3_gadget_ep0_enable,
1209         .disable        = dwc3_gadget_ep0_disable,
1210         .alloc_request  = dwc3_gadget_ep_alloc_request,
1211         .free_request   = dwc3_gadget_ep_free_request,
1212         .queue          = dwc3_gadget_ep0_queue,
1213         .dequeue        = dwc3_gadget_ep_dequeue,
1214         .set_halt       = dwc3_gadget_ep_set_halt,
1215         .set_wedge      = dwc3_gadget_ep_set_wedge,
1216 };
1217
1218 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1219         .enable         = dwc3_gadget_ep_enable,
1220         .disable        = dwc3_gadget_ep_disable,
1221         .alloc_request  = dwc3_gadget_ep_alloc_request,
1222         .free_request   = dwc3_gadget_ep_free_request,
1223         .queue          = dwc3_gadget_ep_queue,
1224         .dequeue        = dwc3_gadget_ep_dequeue,
1225         .set_halt       = dwc3_gadget_ep_set_halt,
1226         .set_wedge      = dwc3_gadget_ep_set_wedge,
1227 };
1228
1229 /* -------------------------------------------------------------------------- */
1230
1231 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1232 {
1233         struct dwc3             *dwc = gadget_to_dwc(g);
1234         u32                     reg;
1235
1236         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1237         return DWC3_DSTS_SOFFN(reg);
1238 }
1239
1240 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1241 {
1242         struct dwc3             *dwc = gadget_to_dwc(g);
1243
1244         unsigned long           timeout;
1245         unsigned long           flags;
1246
1247         u32                     reg;
1248
1249         int                     ret = 0;
1250
1251         u8                      link_state;
1252         u8                      speed;
1253
1254         spin_lock_irqsave(&dwc->lock, flags);
1255
1256         /*
1257          * According to the Databook Remote wakeup request should
1258          * be issued only when the device is in early suspend state.
1259          *
1260          * We can check that via USB Link State bits in DSTS register.
1261          */
1262         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1263
1264         speed = reg & DWC3_DSTS_CONNECTSPD;
1265         if (speed == DWC3_DSTS_SUPERSPEED) {
1266                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1267                 ret = -EINVAL;
1268                 goto out;
1269         }
1270
1271         link_state = DWC3_DSTS_USBLNKST(reg);
1272
1273         switch (link_state) {
1274         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1275         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1276                 break;
1277         default:
1278                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1279                                 link_state);
1280                 ret = -EINVAL;
1281                 goto out;
1282         }
1283
1284         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1285         if (ret < 0) {
1286                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1287                 goto out;
1288         }
1289
1290         /* write zeroes to Link Change Request */
1291         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1292         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1293
1294         /* pool until Link State change to ON */
1295         timeout = jiffies + msecs_to_jiffies(100);
1296
1297         while (!(time_after(jiffies, timeout))) {
1298                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1299
1300                 /* in HS, means ON */
1301                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1302                         break;
1303         }
1304
1305         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1306                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1307                 ret = -EINVAL;
1308         }
1309
1310 out:
1311         spin_unlock_irqrestore(&dwc->lock, flags);
1312
1313         return ret;
1314 }
1315
1316 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1317                 int is_selfpowered)
1318 {
1319         struct dwc3             *dwc = gadget_to_dwc(g);
1320
1321         dwc->is_selfpowered = !!is_selfpowered;
1322
1323         return 0;
1324 }
1325
1326 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1327 {
1328         u32                     reg;
1329         u32                     timeout = 500;
1330
1331         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1332         if (is_on) {
1333                 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1334                 reg |= (DWC3_DCTL_RUN_STOP
1335                                 | DWC3_DCTL_TRGTULST_RX_DET);
1336         } else {
1337                 reg &= ~DWC3_DCTL_RUN_STOP;
1338         }
1339
1340         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1341
1342         do {
1343                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1344                 if (is_on) {
1345                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1346                                 break;
1347                 } else {
1348                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1349                                 break;
1350                 }
1351                 timeout--;
1352                 if (!timeout)
1353                         break;
1354                 udelay(1);
1355         } while (1);
1356
1357         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1358                         dwc->gadget_driver
1359                         ? dwc->gadget_driver->function : "no-function",
1360                         is_on ? "connect" : "disconnect");
1361 }
1362
1363 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1364 {
1365         struct dwc3             *dwc = gadget_to_dwc(g);
1366         unsigned long           flags;
1367
1368         is_on = !!is_on;
1369
1370         spin_lock_irqsave(&dwc->lock, flags);
1371         dwc3_gadget_run_stop(dwc, is_on);
1372         spin_unlock_irqrestore(&dwc->lock, flags);
1373
1374         return 0;
1375 }
1376
1377 static int dwc3_gadget_start(struct usb_gadget *g,
1378                 struct usb_gadget_driver *driver)
1379 {
1380         struct dwc3             *dwc = gadget_to_dwc(g);
1381         struct dwc3_ep          *dep;
1382         unsigned long           flags;
1383         int                     ret = 0;
1384         u32                     reg;
1385
1386         spin_lock_irqsave(&dwc->lock, flags);
1387
1388         if (dwc->gadget_driver) {
1389                 dev_err(dwc->dev, "%s is already bound to %s\n",
1390                                 dwc->gadget.name,
1391                                 dwc->gadget_driver->driver.name);
1392                 ret = -EBUSY;
1393                 goto err0;
1394         }
1395
1396         dwc->gadget_driver      = driver;
1397         dwc->gadget.dev.driver  = &driver->driver;
1398
1399         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1400         reg &= ~(DWC3_DCFG_SPEED_MASK);
1401         reg |= dwc->maximum_speed;
1402         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1403
1404         dwc->start_config_issued = false;
1405
1406         /* Start with SuperSpeed Default */
1407         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1408
1409         dep = dwc->eps[0];
1410         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1411         if (ret) {
1412                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1413                 goto err0;
1414         }
1415
1416         dep = dwc->eps[1];
1417         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1418         if (ret) {
1419                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1420                 goto err1;
1421         }
1422
1423         /* begin to receive SETUP packets */
1424         dwc->ep0state = EP0_SETUP_PHASE;
1425         dwc3_ep0_out_start(dwc);
1426
1427         spin_unlock_irqrestore(&dwc->lock, flags);
1428
1429         return 0;
1430
1431 err1:
1432         __dwc3_gadget_ep_disable(dwc->eps[0]);
1433
1434 err0:
1435         spin_unlock_irqrestore(&dwc->lock, flags);
1436
1437         return ret;
1438 }
1439
1440 static int dwc3_gadget_stop(struct usb_gadget *g,
1441                 struct usb_gadget_driver *driver)
1442 {
1443         struct dwc3             *dwc = gadget_to_dwc(g);
1444         unsigned long           flags;
1445
1446         spin_lock_irqsave(&dwc->lock, flags);
1447
1448         __dwc3_gadget_ep_disable(dwc->eps[0]);
1449         __dwc3_gadget_ep_disable(dwc->eps[1]);
1450
1451         dwc->gadget_driver      = NULL;
1452         dwc->gadget.dev.driver  = NULL;
1453
1454         spin_unlock_irqrestore(&dwc->lock, flags);
1455
1456         return 0;
1457 }
1458 static const struct usb_gadget_ops dwc3_gadget_ops = {
1459         .get_frame              = dwc3_gadget_get_frame,
1460         .wakeup                 = dwc3_gadget_wakeup,
1461         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1462         .pullup                 = dwc3_gadget_pullup,
1463         .udc_start              = dwc3_gadget_start,
1464         .udc_stop               = dwc3_gadget_stop,
1465 };
1466
1467 /* -------------------------------------------------------------------------- */
1468
1469 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1470 {
1471         struct dwc3_ep                  *dep;
1472         u8                              epnum;
1473
1474         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1475
1476         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1477                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1478                 if (!dep) {
1479                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1480                                         epnum);
1481                         return -ENOMEM;
1482                 }
1483
1484                 dep->dwc = dwc;
1485                 dep->number = epnum;
1486                 dwc->eps[epnum] = dep;
1487
1488                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1489                                 (epnum & 1) ? "in" : "out");
1490                 dep->endpoint.name = dep->name;
1491                 dep->direction = (epnum & 1);
1492
1493                 if (epnum == 0 || epnum == 1) {
1494                         dep->endpoint.maxpacket = 512;
1495                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1496                         if (!epnum)
1497                                 dwc->gadget.ep0 = &dep->endpoint;
1498                 } else {
1499                         int             ret;
1500
1501                         dep->endpoint.maxpacket = 1024;
1502                         dep->endpoint.max_streams = 15;
1503                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1504                         list_add_tail(&dep->endpoint.ep_list,
1505                                         &dwc->gadget.ep_list);
1506
1507                         ret = dwc3_alloc_trb_pool(dep);
1508                         if (ret)
1509                                 return ret;
1510                 }
1511
1512                 INIT_LIST_HEAD(&dep->request_list);
1513                 INIT_LIST_HEAD(&dep->req_queued);
1514         }
1515
1516         return 0;
1517 }
1518
1519 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1520 {
1521         struct dwc3_ep                  *dep;
1522         u8                              epnum;
1523
1524         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1525                 dep = dwc->eps[epnum];
1526                 dwc3_free_trb_pool(dep);
1527
1528                 if (epnum != 0 && epnum != 1)
1529                         list_del(&dep->endpoint.ep_list);
1530
1531                 kfree(dep);
1532         }
1533 }
1534
1535 static void dwc3_gadget_release(struct device *dev)
1536 {
1537         dev_dbg(dev, "%s\n", __func__);
1538 }
1539
1540 /* -------------------------------------------------------------------------- */
1541 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1542                 const struct dwc3_event_depevt *event, int status)
1543 {
1544         struct dwc3_request     *req;
1545         struct dwc3_trb         *trb;
1546         unsigned int            count;
1547         unsigned int            s_pkt = 0;
1548
1549         do {
1550                 req = next_request(&dep->req_queued);
1551                 if (!req) {
1552                         WARN_ON_ONCE(1);
1553                         return 1;
1554                 }
1555
1556                 trb = req->trb;
1557
1558                 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1559                         /*
1560                          * We continue despite the error. There is not much we
1561                          * can do. If we don't clean in up we loop for ever. If
1562                          * we skip the TRB than it gets overwritten reused after
1563                          * a while since we use them in a ring buffer. a BUG()
1564                          * would help. Lets hope that if this occures, someone
1565                          * fixes the root cause instead of looking away :)
1566                          */
1567                         dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1568                                         dep->name, req->trb);
1569                 count = trb->size & DWC3_TRB_SIZE_MASK;
1570
1571                 if (dep->direction) {
1572                         if (count) {
1573                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1574                                                 dep->name);
1575                                 status = -ECONNRESET;
1576                         }
1577                 } else {
1578                         if (count && (event->status & DEPEVT_STATUS_SHORT))
1579                                 s_pkt = 1;
1580                 }
1581
1582                 /*
1583                  * We assume here we will always receive the entire data block
1584                  * which we should receive. Meaning, if we program RX to
1585                  * receive 4K but we receive only 2K, we assume that's all we
1586                  * should receive and we simply bounce the request back to the
1587                  * gadget driver for further processing.
1588                  */
1589                 req->request.actual += req->request.length - count;
1590                 dwc3_gadget_giveback(dep, req, status);
1591                 if (s_pkt)
1592                         break;
1593                 if ((event->status & DEPEVT_STATUS_LST) &&
1594                                 (trb->ctrl & DWC3_TRB_CTRL_LST))
1595                         break;
1596                 if ((event->status & DEPEVT_STATUS_IOC) &&
1597                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1598                         break;
1599         } while (1);
1600
1601         if ((event->status & DEPEVT_STATUS_IOC) &&
1602                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1603                 return 0;
1604         return 1;
1605 }
1606
1607 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1608                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1609                 int start_new)
1610 {
1611         unsigned                status = 0;
1612         int                     clean_busy;
1613
1614         if (event->status & DEPEVT_STATUS_BUSERR)
1615                 status = -ECONNRESET;
1616
1617         clean_busy =  dwc3_cleanup_done_reqs(dwc, dep, event, status);
1618         if (clean_busy) {
1619                 dep->flags &= ~DWC3_EP_BUSY;
1620                 dep->res_trans_idx = 0;
1621         }
1622
1623         /*
1624          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1625          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1626          */
1627         if (dwc->revision < DWC3_REVISION_183A) {
1628                 u32             reg;
1629                 int             i;
1630
1631                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1632                         struct dwc3_ep  *dep = dwc->eps[i];
1633
1634                         if (!(dep->flags & DWC3_EP_ENABLED))
1635                                 continue;
1636
1637                         if (!list_empty(&dep->req_queued))
1638                                 return;
1639                 }
1640
1641                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1642                 reg |= dwc->u1u2;
1643                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1644
1645                 dwc->u1u2 = 0;
1646         }
1647 }
1648
1649 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1650                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1651 {
1652         u32 uf;
1653
1654         if (list_empty(&dep->request_list)) {
1655                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1656                         dep->name);
1657                 return;
1658         }
1659
1660         if (event->parameters) {
1661                 u32 mask;
1662
1663                 mask = ~(dep->interval - 1);
1664                 uf = event->parameters & mask;
1665                 /* 4 micro frames in the future */
1666                 uf += dep->interval * 4;
1667         } else {
1668                 uf = 0;
1669         }
1670
1671         __dwc3_gadget_kick_transfer(dep, uf, 1);
1672 }
1673
1674 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1675                 const struct dwc3_event_depevt *event)
1676 {
1677         struct dwc3 *dwc = dep->dwc;
1678         struct dwc3_event_depevt mod_ev = *event;
1679
1680         /*
1681          * We were asked to remove one requests. It is possible that this
1682          * request and a few other were started together and have the same
1683          * transfer index. Since we stopped the complete endpoint we don't
1684          * know how many requests were already completed (and not yet)
1685          * reported and how could be done (later). We purge them all until
1686          * the end of the list.
1687          */
1688         mod_ev.status = DEPEVT_STATUS_LST;
1689         dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1690         dep->flags &= ~DWC3_EP_BUSY;
1691         /* pending requets are ignored and are queued on XferNotReady */
1692 }
1693
1694 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1695                 const struct dwc3_event_depevt *event)
1696 {
1697         u32 param = event->parameters;
1698         u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1699
1700         switch (cmd_type) {
1701         case DWC3_DEPCMD_ENDTRANSFER:
1702                 dwc3_process_ep_cmd_complete(dep, event);
1703                 break;
1704         case DWC3_DEPCMD_STARTTRANSFER:
1705                 dep->res_trans_idx = param & 0x7f;
1706                 break;
1707         default:
1708                 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1709                                 __func__, cmd_type);
1710                 break;
1711         };
1712 }
1713
1714 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1715                 const struct dwc3_event_depevt *event)
1716 {
1717         struct dwc3_ep          *dep;
1718         u8                      epnum = event->endpoint_number;
1719
1720         dep = dwc->eps[epnum];
1721
1722         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1723                         dwc3_ep_event_string(event->endpoint_event));
1724
1725         if (epnum == 0 || epnum == 1) {
1726                 dwc3_ep0_interrupt(dwc, event);
1727                 return;
1728         }
1729
1730         switch (event->endpoint_event) {
1731         case DWC3_DEPEVT_XFERCOMPLETE:
1732                 if (usb_endpoint_xfer_isoc(dep->desc)) {
1733                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1734                                         dep->name);
1735                         return;
1736                 }
1737
1738                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1739                 break;
1740         case DWC3_DEPEVT_XFERINPROGRESS:
1741                 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1742                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1743                                         dep->name);
1744                         return;
1745                 }
1746
1747                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1748                 break;
1749         case DWC3_DEPEVT_XFERNOTREADY:
1750                 if (usb_endpoint_xfer_isoc(dep->desc)) {
1751                         dwc3_gadget_start_isoc(dwc, dep, event);
1752                 } else {
1753                         int ret;
1754
1755                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1756                                         dep->name, event->status &
1757                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1758                                         ? "Transfer Active"
1759                                         : "Transfer Not Active");
1760
1761                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1762                         if (!ret || ret == -EBUSY)
1763                                 return;
1764
1765                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1766                                         dep->name);
1767                 }
1768
1769                 break;
1770         case DWC3_DEPEVT_STREAMEVT:
1771                 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1772                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1773                                         dep->name);
1774                         return;
1775                 }
1776
1777                 switch (event->status) {
1778                 case DEPEVT_STREAMEVT_FOUND:
1779                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1780                                         event->parameters);
1781
1782                         break;
1783                 case DEPEVT_STREAMEVT_NOTFOUND:
1784                         /* FALLTHROUGH */
1785                 default:
1786                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1787                 }
1788                 break;
1789         case DWC3_DEPEVT_RXTXFIFOEVT:
1790                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1791                 break;
1792         case DWC3_DEPEVT_EPCMDCMPLT:
1793                 dwc3_ep_cmd_compl(dep, event);
1794                 break;
1795         }
1796 }
1797
1798 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1799 {
1800         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1801                 spin_unlock(&dwc->lock);
1802                 dwc->gadget_driver->disconnect(&dwc->gadget);
1803                 spin_lock(&dwc->lock);
1804         }
1805 }
1806
1807 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1808 {
1809         struct dwc3_ep *dep;
1810         struct dwc3_gadget_ep_cmd_params params;
1811         u32 cmd;
1812         int ret;
1813
1814         dep = dwc->eps[epnum];
1815
1816         WARN_ON(!dep->res_trans_idx);
1817         if (dep->res_trans_idx) {
1818                 cmd = DWC3_DEPCMD_ENDTRANSFER;
1819                 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1820                 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1821                 memset(&params, 0, sizeof(params));
1822                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1823                 WARN_ON_ONCE(ret);
1824                 dep->res_trans_idx = 0;
1825         }
1826 }
1827
1828 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1829 {
1830         u32 epnum;
1831
1832         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1833                 struct dwc3_ep *dep;
1834
1835                 dep = dwc->eps[epnum];
1836                 if (!(dep->flags & DWC3_EP_ENABLED))
1837                         continue;
1838
1839                 dwc3_remove_requests(dwc, dep);
1840         }
1841 }
1842
1843 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1844 {
1845         u32 epnum;
1846
1847         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1848                 struct dwc3_ep *dep;
1849                 struct dwc3_gadget_ep_cmd_params params;
1850                 int ret;
1851
1852                 dep = dwc->eps[epnum];
1853
1854                 if (!(dep->flags & DWC3_EP_STALL))
1855                         continue;
1856
1857                 dep->flags &= ~DWC3_EP_STALL;
1858
1859                 memset(&params, 0, sizeof(params));
1860                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1861                                 DWC3_DEPCMD_CLEARSTALL, &params);
1862                 WARN_ON_ONCE(ret);
1863         }
1864 }
1865
1866 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1867 {
1868         dev_vdbg(dwc->dev, "%s\n", __func__);
1869 #if 0
1870         XXX
1871         U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1872         enable it before we can disable it.
1873
1874         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1875         reg &= ~DWC3_DCTL_INITU1ENA;
1876         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1877
1878         reg &= ~DWC3_DCTL_INITU2ENA;
1879         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1880 #endif
1881
1882         dwc3_stop_active_transfers(dwc);
1883         dwc3_disconnect_gadget(dwc);
1884         dwc->start_config_issued = false;
1885
1886         dwc->gadget.speed = USB_SPEED_UNKNOWN;
1887         dwc->setup_packet_pending = false;
1888 }
1889
1890 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1891 {
1892         u32                     reg;
1893
1894         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1895
1896         if (on)
1897                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1898         else
1899                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1900
1901         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1902 }
1903
1904 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1905 {
1906         u32                     reg;
1907
1908         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1909
1910         if (on)
1911                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1912         else
1913                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1914
1915         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1916 }
1917
1918 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1919 {
1920         u32                     reg;
1921
1922         dev_vdbg(dwc->dev, "%s\n", __func__);
1923
1924         /*
1925          * WORKAROUND: DWC3 revisions <1.88a have an issue which
1926          * would cause a missing Disconnect Event if there's a
1927          * pending Setup Packet in the FIFO.
1928          *
1929          * There's no suggested workaround on the official Bug
1930          * report, which states that "unless the driver/application
1931          * is doing any special handling of a disconnect event,
1932          * there is no functional issue".
1933          *
1934          * Unfortunately, it turns out that we _do_ some special
1935          * handling of a disconnect event, namely complete all
1936          * pending transfers, notify gadget driver of the
1937          * disconnection, and so on.
1938          *
1939          * Our suggested workaround is to follow the Disconnect
1940          * Event steps here, instead, based on a setup_packet_pending
1941          * flag. Such flag gets set whenever we have a XferNotReady
1942          * event on EP0 and gets cleared on XferComplete for the
1943          * same endpoint.
1944          *
1945          * Refers to:
1946          *
1947          * STAR#9000466709: RTL: Device : Disconnect event not
1948          * generated if setup packet pending in FIFO
1949          */
1950         if (dwc->revision < DWC3_REVISION_188A) {
1951                 if (dwc->setup_packet_pending)
1952                         dwc3_gadget_disconnect_interrupt(dwc);
1953         }
1954
1955         /* after reset -> Default State */
1956         dwc->dev_state = DWC3_DEFAULT_STATE;
1957
1958         /* Enable PHYs */
1959         dwc3_gadget_usb2_phy_power(dwc, true);
1960         dwc3_gadget_usb3_phy_power(dwc, true);
1961
1962         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1963                 dwc3_disconnect_gadget(dwc);
1964
1965         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1966         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1967         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1968         dwc->test_mode = false;
1969
1970         dwc3_stop_active_transfers(dwc);
1971         dwc3_clear_stall_all_ep(dwc);
1972         dwc->start_config_issued = false;
1973
1974         /* Reset device address to zero */
1975         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1976         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1977         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1978 }
1979
1980 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1981 {
1982         u32 reg;
1983         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1984
1985         /*
1986          * We change the clock only at SS but I dunno why I would want to do
1987          * this. Maybe it becomes part of the power saving plan.
1988          */
1989
1990         if (speed != DWC3_DSTS_SUPERSPEED)
1991                 return;
1992
1993         /*
1994          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1995          * each time on Connect Done.
1996          */
1997         if (!usb30_clock)
1998                 return;
1999
2000         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2001         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2002         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2003 }
2004
2005 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
2006 {
2007         switch (speed) {
2008         case USB_SPEED_SUPER:
2009                 dwc3_gadget_usb2_phy_power(dwc, false);
2010                 break;
2011         case USB_SPEED_HIGH:
2012         case USB_SPEED_FULL:
2013         case USB_SPEED_LOW:
2014                 dwc3_gadget_usb3_phy_power(dwc, false);
2015                 break;
2016         }
2017 }
2018
2019 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2020 {
2021         struct dwc3_gadget_ep_cmd_params params;
2022         struct dwc3_ep          *dep;
2023         int                     ret;
2024         u32                     reg;
2025         u8                      speed;
2026
2027         dev_vdbg(dwc->dev, "%s\n", __func__);
2028
2029         memset(&params, 0x00, sizeof(params));
2030
2031         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2032         speed = reg & DWC3_DSTS_CONNECTSPD;
2033         dwc->speed = speed;
2034
2035         dwc3_update_ram_clk_sel(dwc, speed);
2036
2037         switch (speed) {
2038         case DWC3_DCFG_SUPERSPEED:
2039                 /*
2040                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2041                  * would cause a missing USB3 Reset event.
2042                  *
2043                  * In such situations, we should force a USB3 Reset
2044                  * event by calling our dwc3_gadget_reset_interrupt()
2045                  * routine.
2046                  *
2047                  * Refers to:
2048                  *
2049                  * STAR#9000483510: RTL: SS : USB3 reset event may
2050                  * not be generated always when the link enters poll
2051                  */
2052                 if (dwc->revision < DWC3_REVISION_190A)
2053                         dwc3_gadget_reset_interrupt(dwc);
2054
2055                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2056                 dwc->gadget.ep0->maxpacket = 512;
2057                 dwc->gadget.speed = USB_SPEED_SUPER;
2058                 break;
2059         case DWC3_DCFG_HIGHSPEED:
2060                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2061                 dwc->gadget.ep0->maxpacket = 64;
2062                 dwc->gadget.speed = USB_SPEED_HIGH;
2063                 break;
2064         case DWC3_DCFG_FULLSPEED2:
2065         case DWC3_DCFG_FULLSPEED1:
2066                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2067                 dwc->gadget.ep0->maxpacket = 64;
2068                 dwc->gadget.speed = USB_SPEED_FULL;
2069                 break;
2070         case DWC3_DCFG_LOWSPEED:
2071                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2072                 dwc->gadget.ep0->maxpacket = 8;
2073                 dwc->gadget.speed = USB_SPEED_LOW;
2074                 break;
2075         }
2076
2077         /* Disable unneded PHY */
2078         dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
2079
2080         dep = dwc->eps[0];
2081         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2082         if (ret) {
2083                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2084                 return;
2085         }
2086
2087         dep = dwc->eps[1];
2088         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2089         if (ret) {
2090                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2091                 return;
2092         }
2093
2094         /*
2095          * Configure PHY via GUSB3PIPECTLn if required.
2096          *
2097          * Update GTXFIFOSIZn
2098          *
2099          * In both cases reset values should be sufficient.
2100          */
2101 }
2102
2103 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2104 {
2105         dev_vdbg(dwc->dev, "%s\n", __func__);
2106
2107         /*
2108          * TODO take core out of low power mode when that's
2109          * implemented.
2110          */
2111
2112         dwc->gadget_driver->resume(&dwc->gadget);
2113 }
2114
2115 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2116                 unsigned int evtinfo)
2117 {
2118         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2119
2120         /*
2121          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2122          * on the link partner, the USB session might do multiple entry/exit
2123          * of low power states before a transfer takes place.
2124          *
2125          * Due to this problem, we might experience lower throughput. The
2126          * suggested workaround is to disable DCTL[12:9] bits if we're
2127          * transitioning from U1/U2 to U0 and enable those bits again
2128          * after a transfer completes and there are no pending transfers
2129          * on any of the enabled endpoints.
2130          *
2131          * This is the first half of that workaround.
2132          *
2133          * Refers to:
2134          *
2135          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2136          * core send LGO_Ux entering U0
2137          */
2138         if (dwc->revision < DWC3_REVISION_183A) {
2139                 if (next == DWC3_LINK_STATE_U0) {
2140                         u32     u1u2;
2141                         u32     reg;
2142
2143                         switch (dwc->link_state) {
2144                         case DWC3_LINK_STATE_U1:
2145                         case DWC3_LINK_STATE_U2:
2146                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2147                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2148                                                 | DWC3_DCTL_ACCEPTU2ENA
2149                                                 | DWC3_DCTL_INITU1ENA
2150                                                 | DWC3_DCTL_ACCEPTU1ENA);
2151
2152                                 if (!dwc->u1u2)
2153                                         dwc->u1u2 = reg & u1u2;
2154
2155                                 reg &= ~u1u2;
2156
2157                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2158                                 break;
2159                         default:
2160                                 /* do nothing */
2161                                 break;
2162                         }
2163                 }
2164         }
2165
2166         dwc->link_state = next;
2167
2168         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2169 }
2170
2171 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2172                 const struct dwc3_event_devt *event)
2173 {
2174         switch (event->type) {
2175         case DWC3_DEVICE_EVENT_DISCONNECT:
2176                 dwc3_gadget_disconnect_interrupt(dwc);
2177                 break;
2178         case DWC3_DEVICE_EVENT_RESET:
2179                 dwc3_gadget_reset_interrupt(dwc);
2180                 break;
2181         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2182                 dwc3_gadget_conndone_interrupt(dwc);
2183                 break;
2184         case DWC3_DEVICE_EVENT_WAKEUP:
2185                 dwc3_gadget_wakeup_interrupt(dwc);
2186                 break;
2187         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2188                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2189                 break;
2190         case DWC3_DEVICE_EVENT_EOPF:
2191                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2192                 break;
2193         case DWC3_DEVICE_EVENT_SOF:
2194                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2195                 break;
2196         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2197                 dev_vdbg(dwc->dev, "Erratic Error\n");
2198                 break;
2199         case DWC3_DEVICE_EVENT_CMD_CMPL:
2200                 dev_vdbg(dwc->dev, "Command Complete\n");
2201                 break;
2202         case DWC3_DEVICE_EVENT_OVERFLOW:
2203                 dev_vdbg(dwc->dev, "Overflow\n");
2204                 break;
2205         default:
2206                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2207         }
2208 }
2209
2210 static void dwc3_process_event_entry(struct dwc3 *dwc,
2211                 const union dwc3_event *event)
2212 {
2213         /* Endpoint IRQ, handle it and return early */
2214         if (event->type.is_devspec == 0) {
2215                 /* depevt */
2216                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2217         }
2218
2219         switch (event->type.type) {
2220         case DWC3_EVENT_TYPE_DEV:
2221                 dwc3_gadget_interrupt(dwc, &event->devt);
2222                 break;
2223         /* REVISIT what to do with Carkit and I2C events ? */
2224         default:
2225                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2226         }
2227 }
2228
2229 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2230 {
2231         struct dwc3_event_buffer *evt;
2232         int left;
2233         u32 count;
2234
2235         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2236         count &= DWC3_GEVNTCOUNT_MASK;
2237         if (!count)
2238                 return IRQ_NONE;
2239
2240         evt = dwc->ev_buffs[buf];
2241         left = count;
2242
2243         while (left > 0) {
2244                 union dwc3_event event;
2245
2246                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2247
2248                 dwc3_process_event_entry(dwc, &event);
2249                 /*
2250                  * XXX we wrap around correctly to the next entry as almost all
2251                  * entries are 4 bytes in size. There is one entry which has 12
2252                  * bytes which is a regular entry followed by 8 bytes data. ATM
2253                  * I don't know how things are organized if were get next to the
2254                  * a boundary so I worry about that once we try to handle that.
2255                  */
2256                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2257                 left -= 4;
2258
2259                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2260         }
2261
2262         return IRQ_HANDLED;
2263 }
2264
2265 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2266 {
2267         struct dwc3                     *dwc = _dwc;
2268         int                             i;
2269         irqreturn_t                     ret = IRQ_NONE;
2270
2271         spin_lock(&dwc->lock);
2272
2273         for (i = 0; i < dwc->num_event_buffers; i++) {
2274                 irqreturn_t status;
2275
2276                 status = dwc3_process_event_buf(dwc, i);
2277                 if (status == IRQ_HANDLED)
2278                         ret = status;
2279         }
2280
2281         spin_unlock(&dwc->lock);
2282
2283         return ret;
2284 }
2285
2286 /**
2287  * dwc3_gadget_init - Initializes gadget related registers
2288  * @dwc: Pointer to out controller context structure
2289  *
2290  * Returns 0 on success otherwise negative errno.
2291  */
2292 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2293 {
2294         u32                                     reg;
2295         int                                     ret;
2296         int                                     irq;
2297
2298         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2299                         &dwc->ctrl_req_addr, GFP_KERNEL);
2300         if (!dwc->ctrl_req) {
2301                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2302                 ret = -ENOMEM;
2303                 goto err0;
2304         }
2305
2306         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2307                         &dwc->ep0_trb_addr, GFP_KERNEL);
2308         if (!dwc->ep0_trb) {
2309                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2310                 ret = -ENOMEM;
2311                 goto err1;
2312         }
2313
2314         dwc->setup_buf = dma_alloc_coherent(dwc->dev,
2315                         sizeof(*dwc->setup_buf) * 2,
2316                         &dwc->setup_buf_addr, GFP_KERNEL);
2317         if (!dwc->setup_buf) {
2318                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2319                 ret = -ENOMEM;
2320                 goto err2;
2321         }
2322
2323         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2324                         512, &dwc->ep0_bounce_addr, GFP_KERNEL);
2325         if (!dwc->ep0_bounce) {
2326                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2327                 ret = -ENOMEM;
2328                 goto err3;
2329         }
2330
2331         dev_set_name(&dwc->gadget.dev, "gadget");
2332
2333         dwc->gadget.ops                 = &dwc3_gadget_ops;
2334         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2335         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2336         dwc->gadget.dev.parent          = dwc->dev;
2337         dwc->gadget.sg_supported        = true;
2338
2339         dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2340
2341         dwc->gadget.dev.dma_parms       = dwc->dev->dma_parms;
2342         dwc->gadget.dev.dma_mask        = dwc->dev->dma_mask;
2343         dwc->gadget.dev.release         = dwc3_gadget_release;
2344         dwc->gadget.name                = "dwc3-gadget";
2345
2346         /*
2347          * REVISIT: Here we should clear all pending IRQs to be
2348          * sure we're starting from a well known location.
2349          */
2350
2351         ret = dwc3_gadget_init_endpoints(dwc);
2352         if (ret)
2353                 goto err4;
2354
2355         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2356
2357         ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2358                         "dwc3", dwc);
2359         if (ret) {
2360                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2361                                 irq, ret);
2362                 goto err5;
2363         }
2364
2365         /* Enable all but Start and End of Frame IRQs */
2366         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2367                         DWC3_DEVTEN_EVNTOVERFLOWEN |
2368                         DWC3_DEVTEN_CMDCMPLTEN |
2369                         DWC3_DEVTEN_ERRTICERREN |
2370                         DWC3_DEVTEN_WKUPEVTEN |
2371                         DWC3_DEVTEN_ULSTCNGEN |
2372                         DWC3_DEVTEN_CONNECTDONEEN |
2373                         DWC3_DEVTEN_USBRSTEN |
2374                         DWC3_DEVTEN_DISCONNEVTEN);
2375         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2376
2377         ret = device_register(&dwc->gadget.dev);
2378         if (ret) {
2379                 dev_err(dwc->dev, "failed to register gadget device\n");
2380                 put_device(&dwc->gadget.dev);
2381                 goto err6;
2382         }
2383
2384         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2385         if (ret) {
2386                 dev_err(dwc->dev, "failed to register udc\n");
2387                 goto err7;
2388         }
2389
2390         return 0;
2391
2392 err7:
2393         device_unregister(&dwc->gadget.dev);
2394
2395 err6:
2396         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2397         free_irq(irq, dwc);
2398
2399 err5:
2400         dwc3_gadget_free_endpoints(dwc);
2401
2402 err4:
2403         dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2404                         dwc->ep0_bounce_addr);
2405
2406 err3:
2407         dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2408                         dwc->setup_buf, dwc->setup_buf_addr);
2409
2410 err2:
2411         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2412                         dwc->ep0_trb, dwc->ep0_trb_addr);
2413
2414 err1:
2415         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2416                         dwc->ctrl_req, dwc->ctrl_req_addr);
2417
2418 err0:
2419         return ret;
2420 }
2421
2422 void dwc3_gadget_exit(struct dwc3 *dwc)
2423 {
2424         int                     irq;
2425
2426         usb_del_gadget_udc(&dwc->gadget);
2427         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2428
2429         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2430         free_irq(irq, dwc);
2431
2432         dwc3_gadget_free_endpoints(dwc);
2433
2434         dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2435                         dwc->ep0_bounce_addr);
2436
2437         dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2438                         dwc->setup_buf, dwc->setup_buf_addr);
2439
2440         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2441                         dwc->ep0_trb, dwc->ep0_trb_addr);
2442
2443         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2444                         dwc->ctrl_req, dwc->ctrl_req_addr);
2445
2446         device_unregister(&dwc->gadget.dev);
2447 }