drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51 #include <linux/usb/composite.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
  58
  59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  60 {
  61         switch (state) {
  62         case EP0_UNCONNECTED:
  63                 return "Unconnected";
  64         case EP0_SETUP_PHASE:
  65                 return "Setup Phase";
  66         case EP0_DATA_PHASE:
  67                 return "Data Phase";
  68         case EP0_STATUS_PHASE:
  69                 return "Status Phase";
  70         default:
  71                 return "UNKNOWN";
  72         }
  73 }
  74
  75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  76                 u32 len, u32 type)
  77 {
  78         struct dwc3_gadget_ep_cmd_params params;
  79         struct dwc3_trb_hw              *trb_hw;
  80         struct dwc3_trb                 trb;
  81         struct dwc3_ep                  *dep;
  82
  83         int                             ret;
  84
  85         dep = dwc->eps[epnum];
  86         if (dep->flags & DWC3_EP_BUSY) {
  87                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  88                 return 0;
  89         }
  90
  91         trb_hw = dwc->ep0_trb;
  92         memset(&trb, 0, sizeof(trb));
  93
  94         trb.trbctl = type;
  95         trb.bplh = buf_dma;
  96         trb.length = len;
  97
  98         trb.hwo = 1;
  99         trb.lst = 1;
 100         trb.ioc = 1;
 101         trb.isp_imi = 1;
 102
 103         dwc3_trb_to_hw(&trb, trb_hw);
 104
 105         memset(&params, 0, sizeof(params));
 106         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 107         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 108
 109         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 110                         DWC3_DEPCMD_STARTTRANSFER, &params);
 111         if (ret < 0) {
 112                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 113                 return ret;
 114         }
 115
 116         dep->flags |= DWC3_EP_BUSY;
 117         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 118                         dep->number);
 119
 120         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 121
 122         return 0;
 123 }
 124
 125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 126                 struct dwc3_request *req)
 127 {
 128         struct dwc3             *dwc = dep->dwc;
 129         u32                     type;
 130         int                     ret = 0;
 131
 132         req->request.actual     = 0;
 133         req->request.status     = -EINPROGRESS;
 134         req->epnum              = dep->number;
 135
 136         list_add_tail(&req->list, &dep->request_list);
 137
 138         /*
 139          * Gadget driver might not be quick enough to queue a request
 140          * before we get a Transfer Not Ready event on this endpoint.
 141          *
 142          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 143          * flag is set, it's telling us that as soon as Gadget queues the
 144          * required request, we should kick the transfer here because the
 145          * IRQ we were waiting for is long gone.
 146          */
 147         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 148                 unsigned        direction;
 149
 150                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 151
 152                 if (dwc->ep0state == EP0_STATUS_PHASE) {
 153                         type = dwc->three_stage_setup
 154                                 ? DWC3_TRBCTL_CONTROL_STATUS3
 155                                 : DWC3_TRBCTL_CONTROL_STATUS2;
 156                 } else if (dwc->ep0state == EP0_DATA_PHASE) {
 157                         type = DWC3_TRBCTL_CONTROL_DATA;
 158                 } else {
 159                         /* should never happen */
 160                         WARN_ON(1);
 161                         return 0;
 162                 }
 163
 164                 ret = dwc3_ep0_start_trans(dwc, direction,
 165                                 req->request.dma, req->request.length, type);
 166                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 167                                 DWC3_EP0_DIR_IN);
 168         } else if (dwc->delayed_status) {
 169                 dwc->delayed_status = false;
 170
 171                 if (dwc->ep0state == EP0_STATUS_PHASE)
 172                         dwc3_ep0_do_control_status(dwc, 1);
 173                 else
 174                         dev_dbg(dwc->dev, "too early for delayed status\n");
 175         }
 176
 177         return ret;
 178 }
 179
 180 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 181                 gfp_t gfp_flags)
 182 {
 183         struct dwc3_request             *req = to_dwc3_request(request);
 184         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 185         struct dwc3                     *dwc = dep->dwc;
 186
 187         unsigned long                   flags;
 188
 189         int                             ret;
 190
 191         spin_lock_irqsave(&dwc->lock, flags);
 192         if (!dep->desc) {
 193                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 194                                 request, dep->name);
 195                 ret = -ESHUTDOWN;
 196                 goto out;
 197         }
 198
 199         /* we share one TRB for ep0/1 */
 200         if (!list_empty(&dep->request_list)) {
 201                 ret = -EBUSY;
 202                 goto out;
 203         }
 204
 205         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 206                         request, dep->name, request->length,
 207                         dwc3_ep0_state_string(dwc->ep0state));
 208
 209         ret = __dwc3_gadget_ep0_queue(dep, req);
 210
 211 out:
 212         spin_unlock_irqrestore(&dwc->lock, flags);
 213
 214         return ret;
 215 }
 216
 217 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 218 {
 219         struct dwc3_ep          *dep = dwc->eps[0];
 220
 221         /* stall is always issued on EP0 */
 222         __dwc3_gadget_ep_set_halt(dep, 1);
 223         dep->flags = DWC3_EP_ENABLED;
 224         dwc->delayed_status = false;
 225
 226         if (!list_empty(&dep->request_list)) {
 227                 struct dwc3_request     *req;
 228
 229                 req = next_request(&dep->request_list);
 230                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 231         }
 232
 233         dwc->ep0state = EP0_SETUP_PHASE;
 234         dwc3_ep0_out_start(dwc);
 235 }
 236
 237 void dwc3_ep0_out_start(struct dwc3 *dwc)
 238 {
 239         int                             ret;
 240
 241         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 242                         DWC3_TRBCTL_CONTROL_SETUP);
 243         WARN_ON(ret < 0);
 244 }
 245
 246 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 247 {
 248         struct dwc3_ep          *dep;
 249         u32                     windex = le16_to_cpu(wIndex_le);
 250         u32                     epnum;
 251
 252         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 253         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 254                 epnum |= 1;
 255
 256         dep = dwc->eps[epnum];
 257         if (dep->flags & DWC3_EP_ENABLED)
 258                 return dep;
 259
 260         return NULL;
 261 }
 262
 263 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 264 {
 265 }
 266 /*
 267  * ch 9.4.5
 268  */
 269 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 270                 struct usb_ctrlrequest *ctrl)
 271 {
 272         struct dwc3_ep          *dep;
 273         u32                     recip;
 274         u16                     usb_status = 0;
 275         __le16                  *response_pkt;
 276
 277         recip = ctrl->bRequestType & USB_RECIP_MASK;
 278         switch (recip) {
 279         case USB_RECIP_DEVICE:
 280                 /*
 281                  * We are self-powered. U1/U2/LTM will be set later
 282                  * once we handle this states. RemoteWakeup is 0 on SS
 283                  */
 284                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 285                 break;
 286
 287         case USB_RECIP_INTERFACE:
 288                 /*
 289                  * Function Remote Wake Capable D0
 290                  * Function Remote Wakeup       D1
 291                  */
 292                 break;
 293
 294         case USB_RECIP_ENDPOINT:
 295                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 296                 if (!dep)
 297                         return -EINVAL;
 298
 299                 if (dep->flags & DWC3_EP_STALL)
 300                         usb_status = 1 << USB_ENDPOINT_HALT;
 301                 break;
 302         default:
 303                 return -EINVAL;
 304         };
 305
 306         response_pkt = (__le16 *) dwc->setup_buf;
 307         *response_pkt = cpu_to_le16(usb_status);
 308
 309         dep = dwc->eps[0];
 310         dwc->ep0_usb_req.dep = dep;
 311         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 312         dwc->ep0_usb_req.request.dma = dwc->setup_buf_addr;
 313         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 314
 315         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 316 }
 317
 318 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 319                 struct usb_ctrlrequest *ctrl, int set)
 320 {
 321         struct dwc3_ep          *dep;
 322         u32                     recip;
 323         u32                     wValue;
 324         u32                     wIndex;
 325         u32                     reg;
 326         int                     ret;
 327         u32                     mode;
 328
 329         wValue = le16_to_cpu(ctrl->wValue);
 330         wIndex = le16_to_cpu(ctrl->wIndex);
 331         recip = ctrl->bRequestType & USB_RECIP_MASK;
 332         switch (recip) {
 333         case USB_RECIP_DEVICE:
 334
 335                 /*
 336                  * 9.4.1 says only only for SS, in AddressState only for
 337                  * default control pipe
 338                  */
 339                 switch (wValue) {
 340                 case USB_DEVICE_U1_ENABLE:
 341                 case USB_DEVICE_U2_ENABLE:
 342                 case USB_DEVICE_LTM_ENABLE:
 343                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 344                                 return -EINVAL;
 345                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 346                                 return -EINVAL;
 347                 }
 348
 349                 /* XXX add U[12] & LTM */
 350                 switch (wValue) {
 351                 case USB_DEVICE_REMOTE_WAKEUP:
 352                         break;
 353                 case USB_DEVICE_U1_ENABLE:
 354                         break;
 355                 case USB_DEVICE_U2_ENABLE:
 356                         break;
 357                 case USB_DEVICE_LTM_ENABLE:
 358                         break;
 359
 360                 case USB_DEVICE_TEST_MODE:
 361                         if ((wIndex & 0xff) != 0)
 362                                 return -EINVAL;
 363                         if (!set)
 364                                 return -EINVAL;
 365
 366                         mode = wIndex >> 8;
 367                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 368                         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
 369
 370                         switch (mode) {
 371                         case TEST_J:
 372                         case TEST_K:
 373                         case TEST_SE0_NAK:
 374                         case TEST_PACKET:
 375                         case TEST_FORCE_EN:
 376                                 reg |= mode << 1;
 377                                 break;
 378                         default:
 379                                 return -EINVAL;
 380                         }
 381                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 382                         break;
 383                 default:
 384                         return -EINVAL;
 385                 }
 386                 break;
 387
 388         case USB_RECIP_INTERFACE:
 389                 switch (wValue) {
 390                 case USB_INTRF_FUNC_SUSPEND:
 391                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 392                                 /* XXX enable Low power suspend */
 393                                 ;
 394                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 395                                 /* XXX enable remote wakeup */
 396                                 ;
 397                         break;
 398                 default:
 399                         return -EINVAL;
 400                 }
 401                 break;
 402
 403         case USB_RECIP_ENDPOINT:
 404                 switch (wValue) {
 405                 case USB_ENDPOINT_HALT:
 406                         dep =  dwc3_wIndex_to_dep(dwc, wIndex);
 407                         if (!dep)
 408                                 return -EINVAL;
 409                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 410                         if (ret)
 411                                 return -EINVAL;
 412                         break;
 413                 default:
 414                         return -EINVAL;
 415                 }
 416                 break;
 417
 418         default:
 419                 return -EINVAL;
 420         };
 421
 422         return 0;
 423 }
 424
 425 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 426 {
 427         u32 addr;
 428         u32 reg;
 429
 430         addr = le16_to_cpu(ctrl->wValue);
 431         if (addr > 127) {
 432                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 433                 return -EINVAL;
 434         }
 435
 436         if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
 437                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 438                 return -EINVAL;
 439         }
 440
 441         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 442         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 443         reg |= DWC3_DCFG_DEVADDR(addr);
 444         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 445
 446         if (addr)
 447                 dwc->dev_state = DWC3_ADDRESS_STATE;
 448         else
 449                 dwc->dev_state = DWC3_DEFAULT_STATE;
 450
 451         return 0;
 452 }
 453
 454 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 455 {
 456         int ret;
 457
 458         spin_unlock(&dwc->lock);
 459         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 460         spin_lock(&dwc->lock);
 461         return ret;
 462 }
 463
 464 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 465 {
 466         u32 cfg;
 467         int ret;
 468
 469         dwc->start_config_issued = false;
 470         cfg = le16_to_cpu(ctrl->wValue);
 471
 472         switch (dwc->dev_state) {
 473         case DWC3_DEFAULT_STATE:
 474                 return -EINVAL;
 475                 break;
 476
 477         case DWC3_ADDRESS_STATE:
 478                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 479                 /* if the cfg matches and the cfg is non zero */
 480                 if (!ret && cfg)
 481                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 482                 break;
 483
 484         case DWC3_CONFIGURED_STATE:
 485                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 486                 if (!cfg)
 487                         dwc->dev_state = DWC3_ADDRESS_STATE;
 488                 break;
 489         default:
 490                 ret = -EINVAL;
 491         }
 492         return ret;
 493 }
 494
 495 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 496 {
 497         int ret;
 498
 499         switch (ctrl->bRequest) {
 500         case USB_REQ_GET_STATUS:
 501                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 502                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 503                 break;
 504         case USB_REQ_CLEAR_FEATURE:
 505                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 506                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 507                 break;
 508         case USB_REQ_SET_FEATURE:
 509                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 510                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 511                 break;
 512         case USB_REQ_SET_ADDRESS:
 513                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 514                 ret = dwc3_ep0_set_address(dwc, ctrl);
 515                 break;
 516         case USB_REQ_SET_CONFIGURATION:
 517                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 518                 ret = dwc3_ep0_set_config(dwc, ctrl);
 519                 break;
 520         default:
 521                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 522                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 523                 break;
 524         };
 525
 526         return ret;
 527 }
 528
 529 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 530                 const struct dwc3_event_depevt *event)
 531 {
 532         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 533         int ret;
 534         u32 len;
 535
 536         if (!dwc->gadget_driver)
 537                 goto err;
 538
 539         len = le16_to_cpu(ctrl->wLength);
 540         if (!len) {
 541                 dwc->three_stage_setup = false;
 542                 dwc->ep0_expect_in = false;
 543                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 544         } else {
 545                 dwc->three_stage_setup = true;
 546                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 547                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 548         }
 549
 550         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 551                 ret = dwc3_ep0_std_request(dwc, ctrl);
 552         else
 553                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 554
 555         if (ret == USB_GADGET_DELAYED_STATUS)
 556                 dwc->delayed_status = true;
 557
 558         if (ret >= 0)
 559                 return;
 560
 561 err:
 562         dwc3_ep0_stall_and_restart(dwc);
 563 }
 564
 565 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 566                 const struct dwc3_event_depevt *event)
 567 {
 568         struct dwc3_request     *r = NULL;
 569         struct usb_request      *ur;
 570         struct dwc3_trb         trb;
 571         struct dwc3_ep          *ep0;
 572         u32                     transferred;
 573         u8                      epnum;
 574
 575         epnum = event->endpoint_number;
 576         ep0 = dwc->eps[0];
 577
 578         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 579
 580         r = next_request(&ep0->request_list);
 581         ur = &r->request;
 582
 583         dwc3_trb_to_nat(dwc->ep0_trb, &trb);
 584
 585         if (dwc->ep0_bounced) {
 586
 587                 transferred = min_t(u32, ur->length,
 588                                 ep0->endpoint.maxpacket - trb.length);
 589                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 590                 dwc->ep0_bounced = false;
 591         } else {
 592                 transferred = ur->length - trb.length;
 593                 ur->actual += transferred;
 594         }
 595
 596         if ((epnum & 1) && ur->actual < ur->length) {
 597                 /* for some reason we did not get everything out */
 598
 599                 dwc3_ep0_stall_and_restart(dwc);
 600         } else {
 601                 /*
 602                  * handle the case where we have to send a zero packet. This
 603                  * seems to be case when req.length > maxpacket. Could it be?
 604                  */
 605                 if (r)
 606                         dwc3_gadget_giveback(ep0, r, 0);
 607         }
 608 }
 609
 610 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 611                 const struct dwc3_event_depevt *event)
 612 {
 613         struct dwc3_request     *r;
 614         struct dwc3_ep          *dep;
 615
 616         dep = dwc->eps[0];
 617
 618         if (!list_empty(&dep->request_list)) {
 619                 r = next_request(&dep->request_list);
 620
 621                 dwc3_gadget_giveback(dep, r, 0);
 622         }
 623
 624         dwc->ep0state = EP0_SETUP_PHASE;
 625         dwc3_ep0_out_start(dwc);
 626 }
 627
 628 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 629                         const struct dwc3_event_depevt *event)
 630 {
 631         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 632
 633         dep->flags &= ~DWC3_EP_BUSY;
 634         dwc->setup_packet_pending = false;
 635
 636         switch (dwc->ep0state) {
 637         case EP0_SETUP_PHASE:
 638                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 639                 dwc3_ep0_inspect_setup(dwc, event);
 640                 break;
 641
 642         case EP0_DATA_PHASE:
 643                 dev_vdbg(dwc->dev, "Data Phase\n");
 644                 dwc3_ep0_complete_data(dwc, event);
 645                 break;
 646
 647         case EP0_STATUS_PHASE:
 648                 dev_vdbg(dwc->dev, "Status Phase\n");
 649                 dwc3_ep0_complete_req(dwc, event);
 650                 break;
 651         default:
 652                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 653         }
 654 }
 655
 656 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 657                 const struct dwc3_event_depevt *event)
 658 {
 659         dwc3_ep0_out_start(dwc);
 660 }
 661
 662 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 663                 const struct dwc3_event_depevt *event)
 664 {
 665         struct dwc3_ep          *dep;
 666         struct dwc3_request     *req;
 667         int                     ret;
 668
 669         dep = dwc->eps[0];
 670
 671         if (list_empty(&dep->request_list)) {
 672                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 673                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 674
 675                 if (event->endpoint_number)
 676                         dep->flags |= DWC3_EP0_DIR_IN;
 677                 return;
 678         }
 679
 680         req = next_request(&dep->request_list);
 681         req->direction = !!event->endpoint_number;
 682
 683         if (req->request.length == 0) {
 684                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 685                                 dwc->ctrl_req_addr, 0,
 686                                 DWC3_TRBCTL_CONTROL_DATA);
 687         } else if ((req->request.length % dep->endpoint.maxpacket)
 688                         && (event->endpoint_number == 0)) {
 689                 dwc3_map_buffer_to_dma(req);
 690
 691                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 692
 693                 dwc->ep0_bounced = true;
 694
 695                 /*
 696                  * REVISIT in case request length is bigger than EP0
 697                  * wMaxPacketSize, we will need two chained TRBs to handle
 698                  * the transfer.
 699                  */
 700                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 701                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 702                                 DWC3_TRBCTL_CONTROL_DATA);
 703         } else {
 704                 dwc3_map_buffer_to_dma(req);
 705
 706                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 707                                 req->request.dma, req->request.length,
 708                                 DWC3_TRBCTL_CONTROL_DATA);
 709         }
 710
 711         WARN_ON(ret < 0);
 712 }
 713
 714 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 715 {
 716         struct dwc3             *dwc = dep->dwc;
 717         u32                     type;
 718
 719         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 720                 : DWC3_TRBCTL_CONTROL_STATUS2;
 721
 722         return dwc3_ep0_start_trans(dwc, dep->number,
 723                         dwc->ctrl_req_addr, 0, type);
 724 }
 725
 726 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
 727 {
 728         struct dwc3_ep          *dep = dwc->eps[epnum];
 729
 730         WARN_ON(dwc3_ep0_start_control_status(dep));
 731 }
 732
 733 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 734                 const struct dwc3_event_depevt *event)
 735 {
 736         dwc->setup_packet_pending = true;
 737
 738         /*
 739          * This part is very tricky: If we has just handled
 740          * XferNotReady(Setup) and we're now expecting a
 741          * XferComplete but, instead, we receive another
 742          * XferNotReady(Setup), we should STALL and restart
 743          * the state machine.
 744          *
 745          * In all other cases, we just continue waiting
 746          * for the XferComplete event.
 747          *
 748          * We are a little bit unsafe here because we're
 749          * not trying to ensure that last event was, indeed,
 750          * XferNotReady(Setup).
 751          *
 752          * Still, we don't expect any condition where that
 753          * should happen and, even if it does, it would be
 754          * another error condition.
 755          */
 756         if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
 757                 switch (event->status) {
 758                 case DEPEVT_STATUS_CONTROL_SETUP:
 759                         dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
 760                         dwc3_ep0_stall_and_restart(dwc);
 761                         break;
 762                 case DEPEVT_STATUS_CONTROL_DATA:
 763                         /* FALLTHROUGH */
 764                 case DEPEVT_STATUS_CONTROL_STATUS:
 765                         /* FALLTHROUGH */
 766                 default:
 767                         dev_vdbg(dwc->dev, "waiting for XferComplete\n");
 768                 }
 769
 770                 return;
 771         }
 772
 773         switch (event->status) {
 774         case DEPEVT_STATUS_CONTROL_SETUP:
 775                 dev_vdbg(dwc->dev, "Control Setup\n");
 776
 777                 dwc->ep0state = EP0_SETUP_PHASE;
 778
 779                 dwc3_ep0_do_control_setup(dwc, event);
 780                 break;
 781
 782         case DEPEVT_STATUS_CONTROL_DATA:
 783                 dev_vdbg(dwc->dev, "Control Data\n");
 784
 785                 dwc->ep0state = EP0_DATA_PHASE;
 786
 787                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 788                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 789                                         dwc->ep0_next_event,
 790                                         DWC3_EP0_NRDY_DATA);
 791
 792                         dwc3_ep0_stall_and_restart(dwc);
 793                         return;
 794                 }
 795
 796                 /*
 797                  * One of the possible error cases is when Host _does_
 798                  * request for Data Phase, but it does so on the wrong
 799                  * direction.
 800                  *
 801                  * Here, we already know ep0_next_event is DATA (see above),
 802                  * so we only need to check for direction.
 803                  */
 804                 if (dwc->ep0_expect_in != event->endpoint_number) {
 805                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 806                         dwc3_ep0_stall_and_restart(dwc);
 807                         return;
 808                 }
 809
 810                 dwc3_ep0_do_control_data(dwc, event);
 811                 break;
 812
 813         case DEPEVT_STATUS_CONTROL_STATUS:
 814                 dev_vdbg(dwc->dev, "Control Status\n");
 815
 816                 dwc->ep0state = EP0_STATUS_PHASE;
 817
 818                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 819                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 820                                         dwc->ep0_next_event,
 821                                         DWC3_EP0_NRDY_STATUS);
 822
 823                         dwc3_ep0_stall_and_restart(dwc);
 824                         return;
 825                 }
 826
 827                 if (dwc->delayed_status) {
 828                         WARN_ON_ONCE(event->endpoint_number != 1);
 829                         dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
 830                         return;
 831                 }
 832
 833                 dwc3_ep0_do_control_status(dwc, event->endpoint_number);
 834         }
 835 }
 836
 837 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 838                 const struct dwc3_event_depevt *event)
 839 {
 840         u8                      epnum = event->endpoint_number;
 841
 842         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 843                         dwc3_ep_event_string(event->endpoint_event),
 844                         epnum >> 1, (epnum & 1) ? "in" : "out",
 845                         dwc3_ep0_state_string(dwc->ep0state));
 846
 847         switch (event->endpoint_event) {
 848         case DWC3_DEPEVT_XFERCOMPLETE:
 849                 dwc3_ep0_xfer_complete(dwc, event);
 850                 break;
 851
 852         case DWC3_DEPEVT_XFERNOTREADY:
 853                 dwc3_ep0_xfernotready(dwc, event);
 854                 break;
 855
 856         case DWC3_DEPEVT_XFERINPROGRESS:
 857         case DWC3_DEPEVT_RXTXFIFOEVT:
 858         case DWC3_DEPEVT_STREAMEVT:
 859         case DWC3_DEPEVT_EPCMDCMPLT:
 860                 break;
 861         }
 862 }