2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
51 #include <linux/usb/composite.h>
57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
78 struct dwc3_gadget_ep_cmd_params params;
79 struct dwc3_trb_hw *trb_hw;
85 dep = dwc->eps[epnum];
86 if (dep->flags & DWC3_EP_BUSY) {
87 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
91 trb_hw = dwc->ep0_trb;
92 memset(&trb, 0, sizeof(trb));
103 dwc3_trb_to_hw(&trb, trb_hw);
105 memset(¶ms, 0, sizeof(params));
106 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
107 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
109 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
110 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
112 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
116 dep->flags |= DWC3_EP_BUSY;
117 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
120 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
126 struct dwc3_request *req)
128 struct dwc3 *dwc = dep->dwc;
132 req->request.actual = 0;
133 req->request.status = -EINPROGRESS;
134 req->epnum = dep->number;
136 list_add_tail(&req->list, &dep->request_list);
139 * Gadget driver might not be quick enough to queue a request
140 * before we get a Transfer Not Ready event on this endpoint.
142 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
143 * flag is set, it's telling us that as soon as Gadget queues the
144 * required request, we should kick the transfer here because the
145 * IRQ we were waiting for is long gone.
147 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
150 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
152 if (dwc->ep0state == EP0_STATUS_PHASE) {
153 type = dwc->three_stage_setup
154 ? DWC3_TRBCTL_CONTROL_STATUS3
155 : DWC3_TRBCTL_CONTROL_STATUS2;
156 } else if (dwc->ep0state == EP0_DATA_PHASE) {
157 type = DWC3_TRBCTL_CONTROL_DATA;
159 /* should never happen */
164 ret = dwc3_ep0_start_trans(dwc, direction,
165 req->request.dma, req->request.length, type);
166 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
168 } else if (dwc->delayed_status) {
169 dwc->delayed_status = false;
171 if (dwc->ep0state == EP0_STATUS_PHASE)
172 dwc3_ep0_do_control_status(dwc, 1);
174 dev_dbg(dwc->dev, "too early for delayed status\n");
180 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
183 struct dwc3_request *req = to_dwc3_request(request);
184 struct dwc3_ep *dep = to_dwc3_ep(ep);
185 struct dwc3 *dwc = dep->dwc;
191 spin_lock_irqsave(&dwc->lock, flags);
193 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
199 /* we share one TRB for ep0/1 */
200 if (!list_empty(&dep->request_list)) {
205 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
206 request, dep->name, request->length,
207 dwc3_ep0_state_string(dwc->ep0state));
209 ret = __dwc3_gadget_ep0_queue(dep, req);
212 spin_unlock_irqrestore(&dwc->lock, flags);
217 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
219 struct dwc3_ep *dep = dwc->eps[0];
221 /* stall is always issued on EP0 */
222 __dwc3_gadget_ep_set_halt(dep, 1);
223 dep->flags = DWC3_EP_ENABLED;
224 dwc->delayed_status = false;
226 if (!list_empty(&dep->request_list)) {
227 struct dwc3_request *req;
229 req = next_request(&dep->request_list);
230 dwc3_gadget_giveback(dep, req, -ECONNRESET);
233 dwc->ep0state = EP0_SETUP_PHASE;
234 dwc3_ep0_out_start(dwc);
237 void dwc3_ep0_out_start(struct dwc3 *dwc)
241 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
242 DWC3_TRBCTL_CONTROL_SETUP);
246 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
249 u32 windex = le16_to_cpu(wIndex_le);
252 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
253 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
256 dep = dwc->eps[epnum];
257 if (dep->flags & DWC3_EP_ENABLED)
263 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
269 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
270 struct usb_ctrlrequest *ctrl)
275 __le16 *response_pkt;
277 recip = ctrl->bRequestType & USB_RECIP_MASK;
279 case USB_RECIP_DEVICE:
281 * We are self-powered. U1/U2/LTM will be set later
282 * once we handle this states. RemoteWakeup is 0 on SS
284 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
287 case USB_RECIP_INTERFACE:
289 * Function Remote Wake Capable D0
290 * Function Remote Wakeup D1
294 case USB_RECIP_ENDPOINT:
295 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
299 if (dep->flags & DWC3_EP_STALL)
300 usb_status = 1 << USB_ENDPOINT_HALT;
306 response_pkt = (__le16 *) dwc->setup_buf;
307 *response_pkt = cpu_to_le16(usb_status);
310 dwc->ep0_usb_req.dep = dep;
311 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
312 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
313 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
315 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
318 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
319 struct usb_ctrlrequest *ctrl, int set)
329 wValue = le16_to_cpu(ctrl->wValue);
330 wIndex = le16_to_cpu(ctrl->wIndex);
331 recip = ctrl->bRequestType & USB_RECIP_MASK;
333 case USB_RECIP_DEVICE:
336 * 9.4.1 says only only for SS, in AddressState only for
337 * default control pipe
340 case USB_DEVICE_U1_ENABLE:
341 case USB_DEVICE_U2_ENABLE:
342 case USB_DEVICE_LTM_ENABLE:
343 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
345 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
349 /* XXX add U[12] & LTM */
351 case USB_DEVICE_REMOTE_WAKEUP:
353 case USB_DEVICE_U1_ENABLE:
355 case USB_DEVICE_U2_ENABLE:
357 case USB_DEVICE_LTM_ENABLE:
360 case USB_DEVICE_TEST_MODE:
361 if ((wIndex & 0xff) != 0)
367 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
368 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
381 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
388 case USB_RECIP_INTERFACE:
390 case USB_INTRF_FUNC_SUSPEND:
391 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
392 /* XXX enable Low power suspend */
394 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
395 /* XXX enable remote wakeup */
403 case USB_RECIP_ENDPOINT:
405 case USB_ENDPOINT_HALT:
406 dep = dwc3_wIndex_to_dep(dwc, wIndex);
409 ret = __dwc3_gadget_ep_set_halt(dep, set);
425 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
430 addr = le16_to_cpu(ctrl->wValue);
432 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
436 if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
437 dev_dbg(dwc->dev, "trying to set address when configured\n");
441 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
442 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
443 reg |= DWC3_DCFG_DEVADDR(addr);
444 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
447 dwc->dev_state = DWC3_ADDRESS_STATE;
449 dwc->dev_state = DWC3_DEFAULT_STATE;
454 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
458 spin_unlock(&dwc->lock);
459 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
460 spin_lock(&dwc->lock);
464 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
469 dwc->start_config_issued = false;
470 cfg = le16_to_cpu(ctrl->wValue);
472 switch (dwc->dev_state) {
473 case DWC3_DEFAULT_STATE:
477 case DWC3_ADDRESS_STATE:
478 ret = dwc3_ep0_delegate_req(dwc, ctrl);
479 /* if the cfg matches and the cfg is non zero */
481 dwc->dev_state = DWC3_CONFIGURED_STATE;
484 case DWC3_CONFIGURED_STATE:
485 ret = dwc3_ep0_delegate_req(dwc, ctrl);
487 dwc->dev_state = DWC3_ADDRESS_STATE;
495 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
499 switch (ctrl->bRequest) {
500 case USB_REQ_GET_STATUS:
501 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
502 ret = dwc3_ep0_handle_status(dwc, ctrl);
504 case USB_REQ_CLEAR_FEATURE:
505 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
506 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
508 case USB_REQ_SET_FEATURE:
509 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
510 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
512 case USB_REQ_SET_ADDRESS:
513 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
514 ret = dwc3_ep0_set_address(dwc, ctrl);
516 case USB_REQ_SET_CONFIGURATION:
517 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
518 ret = dwc3_ep0_set_config(dwc, ctrl);
521 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
522 ret = dwc3_ep0_delegate_req(dwc, ctrl);
529 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
530 const struct dwc3_event_depevt *event)
532 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
536 if (!dwc->gadget_driver)
539 len = le16_to_cpu(ctrl->wLength);
541 dwc->three_stage_setup = false;
542 dwc->ep0_expect_in = false;
543 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
545 dwc->three_stage_setup = true;
546 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
547 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
550 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
551 ret = dwc3_ep0_std_request(dwc, ctrl);
553 ret = dwc3_ep0_delegate_req(dwc, ctrl);
555 if (ret == USB_GADGET_DELAYED_STATUS)
556 dwc->delayed_status = true;
562 dwc3_ep0_stall_and_restart(dwc);
565 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
566 const struct dwc3_event_depevt *event)
568 struct dwc3_request *r = NULL;
569 struct usb_request *ur;
575 epnum = event->endpoint_number;
578 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
580 r = next_request(&ep0->request_list);
583 dwc3_trb_to_nat(dwc->ep0_trb, &trb);
585 if (dwc->ep0_bounced) {
587 transferred = min_t(u32, ur->length,
588 ep0->endpoint.maxpacket - trb.length);
589 memcpy(ur->buf, dwc->ep0_bounce, transferred);
590 dwc->ep0_bounced = false;
592 transferred = ur->length - trb.length;
593 ur->actual += transferred;
596 if ((epnum & 1) && ur->actual < ur->length) {
597 /* for some reason we did not get everything out */
599 dwc3_ep0_stall_and_restart(dwc);
602 * handle the case where we have to send a zero packet. This
603 * seems to be case when req.length > maxpacket. Could it be?
606 dwc3_gadget_giveback(ep0, r, 0);
610 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
611 const struct dwc3_event_depevt *event)
613 struct dwc3_request *r;
618 if (!list_empty(&dep->request_list)) {
619 r = next_request(&dep->request_list);
621 dwc3_gadget_giveback(dep, r, 0);
624 dwc->ep0state = EP0_SETUP_PHASE;
625 dwc3_ep0_out_start(dwc);
628 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
629 const struct dwc3_event_depevt *event)
631 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
633 dep->flags &= ~DWC3_EP_BUSY;
634 dwc->setup_packet_pending = false;
636 switch (dwc->ep0state) {
637 case EP0_SETUP_PHASE:
638 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
639 dwc3_ep0_inspect_setup(dwc, event);
643 dev_vdbg(dwc->dev, "Data Phase\n");
644 dwc3_ep0_complete_data(dwc, event);
647 case EP0_STATUS_PHASE:
648 dev_vdbg(dwc->dev, "Status Phase\n");
649 dwc3_ep0_complete_req(dwc, event);
652 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
656 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
657 const struct dwc3_event_depevt *event)
659 dwc3_ep0_out_start(dwc);
662 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
663 const struct dwc3_event_depevt *event)
666 struct dwc3_request *req;
671 if (list_empty(&dep->request_list)) {
672 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
673 dep->flags |= DWC3_EP_PENDING_REQUEST;
675 if (event->endpoint_number)
676 dep->flags |= DWC3_EP0_DIR_IN;
680 req = next_request(&dep->request_list);
681 req->direction = !!event->endpoint_number;
683 if (req->request.length == 0) {
684 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
685 dwc->ctrl_req_addr, 0,
686 DWC3_TRBCTL_CONTROL_DATA);
687 } else if ((req->request.length % dep->endpoint.maxpacket)
688 && (event->endpoint_number == 0)) {
689 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
690 event->endpoint_number);
692 dev_dbg(dwc->dev, "failed to map request\n");
696 WARN_ON(req->request.length > dep->endpoint.maxpacket);
698 dwc->ep0_bounced = true;
701 * REVISIT in case request length is bigger than EP0
702 * wMaxPacketSize, we will need two chained TRBs to handle
705 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
706 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
707 DWC3_TRBCTL_CONTROL_DATA);
709 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
710 event->endpoint_number);
712 dev_dbg(dwc->dev, "failed to map request\n");
716 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
717 req->request.dma, req->request.length,
718 DWC3_TRBCTL_CONTROL_DATA);
724 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
726 struct dwc3 *dwc = dep->dwc;
729 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
730 : DWC3_TRBCTL_CONTROL_STATUS2;
732 return dwc3_ep0_start_trans(dwc, dep->number,
733 dwc->ctrl_req_addr, 0, type);
736 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
738 struct dwc3_ep *dep = dwc->eps[epnum];
740 WARN_ON(dwc3_ep0_start_control_status(dep));
743 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
744 const struct dwc3_event_depevt *event)
746 dwc->setup_packet_pending = true;
749 * This part is very tricky: If we has just handled
750 * XferNotReady(Setup) and we're now expecting a
751 * XferComplete but, instead, we receive another
752 * XferNotReady(Setup), we should STALL and restart
755 * In all other cases, we just continue waiting
756 * for the XferComplete event.
758 * We are a little bit unsafe here because we're
759 * not trying to ensure that last event was, indeed,
760 * XferNotReady(Setup).
762 * Still, we don't expect any condition where that
763 * should happen and, even if it does, it would be
764 * another error condition.
766 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
767 switch (event->status) {
768 case DEPEVT_STATUS_CONTROL_SETUP:
769 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
770 dwc3_ep0_stall_and_restart(dwc);
772 case DEPEVT_STATUS_CONTROL_DATA:
774 case DEPEVT_STATUS_CONTROL_STATUS:
777 dev_vdbg(dwc->dev, "waiting for XferComplete\n");
783 switch (event->status) {
784 case DEPEVT_STATUS_CONTROL_SETUP:
785 dev_vdbg(dwc->dev, "Control Setup\n");
787 dwc->ep0state = EP0_SETUP_PHASE;
789 dwc3_ep0_do_control_setup(dwc, event);
792 case DEPEVT_STATUS_CONTROL_DATA:
793 dev_vdbg(dwc->dev, "Control Data\n");
795 dwc->ep0state = EP0_DATA_PHASE;
797 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
798 dev_vdbg(dwc->dev, "Expected %d got %d\n",
802 dwc3_ep0_stall_and_restart(dwc);
807 * One of the possible error cases is when Host _does_
808 * request for Data Phase, but it does so on the wrong
811 * Here, we already know ep0_next_event is DATA (see above),
812 * so we only need to check for direction.
814 if (dwc->ep0_expect_in != event->endpoint_number) {
815 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
816 dwc3_ep0_stall_and_restart(dwc);
820 dwc3_ep0_do_control_data(dwc, event);
823 case DEPEVT_STATUS_CONTROL_STATUS:
824 dev_vdbg(dwc->dev, "Control Status\n");
826 dwc->ep0state = EP0_STATUS_PHASE;
828 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
829 dev_vdbg(dwc->dev, "Expected %d got %d\n",
831 DWC3_EP0_NRDY_STATUS);
833 dwc3_ep0_stall_and_restart(dwc);
837 if (dwc->delayed_status) {
838 WARN_ON_ONCE(event->endpoint_number != 1);
839 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
843 dwc3_ep0_do_control_status(dwc, event->endpoint_number);
847 void dwc3_ep0_interrupt(struct dwc3 *dwc,
848 const struct dwc3_event_depevt *event)
850 u8 epnum = event->endpoint_number;
852 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
853 dwc3_ep_event_string(event->endpoint_event),
854 epnum >> 1, (epnum & 1) ? "in" : "out",
855 dwc3_ep0_state_string(dwc->ep0state));
857 switch (event->endpoint_event) {
858 case DWC3_DEPEVT_XFERCOMPLETE:
859 dwc3_ep0_xfer_complete(dwc, event);
862 case DWC3_DEPEVT_XFERNOTREADY:
863 dwc3_ep0_xfernotready(dwc, event);
866 case DWC3_DEPEVT_XFERINPROGRESS:
867 case DWC3_DEPEVT_RXTXFIFOEVT:
868 case DWC3_DEPEVT_STREAMEVT:
869 case DWC3_DEPEVT_EPCMDCMPLT: