2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
59 u32 len, u32 type, bool chain)
61 struct dwc3_gadget_ep_cmd_params params;
67 dep = dwc->eps[epnum];
68 if (dep->flags & DWC3_EP_BUSY) {
69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
73 trb = &dwc->ep0_trb[dep->free_slot];
78 trb->bpl = lower_32_bits(buf_dma);
79 trb->bph = upper_32_bits(buf_dma);
83 trb->ctrl |= (DWC3_TRB_CTRL_HWO
84 | DWC3_TRB_CTRL_ISP_IMI);
87 trb->ctrl |= DWC3_TRB_CTRL_CHN;
89 trb->ctrl |= (DWC3_TRB_CTRL_IOC
95 memset(¶ms, 0, sizeof(params));
96 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
97 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
99 trace_dwc3_prepare_trb(dep, trb);
101 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
102 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
104 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
109 dep->flags |= DWC3_EP_BUSY;
110 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
113 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
119 struct dwc3_request *req)
121 struct dwc3 *dwc = dep->dwc;
123 req->request.actual = 0;
124 req->request.status = -EINPROGRESS;
125 req->epnum = dep->number;
127 list_add_tail(&req->list, &dep->request_list);
130 * Gadget driver might not be quick enough to queue a request
131 * before we get a Transfer Not Ready event on this endpoint.
133 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
134 * flag is set, it's telling us that as soon as Gadget queues the
135 * required request, we should kick the transfer here because the
136 * IRQ we were waiting for is long gone.
138 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
141 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
143 if (dwc->ep0state != EP0_DATA_PHASE) {
144 dev_WARN(dwc->dev, "Unexpected pending request\n");
148 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
150 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
157 * In case gadget driver asked us to delay the STATUS phase,
160 if (dwc->delayed_status) {
163 direction = !dwc->ep0_expect_in;
164 dwc->delayed_status = false;
165 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
167 if (dwc->ep0state == EP0_STATUS_PHASE)
168 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
170 dwc3_trace(trace_dwc3_ep0,
171 "too early for delayed status");
177 * Unfortunately we have uncovered a limitation wrt the Data Phase.
179 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
180 * come before issueing Start Transfer command, but if we do, we will
181 * miss situations where the host starts another SETUP phase instead of
182 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
183 * Layer Compliance Suite.
185 * The problem surfaces due to the fact that in case of back-to-back
186 * SETUP packets there will be no XferNotReady(DATA) generated and we
187 * will be stuck waiting for XferNotReady(DATA) forever.
189 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
190 * it tells us to start Data Phase right away. It also mentions that if
191 * we receive a SETUP phase instead of the DATA phase, core will issue
192 * XferComplete for the DATA phase, before actually initiating it in
193 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
194 * can only be used to print some debugging logs, as the core expects
195 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
196 * just so it completes right away, without transferring anything and,
197 * only then, we can go back to the SETUP phase.
199 * Because of this scenario, SNPS decided to change the programming
200 * model of control transfers and support on-demand transfers only for
201 * the STATUS phase. To fix the issue we have now, we will always wait
202 * for gadget driver to queue the DATA phase's struct usb_request, then
203 * start it right away.
205 * If we're actually in a 2-stage transfer, we will wait for
206 * XferNotReady(STATUS).
208 if (dwc->three_stage_setup) {
211 direction = dwc->ep0_expect_in;
212 dwc->ep0state = EP0_DATA_PHASE;
214 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
216 dep->flags &= ~DWC3_EP0_DIR_IN;
222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
225 struct dwc3_request *req = to_dwc3_request(request);
226 struct dwc3_ep *dep = to_dwc3_ep(ep);
227 struct dwc3 *dwc = dep->dwc;
233 spin_lock_irqsave(&dwc->lock, flags);
234 if (!dep->endpoint.desc) {
235 dwc3_trace(trace_dwc3_ep0,
236 "trying to queue request %p to disabled %s",
242 /* we share one TRB for ep0/1 */
243 if (!list_empty(&dep->request_list)) {
248 dwc3_trace(trace_dwc3_ep0,
249 "queueing request %p to %s length %d state '%s'",
250 request, dep->name, request->length,
251 dwc3_ep0_state_string(dwc->ep0state));
253 ret = __dwc3_gadget_ep0_queue(dep, req);
256 spin_unlock_irqrestore(&dwc->lock, flags);
261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
265 /* reinitialize physical ep1 */
267 dep->flags = DWC3_EP_ENABLED;
269 /* stall is always issued on EP0 */
271 __dwc3_gadget_ep_set_halt(dep, 1, false);
272 dep->flags = DWC3_EP_ENABLED;
273 dwc->delayed_status = false;
275 if (!list_empty(&dep->request_list)) {
276 struct dwc3_request *req;
278 req = next_request(&dep->request_list);
279 dwc3_gadget_giveback(dep, req, -ECONNRESET);
282 dwc->ep0state = EP0_SETUP_PHASE;
283 dwc3_ep0_out_start(dwc);
286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
288 struct dwc3_ep *dep = to_dwc3_ep(ep);
289 struct dwc3 *dwc = dep->dwc;
291 dwc3_ep0_stall_and_restart(dwc);
296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
298 struct dwc3_ep *dep = to_dwc3_ep(ep);
299 struct dwc3 *dwc = dep->dwc;
303 spin_lock_irqsave(&dwc->lock, flags);
304 ret = __dwc3_gadget_ep0_set_halt(ep, value);
305 spin_unlock_irqrestore(&dwc->lock, flags);
310 void dwc3_ep0_out_start(struct dwc3 *dwc)
314 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
315 DWC3_TRBCTL_CONTROL_SETUP, false);
319 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
322 u32 windex = le16_to_cpu(wIndex_le);
325 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
326 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
329 dep = dwc->eps[epnum];
330 if (dep->flags & DWC3_EP_ENABLED)
336 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
342 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
343 struct usb_ctrlrequest *ctrl)
349 __le16 *response_pkt;
351 recip = ctrl->bRequestType & USB_RECIP_MASK;
353 case USB_RECIP_DEVICE:
355 * LTM will be set once we know how to set this in HW.
357 usb_status |= dwc->gadget.is_selfpowered;
359 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 if (reg & DWC3_DCTL_INITU1ENA)
362 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
363 if (reg & DWC3_DCTL_INITU2ENA)
364 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
369 case USB_RECIP_INTERFACE:
371 * Function Remote Wake Capable D0
372 * Function Remote Wakeup D1
376 case USB_RECIP_ENDPOINT:
377 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
381 if (dep->flags & DWC3_EP_STALL)
382 usb_status = 1 << USB_ENDPOINT_HALT;
388 response_pkt = (__le16 *) dwc->setup_buf;
389 *response_pkt = cpu_to_le16(usb_status);
392 dwc->ep0_usb_req.dep = dep;
393 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
394 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
395 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
397 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
400 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
401 struct usb_ctrlrequest *ctrl, int set)
409 enum usb_device_state state;
411 wValue = le16_to_cpu(ctrl->wValue);
412 wIndex = le16_to_cpu(ctrl->wIndex);
413 recip = ctrl->bRequestType & USB_RECIP_MASK;
414 state = dwc->gadget.state;
417 case USB_RECIP_DEVICE:
420 case USB_DEVICE_REMOTE_WAKEUP:
423 * 9.4.1 says only only for SS, in AddressState only for
424 * default control pipe
426 case USB_DEVICE_U1_ENABLE:
427 if (state != USB_STATE_CONFIGURED)
429 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
432 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 reg |= DWC3_DCTL_INITU1ENA;
436 reg &= ~DWC3_DCTL_INITU1ENA;
437 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
440 case USB_DEVICE_U2_ENABLE:
441 if (state != USB_STATE_CONFIGURED)
443 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
446 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
448 reg |= DWC3_DCTL_INITU2ENA;
450 reg &= ~DWC3_DCTL_INITU2ENA;
451 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
454 case USB_DEVICE_LTM_ENABLE:
457 case USB_DEVICE_TEST_MODE:
458 if ((wIndex & 0xff) != 0)
463 dwc->test_mode_nr = wIndex >> 8;
464 dwc->test_mode = true;
471 case USB_RECIP_INTERFACE:
473 case USB_INTRF_FUNC_SUSPEND:
474 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
475 /* XXX enable Low power suspend */
477 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
478 /* XXX enable remote wakeup */
486 case USB_RECIP_ENDPOINT:
488 case USB_ENDPOINT_HALT:
489 dep = dwc3_wIndex_to_dep(dwc, wIndex);
492 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
494 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
510 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
512 enum usb_device_state state = dwc->gadget.state;
516 addr = le16_to_cpu(ctrl->wValue);
518 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
522 if (state == USB_STATE_CONFIGURED) {
523 dwc3_trace(trace_dwc3_ep0,
524 "trying to set address when configured");
528 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
529 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
530 reg |= DWC3_DCFG_DEVADDR(addr);
531 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
534 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
536 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
541 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
545 spin_unlock(&dwc->lock);
546 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
547 spin_lock(&dwc->lock);
551 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
553 enum usb_device_state state = dwc->gadget.state;
558 cfg = le16_to_cpu(ctrl->wValue);
561 case USB_STATE_DEFAULT:
564 case USB_STATE_ADDRESS:
565 ret = dwc3_ep0_delegate_req(dwc, ctrl);
566 /* if the cfg matches and the cfg is non zero */
567 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
570 * only change state if set_config has already
571 * been processed. If gadget driver returns
572 * USB_GADGET_DELAYED_STATUS, we will wait
573 * to change the state on the next usb_ep_queue()
576 usb_gadget_set_state(&dwc->gadget,
577 USB_STATE_CONFIGURED);
580 * Enable transition to U1/U2 state when
581 * nothing is pending from application.
583 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
584 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
585 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
587 dwc->resize_fifos = true;
588 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
592 case USB_STATE_CONFIGURED:
593 ret = dwc3_ep0_delegate_req(dwc, ctrl);
595 usb_gadget_set_state(&dwc->gadget,
604 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
606 struct dwc3_ep *dep = to_dwc3_ep(ep);
607 struct dwc3 *dwc = dep->dwc;
621 memcpy(&timing, req->buf, sizeof(timing));
623 dwc->u1sel = timing.u1sel;
624 dwc->u1pel = timing.u1pel;
625 dwc->u2sel = le16_to_cpu(timing.u2sel);
626 dwc->u2pel = le16_to_cpu(timing.u2pel);
628 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
629 if (reg & DWC3_DCTL_INITU2ENA)
631 if (reg & DWC3_DCTL_INITU1ENA)
635 * According to Synopsys Databook, if parameter is
636 * greater than 125, a value of zero should be
637 * programmed in the register.
642 /* now that we have the time, issue DGCMD Set Sel */
643 ret = dwc3_send_gadget_generic_command(dwc,
644 DWC3_DGCMD_SET_PERIODIC_PAR, param);
648 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
651 enum usb_device_state state = dwc->gadget.state;
655 if (state == USB_STATE_DEFAULT)
658 wValue = le16_to_cpu(ctrl->wValue);
659 wLength = le16_to_cpu(ctrl->wLength);
662 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
668 * To handle Set SEL we need to receive 6 bytes from Host. So let's
669 * queue a usb_request for 6 bytes.
671 * Remember, though, this controller can't handle non-wMaxPacketSize
672 * aligned transfers on the OUT direction, so we queue a request for
673 * wMaxPacketSize instead.
676 dwc->ep0_usb_req.dep = dep;
677 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
678 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
679 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
681 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
684 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
690 wValue = le16_to_cpu(ctrl->wValue);
691 wLength = le16_to_cpu(ctrl->wLength);
692 wIndex = le16_to_cpu(ctrl->wIndex);
694 if (wIndex || wLength)
698 * REVISIT It's unclear from Databook what to do with this
699 * value. For now, just cache it.
701 dwc->isoch_delay = wValue;
706 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
710 switch (ctrl->bRequest) {
711 case USB_REQ_GET_STATUS:
712 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
713 ret = dwc3_ep0_handle_status(dwc, ctrl);
715 case USB_REQ_CLEAR_FEATURE:
716 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
717 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
719 case USB_REQ_SET_FEATURE:
720 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
721 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
723 case USB_REQ_SET_ADDRESS:
724 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
725 ret = dwc3_ep0_set_address(dwc, ctrl);
727 case USB_REQ_SET_CONFIGURATION:
728 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
729 ret = dwc3_ep0_set_config(dwc, ctrl);
731 case USB_REQ_SET_SEL:
732 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
733 ret = dwc3_ep0_set_sel(dwc, ctrl);
735 case USB_REQ_SET_ISOCH_DELAY:
736 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
737 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
740 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
741 ret = dwc3_ep0_delegate_req(dwc, ctrl);
748 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
749 const struct dwc3_event_depevt *event)
751 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
755 if (!dwc->gadget_driver)
758 trace_dwc3_ctrl_req(ctrl);
760 len = le16_to_cpu(ctrl->wLength);
762 dwc->three_stage_setup = false;
763 dwc->ep0_expect_in = false;
764 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
766 dwc->three_stage_setup = true;
767 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
768 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
771 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
772 ret = dwc3_ep0_std_request(dwc, ctrl);
774 ret = dwc3_ep0_delegate_req(dwc, ctrl);
776 if (ret == USB_GADGET_DELAYED_STATUS)
777 dwc->delayed_status = true;
781 dwc3_ep0_stall_and_restart(dwc);
784 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
785 const struct dwc3_event_depevt *event)
787 struct dwc3_request *r = NULL;
788 struct usb_request *ur;
789 struct dwc3_trb *trb;
791 unsigned transfer_size = 0;
793 unsigned remaining_ur_length;
800 epnum = event->endpoint_number;
803 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
807 trace_dwc3_complete_trb(ep0, trb);
809 r = next_request(&ep0->request_list);
813 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
814 if (status == DWC3_TRBSTS_SETUP_PENDING) {
815 dwc->setup_packet_pending = true;
817 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
820 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
827 remaining_ur_length = ur->length;
829 length = trb->size & DWC3_TRB_SIZE_MASK;
831 maxp = ep0->endpoint.maxpacket;
833 if (dwc->ep0_bounced) {
835 * Handle the first TRB before handling the bounce buffer if
836 * the request length is greater than the bounce buffer size
838 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
839 transfer_size = ALIGN(ur->length - maxp, maxp);
840 transferred = transfer_size - length;
841 buf = (u8 *)buf + transferred;
842 ur->actual += transferred;
843 remaining_ur_length -= transferred;
846 length = trb->size & DWC3_TRB_SIZE_MASK;
851 transfer_size = roundup((ur->length - transfer_size),
854 transferred = min_t(u32, remaining_ur_length,
855 transfer_size - length);
856 memcpy(buf, dwc->ep0_bounce, transferred);
858 transferred = ur->length - length;
861 ur->actual += transferred;
863 if ((epnum & 1) && ur->actual < ur->length) {
864 /* for some reason we did not get everything out */
866 dwc3_ep0_stall_and_restart(dwc);
868 dwc3_gadget_giveback(ep0, r, 0);
870 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
871 ur->length && ur->zero) {
874 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
876 ret = dwc3_ep0_start_trans(dwc, epnum,
877 dwc->ctrl_req_addr, 0,
878 DWC3_TRBCTL_CONTROL_DATA, false);
884 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
885 const struct dwc3_event_depevt *event)
887 struct dwc3_request *r;
889 struct dwc3_trb *trb;
895 trace_dwc3_complete_trb(dep, trb);
897 if (!list_empty(&dep->request_list)) {
898 r = next_request(&dep->request_list);
900 dwc3_gadget_giveback(dep, r, 0);
903 if (dwc->test_mode) {
906 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
908 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
910 dwc3_ep0_stall_and_restart(dwc);
915 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
916 if (status == DWC3_TRBSTS_SETUP_PENDING) {
917 dwc->setup_packet_pending = true;
918 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
921 dwc->ep0state = EP0_SETUP_PHASE;
922 dwc3_ep0_out_start(dwc);
925 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
926 const struct dwc3_event_depevt *event)
928 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
930 dep->flags &= ~DWC3_EP_BUSY;
931 dep->resource_index = 0;
932 dwc->setup_packet_pending = false;
934 switch (dwc->ep0state) {
935 case EP0_SETUP_PHASE:
936 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
937 dwc3_ep0_inspect_setup(dwc, event);
941 dwc3_trace(trace_dwc3_ep0, "Data Phase");
942 dwc3_ep0_complete_data(dwc, event);
945 case EP0_STATUS_PHASE:
946 dwc3_trace(trace_dwc3_ep0, "Status Phase");
947 dwc3_ep0_complete_status(dwc, event);
950 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
954 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
955 struct dwc3_ep *dep, struct dwc3_request *req)
959 req->direction = !!dep->number;
961 if (req->request.length == 0) {
962 ret = dwc3_ep0_start_trans(dwc, dep->number,
963 dwc->ctrl_req_addr, 0,
964 DWC3_TRBCTL_CONTROL_DATA, false);
965 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
966 && (dep->number == 0)) {
967 u32 transfer_size = 0;
970 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
973 dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
977 maxpacket = dep->endpoint.maxpacket;
979 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
980 transfer_size = ALIGN(req->request.length - maxpacket,
982 ret = dwc3_ep0_start_trans(dwc, dep->number,
985 DWC3_TRBCTL_CONTROL_DATA,
989 transfer_size = roundup((req->request.length - transfer_size),
992 dwc->ep0_bounced = true;
994 ret = dwc3_ep0_start_trans(dwc, dep->number,
995 dwc->ep0_bounce_addr, transfer_size,
996 DWC3_TRBCTL_CONTROL_DATA, false);
998 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1001 dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1005 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1006 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1013 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1015 struct dwc3 *dwc = dep->dwc;
1018 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1019 : DWC3_TRBCTL_CONTROL_STATUS2;
1021 return dwc3_ep0_start_trans(dwc, dep->number,
1022 dwc->ctrl_req_addr, 0, type, false);
1025 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1027 if (dwc->resize_fifos) {
1028 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1029 dwc3_gadget_resize_tx_fifos(dwc);
1030 dwc->resize_fifos = 0;
1033 WARN_ON(dwc3_ep0_start_control_status(dep));
1036 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1037 const struct dwc3_event_depevt *event)
1039 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1041 __dwc3_ep0_do_control_status(dwc, dep);
1044 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1046 struct dwc3_gadget_ep_cmd_params params;
1050 if (!dep->resource_index)
1053 cmd = DWC3_DEPCMD_ENDTRANSFER;
1054 cmd |= DWC3_DEPCMD_CMDIOC;
1055 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1056 memset(¶ms, 0, sizeof(params));
1057 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1059 dep->resource_index = 0;
1062 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1063 const struct dwc3_event_depevt *event)
1065 switch (event->status) {
1066 case DEPEVT_STATUS_CONTROL_DATA:
1067 dwc3_trace(trace_dwc3_ep0, "Control Data");
1070 * We already have a DATA transfer in the controller's cache,
1071 * if we receive a XferNotReady(DATA) we will ignore it, unless
1072 * it's for the wrong direction.
1074 * In that case, we must issue END_TRANSFER command to the Data
1075 * Phase we already have started and issue SetStall on the
1078 if (dwc->ep0_expect_in != event->endpoint_number) {
1079 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1081 dwc3_trace(trace_dwc3_ep0,
1082 "Wrong direction for Data phase");
1083 dwc3_ep0_end_control_data(dwc, dep);
1084 dwc3_ep0_stall_and_restart(dwc);
1090 case DEPEVT_STATUS_CONTROL_STATUS:
1091 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1094 dwc3_trace(trace_dwc3_ep0, "Control Status");
1096 dwc->ep0state = EP0_STATUS_PHASE;
1098 if (dwc->delayed_status) {
1099 WARN_ON_ONCE(event->endpoint_number != 1);
1100 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1104 dwc3_ep0_do_control_status(dwc, event);
1108 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1109 const struct dwc3_event_depevt *event)
1111 u8 epnum = event->endpoint_number;
1113 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1114 dwc3_ep_event_string(event->endpoint_event),
1115 epnum >> 1, (epnum & 1) ? "in" : "out",
1116 dwc3_ep0_state_string(dwc->ep0state));
1118 switch (event->endpoint_event) {
1119 case DWC3_DEPEVT_XFERCOMPLETE:
1120 dwc3_ep0_xfer_complete(dwc, event);
1123 case DWC3_DEPEVT_XFERNOTREADY:
1124 dwc3_ep0_xfernotready(dwc, event);
1127 case DWC3_DEPEVT_XFERINPROGRESS:
1128 case DWC3_DEPEVT_RXTXFIFOEVT:
1129 case DWC3_DEPEVT_STREAMEVT:
1130 case DWC3_DEPEVT_EPCMDCMPLT: