drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36 {
  37         struct dwc3_trb                 *trb;
  38         struct dwc3                     *dwc;
  39
  40         dwc = dep->dwc;
  41         trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43         if (chain)
  44                 dep->trb_enqueue++;
  45
  46         trb->bpl = lower_32_bits(buf_dma);
  47         trb->bph = upper_32_bits(buf_dma);
  48         trb->size = len;
  49         trb->ctrl = type;
  50
  51         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                         | DWC3_TRB_CTRL_ISP_IMI);
  53
  54         if (chain)
  55                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56         else
  57                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                 | DWC3_TRB_CTRL_LST);
  59
  60         trace_dwc3_prepare_trb(dep, trb);
  61 }
  62
  63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64 {
  65         struct dwc3_gadget_ep_cmd_params params;
  66         struct dwc3                     *dwc;
  67         int                             ret;
  68
  69         if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  70                 return 0;
  71
  72         dwc = dep->dwc;
  73
  74         memset(&params, 0, sizeof(params));
  75         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79         if (ret < 0)
  80                 return ret;
  81
  82         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  83
  84         return 0;
  85 }
  86
  87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  88                 struct dwc3_request *req)
  89 {
  90         struct dwc3             *dwc = dep->dwc;
  91
  92         req->request.actual     = 0;
  93         req->request.status     = -EINPROGRESS;
  94         req->epnum              = dep->number;
  95
  96         list_add_tail(&req->list, &dep->pending_list);
  97
  98         /*
  99          * Gadget driver might not be quick enough to queue a request
 100          * before we get a Transfer Not Ready event on this endpoint.
 101          *
 102          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 103          * flag is set, it's telling us that as soon as Gadget queues the
 104          * required request, we should kick the transfer here because the
 105          * IRQ we were waiting for is long gone.
 106          */
 107         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 108                 unsigned int direction;
 109
 110                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 111
 112                 if (dwc->ep0state != EP0_DATA_PHASE) {
 113                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 114                         return 0;
 115                 }
 116
 117                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 118
 119                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 120                                 DWC3_EP0_DIR_IN);
 121
 122                 return 0;
 123         }
 124
 125         /*
 126          * In case gadget driver asked us to delay the STATUS phase,
 127          * handle it here.
 128          */
 129         if (dwc->delayed_status) {
 130                 unsigned int direction;
 131
 132                 direction = !dwc->ep0_expect_in;
 133                 dwc->delayed_status = false;
 134                 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
 135
 136                 if (dwc->ep0state == EP0_STATUS_PHASE)
 137                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 138
 139                 return 0;
 140         }
 141
 142         /*
 143          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 144          *
 145          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 146          * come before issueing Start Transfer command, but if we do, we will
 147          * miss situations where the host starts another SETUP phase instead of
 148          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 149          * Layer Compliance Suite.
 150          *
 151          * The problem surfaces due to the fact that in case of back-to-back
 152          * SETUP packets there will be no XferNotReady(DATA) generated and we
 153          * will be stuck waiting for XferNotReady(DATA) forever.
 154          *
 155          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 156          * it tells us to start Data Phase right away. It also mentions that if
 157          * we receive a SETUP phase instead of the DATA phase, core will issue
 158          * XferComplete for the DATA phase, before actually initiating it in
 159          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 160          * can only be used to print some debugging logs, as the core expects
 161          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 162          * just so it completes right away, without transferring anything and,
 163          * only then, we can go back to the SETUP phase.
 164          *
 165          * Because of this scenario, SNPS decided to change the programming
 166          * model of control transfers and support on-demand transfers only for
 167          * the STATUS phase. To fix the issue we have now, we will always wait
 168          * for gadget driver to queue the DATA phase's struct usb_request, then
 169          * start it right away.
 170          *
 171          * If we're actually in a 2-stage transfer, we will wait for
 172          * XferNotReady(STATUS).
 173          */
 174         if (dwc->three_stage_setup) {
 175                 unsigned int direction;
 176
 177                 direction = dwc->ep0_expect_in;
 178                 dwc->ep0state = EP0_DATA_PHASE;
 179
 180                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 181
 182                 dep->flags &= ~DWC3_EP0_DIR_IN;
 183         }
 184
 185         return 0;
 186 }
 187
 188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 189                 gfp_t gfp_flags)
 190 {
 191         struct dwc3_request             *req = to_dwc3_request(request);
 192         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 193         struct dwc3                     *dwc = dep->dwc;
 194
 195         unsigned long                   flags;
 196
 197         int                             ret;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
 201                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 202                                 dep->name);
 203                 ret = -ESHUTDOWN;
 204                 goto out;
 205         }
 206
 207         /* we share one TRB for ep0/1 */
 208         if (!list_empty(&dep->pending_list)) {
 209                 ret = -EBUSY;
 210                 goto out;
 211         }
 212
 213         ret = __dwc3_gadget_ep0_queue(dep, req);
 214
 215 out:
 216         spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218         return ret;
 219 }
 220
 221 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 222 {
 223         struct dwc3_ep          *dep;
 224
 225         /* reinitialize physical ep1 */
 226         dep = dwc->eps[1];
 227         dep->flags = DWC3_EP_ENABLED;
 228
 229         /* stall is always issued on EP0 */
 230         dep = dwc->eps[0];
 231         __dwc3_gadget_ep_set_halt(dep, 1, false);
 232         dep->flags = DWC3_EP_ENABLED;
 233         dwc->delayed_status = false;
 234
 235         if (!list_empty(&dep->pending_list)) {
 236                 struct dwc3_request     *req;
 237
 238                 req = next_request(&dep->pending_list);
 239                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 240         }
 241
 242         dwc->eps[0]->trb_enqueue = 0;
 243         dwc->eps[1]->trb_enqueue = 0;
 244         dwc->ep0state = EP0_SETUP_PHASE;
 245         dwc3_ep0_out_start(dwc);
 246 }
 247
 248 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 249 {
 250         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 251         struct dwc3                     *dwc = dep->dwc;
 252
 253         dwc3_ep0_stall_and_restart(dwc);
 254
 255         return 0;
 256 }
 257
 258 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 259 {
 260         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 261         struct dwc3                     *dwc = dep->dwc;
 262         unsigned long                   flags;
 263         int                             ret;
 264
 265         spin_lock_irqsave(&dwc->lock, flags);
 266         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 267         spin_unlock_irqrestore(&dwc->lock, flags);
 268
 269         return ret;
 270 }
 271
 272 void dwc3_ep0_out_start(struct dwc3 *dwc)
 273 {
 274         struct dwc3_ep                  *dep;
 275         int                             ret;
 276         int                             i;
 277
 278         complete(&dwc->ep0_in_setup);
 279
 280         dep = dwc->eps[0];
 281         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 282                         DWC3_TRBCTL_CONTROL_SETUP, false);
 283         ret = dwc3_ep0_start_trans(dep);
 284         WARN_ON(ret < 0);
 285         for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
 286                 struct dwc3_ep *dwc3_ep;
 287
 288                 dwc3_ep = dwc->eps[i];
 289                 if (!dwc3_ep)
 290                         continue;
 291
 292                 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
 293                         continue;
 294
 295                 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
 296                 if (dwc->connected)
 297                         dwc3_stop_active_transfer(dwc3_ep, true, true);
 298                 else
 299                         dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
 300         }
 301 }
 302
 303 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 304 {
 305         struct dwc3_ep          *dep;
 306         u32                     windex = le16_to_cpu(wIndex_le);
 307         u32                     epnum;
 308
 309         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 310         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 311                 epnum |= 1;
 312
 313         dep = dwc->eps[epnum];
 314         if (dep == NULL)
 315                 return NULL;
 316
 317         if (dep->flags & DWC3_EP_ENABLED)
 318                 return dep;
 319
 320         return NULL;
 321 }
 322
 323 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 324 {
 325 }
 326 /*
 327  * ch 9.4.5
 328  */
 329 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 330                 struct usb_ctrlrequest *ctrl)
 331 {
 332         struct dwc3_ep          *dep;
 333         u32                     recip;
 334         u32                     value;
 335         u32                     reg;
 336         u16                     usb_status = 0;
 337         __le16                  *response_pkt;
 338
 339         /* We don't support PTM_STATUS */
 340         value = le16_to_cpu(ctrl->wValue);
 341         if (value != 0)
 342                 return -EINVAL;
 343
 344         recip = ctrl->bRequestType & USB_RECIP_MASK;
 345         switch (recip) {
 346         case USB_RECIP_DEVICE:
 347                 /*
 348                  * LTM will be set once we know how to set this in HW.
 349                  */
 350                 usb_status |= dwc->gadget->is_selfpowered;
 351
 352                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 353                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 354                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 355                         if (reg & DWC3_DCTL_INITU1ENA)
 356                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 357                         if (reg & DWC3_DCTL_INITU2ENA)
 358                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 359                 } else {
 360                         usb_status |= dwc->gadget->wakeup_armed <<
 361                                         USB_DEVICE_REMOTE_WAKEUP;
 362                 }
 363
 364                 break;
 365
 366         case USB_RECIP_INTERFACE:
 367                 /*
 368                  * Function Remote Wake Capable D0
 369                  * Function Remote Wakeup       D1
 370                  */
 371                 break;
 372
 373         case USB_RECIP_ENDPOINT:
 374                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 375                 if (!dep)
 376                         return -EINVAL;
 377
 378                 if (dep->flags & DWC3_EP_STALL)
 379                         usb_status = 1 << USB_ENDPOINT_HALT;
 380                 break;
 381         default:
 382                 return -EINVAL;
 383         }
 384
 385         response_pkt = (__le16 *) dwc->setup_buf;
 386         *response_pkt = cpu_to_le16(usb_status);
 387
 388         dep = dwc->eps[0];
 389         dwc->ep0_usb_req.dep = dep;
 390         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 391         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 392         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 393
 394         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 395 }
 396
 397 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 398                 int set)
 399 {
 400         u32 reg;
 401
 402         if (state != USB_STATE_CONFIGURED)
 403                 return -EINVAL;
 404         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 405                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 406                 return -EINVAL;
 407         if (set && dwc->dis_u1_entry_quirk)
 408                 return -EINVAL;
 409
 410         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 411         if (set)
 412                 reg |= DWC3_DCTL_INITU1ENA;
 413         else
 414                 reg &= ~DWC3_DCTL_INITU1ENA;
 415         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 416
 417         return 0;
 418 }
 419
 420 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 421                 int set)
 422 {
 423         u32 reg;
 424
 425
 426         if (state != USB_STATE_CONFIGURED)
 427                 return -EINVAL;
 428         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 429                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 430                 return -EINVAL;
 431         if (set && dwc->dis_u2_entry_quirk)
 432                 return -EINVAL;
 433
 434         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435         if (set)
 436                 reg |= DWC3_DCTL_INITU2ENA;
 437         else
 438                 reg &= ~DWC3_DCTL_INITU2ENA;
 439         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440
 441         return 0;
 442 }
 443
 444 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 445                 u32 wIndex, int set)
 446 {
 447         if ((wIndex & 0xff) != 0)
 448                 return -EINVAL;
 449         if (!set)
 450                 return -EINVAL;
 451
 452         switch (wIndex >> 8) {
 453         case USB_TEST_J:
 454         case USB_TEST_K:
 455         case USB_TEST_SE0_NAK:
 456         case USB_TEST_PACKET:
 457         case USB_TEST_FORCE_ENABLE:
 458                 dwc->test_mode_nr = wIndex >> 8;
 459                 dwc->test_mode = true;
 460                 break;
 461         default:
 462                 return -EINVAL;
 463         }
 464
 465         return 0;
 466 }
 467
 468 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 469                 struct usb_ctrlrequest *ctrl, int set)
 470 {
 471         enum usb_device_state   state;
 472         u32                     wValue;
 473         u32                     wIndex;
 474         int                     ret = 0;
 475
 476         wValue = le16_to_cpu(ctrl->wValue);
 477         wIndex = le16_to_cpu(ctrl->wIndex);
 478         state = dwc->gadget->state;
 479
 480         switch (wValue) {
 481         case USB_DEVICE_REMOTE_WAKEUP:
 482                 if (dwc->wakeup_configured)
 483                         dwc->gadget->wakeup_armed = set;
 484                 else
 485                         ret = -EINVAL;
 486                 break;
 487         /*
 488          * 9.4.1 says only for SS, in AddressState only for
 489          * default control pipe
 490          */
 491         case USB_DEVICE_U1_ENABLE:
 492                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 493                 break;
 494         case USB_DEVICE_U2_ENABLE:
 495                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 496                 break;
 497         case USB_DEVICE_LTM_ENABLE:
 498                 ret = -EINVAL;
 499                 break;
 500         case USB_DEVICE_TEST_MODE:
 501                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 502                 break;
 503         default:
 504                 ret = -EINVAL;
 505         }
 506
 507         return ret;
 508 }
 509
 510 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 511                 struct usb_ctrlrequest *ctrl, int set)
 512 {
 513         u32                     wValue;
 514         int                     ret = 0;
 515
 516         wValue = le16_to_cpu(ctrl->wValue);
 517
 518         switch (wValue) {
 519         case USB_INTRF_FUNC_SUSPEND:
 520                 /*
 521                  * REVISIT: Ideally we would enable some low power mode here,
 522                  * however it's unclear what we should be doing here.
 523                  *
 524                  * For now, we're not doing anything, just making sure we return
 525                  * 0 so USB Command Verifier tests pass without any errors.
 526                  */
 527                 break;
 528         default:
 529                 ret = -EINVAL;
 530         }
 531
 532         return ret;
 533 }
 534
 535 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 536                 struct usb_ctrlrequest *ctrl, int set)
 537 {
 538         struct dwc3_ep          *dep;
 539         u32                     wValue;
 540         int                     ret;
 541
 542         wValue = le16_to_cpu(ctrl->wValue);
 543
 544         switch (wValue) {
 545         case USB_ENDPOINT_HALT:
 546                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 547                 if (!dep)
 548                         return -EINVAL;
 549
 550                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 551                         break;
 552
 553                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 554                 if (ret)
 555                         return -EINVAL;
 556
 557                 /* ClearFeature(Halt) may need delayed status */
 558                 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
 559                         return USB_GADGET_DELAYED_STATUS;
 560
 561                 break;
 562         default:
 563                 return -EINVAL;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 570                 struct usb_ctrlrequest *ctrl, int set)
 571 {
 572         u32                     recip;
 573         int                     ret;
 574
 575         recip = ctrl->bRequestType & USB_RECIP_MASK;
 576
 577         switch (recip) {
 578         case USB_RECIP_DEVICE:
 579                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 580                 break;
 581         case USB_RECIP_INTERFACE:
 582                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 583                 break;
 584         case USB_RECIP_ENDPOINT:
 585                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 586                 break;
 587         default:
 588                 ret = -EINVAL;
 589         }
 590
 591         return ret;
 592 }
 593
 594 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 595 {
 596         enum usb_device_state state = dwc->gadget->state;
 597         u32 addr;
 598         u32 reg;
 599
 600         addr = le16_to_cpu(ctrl->wValue);
 601         if (addr > 127) {
 602                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 603                 return -EINVAL;
 604         }
 605
 606         if (state == USB_STATE_CONFIGURED) {
 607                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 608                 return -EINVAL;
 609         }
 610
 611         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 612         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 613         reg |= DWC3_DCFG_DEVADDR(addr);
 614         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 615
 616         if (addr)
 617                 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
 618         else
 619                 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
 620
 621         return 0;
 622 }
 623
 624 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 625 {
 626         int ret = -EINVAL;
 627
 628         if (dwc->async_callbacks) {
 629                 spin_unlock(&dwc->lock);
 630                 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
 631                 spin_lock(&dwc->lock);
 632         }
 633         return ret;
 634 }
 635
 636 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 637 {
 638         enum usb_device_state state = dwc->gadget->state;
 639         u32 cfg;
 640         int ret;
 641         u32 reg;
 642
 643         cfg = le16_to_cpu(ctrl->wValue);
 644
 645         switch (state) {
 646         case USB_STATE_DEFAULT:
 647                 return -EINVAL;
 648
 649         case USB_STATE_ADDRESS:
 650                 dwc3_gadget_clear_tx_fifos(dwc);
 651
 652                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 653                 /* if the cfg matches and the cfg is non zero */
 654                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 655
 656                         /*
 657                          * only change state if set_config has already
 658                          * been processed. If gadget driver returns
 659                          * USB_GADGET_DELAYED_STATUS, we will wait
 660                          * to change the state on the next usb_ep_queue()
 661                          */
 662                         if (ret == 0)
 663                                 usb_gadget_set_state(dwc->gadget,
 664                                                 USB_STATE_CONFIGURED);
 665
 666                         /*
 667                          * Enable transition to U1/U2 state when
 668                          * nothing is pending from application.
 669                          */
 670                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 671                         if (!dwc->dis_u1_entry_quirk)
 672                                 reg |= DWC3_DCTL_ACCEPTU1ENA;
 673                         if (!dwc->dis_u2_entry_quirk)
 674                                 reg |= DWC3_DCTL_ACCEPTU2ENA;
 675                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 676                 }
 677                 break;
 678
 679         case USB_STATE_CONFIGURED:
 680                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 681                 if (!cfg && !ret)
 682                         usb_gadget_set_state(dwc->gadget,
 683                                         USB_STATE_ADDRESS);
 684                 break;
 685         default:
 686                 ret = -EINVAL;
 687         }
 688         return ret;
 689 }
 690
 691 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 692 {
 693         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 694         struct dwc3     *dwc = dep->dwc;
 695
 696         u32             param = 0;
 697         u32             reg;
 698
 699         struct timing {
 700                 u8      u1sel;
 701                 u8      u1pel;
 702                 __le16  u2sel;
 703                 __le16  u2pel;
 704         } __packed timing;
 705
 706         int             ret;
 707
 708         memcpy(&timing, req->buf, sizeof(timing));
 709
 710         dwc->u1sel = timing.u1sel;
 711         dwc->u1pel = timing.u1pel;
 712         dwc->u2sel = le16_to_cpu(timing.u2sel);
 713         dwc->u2pel = le16_to_cpu(timing.u2pel);
 714
 715         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 716         if (reg & DWC3_DCTL_INITU2ENA)
 717                 param = dwc->u2pel;
 718         if (reg & DWC3_DCTL_INITU1ENA)
 719                 param = dwc->u1pel;
 720
 721         /*
 722          * According to Synopsys Databook, if parameter is
 723          * greater than 125, a value of zero should be
 724          * programmed in the register.
 725          */
 726         if (param > 125)
 727                 param = 0;
 728
 729         /* now that we have the time, issue DGCMD Set Sel */
 730         ret = dwc3_send_gadget_generic_command(dwc,
 731                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 732         WARN_ON(ret < 0);
 733 }
 734
 735 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 736 {
 737         struct dwc3_ep  *dep;
 738         enum usb_device_state state = dwc->gadget->state;
 739         u16             wLength;
 740
 741         if (state == USB_STATE_DEFAULT)
 742                 return -EINVAL;
 743
 744         wLength = le16_to_cpu(ctrl->wLength);
 745
 746         if (wLength != 6) {
 747                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 748                                 wLength);
 749                 return -EINVAL;
 750         }
 751
 752         /*
 753          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 754          * queue a usb_request for 6 bytes.
 755          *
 756          * Remember, though, this controller can't handle non-wMaxPacketSize
 757          * aligned transfers on the OUT direction, so we queue a request for
 758          * wMaxPacketSize instead.
 759          */
 760         dep = dwc->eps[0];
 761         dwc->ep0_usb_req.dep = dep;
 762         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 763         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 764         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 765
 766         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 767 }
 768
 769 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 770 {
 771         u16             wLength;
 772         u16             wValue;
 773         u16             wIndex;
 774
 775         wValue = le16_to_cpu(ctrl->wValue);
 776         wLength = le16_to_cpu(ctrl->wLength);
 777         wIndex = le16_to_cpu(ctrl->wIndex);
 778
 779         if (wIndex || wLength)
 780                 return -EINVAL;
 781
 782         dwc->gadget->isoch_delay = wValue;
 783
 784         return 0;
 785 }
 786
 787 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 788 {
 789         int ret;
 790
 791         switch (ctrl->bRequest) {
 792         case USB_REQ_GET_STATUS:
 793                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 794                 break;
 795         case USB_REQ_CLEAR_FEATURE:
 796                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 797                 break;
 798         case USB_REQ_SET_FEATURE:
 799                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 800                 break;
 801         case USB_REQ_SET_ADDRESS:
 802                 ret = dwc3_ep0_set_address(dwc, ctrl);
 803                 break;
 804         case USB_REQ_SET_CONFIGURATION:
 805                 ret = dwc3_ep0_set_config(dwc, ctrl);
 806                 break;
 807         case USB_REQ_SET_SEL:
 808                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 809                 break;
 810         case USB_REQ_SET_ISOCH_DELAY:
 811                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 812                 break;
 813         default:
 814                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 815                 break;
 816         }
 817
 818         return ret;
 819 }
 820
 821 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 822                 const struct dwc3_event_depevt *event)
 823 {
 824         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 825         int ret = -EINVAL;
 826         u32 len;
 827
 828         if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
 829                 goto out;
 830
 831         trace_dwc3_ctrl_req(ctrl);
 832
 833         len = le16_to_cpu(ctrl->wLength);
 834         if (!len) {
 835                 dwc->three_stage_setup = false;
 836                 dwc->ep0_expect_in = false;
 837                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 838         } else {
 839                 dwc->three_stage_setup = true;
 840                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 841                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 842         }
 843
 844         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 845                 ret = dwc3_ep0_std_request(dwc, ctrl);
 846         else
 847                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 848
 849         if (ret == USB_GADGET_DELAYED_STATUS)
 850                 dwc->delayed_status = true;
 851
 852 out:
 853         if (ret < 0)
 854                 dwc3_ep0_stall_and_restart(dwc);
 855 }
 856
 857 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 858                 const struct dwc3_event_depevt *event)
 859 {
 860         struct dwc3_request     *r;
 861         struct usb_request      *ur;
 862         struct dwc3_trb         *trb;
 863         struct dwc3_ep          *ep0;
 864         u32                     transferred = 0;
 865         u32                     status;
 866         u32                     length;
 867         u8                      epnum;
 868
 869         epnum = event->endpoint_number;
 870         ep0 = dwc->eps[0];
 871
 872         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 873         trb = dwc->ep0_trb;
 874         trace_dwc3_complete_trb(ep0, trb);
 875
 876         r = next_request(&ep0->pending_list);
 877         if (!r)
 878                 return;
 879
 880         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 881         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 882                 dwc->setup_packet_pending = true;
 883                 if (r)
 884                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 885
 886                 return;
 887         }
 888
 889         ur = &r->request;
 890
 891         length = trb->size & DWC3_TRB_SIZE_MASK;
 892         transferred = ur->length - length;
 893         ur->actual += transferred;
 894
 895         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 896              ur->length && ur->zero) || dwc->ep0_bounced) {
 897                 trb++;
 898                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 899                 trace_dwc3_complete_trb(ep0, trb);
 900
 901                 if (r->direction)
 902                         dwc->eps[1]->trb_enqueue = 0;
 903                 else
 904                         dwc->eps[0]->trb_enqueue = 0;
 905
 906                 dwc->ep0_bounced = false;
 907         }
 908
 909         if ((epnum & 1) && ur->actual < ur->length)
 910                 dwc3_ep0_stall_and_restart(dwc);
 911         else
 912                 dwc3_gadget_giveback(ep0, r, 0);
 913 }
 914
 915 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 916                 const struct dwc3_event_depevt *event)
 917 {
 918         struct dwc3_request     *r;
 919         struct dwc3_ep          *dep;
 920         struct dwc3_trb         *trb;
 921         u32                     status;
 922
 923         dep = dwc->eps[0];
 924         trb = dwc->ep0_trb;
 925
 926         trace_dwc3_complete_trb(dep, trb);
 927
 928         if (!list_empty(&dep->pending_list)) {
 929                 r = next_request(&dep->pending_list);
 930
 931                 dwc3_gadget_giveback(dep, r, 0);
 932         }
 933
 934         if (dwc->test_mode) {
 935                 int ret;
 936
 937                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 938                 if (ret < 0) {
 939                         dev_err(dwc->dev, "invalid test #%d\n",
 940                                         dwc->test_mode_nr);
 941                         dwc3_ep0_stall_and_restart(dwc);
 942                         return;
 943                 }
 944         }
 945
 946         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 947         if (status == DWC3_TRBSTS_SETUP_PENDING)
 948                 dwc->setup_packet_pending = true;
 949
 950         dwc->ep0state = EP0_SETUP_PHASE;
 951         dwc3_ep0_out_start(dwc);
 952 }
 953
 954 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 955                         const struct dwc3_event_depevt *event)
 956 {
 957         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 958
 959         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 960         dep->resource_index = 0;
 961         dwc->setup_packet_pending = false;
 962
 963         switch (dwc->ep0state) {
 964         case EP0_SETUP_PHASE:
 965                 dwc3_ep0_inspect_setup(dwc, event);
 966                 break;
 967
 968         case EP0_DATA_PHASE:
 969                 dwc3_ep0_complete_data(dwc, event);
 970                 break;
 971
 972         case EP0_STATUS_PHASE:
 973                 dwc3_ep0_complete_status(dwc, event);
 974                 break;
 975         default:
 976                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 977         }
 978 }
 979
 980 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 981                 struct dwc3_ep *dep, struct dwc3_request *req)
 982 {
 983         unsigned int            trb_length = 0;
 984         int                     ret;
 985
 986         req->direction = !!dep->number;
 987
 988         if (req->request.length == 0) {
 989                 if (!req->direction)
 990                         trb_length = dep->endpoint.maxpacket;
 991
 992                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 993                                 DWC3_TRBCTL_CONTROL_DATA, false);
 994                 ret = dwc3_ep0_start_trans(dep);
 995         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 996                         && (dep->number == 0)) {
 997                 u32     maxpacket;
 998                 u32     rem;
 999
1000                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1001                                 &req->request, dep->number);
1002                 if (ret)
1003                         return;
1004
1005                 maxpacket = dep->endpoint.maxpacket;
1006                 rem = req->request.length % maxpacket;
1007                 dwc->ep0_bounced = true;
1008
1009                 /* prepare normal TRB */
1010                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1011                                          req->request.length,
1012                                          DWC3_TRBCTL_CONTROL_DATA,
1013                                          true);
1014
1015                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1016
1017                 /* Now prepare one extra TRB to align transfer size */
1018                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1019                                          maxpacket - rem,
1020                                          DWC3_TRBCTL_CONTROL_DATA,
1021                                          false);
1022                 ret = dwc3_ep0_start_trans(dep);
1023         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1024                    req->request.length && req->request.zero) {
1025
1026                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1027                                 &req->request, dep->number);
1028                 if (ret)
1029                         return;
1030
1031                 /* prepare normal TRB */
1032                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1033                                          req->request.length,
1034                                          DWC3_TRBCTL_CONTROL_DATA,
1035                                          true);
1036
1037                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1038
1039                 if (!req->direction)
1040                         trb_length = dep->endpoint.maxpacket;
1041
1042                 /* Now prepare one extra TRB to align transfer size */
1043                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1044                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1045                                          false);
1046                 ret = dwc3_ep0_start_trans(dep);
1047         } else {
1048                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1049                                 &req->request, dep->number);
1050                 if (ret)
1051                         return;
1052
1053                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1054                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1055                                 false);
1056
1057                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1058
1059                 ret = dwc3_ep0_start_trans(dep);
1060         }
1061
1062         WARN_ON(ret < 0);
1063 }
1064
1065 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1066 {
1067         struct dwc3             *dwc = dep->dwc;
1068         u32                     type;
1069
1070         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1071                 : DWC3_TRBCTL_CONTROL_STATUS2;
1072
1073         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1074         return dwc3_ep0_start_trans(dep);
1075 }
1076
1077 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1078 {
1079         WARN_ON(dwc3_ep0_start_control_status(dep));
1080 }
1081
1082 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1083                 const struct dwc3_event_depevt *event)
1084 {
1085         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1086
1087         __dwc3_ep0_do_control_status(dwc, dep);
1088 }
1089
1090 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1091 {
1092         unsigned int direction = !dwc->ep0_expect_in;
1093
1094         dwc->delayed_status = false;
1095         dwc->clear_stall_protocol = 0;
1096
1097         if (dwc->ep0state != EP0_STATUS_PHASE)
1098                 return;
1099
1100         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1101 }
1102
1103 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1104 {
1105         struct dwc3_gadget_ep_cmd_params params;
1106         u32                     cmd;
1107         int                     ret;
1108
1109         /*
1110          * For status/DATA OUT stage, TRB will be queued on ep0 out
1111          * endpoint for which resource index is zero. Hence allow
1112          * queuing ENDXFER command for ep0 out endpoint.
1113          */
1114         if (!dep->resource_index && dep->number)
1115                 return;
1116
1117         cmd = DWC3_DEPCMD_ENDTRANSFER;
1118         cmd |= DWC3_DEPCMD_CMDIOC;
1119         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1120         memset(&params, 0, sizeof(params));
1121         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1122         WARN_ON_ONCE(ret);
1123         dep->resource_index = 0;
1124 }
1125
1126 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1127                 const struct dwc3_event_depevt *event)
1128 {
1129         switch (event->status) {
1130         case DEPEVT_STATUS_CONTROL_DATA:
1131                 if (!dwc->softconnect || !dwc->connected)
1132                         return;
1133                 /*
1134                  * We already have a DATA transfer in the controller's cache,
1135                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1136                  * it's for the wrong direction.
1137                  *
1138                  * In that case, we must issue END_TRANSFER command to the Data
1139                  * Phase we already have started and issue SetStall on the
1140                  * control endpoint.
1141                  */
1142                 if (dwc->ep0_expect_in != event->endpoint_number) {
1143                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1144
1145                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1146                         dwc3_ep0_end_control_data(dwc, dep);
1147                         dwc3_ep0_stall_and_restart(dwc);
1148                         return;
1149                 }
1150
1151                 break;
1152
1153         case DEPEVT_STATUS_CONTROL_STATUS:
1154                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1155                         return;
1156
1157                 if (dwc->setup_packet_pending) {
1158                         dwc3_ep0_stall_and_restart(dwc);
1159                         return;
1160                 }
1161
1162                 dwc->ep0state = EP0_STATUS_PHASE;
1163
1164                 if (dwc->delayed_status) {
1165                         struct dwc3_ep *dep = dwc->eps[0];
1166
1167                         WARN_ON_ONCE(event->endpoint_number != 1);
1168                         /*
1169                          * We should handle the delay STATUS phase here if the
1170                          * request for handling delay STATUS has been queued
1171                          * into the list.
1172                          */
1173                         if (!list_empty(&dep->pending_list)) {
1174                                 dwc->delayed_status = false;
1175                                 usb_gadget_set_state(dwc->gadget,
1176                                                      USB_STATE_CONFIGURED);
1177                                 dwc3_ep0_do_control_status(dwc, event);
1178                         }
1179
1180                         return;
1181                 }
1182
1183                 dwc3_ep0_do_control_status(dwc, event);
1184         }
1185 }
1186
1187 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1188                 const struct dwc3_event_depevt *event)
1189 {
1190         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1191         u8              cmd;
1192
1193         switch (event->endpoint_event) {
1194         case DWC3_DEPEVT_XFERCOMPLETE:
1195                 dwc3_ep0_xfer_complete(dwc, event);
1196                 break;
1197
1198         case DWC3_DEPEVT_XFERNOTREADY:
1199                 dwc3_ep0_xfernotready(dwc, event);
1200                 break;
1201
1202         case DWC3_DEPEVT_XFERINPROGRESS:
1203         case DWC3_DEPEVT_RXTXFIFOEVT:
1204         case DWC3_DEPEVT_STREAMEVT:
1205                 break;
1206         case DWC3_DEPEVT_EPCMDCMPLT:
1207                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1208
1209                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1210                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1211                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1212                 }
1213                 break;
1214         }
1215 }