drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36 {
  37         struct dwc3_trb                 *trb;
  38         struct dwc3                     *dwc;
  39
  40         dwc = dep->dwc;
  41         trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43         if (chain)
  44                 dep->trb_enqueue++;
  45
  46         trb->bpl = lower_32_bits(buf_dma);
  47         trb->bph = upper_32_bits(buf_dma);
  48         trb->size = len;
  49         trb->ctrl = type;
  50
  51         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                         | DWC3_TRB_CTRL_ISP_IMI);
  53
  54         if (chain)
  55                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56         else
  57                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                 | DWC3_TRB_CTRL_LST);
  59
  60         trace_dwc3_prepare_trb(dep, trb);
  61 }
  62
  63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64 {
  65         struct dwc3_gadget_ep_cmd_params params;
  66         struct dwc3                     *dwc;
  67         int                             ret;
  68
  69         if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  70                 return 0;
  71
  72         dwc = dep->dwc;
  73
  74         memset(&params, 0, sizeof(params));
  75         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79         if (ret < 0)
  80                 return ret;
  81
  82         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  83
  84         return 0;
  85 }
  86
  87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  88                 struct dwc3_request *req)
  89 {
  90         struct dwc3             *dwc = dep->dwc;
  91
  92         req->request.actual     = 0;
  93         req->request.status     = -EINPROGRESS;
  94         req->epnum              = dep->number;
  95
  96         list_add_tail(&req->list, &dep->pending_list);
  97
  98         /*
  99          * Gadget driver might not be quick enough to queue a request
 100          * before we get a Transfer Not Ready event on this endpoint.
 101          *
 102          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 103          * flag is set, it's telling us that as soon as Gadget queues the
 104          * required request, we should kick the transfer here because the
 105          * IRQ we were waiting for is long gone.
 106          */
 107         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 108                 unsigned int direction;
 109
 110                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 111
 112                 if (dwc->ep0state != EP0_DATA_PHASE) {
 113                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 114                         return 0;
 115                 }
 116
 117                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 118
 119                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 120                                 DWC3_EP0_DIR_IN);
 121
 122                 return 0;
 123         }
 124
 125         /*
 126          * In case gadget driver asked us to delay the STATUS phase,
 127          * handle it here.
 128          */
 129         if (dwc->delayed_status) {
 130                 unsigned int direction;
 131
 132                 direction = !dwc->ep0_expect_in;
 133                 dwc->delayed_status = false;
 134                 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
 135
 136                 if (dwc->ep0state == EP0_STATUS_PHASE)
 137                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 138
 139                 return 0;
 140         }
 141
 142         /*
 143          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 144          *
 145          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 146          * come before issueing Start Transfer command, but if we do, we will
 147          * miss situations where the host starts another SETUP phase instead of
 148          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 149          * Layer Compliance Suite.
 150          *
 151          * The problem surfaces due to the fact that in case of back-to-back
 152          * SETUP packets there will be no XferNotReady(DATA) generated and we
 153          * will be stuck waiting for XferNotReady(DATA) forever.
 154          *
 155          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 156          * it tells us to start Data Phase right away. It also mentions that if
 157          * we receive a SETUP phase instead of the DATA phase, core will issue
 158          * XferComplete for the DATA phase, before actually initiating it in
 159          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 160          * can only be used to print some debugging logs, as the core expects
 161          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 162          * just so it completes right away, without transferring anything and,
 163          * only then, we can go back to the SETUP phase.
 164          *
 165          * Because of this scenario, SNPS decided to change the programming
 166          * model of control transfers and support on-demand transfers only for
 167          * the STATUS phase. To fix the issue we have now, we will always wait
 168          * for gadget driver to queue the DATA phase's struct usb_request, then
 169          * start it right away.
 170          *
 171          * If we're actually in a 2-stage transfer, we will wait for
 172          * XferNotReady(STATUS).
 173          */
 174         if (dwc->three_stage_setup) {
 175                 unsigned int direction;
 176
 177                 direction = dwc->ep0_expect_in;
 178                 dwc->ep0state = EP0_DATA_PHASE;
 179
 180                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 181
 182                 dep->flags &= ~DWC3_EP0_DIR_IN;
 183         }
 184
 185         return 0;
 186 }
 187
 188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 189                 gfp_t gfp_flags)
 190 {
 191         struct dwc3_request             *req = to_dwc3_request(request);
 192         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 193         struct dwc3                     *dwc = dep->dwc;
 194
 195         unsigned long                   flags;
 196
 197         int                             ret;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         if (!dep->endpoint.desc || !dwc->pullups_connected) {
 201                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 202                                 dep->name);
 203                 ret = -ESHUTDOWN;
 204                 goto out;
 205         }
 206
 207         /* we share one TRB for ep0/1 */
 208         if (!list_empty(&dep->pending_list)) {
 209                 ret = -EBUSY;
 210                 goto out;
 211         }
 212
 213         ret = __dwc3_gadget_ep0_queue(dep, req);
 214
 215 out:
 216         spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218         return ret;
 219 }
 220
 221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 222 {
 223         struct dwc3_ep          *dep;
 224
 225         /* reinitialize physical ep1 */
 226         dep = dwc->eps[1];
 227         dep->flags = DWC3_EP_ENABLED;
 228
 229         /* stall is always issued on EP0 */
 230         dep = dwc->eps[0];
 231         __dwc3_gadget_ep_set_halt(dep, 1, false);
 232         dep->flags = DWC3_EP_ENABLED;
 233         dwc->delayed_status = false;
 234
 235         if (!list_empty(&dep->pending_list)) {
 236                 struct dwc3_request     *req;
 237
 238                 req = next_request(&dep->pending_list);
 239                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 240         }
 241
 242         dwc->ep0state = EP0_SETUP_PHASE;
 243         dwc3_ep0_out_start(dwc);
 244 }
 245
 246 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 247 {
 248         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 249         struct dwc3                     *dwc = dep->dwc;
 250
 251         dwc3_ep0_stall_and_restart(dwc);
 252
 253         return 0;
 254 }
 255
 256 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 257 {
 258         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 259         struct dwc3                     *dwc = dep->dwc;
 260         unsigned long                   flags;
 261         int                             ret;
 262
 263         spin_lock_irqsave(&dwc->lock, flags);
 264         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 265         spin_unlock_irqrestore(&dwc->lock, flags);
 266
 267         return ret;
 268 }
 269
 270 void dwc3_ep0_out_start(struct dwc3 *dwc)
 271 {
 272         struct dwc3_ep                  *dep;
 273         int                             ret;
 274
 275         complete(&dwc->ep0_in_setup);
 276
 277         dep = dwc->eps[0];
 278         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 279                         DWC3_TRBCTL_CONTROL_SETUP, false);
 280         ret = dwc3_ep0_start_trans(dep);
 281         WARN_ON(ret < 0);
 282 }
 283
 284 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 285 {
 286         struct dwc3_ep          *dep;
 287         u32                     windex = le16_to_cpu(wIndex_le);
 288         u32                     epnum;
 289
 290         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 291         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 292                 epnum |= 1;
 293
 294         dep = dwc->eps[epnum];
 295         if (dep == NULL)
 296                 return NULL;
 297
 298         if (dep->flags & DWC3_EP_ENABLED)
 299                 return dep;
 300
 301         return NULL;
 302 }
 303
 304 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 305 {
 306 }
 307 /*
 308  * ch 9.4.5
 309  */
 310 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 311                 struct usb_ctrlrequest *ctrl)
 312 {
 313         struct dwc3_ep          *dep;
 314         u32                     recip;
 315         u32                     value;
 316         u32                     reg;
 317         u16                     usb_status = 0;
 318         __le16                  *response_pkt;
 319
 320         /* We don't support PTM_STATUS */
 321         value = le16_to_cpu(ctrl->wValue);
 322         if (value != 0)
 323                 return -EINVAL;
 324
 325         recip = ctrl->bRequestType & USB_RECIP_MASK;
 326         switch (recip) {
 327         case USB_RECIP_DEVICE:
 328                 /*
 329                  * LTM will be set once we know how to set this in HW.
 330                  */
 331                 usb_status |= dwc->gadget->is_selfpowered;
 332
 333                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 334                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 335                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 336                         if (reg & DWC3_DCTL_INITU1ENA)
 337                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 338                         if (reg & DWC3_DCTL_INITU2ENA)
 339                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 340                 }
 341
 342                 break;
 343
 344         case USB_RECIP_INTERFACE:
 345                 /*
 346                  * Function Remote Wake Capable D0
 347                  * Function Remote Wakeup       D1
 348                  */
 349                 break;
 350
 351         case USB_RECIP_ENDPOINT:
 352                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 353                 if (!dep)
 354                         return -EINVAL;
 355
 356                 if (dep->flags & DWC3_EP_STALL)
 357                         usb_status = 1 << USB_ENDPOINT_HALT;
 358                 break;
 359         default:
 360                 return -EINVAL;
 361         }
 362
 363         response_pkt = (__le16 *) dwc->setup_buf;
 364         *response_pkt = cpu_to_le16(usb_status);
 365
 366         dep = dwc->eps[0];
 367         dwc->ep0_usb_req.dep = dep;
 368         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 369         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 370         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 371
 372         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 373 }
 374
 375 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 376                 int set)
 377 {
 378         u32 reg;
 379
 380         if (state != USB_STATE_CONFIGURED)
 381                 return -EINVAL;
 382         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 383                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 384                 return -EINVAL;
 385         if (set && dwc->dis_u1_entry_quirk)
 386                 return -EINVAL;
 387
 388         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 389         if (set)
 390                 reg |= DWC3_DCTL_INITU1ENA;
 391         else
 392                 reg &= ~DWC3_DCTL_INITU1ENA;
 393         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 394
 395         return 0;
 396 }
 397
 398 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 399                 int set)
 400 {
 401         u32 reg;
 402
 403
 404         if (state != USB_STATE_CONFIGURED)
 405                 return -EINVAL;
 406         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 407                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 408                 return -EINVAL;
 409         if (set && dwc->dis_u2_entry_quirk)
 410                 return -EINVAL;
 411
 412         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 413         if (set)
 414                 reg |= DWC3_DCTL_INITU2ENA;
 415         else
 416                 reg &= ~DWC3_DCTL_INITU2ENA;
 417         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 418
 419         return 0;
 420 }
 421
 422 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 423                 u32 wIndex, int set)
 424 {
 425         if ((wIndex & 0xff) != 0)
 426                 return -EINVAL;
 427         if (!set)
 428                 return -EINVAL;
 429
 430         switch (wIndex >> 8) {
 431         case USB_TEST_J:
 432         case USB_TEST_K:
 433         case USB_TEST_SE0_NAK:
 434         case USB_TEST_PACKET:
 435         case USB_TEST_FORCE_ENABLE:
 436                 dwc->test_mode_nr = wIndex >> 8;
 437                 dwc->test_mode = true;
 438                 break;
 439         default:
 440                 return -EINVAL;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 447                 struct usb_ctrlrequest *ctrl, int set)
 448 {
 449         enum usb_device_state   state;
 450         u32                     wValue;
 451         u32                     wIndex;
 452         int                     ret = 0;
 453
 454         wValue = le16_to_cpu(ctrl->wValue);
 455         wIndex = le16_to_cpu(ctrl->wIndex);
 456         state = dwc->gadget->state;
 457
 458         switch (wValue) {
 459         case USB_DEVICE_REMOTE_WAKEUP:
 460                 break;
 461         /*
 462          * 9.4.1 says only only for SS, in AddressState only for
 463          * default control pipe
 464          */
 465         case USB_DEVICE_U1_ENABLE:
 466                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 467                 break;
 468         case USB_DEVICE_U2_ENABLE:
 469                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 470                 break;
 471         case USB_DEVICE_LTM_ENABLE:
 472                 ret = -EINVAL;
 473                 break;
 474         case USB_DEVICE_TEST_MODE:
 475                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 476                 break;
 477         default:
 478                 ret = -EINVAL;
 479         }
 480
 481         return ret;
 482 }
 483
 484 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 485                 struct usb_ctrlrequest *ctrl, int set)
 486 {
 487         u32                     wValue;
 488         int                     ret = 0;
 489
 490         wValue = le16_to_cpu(ctrl->wValue);
 491
 492         switch (wValue) {
 493         case USB_INTRF_FUNC_SUSPEND:
 494                 /*
 495                  * REVISIT: Ideally we would enable some low power mode here,
 496                  * however it's unclear what we should be doing here.
 497                  *
 498                  * For now, we're not doing anything, just making sure we return
 499                  * 0 so USB Command Verifier tests pass without any errors.
 500                  */
 501                 break;
 502         default:
 503                 ret = -EINVAL;
 504         }
 505
 506         return ret;
 507 }
 508
 509 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 510                 struct usb_ctrlrequest *ctrl, int set)
 511 {
 512         struct dwc3_ep          *dep;
 513         u32                     wValue;
 514         int                     ret;
 515
 516         wValue = le16_to_cpu(ctrl->wValue);
 517
 518         switch (wValue) {
 519         case USB_ENDPOINT_HALT:
 520                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 521                 if (!dep)
 522                         return -EINVAL;
 523
 524                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 525                         break;
 526
 527                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 528                 if (ret)
 529                         return -EINVAL;
 530
 531                 /* ClearFeature(Halt) may need delayed status */
 532                 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
 533                         return USB_GADGET_DELAYED_STATUS;
 534
 535                 break;
 536         default:
 537                 return -EINVAL;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 544                 struct usb_ctrlrequest *ctrl, int set)
 545 {
 546         u32                     recip;
 547         int                     ret;
 548
 549         recip = ctrl->bRequestType & USB_RECIP_MASK;
 550
 551         switch (recip) {
 552         case USB_RECIP_DEVICE:
 553                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 554                 break;
 555         case USB_RECIP_INTERFACE:
 556                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 557                 break;
 558         case USB_RECIP_ENDPOINT:
 559                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 560                 break;
 561         default:
 562                 ret = -EINVAL;
 563         }
 564
 565         return ret;
 566 }
 567
 568 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 569 {
 570         enum usb_device_state state = dwc->gadget->state;
 571         u32 addr;
 572         u32 reg;
 573
 574         addr = le16_to_cpu(ctrl->wValue);
 575         if (addr > 127) {
 576                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 577                 return -EINVAL;
 578         }
 579
 580         if (state == USB_STATE_CONFIGURED) {
 581                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 582                 return -EINVAL;
 583         }
 584
 585         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 586         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 587         reg |= DWC3_DCFG_DEVADDR(addr);
 588         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 589
 590         if (addr)
 591                 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
 592         else
 593                 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
 594
 595         return 0;
 596 }
 597
 598 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 599 {
 600         int ret = -EINVAL;
 601
 602         if (dwc->async_callbacks) {
 603                 spin_unlock(&dwc->lock);
 604                 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
 605                 spin_lock(&dwc->lock);
 606         }
 607         return ret;
 608 }
 609
 610 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 611 {
 612         enum usb_device_state state = dwc->gadget->state;
 613         u32 cfg;
 614         int ret;
 615         u32 reg;
 616
 617         cfg = le16_to_cpu(ctrl->wValue);
 618
 619         switch (state) {
 620         case USB_STATE_DEFAULT:
 621                 return -EINVAL;
 622
 623         case USB_STATE_ADDRESS:
 624                 dwc3_gadget_clear_tx_fifos(dwc);
 625
 626                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 627                 /* if the cfg matches and the cfg is non zero */
 628                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 629
 630                         /*
 631                          * only change state if set_config has already
 632                          * been processed. If gadget driver returns
 633                          * USB_GADGET_DELAYED_STATUS, we will wait
 634                          * to change the state on the next usb_ep_queue()
 635                          */
 636                         if (ret == 0)
 637                                 usb_gadget_set_state(dwc->gadget,
 638                                                 USB_STATE_CONFIGURED);
 639
 640                         /*
 641                          * Enable transition to U1/U2 state when
 642                          * nothing is pending from application.
 643                          */
 644                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 645                         if (!dwc->dis_u1_entry_quirk)
 646                                 reg |= DWC3_DCTL_ACCEPTU1ENA;
 647                         if (!dwc->dis_u2_entry_quirk)
 648                                 reg |= DWC3_DCTL_ACCEPTU2ENA;
 649                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 650                 }
 651                 break;
 652
 653         case USB_STATE_CONFIGURED:
 654                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 655                 if (!cfg && !ret)
 656                         usb_gadget_set_state(dwc->gadget,
 657                                         USB_STATE_ADDRESS);
 658                 break;
 659         default:
 660                 ret = -EINVAL;
 661         }
 662         return ret;
 663 }
 664
 665 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 666 {
 667         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 668         struct dwc3     *dwc = dep->dwc;
 669
 670         u32             param = 0;
 671         u32             reg;
 672
 673         struct timing {
 674                 u8      u1sel;
 675                 u8      u1pel;
 676                 __le16  u2sel;
 677                 __le16  u2pel;
 678         } __packed timing;
 679
 680         int             ret;
 681
 682         memcpy(&timing, req->buf, sizeof(timing));
 683
 684         dwc->u1sel = timing.u1sel;
 685         dwc->u1pel = timing.u1pel;
 686         dwc->u2sel = le16_to_cpu(timing.u2sel);
 687         dwc->u2pel = le16_to_cpu(timing.u2pel);
 688
 689         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 690         if (reg & DWC3_DCTL_INITU2ENA)
 691                 param = dwc->u2pel;
 692         if (reg & DWC3_DCTL_INITU1ENA)
 693                 param = dwc->u1pel;
 694
 695         /*
 696          * According to Synopsys Databook, if parameter is
 697          * greater than 125, a value of zero should be
 698          * programmed in the register.
 699          */
 700         if (param > 125)
 701                 param = 0;
 702
 703         /* now that we have the time, issue DGCMD Set Sel */
 704         ret = dwc3_send_gadget_generic_command(dwc,
 705                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 706         WARN_ON(ret < 0);
 707 }
 708
 709 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 710 {
 711         struct dwc3_ep  *dep;
 712         enum usb_device_state state = dwc->gadget->state;
 713         u16             wLength;
 714
 715         if (state == USB_STATE_DEFAULT)
 716                 return -EINVAL;
 717
 718         wLength = le16_to_cpu(ctrl->wLength);
 719
 720         if (wLength != 6) {
 721                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 722                                 wLength);
 723                 return -EINVAL;
 724         }
 725
 726         /*
 727          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 728          * queue a usb_request for 6 bytes.
 729          *
 730          * Remember, though, this controller can't handle non-wMaxPacketSize
 731          * aligned transfers on the OUT direction, so we queue a request for
 732          * wMaxPacketSize instead.
 733          */
 734         dep = dwc->eps[0];
 735         dwc->ep0_usb_req.dep = dep;
 736         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 737         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 738         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 739
 740         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 741 }
 742
 743 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 744 {
 745         u16             wLength;
 746         u16             wValue;
 747         u16             wIndex;
 748
 749         wValue = le16_to_cpu(ctrl->wValue);
 750         wLength = le16_to_cpu(ctrl->wLength);
 751         wIndex = le16_to_cpu(ctrl->wIndex);
 752
 753         if (wIndex || wLength)
 754                 return -EINVAL;
 755
 756         dwc->gadget->isoch_delay = wValue;
 757
 758         return 0;
 759 }
 760
 761 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 762 {
 763         int ret;
 764
 765         switch (ctrl->bRequest) {
 766         case USB_REQ_GET_STATUS:
 767                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 768                 break;
 769         case USB_REQ_CLEAR_FEATURE:
 770                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 771                 break;
 772         case USB_REQ_SET_FEATURE:
 773                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 774                 break;
 775         case USB_REQ_SET_ADDRESS:
 776                 ret = dwc3_ep0_set_address(dwc, ctrl);
 777                 break;
 778         case USB_REQ_SET_CONFIGURATION:
 779                 ret = dwc3_ep0_set_config(dwc, ctrl);
 780                 break;
 781         case USB_REQ_SET_SEL:
 782                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 783                 break;
 784         case USB_REQ_SET_ISOCH_DELAY:
 785                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 786                 break;
 787         default:
 788                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 789                 break;
 790         }
 791
 792         return ret;
 793 }
 794
 795 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 796                 const struct dwc3_event_depevt *event)
 797 {
 798         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 799         int ret = -EINVAL;
 800         u32 len;
 801
 802         if (!dwc->gadget_driver)
 803                 goto out;
 804
 805         trace_dwc3_ctrl_req(ctrl);
 806
 807         len = le16_to_cpu(ctrl->wLength);
 808         if (!len) {
 809                 dwc->three_stage_setup = false;
 810                 dwc->ep0_expect_in = false;
 811                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 812         } else {
 813                 dwc->three_stage_setup = true;
 814                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 815                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 816         }
 817
 818         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 819                 ret = dwc3_ep0_std_request(dwc, ctrl);
 820         else
 821                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 822
 823         if (ret == USB_GADGET_DELAYED_STATUS)
 824                 dwc->delayed_status = true;
 825
 826 out:
 827         if (ret < 0)
 828                 dwc3_ep0_stall_and_restart(dwc);
 829 }
 830
 831 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 832                 const struct dwc3_event_depevt *event)
 833 {
 834         struct dwc3_request     *r;
 835         struct usb_request      *ur;
 836         struct dwc3_trb         *trb;
 837         struct dwc3_ep          *ep0;
 838         u32                     transferred = 0;
 839         u32                     status;
 840         u32                     length;
 841         u8                      epnum;
 842
 843         epnum = event->endpoint_number;
 844         ep0 = dwc->eps[0];
 845
 846         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 847         trb = dwc->ep0_trb;
 848         trace_dwc3_complete_trb(ep0, trb);
 849
 850         r = next_request(&ep0->pending_list);
 851         if (!r)
 852                 return;
 853
 854         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 855         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 856                 dwc->setup_packet_pending = true;
 857                 if (r)
 858                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 859
 860                 return;
 861         }
 862
 863         ur = &r->request;
 864
 865         length = trb->size & DWC3_TRB_SIZE_MASK;
 866         transferred = ur->length - length;
 867         ur->actual += transferred;
 868
 869         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 870              ur->length && ur->zero) || dwc->ep0_bounced) {
 871                 trb++;
 872                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 873                 trace_dwc3_complete_trb(ep0, trb);
 874
 875                 if (r->direction)
 876                         dwc->eps[1]->trb_enqueue = 0;
 877                 else
 878                         dwc->eps[0]->trb_enqueue = 0;
 879
 880                 dwc->ep0_bounced = false;
 881         }
 882
 883         if ((epnum & 1) && ur->actual < ur->length)
 884                 dwc3_ep0_stall_and_restart(dwc);
 885         else
 886                 dwc3_gadget_giveback(ep0, r, 0);
 887 }
 888
 889 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 890                 const struct dwc3_event_depevt *event)
 891 {
 892         struct dwc3_request     *r;
 893         struct dwc3_ep          *dep;
 894         struct dwc3_trb         *trb;
 895         u32                     status;
 896
 897         dep = dwc->eps[0];
 898         trb = dwc->ep0_trb;
 899
 900         trace_dwc3_complete_trb(dep, trb);
 901
 902         if (!list_empty(&dep->pending_list)) {
 903                 r = next_request(&dep->pending_list);
 904
 905                 dwc3_gadget_giveback(dep, r, 0);
 906         }
 907
 908         if (dwc->test_mode) {
 909                 int ret;
 910
 911                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 912                 if (ret < 0) {
 913                         dev_err(dwc->dev, "invalid test #%d\n",
 914                                         dwc->test_mode_nr);
 915                         dwc3_ep0_stall_and_restart(dwc);
 916                         return;
 917                 }
 918         }
 919
 920         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 921         if (status == DWC3_TRBSTS_SETUP_PENDING)
 922                 dwc->setup_packet_pending = true;
 923
 924         dwc->ep0state = EP0_SETUP_PHASE;
 925         dwc3_ep0_out_start(dwc);
 926 }
 927
 928 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 929                         const struct dwc3_event_depevt *event)
 930 {
 931         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 932
 933         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 934         dep->resource_index = 0;
 935         dwc->setup_packet_pending = false;
 936
 937         switch (dwc->ep0state) {
 938         case EP0_SETUP_PHASE:
 939                 dwc3_ep0_inspect_setup(dwc, event);
 940                 break;
 941
 942         case EP0_DATA_PHASE:
 943                 dwc3_ep0_complete_data(dwc, event);
 944                 break;
 945
 946         case EP0_STATUS_PHASE:
 947                 dwc3_ep0_complete_status(dwc, event);
 948                 break;
 949         default:
 950                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 951         }
 952 }
 953
 954 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 955                 struct dwc3_ep *dep, struct dwc3_request *req)
 956 {
 957         unsigned int            trb_length = 0;
 958         int                     ret;
 959
 960         req->direction = !!dep->number;
 961
 962         if (req->request.length == 0) {
 963                 if (!req->direction)
 964                         trb_length = dep->endpoint.maxpacket;
 965
 966                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 967                                 DWC3_TRBCTL_CONTROL_DATA, false);
 968                 ret = dwc3_ep0_start_trans(dep);
 969         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 970                         && (dep->number == 0)) {
 971                 u32     maxpacket;
 972                 u32     rem;
 973
 974                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 975                                 &req->request, dep->number);
 976                 if (ret)
 977                         return;
 978
 979                 maxpacket = dep->endpoint.maxpacket;
 980                 rem = req->request.length % maxpacket;
 981                 dwc->ep0_bounced = true;
 982
 983                 /* prepare normal TRB */
 984                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 985                                          req->request.length,
 986                                          DWC3_TRBCTL_CONTROL_DATA,
 987                                          true);
 988
 989                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 990
 991                 /* Now prepare one extra TRB to align transfer size */
 992                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
 993                                          maxpacket - rem,
 994                                          DWC3_TRBCTL_CONTROL_DATA,
 995                                          false);
 996                 ret = dwc3_ep0_start_trans(dep);
 997         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
 998                    req->request.length && req->request.zero) {
 999
1000                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1001                                 &req->request, dep->number);
1002                 if (ret)
1003                         return;
1004
1005                 /* prepare normal TRB */
1006                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1007                                          req->request.length,
1008                                          DWC3_TRBCTL_CONTROL_DATA,
1009                                          true);
1010
1011                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1012
1013                 if (!req->direction)
1014                         trb_length = dep->endpoint.maxpacket;
1015
1016                 /* Now prepare one extra TRB to align transfer size */
1017                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1018                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1019                                          false);
1020                 ret = dwc3_ep0_start_trans(dep);
1021         } else {
1022                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1023                                 &req->request, dep->number);
1024                 if (ret)
1025                         return;
1026
1027                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1028                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1029                                 false);
1030
1031                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1032
1033                 ret = dwc3_ep0_start_trans(dep);
1034         }
1035
1036         WARN_ON(ret < 0);
1037 }
1038
1039 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1040 {
1041         struct dwc3             *dwc = dep->dwc;
1042         u32                     type;
1043
1044         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1045                 : DWC3_TRBCTL_CONTROL_STATUS2;
1046
1047         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1048         return dwc3_ep0_start_trans(dep);
1049 }
1050
1051 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1052 {
1053         WARN_ON(dwc3_ep0_start_control_status(dep));
1054 }
1055
1056 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1057                 const struct dwc3_event_depevt *event)
1058 {
1059         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1060
1061         __dwc3_ep0_do_control_status(dwc, dep);
1062 }
1063
1064 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1065 {
1066         unsigned int direction = !dwc->ep0_expect_in;
1067
1068         dwc->delayed_status = false;
1069
1070         if (dwc->ep0state != EP0_STATUS_PHASE)
1071                 return;
1072
1073         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1074 }
1075
1076 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1077 {
1078         struct dwc3_gadget_ep_cmd_params params;
1079         u32                     cmd;
1080         int                     ret;
1081
1082         if (!dep->resource_index)
1083                 return;
1084
1085         cmd = DWC3_DEPCMD_ENDTRANSFER;
1086         cmd |= DWC3_DEPCMD_CMDIOC;
1087         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1088         memset(&params, 0, sizeof(params));
1089         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1090         WARN_ON_ONCE(ret);
1091         dep->resource_index = 0;
1092 }
1093
1094 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1095                 const struct dwc3_event_depevt *event)
1096 {
1097         switch (event->status) {
1098         case DEPEVT_STATUS_CONTROL_DATA:
1099                 /*
1100                  * We already have a DATA transfer in the controller's cache,
1101                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1102                  * it's for the wrong direction.
1103                  *
1104                  * In that case, we must issue END_TRANSFER command to the Data
1105                  * Phase we already have started and issue SetStall on the
1106                  * control endpoint.
1107                  */
1108                 if (dwc->ep0_expect_in != event->endpoint_number) {
1109                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1110
1111                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1112                         dwc3_ep0_end_control_data(dwc, dep);
1113                         dwc3_ep0_stall_and_restart(dwc);
1114                         return;
1115                 }
1116
1117                 break;
1118
1119         case DEPEVT_STATUS_CONTROL_STATUS:
1120                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1121                         return;
1122
1123                 dwc->ep0state = EP0_STATUS_PHASE;
1124
1125                 if (dwc->delayed_status) {
1126                         struct dwc3_ep *dep = dwc->eps[0];
1127
1128                         WARN_ON_ONCE(event->endpoint_number != 1);
1129                         /*
1130                          * We should handle the delay STATUS phase here if the
1131                          * request for handling delay STATUS has been queued
1132                          * into the list.
1133                          */
1134                         if (!list_empty(&dep->pending_list)) {
1135                                 dwc->delayed_status = false;
1136                                 usb_gadget_set_state(dwc->gadget,
1137                                                      USB_STATE_CONFIGURED);
1138                                 dwc3_ep0_do_control_status(dwc, event);
1139                         }
1140
1141                         return;
1142                 }
1143
1144                 dwc3_ep0_do_control_status(dwc, event);
1145         }
1146 }
1147
1148 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1149                 const struct dwc3_event_depevt *event)
1150 {
1151         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1152         u8              cmd;
1153
1154         switch (event->endpoint_event) {
1155         case DWC3_DEPEVT_XFERCOMPLETE:
1156                 dwc3_ep0_xfer_complete(dwc, event);
1157                 break;
1158
1159         case DWC3_DEPEVT_XFERNOTREADY:
1160                 dwc3_ep0_xfernotready(dwc, event);
1161                 break;
1162
1163         case DWC3_DEPEVT_XFERINPROGRESS:
1164         case DWC3_DEPEVT_RXTXFIFOEVT:
1165         case DWC3_DEPEVT_STREAMEVT:
1166                 break;
1167         case DWC3_DEPEVT_EPCMDCMPLT:
1168                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1169
1170                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1171                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1172                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1173                 }
1174                 break;
1175         }
1176 }