drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     dwc->revision >= DWC3_REVISION_330A)
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111
 112         dwc->current_dr_role = mode;
 113 }
 114
 115 static void __dwc3_set_mode(struct work_struct *work)
 116 {
 117         struct dwc3 *dwc = work_to_dwc(work);
 118         unsigned long flags;
 119         int ret;
 120
 121         if (dwc->dr_mode != USB_DR_MODE_OTG)
 122                 return;
 123
 124         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 125                 dwc3_otg_update(dwc, 0);
 126
 127         if (!dwc->desired_dr_role)
 128                 return;
 129
 130         if (dwc->desired_dr_role == dwc->current_dr_role)
 131                 return;
 132
 133         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 134                 return;
 135
 136         switch (dwc->current_dr_role) {
 137         case DWC3_GCTL_PRTCAP_HOST:
 138                 dwc3_host_exit(dwc);
 139                 break;
 140         case DWC3_GCTL_PRTCAP_DEVICE:
 141                 dwc3_gadget_exit(dwc);
 142                 dwc3_event_buffers_cleanup(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_OTG:
 145                 dwc3_otg_exit(dwc);
 146                 spin_lock_irqsave(&dwc->lock, flags);
 147                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 148                 spin_unlock_irqrestore(&dwc->lock, flags);
 149                 dwc3_otg_update(dwc, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         spin_lock_irqsave(&dwc->lock, flags);
 156
 157         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 158
 159         spin_unlock_irqrestore(&dwc->lock, flags);
 160
 161         switch (dwc->desired_dr_role) {
 162         case DWC3_GCTL_PRTCAP_HOST:
 163                 ret = dwc3_host_init(dwc);
 164                 if (ret) {
 165                         dev_err(dwc->dev, "failed to initialize host\n");
 166                 } else {
 167                         if (dwc->usb2_phy)
 168                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 169                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 171                 }
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_event_buffers_setup(dwc);
 175
 176                 if (dwc->usb2_phy)
 177                         otg_set_vbus(dwc->usb2_phy->otg, false);
 178                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 179                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 180
 181                 ret = dwc3_gadget_init(dwc);
 182                 if (ret)
 183                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 184                 break;
 185         case DWC3_GCTL_PRTCAP_OTG:
 186                 dwc3_otg_init(dwc);
 187                 dwc3_otg_update(dwc, 0);
 188                 break;
 189         default:
 190                 break;
 191         }
 192
 193 }
 194
 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 196 {
 197         unsigned long flags;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         dwc->desired_dr_role = mode;
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202
 203         queue_work(system_freezable_wq, &dwc->drd_work);
 204 }
 205
 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 207 {
 208         struct dwc3             *dwc = dep->dwc;
 209         u32                     reg;
 210
 211         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 212                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 213                         DWC3_GDBGFIFOSPACE_TYPE(type));
 214
 215         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 216
 217         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 218 }
 219
 220 /**
 221  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 222  * @dwc: pointer to our context structure
 223  */
 224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 225 {
 226         u32             reg;
 227         int             retries = 1000;
 228         int             ret;
 229
 230         usb_phy_init(dwc->usb2_phy);
 231         usb_phy_init(dwc->usb3_phy);
 232         ret = phy_init(dwc->usb2_generic_phy);
 233         if (ret < 0)
 234                 return ret;
 235
 236         ret = phy_init(dwc->usb3_generic_phy);
 237         if (ret < 0) {
 238                 phy_exit(dwc->usb2_generic_phy);
 239                 return ret;
 240         }
 241
 242         /*
 243          * We're resetting only the device side because, if we're in host mode,
 244          * XHCI driver will reset the host block. If dwc3 was configured for
 245          * host-only mode, then we can return early.
 246          */
 247         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 248                 return 0;
 249
 250         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 251         reg |= DWC3_DCTL_CSFTRST;
 252         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 253
 254         /*
 255          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 256          * is cleared only after all the clocks are synchronized. This can
 257          * take a little more than 50ms. Set the polling rate at 20ms
 258          * for 10 times instead.
 259          */
 260         if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
 261                 retries = 10;
 262
 263         do {
 264                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 265                 if (!(reg & DWC3_DCTL_CSFTRST))
 266                         goto done;
 267
 268                 if (dwc3_is_usb31(dwc) &&
 269                     dwc->revision >= DWC3_USB31_REVISION_190A)
 270                         msleep(20);
 271                 else
 272                         udelay(1);
 273         } while (--retries);
 274
 275         phy_exit(dwc->usb3_generic_phy);
 276         phy_exit(dwc->usb2_generic_phy);
 277
 278         return -ETIMEDOUT;
 279
 280 done:
 281         /*
 282          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 283          * is cleared, we must wait at least 50ms before accessing the PHY
 284          * domain (synchronization delay).
 285          */
 286         if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
 287                 msleep(50);
 288
 289         return 0;
 290 }
 291
 292 /*
 293  * dwc3_frame_length_adjustment - Adjusts frame length if required
 294  * @dwc3: Pointer to our controller context structure
 295  */
 296 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 297 {
 298         u32 reg;
 299         u32 dft;
 300
 301         if (dwc->revision < DWC3_REVISION_250A)
 302                 return;
 303
 304         if (dwc->fladj == 0)
 305                 return;
 306
 307         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 308         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 309         if (dft != dwc->fladj) {
 310                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 311                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 312                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 313         }
 314 }
 315
 316 /**
 317  * dwc3_free_one_event_buffer - Frees one event buffer
 318  * @dwc: Pointer to our controller context structure
 319  * @evt: Pointer to event buffer to be freed
 320  */
 321 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 322                 struct dwc3_event_buffer *evt)
 323 {
 324         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 325 }
 326
 327 /**
 328  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 329  * @dwc: Pointer to our controller context structure
 330  * @length: size of the event buffer
 331  *
 332  * Returns a pointer to the allocated event buffer structure on success
 333  * otherwise ERR_PTR(errno).
 334  */
 335 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 336                 unsigned length)
 337 {
 338         struct dwc3_event_buffer        *evt;
 339
 340         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 341         if (!evt)
 342                 return ERR_PTR(-ENOMEM);
 343
 344         evt->dwc        = dwc;
 345         evt->length     = length;
 346         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 347         if (!evt->cache)
 348                 return ERR_PTR(-ENOMEM);
 349
 350         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 351                         &evt->dma, GFP_KERNEL);
 352         if (!evt->buf)
 353                 return ERR_PTR(-ENOMEM);
 354
 355         return evt;
 356 }
 357
 358 /**
 359  * dwc3_free_event_buffers - frees all allocated event buffers
 360  * @dwc: Pointer to our controller context structure
 361  */
 362 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 363 {
 364         struct dwc3_event_buffer        *evt;
 365
 366         evt = dwc->ev_buf;
 367         if (evt)
 368                 dwc3_free_one_event_buffer(dwc, evt);
 369 }
 370
 371 /**
 372  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 373  * @dwc: pointer to our controller context structure
 374  * @length: size of event buffer
 375  *
 376  * Returns 0 on success otherwise negative errno. In the error case, dwc
 377  * may contain some buffers allocated but not all which were requested.
 378  */
 379 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 380 {
 381         struct dwc3_event_buffer *evt;
 382
 383         evt = dwc3_alloc_one_event_buffer(dwc, length);
 384         if (IS_ERR(evt)) {
 385                 dev_err(dwc->dev, "can't allocate event buffer\n");
 386                 return PTR_ERR(evt);
 387         }
 388         dwc->ev_buf = evt;
 389
 390         return 0;
 391 }
 392
 393 /**
 394  * dwc3_event_buffers_setup - setup our allocated event buffers
 395  * @dwc: pointer to our controller context structure
 396  *
 397  * Returns 0 on success otherwise negative errno.
 398  */
 399 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 400 {
 401         struct dwc3_event_buffer        *evt;
 402
 403         evt = dwc->ev_buf;
 404         evt->lpos = 0;
 405         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 406                         lower_32_bits(evt->dma));
 407         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 408                         upper_32_bits(evt->dma));
 409         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 410                         DWC3_GEVNTSIZ_SIZE(evt->length));
 411         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 412
 413         return 0;
 414 }
 415
 416 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 417 {
 418         struct dwc3_event_buffer        *evt;
 419
 420         evt = dwc->ev_buf;
 421
 422         evt->lpos = 0;
 423
 424         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 425         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 426         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 427                         | DWC3_GEVNTSIZ_SIZE(0));
 428         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 429 }
 430
 431 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 432 {
 433         if (!dwc->has_hibernation)
 434                 return 0;
 435
 436         if (!dwc->nr_scratch)
 437                 return 0;
 438
 439         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 440                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 441         if (!dwc->scratchbuf)
 442                 return -ENOMEM;
 443
 444         return 0;
 445 }
 446
 447 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 448 {
 449         dma_addr_t scratch_addr;
 450         u32 param;
 451         int ret;
 452
 453         if (!dwc->has_hibernation)
 454                 return 0;
 455
 456         if (!dwc->nr_scratch)
 457                 return 0;
 458
 459          /* should never fall here */
 460         if (!WARN_ON(dwc->scratchbuf))
 461                 return 0;
 462
 463         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 464                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 465                         DMA_BIDIRECTIONAL);
 466         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 467                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 468                 ret = -EFAULT;
 469                 goto err0;
 470         }
 471
 472         dwc->scratch_addr = scratch_addr;
 473
 474         param = lower_32_bits(scratch_addr);
 475
 476         ret = dwc3_send_gadget_generic_command(dwc,
 477                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 478         if (ret < 0)
 479                 goto err1;
 480
 481         param = upper_32_bits(scratch_addr);
 482
 483         ret = dwc3_send_gadget_generic_command(dwc,
 484                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 485         if (ret < 0)
 486                 goto err1;
 487
 488         return 0;
 489
 490 err1:
 491         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 492                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 493
 494 err0:
 495         return ret;
 496 }
 497
 498 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 499 {
 500         if (!dwc->has_hibernation)
 501                 return;
 502
 503         if (!dwc->nr_scratch)
 504                 return;
 505
 506          /* should never fall here */
 507         if (!WARN_ON(dwc->scratchbuf))
 508                 return;
 509
 510         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 511                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 512         kfree(dwc->scratchbuf);
 513 }
 514
 515 static void dwc3_core_num_eps(struct dwc3 *dwc)
 516 {
 517         struct dwc3_hwparams    *parms = &dwc->hwparams;
 518
 519         dwc->num_eps = DWC3_NUM_EPS(parms);
 520 }
 521
 522 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 523 {
 524         struct dwc3_hwparams    *parms = &dwc->hwparams;
 525
 526         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 527         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 528         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 529         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 530         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 531         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 532         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 533         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 534         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 535 }
 536
 537 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 538 {
 539         int intf;
 540         int ret = 0;
 541
 542         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 543
 544         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 545             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 546              dwc->hsphy_interface &&
 547              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 548                 ret = dwc3_ulpi_init(dwc);
 549
 550         return ret;
 551 }
 552
 553 /**
 554  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 555  * @dwc: Pointer to our controller context structure
 556  *
 557  * Returns 0 on success. The USB PHY interfaces are configured but not
 558  * initialized. The PHY interfaces and the PHYs get initialized together with
 559  * the core in dwc3_core_init.
 560  */
 561 static int dwc3_phy_setup(struct dwc3 *dwc)
 562 {
 563         unsigned int hw_mode;
 564         u32 reg;
 565
 566         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 567
 568         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 569
 570         /*
 571          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 572          * PHYs. Also, this bit is not supposed to be used in normal operation.
 573          */
 574         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 575
 576         /*
 577          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 578          * to '0' during coreConsultant configuration. So default value
 579          * will be '0' when the core is reset. Application needs to set it
 580          * to '1' after the core initialization is completed.
 581          */
 582         if (dwc->revision > DWC3_REVISION_194A)
 583                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 584
 585         /*
 586          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 587          * power-on reset, and it can be set after core initialization, which is
 588          * after device soft-reset during initialization.
 589          */
 590         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 591                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 592
 593         if (dwc->u2ss_inp3_quirk)
 594                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 595
 596         if (dwc->dis_rxdet_inp3_quirk)
 597                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 598
 599         if (dwc->req_p1p2p3_quirk)
 600                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 601
 602         if (dwc->del_p1p2p3_quirk)
 603                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 604
 605         if (dwc->del_phy_power_chg_quirk)
 606                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 607
 608         if (dwc->lfps_filter_quirk)
 609                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 610
 611         if (dwc->rx_detect_poll_quirk)
 612                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 613
 614         if (dwc->tx_de_emphasis_quirk)
 615                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 616
 617         if (dwc->dis_u3_susphy_quirk)
 618                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 619
 620         if (dwc->dis_del_phy_power_chg_quirk)
 621                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 622
 623         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 624
 625         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 626
 627         /* Select the HS PHY interface */
 628         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 629         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 630                 if (dwc->hsphy_interface &&
 631                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 632                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 633                         break;
 634                 } else if (dwc->hsphy_interface &&
 635                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 636                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 637                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 638                 } else {
 639                         /* Relying on default value. */
 640                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 641                                 break;
 642                 }
 643                 /* FALLTHROUGH */
 644         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 645                 /* FALLTHROUGH */
 646         default:
 647                 break;
 648         }
 649
 650         switch (dwc->hsphy_mode) {
 651         case USBPHY_INTERFACE_MODE_UTMI:
 652                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 653                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 654                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 655                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 656                 break;
 657         case USBPHY_INTERFACE_MODE_UTMIW:
 658                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 659                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 660                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 661                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 662                 break;
 663         default:
 664                 break;
 665         }
 666
 667         /*
 668          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 669          * '0' during coreConsultant configuration. So default value will
 670          * be '0' when the core is reset. Application needs to set it to
 671          * '1' after the core initialization is completed.
 672          */
 673         if (dwc->revision > DWC3_REVISION_194A)
 674                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 675
 676         /*
 677          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 678          * power-on reset, and it can be set after core initialization, which is
 679          * after device soft-reset during initialization.
 680          */
 681         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 682                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 683
 684         if (dwc->dis_u2_susphy_quirk)
 685                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 686
 687         if (dwc->dis_enblslpm_quirk)
 688                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 689         else
 690                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 691
 692         if (dwc->dis_u2_freeclk_exists_quirk)
 693                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 694
 695         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 696
 697         return 0;
 698 }
 699
 700 static void dwc3_core_exit(struct dwc3 *dwc)
 701 {
 702         dwc3_event_buffers_cleanup(dwc);
 703
 704         usb_phy_shutdown(dwc->usb2_phy);
 705         usb_phy_shutdown(dwc->usb3_phy);
 706         phy_exit(dwc->usb2_generic_phy);
 707         phy_exit(dwc->usb3_generic_phy);
 708
 709         usb_phy_set_suspend(dwc->usb2_phy, 1);
 710         usb_phy_set_suspend(dwc->usb3_phy, 1);
 711         phy_power_off(dwc->usb2_generic_phy);
 712         phy_power_off(dwc->usb3_generic_phy);
 713         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 714         reset_control_assert(dwc->reset);
 715 }
 716
 717 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 718 {
 719         u32 reg;
 720
 721         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 722
 723         /* This should read as U3 followed by revision number */
 724         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 725                 /* Detected DWC_usb3 IP */
 726                 dwc->revision = reg;
 727         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 728                 /* Detected DWC_usb31 IP */
 729                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 730                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 731                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 732         } else {
 733                 return false;
 734         }
 735
 736         return true;
 737 }
 738
 739 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 740 {
 741         u32 hwparams4 = dwc->hwparams.hwparams4;
 742         u32 reg;
 743
 744         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 745         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 746
 747         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 748         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 749                 /**
 750                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 751                  * issue which would cause xHCI compliance tests to fail.
 752                  *
 753                  * Because of that we cannot enable clock gating on such
 754                  * configurations.
 755                  *
 756                  * Refers to:
 757                  *
 758                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 759                  * SOF/ITP Mode Used
 760                  */
 761                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 762                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 763                                 (dwc->revision >= DWC3_REVISION_210A &&
 764                                 dwc->revision <= DWC3_REVISION_250A))
 765                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 766                 else
 767                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 768                 break;
 769         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 770                 /* enable hibernation here */
 771                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 772
 773                 /*
 774                  * REVISIT Enabling this bit so that host-mode hibernation
 775                  * will work. Device-mode hibernation is not yet implemented.
 776                  */
 777                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 778                 break;
 779         default:
 780                 /* nothing */
 781                 break;
 782         }
 783
 784         /* check if current dwc3 is on simulation board */
 785         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 786                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 787                 dwc->is_fpga = true;
 788         }
 789
 790         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 791                         "disable_scramble cannot be used on non-FPGA builds\n");
 792
 793         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 794                 reg |= DWC3_GCTL_DISSCRAMBLE;
 795         else
 796                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 797
 798         if (dwc->u2exit_lfps_quirk)
 799                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 800
 801         /*
 802          * WORKAROUND: DWC3 revisions <1.90a have a bug
 803          * where the device can fail to connect at SuperSpeed
 804          * and falls back to high-speed mode which causes
 805          * the device to enter a Connect/Disconnect loop
 806          */
 807         if (dwc->revision < DWC3_REVISION_190A)
 808                 reg |= DWC3_GCTL_U2RSTECN;
 809
 810         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 811 }
 812
 813 static int dwc3_core_get_phy(struct dwc3 *dwc);
 814 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 815
 816 /* set global incr burst type configuration registers */
 817 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 818 {
 819         struct device *dev = dwc->dev;
 820         /* incrx_mode : for INCR burst type. */
 821         bool incrx_mode;
 822         /* incrx_size : for size of INCRX burst. */
 823         u32 incrx_size;
 824         u32 *vals;
 825         u32 cfg;
 826         int ntype;
 827         int ret;
 828         int i;
 829
 830         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 831
 832         /*
 833          * Handle property "snps,incr-burst-type-adjustment".
 834          * Get the number of value from this property:
 835          * result <= 0, means this property is not supported.
 836          * result = 1, means INCRx burst mode supported.
 837          * result > 1, means undefined length burst mode supported.
 838          */
 839         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 840         if (ntype <= 0)
 841                 return;
 842
 843         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 844         if (!vals) {
 845                 dev_err(dev, "Error to get memory\n");
 846                 return;
 847         }
 848
 849         /* Get INCR burst type, and parse it */
 850         ret = device_property_read_u32_array(dev,
 851                         "snps,incr-burst-type-adjustment", vals, ntype);
 852         if (ret) {
 853                 kfree(vals);
 854                 dev_err(dev, "Error to get property\n");
 855                 return;
 856         }
 857
 858         incrx_size = *vals;
 859
 860         if (ntype > 1) {
 861                 /* INCRX (undefined length) burst mode */
 862                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 863                 for (i = 1; i < ntype; i++) {
 864                         if (vals[i] > incrx_size)
 865                                 incrx_size = vals[i];
 866                 }
 867         } else {
 868                 /* INCRX burst mode */
 869                 incrx_mode = INCRX_BURST_MODE;
 870         }
 871
 872         kfree(vals);
 873
 874         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 875         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 876         if (incrx_mode)
 877                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 878         switch (incrx_size) {
 879         case 256:
 880                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 881                 break;
 882         case 128:
 883                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 884                 break;
 885         case 64:
 886                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 887                 break;
 888         case 32:
 889                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 890                 break;
 891         case 16:
 892                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 893                 break;
 894         case 8:
 895                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 896                 break;
 897         case 4:
 898                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 899                 break;
 900         case 1:
 901                 break;
 902         default:
 903                 dev_err(dev, "Invalid property\n");
 904                 break;
 905         }
 906
 907         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 908 }
 909
 910 /**
 911  * dwc3_core_init - Low-level initialization of DWC3 Core
 912  * @dwc: Pointer to our controller context structure
 913  *
 914  * Returns 0 on success otherwise negative errno.
 915  */
 916 static int dwc3_core_init(struct dwc3 *dwc)
 917 {
 918         unsigned int            hw_mode;
 919         u32                     reg;
 920         int                     ret;
 921
 922         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 923
 924         /*
 925          * Write Linux Version Code to our GUID register so it's easy to figure
 926          * out which kernel version a bug was found.
 927          */
 928         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 929
 930         /* Handle USB2.0-only core configuration */
 931         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 932                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 933                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 934                         dwc->maximum_speed = USB_SPEED_HIGH;
 935         }
 936
 937         ret = dwc3_phy_setup(dwc);
 938         if (ret)
 939                 goto err0;
 940
 941         if (!dwc->ulpi_ready) {
 942                 ret = dwc3_core_ulpi_init(dwc);
 943                 if (ret)
 944                         goto err0;
 945                 dwc->ulpi_ready = true;
 946         }
 947
 948         if (!dwc->phys_ready) {
 949                 ret = dwc3_core_get_phy(dwc);
 950                 if (ret)
 951                         goto err0a;
 952                 dwc->phys_ready = true;
 953         }
 954
 955         ret = dwc3_core_soft_reset(dwc);
 956         if (ret)
 957                 goto err0a;
 958
 959         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
 960             dwc->revision > DWC3_REVISION_194A) {
 961                 if (!dwc->dis_u3_susphy_quirk) {
 962                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 963                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 964                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 965                 }
 966
 967                 if (!dwc->dis_u2_susphy_quirk) {
 968                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 969                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 970                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 971                 }
 972         }
 973
 974         dwc3_core_setup_global_control(dwc);
 975         dwc3_core_num_eps(dwc);
 976
 977         ret = dwc3_setup_scratch_buffers(dwc);
 978         if (ret)
 979                 goto err1;
 980
 981         /* Adjust Frame Length */
 982         dwc3_frame_length_adjustment(dwc);
 983
 984         dwc3_set_incr_burst_type(dwc);
 985
 986         usb_phy_set_suspend(dwc->usb2_phy, 0);
 987         usb_phy_set_suspend(dwc->usb3_phy, 0);
 988         ret = phy_power_on(dwc->usb2_generic_phy);
 989         if (ret < 0)
 990                 goto err2;
 991
 992         ret = phy_power_on(dwc->usb3_generic_phy);
 993         if (ret < 0)
 994                 goto err3;
 995
 996         ret = dwc3_event_buffers_setup(dwc);
 997         if (ret) {
 998                 dev_err(dwc->dev, "failed to setup event buffers\n");
 999                 goto err4;
1000         }
1001
1002         /*
1003          * ENDXFER polling is available on version 3.10a and later of
1004          * the DWC_usb3 controller. It is NOT available in the
1005          * DWC_usb31 controller.
1006          */
1007         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
1008                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1009                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1010                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1011         }
1012
1013         if (dwc->revision >= DWC3_REVISION_250A) {
1014                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1015
1016                 /*
1017                  * Enable hardware control of sending remote wakeup
1018                  * in HS when the device is in the L1 state.
1019                  */
1020                 if (dwc->revision >= DWC3_REVISION_290A)
1021                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1022
1023                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1024                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1025
1026                 if (dwc->parkmode_disable_ss_quirk)
1027                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1028
1029                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1030         }
1031
1032         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1033             dwc->dr_mode == USB_DR_MODE_OTG) {
1034                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1035
1036                 /*
1037                  * Enable Auto retry Feature to make the controller operating in
1038                  * Host mode on seeing transaction errors(CRC errors or internal
1039                  * overrun scenerios) on IN transfers to reply to the device
1040                  * with a non-terminating retry ACK (i.e, an ACK transcation
1041                  * packet with Retry=1 & Nump != 0)
1042                  */
1043                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1044
1045                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1046         }
1047
1048         /*
1049          * Must config both number of packets and max burst settings to enable
1050          * RX and/or TX threshold.
1051          */
1052         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1053                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1054                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1055                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1056                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1057
1058                 if (rx_thr_num && rx_maxburst) {
1059                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1060                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1061
1062                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1063                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1064
1065                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1066                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1067
1068                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1069                 }
1070
1071                 if (tx_thr_num && tx_maxburst) {
1072                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1073                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1074
1075                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1076                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1077
1078                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1079                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1080
1081                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1082                 }
1083         }
1084
1085         return 0;
1086
1087 err4:
1088         phy_power_off(dwc->usb3_generic_phy);
1089
1090 err3:
1091         phy_power_off(dwc->usb2_generic_phy);
1092
1093 err2:
1094         usb_phy_set_suspend(dwc->usb2_phy, 1);
1095         usb_phy_set_suspend(dwc->usb3_phy, 1);
1096
1097 err1:
1098         usb_phy_shutdown(dwc->usb2_phy);
1099         usb_phy_shutdown(dwc->usb3_phy);
1100         phy_exit(dwc->usb2_generic_phy);
1101         phy_exit(dwc->usb3_generic_phy);
1102
1103 err0a:
1104         dwc3_ulpi_exit(dwc);
1105
1106 err0:
1107         return ret;
1108 }
1109
1110 static int dwc3_core_get_phy(struct dwc3 *dwc)
1111 {
1112         struct device           *dev = dwc->dev;
1113         struct device_node      *node = dev->of_node;
1114         int ret;
1115
1116         if (node) {
1117                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1118                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1119         } else {
1120                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1121                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1122         }
1123
1124         if (IS_ERR(dwc->usb2_phy)) {
1125                 ret = PTR_ERR(dwc->usb2_phy);
1126                 if (ret == -ENXIO || ret == -ENODEV) {
1127                         dwc->usb2_phy = NULL;
1128                 } else if (ret == -EPROBE_DEFER) {
1129                         return ret;
1130                 } else {
1131                         dev_err(dev, "no usb2 phy configured\n");
1132                         return ret;
1133                 }
1134         }
1135
1136         if (IS_ERR(dwc->usb3_phy)) {
1137                 ret = PTR_ERR(dwc->usb3_phy);
1138                 if (ret == -ENXIO || ret == -ENODEV) {
1139                         dwc->usb3_phy = NULL;
1140                 } else if (ret == -EPROBE_DEFER) {
1141                         return ret;
1142                 } else {
1143                         dev_err(dev, "no usb3 phy configured\n");
1144                         return ret;
1145                 }
1146         }
1147
1148         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1149         if (IS_ERR(dwc->usb2_generic_phy)) {
1150                 ret = PTR_ERR(dwc->usb2_generic_phy);
1151                 if (ret == -ENOSYS || ret == -ENODEV) {
1152                         dwc->usb2_generic_phy = NULL;
1153                 } else if (ret == -EPROBE_DEFER) {
1154                         return ret;
1155                 } else {
1156                         dev_err(dev, "no usb2 phy configured\n");
1157                         return ret;
1158                 }
1159         }
1160
1161         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1162         if (IS_ERR(dwc->usb3_generic_phy)) {
1163                 ret = PTR_ERR(dwc->usb3_generic_phy);
1164                 if (ret == -ENOSYS || ret == -ENODEV) {
1165                         dwc->usb3_generic_phy = NULL;
1166                 } else if (ret == -EPROBE_DEFER) {
1167                         return ret;
1168                 } else {
1169                         dev_err(dev, "no usb3 phy configured\n");
1170                         return ret;
1171                 }
1172         }
1173
1174         return 0;
1175 }
1176
1177 static int dwc3_core_init_mode(struct dwc3 *dwc)
1178 {
1179         struct device *dev = dwc->dev;
1180         int ret;
1181
1182         switch (dwc->dr_mode) {
1183         case USB_DR_MODE_PERIPHERAL:
1184                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1185
1186                 if (dwc->usb2_phy)
1187                         otg_set_vbus(dwc->usb2_phy->otg, false);
1188                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1189                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1190
1191                 ret = dwc3_gadget_init(dwc);
1192                 if (ret) {
1193                         if (ret != -EPROBE_DEFER)
1194                                 dev_err(dev, "failed to initialize gadget\n");
1195                         return ret;
1196                 }
1197                 break;
1198         case USB_DR_MODE_HOST:
1199                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1200
1201                 if (dwc->usb2_phy)
1202                         otg_set_vbus(dwc->usb2_phy->otg, true);
1203                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1204                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1205
1206                 ret = dwc3_host_init(dwc);
1207                 if (ret) {
1208                         if (ret != -EPROBE_DEFER)
1209                                 dev_err(dev, "failed to initialize host\n");
1210                         return ret;
1211                 }
1212                 break;
1213         case USB_DR_MODE_OTG:
1214                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1215                 ret = dwc3_drd_init(dwc);
1216                 if (ret) {
1217                         if (ret != -EPROBE_DEFER)
1218                                 dev_err(dev, "failed to initialize dual-role\n");
1219                         return ret;
1220                 }
1221                 break;
1222         default:
1223                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1224                 return -EINVAL;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1231 {
1232         switch (dwc->dr_mode) {
1233         case USB_DR_MODE_PERIPHERAL:
1234                 dwc3_gadget_exit(dwc);
1235                 break;
1236         case USB_DR_MODE_HOST:
1237                 dwc3_host_exit(dwc);
1238                 break;
1239         case USB_DR_MODE_OTG:
1240                 dwc3_drd_exit(dwc);
1241                 break;
1242         default:
1243                 /* do nothing */
1244                 break;
1245         }
1246
1247         /* de-assert DRVVBUS for HOST and OTG mode */
1248         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1249 }
1250
1251 static void dwc3_get_properties(struct dwc3 *dwc)
1252 {
1253         struct device           *dev = dwc->dev;
1254         u8                      lpm_nyet_threshold;
1255         u8                      tx_de_emphasis;
1256         u8                      hird_threshold;
1257         u8                      rx_thr_num_pkt_prd;
1258         u8                      rx_max_burst_prd;
1259         u8                      tx_thr_num_pkt_prd;
1260         u8                      tx_max_burst_prd;
1261
1262         /* default to highest possible threshold */
1263         lpm_nyet_threshold = 0xf;
1264
1265         /* default to -3.5dB de-emphasis */
1266         tx_de_emphasis = 1;
1267
1268         /*
1269          * default to assert utmi_sleep_n and use maximum allowed HIRD
1270          * threshold value of 0b1100
1271          */
1272         hird_threshold = 12;
1273
1274         dwc->maximum_speed = usb_get_maximum_speed(dev);
1275         dwc->dr_mode = usb_get_dr_mode(dev);
1276         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1277
1278         dwc->sysdev_is_parent = device_property_read_bool(dev,
1279                                 "linux,sysdev_is_parent");
1280         if (dwc->sysdev_is_parent)
1281                 dwc->sysdev = dwc->dev->parent;
1282         else
1283                 dwc->sysdev = dwc->dev;
1284
1285         dwc->has_lpm_erratum = device_property_read_bool(dev,
1286                                 "snps,has-lpm-erratum");
1287         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1288                                 &lpm_nyet_threshold);
1289         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1290                                 "snps,is-utmi-l1-suspend");
1291         device_property_read_u8(dev, "snps,hird-threshold",
1292                                 &hird_threshold);
1293         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1294                                 "snps,dis-start-transfer-quirk");
1295         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1296                                 "snps,usb3_lpm_capable");
1297         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1298                                 "snps,usb2-lpm-disable");
1299         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1300                                 &rx_thr_num_pkt_prd);
1301         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1302                                 &rx_max_burst_prd);
1303         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1304                                 &tx_thr_num_pkt_prd);
1305         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1306                                 &tx_max_burst_prd);
1307
1308         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1309                                 "snps,disable_scramble_quirk");
1310         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1311                                 "snps,u2exit_lfps_quirk");
1312         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1313                                 "snps,u2ss_inp3_quirk");
1314         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1315                                 "snps,req_p1p2p3_quirk");
1316         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1317                                 "snps,del_p1p2p3_quirk");
1318         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1319                                 "snps,del_phy_power_chg_quirk");
1320         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1321                                 "snps,lfps_filter_quirk");
1322         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1323                                 "snps,rx_detect_poll_quirk");
1324         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1325                                 "snps,dis_u3_susphy_quirk");
1326         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1327                                 "snps,dis_u2_susphy_quirk");
1328         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1329                                 "snps,dis_enblslpm_quirk");
1330         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1331                                 "snps,dis-u1-entry-quirk");
1332         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1333                                 "snps,dis-u2-entry-quirk");
1334         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1335                                 "snps,dis_rxdet_inp3_quirk");
1336         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1337                                 "snps,dis-u2-freeclk-exists-quirk");
1338         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1339                                 "snps,dis-del-phy-power-chg-quirk");
1340         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1341                                 "snps,dis-tx-ipgap-linecheck-quirk");
1342         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1343                                 "snps,parkmode-disable-ss-quirk");
1344
1345         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1346                                 "snps,tx_de_emphasis_quirk");
1347         device_property_read_u8(dev, "snps,tx_de_emphasis",
1348                                 &tx_de_emphasis);
1349         device_property_read_string(dev, "snps,hsphy_interface",
1350                                     &dwc->hsphy_interface);
1351         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1352                                  &dwc->fladj);
1353
1354         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1355                                 "snps,dis_metastability_quirk");
1356
1357         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1358         dwc->tx_de_emphasis = tx_de_emphasis;
1359
1360         dwc->hird_threshold = hird_threshold;
1361
1362         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1363         dwc->rx_max_burst_prd = rx_max_burst_prd;
1364
1365         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1366         dwc->tx_max_burst_prd = tx_max_burst_prd;
1367
1368         dwc->imod_interval = 0;
1369 }
1370
1371 /* check whether the core supports IMOD */
1372 bool dwc3_has_imod(struct dwc3 *dwc)
1373 {
1374         return ((dwc3_is_usb3(dwc) &&
1375                  dwc->revision >= DWC3_REVISION_300A) ||
1376                 (dwc3_is_usb31(dwc) &&
1377                  dwc->revision >= DWC3_USB31_REVISION_120A));
1378 }
1379
1380 static void dwc3_check_params(struct dwc3 *dwc)
1381 {
1382         struct device *dev = dwc->dev;
1383
1384         /* Check for proper value of imod_interval */
1385         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1386                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1387                 dwc->imod_interval = 0;
1388         }
1389
1390         /*
1391          * Workaround for STAR 9000961433 which affects only version
1392          * 3.00a of the DWC_usb3 core. This prevents the controller
1393          * interrupt from being masked while handling events. IMOD
1394          * allows us to work around this issue. Enable it for the
1395          * affected version.
1396          */
1397         if (!dwc->imod_interval &&
1398             (dwc->revision == DWC3_REVISION_300A))
1399                 dwc->imod_interval = 1;
1400
1401         /* Check the maximum_speed parameter */
1402         switch (dwc->maximum_speed) {
1403         case USB_SPEED_LOW:
1404         case USB_SPEED_FULL:
1405         case USB_SPEED_HIGH:
1406         case USB_SPEED_SUPER:
1407         case USB_SPEED_SUPER_PLUS:
1408                 break;
1409         default:
1410                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1411                         dwc->maximum_speed);
1412                 /* fall through */
1413         case USB_SPEED_UNKNOWN:
1414                 /* default to superspeed */
1415                 dwc->maximum_speed = USB_SPEED_SUPER;
1416
1417                 /*
1418                  * default to superspeed plus if we are capable.
1419                  */
1420                 if (dwc3_is_usb31(dwc) &&
1421                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1422                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1423                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1424
1425                 break;
1426         }
1427 }
1428
1429 static int dwc3_probe(struct platform_device *pdev)
1430 {
1431         struct device           *dev = &pdev->dev;
1432         struct resource         *res, dwc_res;
1433         struct dwc3             *dwc;
1434
1435         int                     ret;
1436
1437         void __iomem            *regs;
1438
1439         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1440         if (!dwc)
1441                 return -ENOMEM;
1442
1443         dwc->dev = dev;
1444
1445         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1446         if (!res) {
1447                 dev_err(dev, "missing memory resource\n");
1448                 return -ENODEV;
1449         }
1450
1451         dwc->xhci_resources[0].start = res->start;
1452         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1453                                         DWC3_XHCI_REGS_END;
1454         dwc->xhci_resources[0].flags = res->flags;
1455         dwc->xhci_resources[0].name = res->name;
1456
1457         /*
1458          * Request memory region but exclude xHCI regs,
1459          * since it will be requested by the xhci-plat driver.
1460          */
1461         dwc_res = *res;
1462         dwc_res.start += DWC3_GLOBALS_REGS_START;
1463
1464         regs = devm_ioremap_resource(dev, &dwc_res);
1465         if (IS_ERR(regs))
1466                 return PTR_ERR(regs);
1467
1468         dwc->regs       = regs;
1469         dwc->regs_size  = resource_size(&dwc_res);
1470
1471         dwc3_get_properties(dwc);
1472
1473         dwc->reset = devm_reset_control_array_get(dev, true, true);
1474         if (IS_ERR(dwc->reset))
1475                 return PTR_ERR(dwc->reset);
1476
1477         if (dev->of_node) {
1478                 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1479                 if (ret == -EPROBE_DEFER)
1480                         return ret;
1481                 /*
1482                  * Clocks are optional, but new DT platforms should support all
1483                  * clocks as required by the DT-binding.
1484                  */
1485                 if (ret < 0)
1486                         dwc->num_clks = 0;
1487                 else
1488                         dwc->num_clks = ret;
1489
1490         }
1491
1492         ret = reset_control_deassert(dwc->reset);
1493         if (ret)
1494                 return ret;
1495
1496         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1497         if (ret)
1498                 goto assert_reset;
1499
1500         if (!dwc3_core_is_valid(dwc)) {
1501                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1502                 ret = -ENODEV;
1503                 goto disable_clks;
1504         }
1505
1506         platform_set_drvdata(pdev, dwc);
1507         dwc3_cache_hwparams(dwc);
1508
1509         spin_lock_init(&dwc->lock);
1510
1511         pm_runtime_set_active(dev);
1512         pm_runtime_use_autosuspend(dev);
1513         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1514         pm_runtime_enable(dev);
1515         ret = pm_runtime_get_sync(dev);
1516         if (ret < 0)
1517                 goto err1;
1518
1519         pm_runtime_forbid(dev);
1520
1521         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1522         if (ret) {
1523                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1524                 ret = -ENOMEM;
1525                 goto err2;
1526         }
1527
1528         ret = dwc3_get_dr_mode(dwc);
1529         if (ret)
1530                 goto err3;
1531
1532         ret = dwc3_alloc_scratch_buffers(dwc);
1533         if (ret)
1534                 goto err3;
1535
1536         ret = dwc3_core_init(dwc);
1537         if (ret) {
1538                 if (ret != -EPROBE_DEFER)
1539                         dev_err(dev, "failed to initialize core: %d\n", ret);
1540                 goto err4;
1541         }
1542
1543         dwc3_check_params(dwc);
1544
1545         ret = dwc3_core_init_mode(dwc);
1546         if (ret)
1547                 goto err5;
1548
1549         dwc3_debugfs_init(dwc);
1550         pm_runtime_put(dev);
1551
1552         return 0;
1553
1554 err5:
1555         dwc3_event_buffers_cleanup(dwc);
1556         dwc3_ulpi_exit(dwc);
1557
1558 err4:
1559         dwc3_free_scratch_buffers(dwc);
1560
1561 err3:
1562         dwc3_free_event_buffers(dwc);
1563
1564 err2:
1565         pm_runtime_allow(&pdev->dev);
1566
1567 err1:
1568         pm_runtime_put_sync(&pdev->dev);
1569         pm_runtime_disable(&pdev->dev);
1570
1571 disable_clks:
1572         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1573 assert_reset:
1574         reset_control_assert(dwc->reset);
1575
1576         return ret;
1577 }
1578
1579 static int dwc3_remove(struct platform_device *pdev)
1580 {
1581         struct dwc3     *dwc = platform_get_drvdata(pdev);
1582
1583         pm_runtime_get_sync(&pdev->dev);
1584
1585         dwc3_debugfs_exit(dwc);
1586         dwc3_core_exit_mode(dwc);
1587
1588         dwc3_core_exit(dwc);
1589         dwc3_ulpi_exit(dwc);
1590
1591         pm_runtime_put_sync(&pdev->dev);
1592         pm_runtime_allow(&pdev->dev);
1593         pm_runtime_disable(&pdev->dev);
1594
1595         dwc3_free_event_buffers(dwc);
1596         dwc3_free_scratch_buffers(dwc);
1597
1598         return 0;
1599 }
1600
1601 #ifdef CONFIG_PM
1602 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1603 {
1604         int ret;
1605
1606         ret = reset_control_deassert(dwc->reset);
1607         if (ret)
1608                 return ret;
1609
1610         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1611         if (ret)
1612                 goto assert_reset;
1613
1614         ret = dwc3_core_init(dwc);
1615         if (ret)
1616                 goto disable_clks;
1617
1618         return 0;
1619
1620 disable_clks:
1621         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1622 assert_reset:
1623         reset_control_assert(dwc->reset);
1624
1625         return ret;
1626 }
1627
1628 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1629 {
1630         unsigned long   flags;
1631         u32 reg;
1632
1633         switch (dwc->current_dr_role) {
1634         case DWC3_GCTL_PRTCAP_DEVICE:
1635                 if (pm_runtime_suspended(dwc->dev))
1636                         break;
1637                 spin_lock_irqsave(&dwc->lock, flags);
1638                 dwc3_gadget_suspend(dwc);
1639                 spin_unlock_irqrestore(&dwc->lock, flags);
1640                 synchronize_irq(dwc->irq_gadget);
1641                 dwc3_core_exit(dwc);
1642                 break;
1643         case DWC3_GCTL_PRTCAP_HOST:
1644                 if (!PMSG_IS_AUTO(msg)) {
1645                         dwc3_core_exit(dwc);
1646                         break;
1647                 }
1648
1649                 /* Let controller to suspend HSPHY before PHY driver suspends */
1650                 if (dwc->dis_u2_susphy_quirk ||
1651                     dwc->dis_enblslpm_quirk) {
1652                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1653                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1654                                 DWC3_GUSB2PHYCFG_SUSPHY;
1655                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1656
1657                         /* Give some time for USB2 PHY to suspend */
1658                         usleep_range(5000, 6000);
1659                 }
1660
1661                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1662                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1663                 break;
1664         case DWC3_GCTL_PRTCAP_OTG:
1665                 /* do nothing during runtime_suspend */
1666                 if (PMSG_IS_AUTO(msg))
1667                         break;
1668
1669                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1670                         spin_lock_irqsave(&dwc->lock, flags);
1671                         dwc3_gadget_suspend(dwc);
1672                         spin_unlock_irqrestore(&dwc->lock, flags);
1673                         synchronize_irq(dwc->irq_gadget);
1674                 }
1675
1676                 dwc3_otg_exit(dwc);
1677                 dwc3_core_exit(dwc);
1678                 break;
1679         default:
1680                 /* do nothing */
1681                 break;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1688 {
1689         unsigned long   flags;
1690         int             ret;
1691         u32             reg;
1692
1693         switch (dwc->current_dr_role) {
1694         case DWC3_GCTL_PRTCAP_DEVICE:
1695                 ret = dwc3_core_init_for_resume(dwc);
1696                 if (ret)
1697                         return ret;
1698
1699                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1700                 spin_lock_irqsave(&dwc->lock, flags);
1701                 dwc3_gadget_resume(dwc);
1702                 spin_unlock_irqrestore(&dwc->lock, flags);
1703                 break;
1704         case DWC3_GCTL_PRTCAP_HOST:
1705                 if (!PMSG_IS_AUTO(msg)) {
1706                         ret = dwc3_core_init_for_resume(dwc);
1707                         if (ret)
1708                                 return ret;
1709                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1710                         break;
1711                 }
1712                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1713                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1714                 if (dwc->dis_u2_susphy_quirk)
1715                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1716
1717                 if (dwc->dis_enblslpm_quirk)
1718                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1719
1720                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1721
1722                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1723                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1724                 break;
1725         case DWC3_GCTL_PRTCAP_OTG:
1726                 /* nothing to do on runtime_resume */
1727                 if (PMSG_IS_AUTO(msg))
1728                         break;
1729
1730                 ret = dwc3_core_init(dwc);
1731                 if (ret)
1732                         return ret;
1733
1734                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1735
1736                 dwc3_otg_init(dwc);
1737                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1738                         dwc3_otg_host_init(dwc);
1739                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1740                         spin_lock_irqsave(&dwc->lock, flags);
1741                         dwc3_gadget_resume(dwc);
1742                         spin_unlock_irqrestore(&dwc->lock, flags);
1743                 }
1744
1745                 break;
1746         default:
1747                 /* do nothing */
1748                 break;
1749         }
1750
1751         return 0;
1752 }
1753
1754 static int dwc3_runtime_checks(struct dwc3 *dwc)
1755 {
1756         switch (dwc->current_dr_role) {
1757         case DWC3_GCTL_PRTCAP_DEVICE:
1758                 if (dwc->connected)
1759                         return -EBUSY;
1760                 break;
1761         case DWC3_GCTL_PRTCAP_HOST:
1762         default:
1763                 /* do nothing */
1764                 break;
1765         }
1766
1767         return 0;
1768 }
1769
1770 static int dwc3_runtime_suspend(struct device *dev)
1771 {
1772         struct dwc3     *dwc = dev_get_drvdata(dev);
1773         int             ret;
1774
1775         if (dwc3_runtime_checks(dwc))
1776                 return -EBUSY;
1777
1778         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1779         if (ret)
1780                 return ret;
1781
1782         device_init_wakeup(dev, true);
1783
1784         return 0;
1785 }
1786
1787 static int dwc3_runtime_resume(struct device *dev)
1788 {
1789         struct dwc3     *dwc = dev_get_drvdata(dev);
1790         int             ret;
1791
1792         device_init_wakeup(dev, false);
1793
1794         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1795         if (ret)
1796                 return ret;
1797
1798         switch (dwc->current_dr_role) {
1799         case DWC3_GCTL_PRTCAP_DEVICE:
1800                 dwc3_gadget_process_pending_events(dwc);
1801                 break;
1802         case DWC3_GCTL_PRTCAP_HOST:
1803         default:
1804                 /* do nothing */
1805                 break;
1806         }
1807
1808         pm_runtime_mark_last_busy(dev);
1809
1810         return 0;
1811 }
1812
1813 static int dwc3_runtime_idle(struct device *dev)
1814 {
1815         struct dwc3     *dwc = dev_get_drvdata(dev);
1816
1817         switch (dwc->current_dr_role) {
1818         case DWC3_GCTL_PRTCAP_DEVICE:
1819                 if (dwc3_runtime_checks(dwc))
1820                         return -EBUSY;
1821                 break;
1822         case DWC3_GCTL_PRTCAP_HOST:
1823         default:
1824                 /* do nothing */
1825                 break;
1826         }
1827
1828         pm_runtime_mark_last_busy(dev);
1829         pm_runtime_autosuspend(dev);
1830
1831         return 0;
1832 }
1833 #endif /* CONFIG_PM */
1834
1835 #ifdef CONFIG_PM_SLEEP
1836 static int dwc3_suspend(struct device *dev)
1837 {
1838         struct dwc3     *dwc = dev_get_drvdata(dev);
1839         int             ret;
1840
1841         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1842         if (ret)
1843                 return ret;
1844
1845         pinctrl_pm_select_sleep_state(dev);
1846
1847         return 0;
1848 }
1849
1850 static int dwc3_resume(struct device *dev)
1851 {
1852         struct dwc3     *dwc = dev_get_drvdata(dev);
1853         int             ret;
1854
1855         pinctrl_pm_select_default_state(dev);
1856
1857         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1858         if (ret)
1859                 return ret;
1860
1861         pm_runtime_disable(dev);
1862         pm_runtime_set_active(dev);
1863         pm_runtime_enable(dev);
1864
1865         return 0;
1866 }
1867 #endif /* CONFIG_PM_SLEEP */
1868
1869 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1870         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1871         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1872                         dwc3_runtime_idle)
1873 };
1874
1875 #ifdef CONFIG_OF
1876 static const struct of_device_id of_dwc3_match[] = {
1877         {
1878                 .compatible = "snps,dwc3"
1879         },
1880         {
1881                 .compatible = "synopsys,dwc3"
1882         },
1883         { },
1884 };
1885 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1886 #endif
1887
1888 #ifdef CONFIG_ACPI
1889
1890 #define ACPI_ID_INTEL_BSW       "808622B7"
1891
1892 static const struct acpi_device_id dwc3_acpi_match[] = {
1893         { ACPI_ID_INTEL_BSW, 0 },
1894         { },
1895 };
1896 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1897 #endif
1898
1899 static struct platform_driver dwc3_driver = {
1900         .probe          = dwc3_probe,
1901         .remove         = dwc3_remove,
1902         .driver         = {
1903                 .name   = "dwc3",
1904                 .of_match_table = of_match_ptr(of_dwc3_match),
1905                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1906                 .pm     = &dwc3_dev_pm_ops,
1907         },
1908 };
1909
1910 module_platform_driver(dwc3_driver);
1911
1912 MODULE_ALIAS("platform:dwc3");
1913 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1914 MODULE_LICENSE("GPL v2");
1915 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");