2 * Copyright (C) 2004-2016 Synopsys, Inc.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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15 * specific prior written permission.
17 * ALTERNATIVELY, this software may be distributed under the terms of the
18 * GNU General Public License ("GPL") as published by the Free Software
19 * Foundation; either version 2 of the License, or (at your option) any
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32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/of_device.h>
41 static const struct dwc2_core_params params_hi6220 = {
42 .otg_cap = 2, /* No HNP/SRP capable */
43 .otg_ver = 0, /* 1.3 */
45 .dma_desc_fs_enable = 0,
46 .speed = 0, /* High Speed */
47 .enable_dynamic_fifo = 1,
48 .en_multiple_tx_fifo = 1,
49 .host_rx_fifo_size = 512,
50 .host_nperio_tx_fifo_size = 512,
51 .host_perio_tx_fifo_size = 512,
52 .max_transfer_size = 65535,
53 .max_packet_count = 511,
55 .phy_type = 1, /* UTMI */
57 .phy_ulpi_ddr = 0, /* Single */
58 .phy_ulpi_ext_vbus = 0,
61 .host_support_fs_ls_low_power = 0,
62 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
65 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
66 GAHBCFG_HBSTLEN_SHIFT,
68 .external_id_pin_ctl = -1,
72 static const struct dwc2_core_params params_bcm2835 = {
73 .otg_cap = 0, /* HNP/SRP capable */
74 .otg_ver = 0, /* 1.3 */
76 .dma_desc_fs_enable = 0,
77 .speed = 0, /* High Speed */
78 .enable_dynamic_fifo = 1,
79 .en_multiple_tx_fifo = 1,
80 .host_rx_fifo_size = 774, /* 774 DWORDs */
81 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
82 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
83 .max_transfer_size = 65535,
84 .max_packet_count = 511,
86 .phy_type = 1, /* UTMI */
87 .phy_utmi_width = 8, /* 8 bits */
88 .phy_ulpi_ddr = 0, /* Single */
89 .phy_ulpi_ext_vbus = 0,
92 .host_support_fs_ls_low_power = 0,
93 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
98 .external_id_pin_ctl = -1,
102 static const struct dwc2_core_params params_rk3066 = {
103 .otg_cap = 2, /* non-HNP/non-SRP */
105 .dma_desc_enable = 0,
106 .dma_desc_fs_enable = 0,
108 .enable_dynamic_fifo = 1,
109 .en_multiple_tx_fifo = -1,
110 .host_rx_fifo_size = 525, /* 525 DWORDs */
111 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
112 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
113 .max_transfer_size = -1,
114 .max_packet_count = -1,
117 .phy_utmi_width = -1,
119 .phy_ulpi_ext_vbus = -1,
122 .host_support_fs_ls_low_power = -1,
123 .host_ls_low_power_phy_clk = -1,
126 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
127 GAHBCFG_HBSTLEN_SHIFT,
129 .external_id_pin_ctl = -1,
133 static const struct dwc2_core_params params_ltq = {
134 .otg_cap = 2, /* non-HNP/non-SRP */
136 .dma_desc_enable = -1,
137 .dma_desc_fs_enable = -1,
139 .enable_dynamic_fifo = -1,
140 .en_multiple_tx_fifo = -1,
141 .host_rx_fifo_size = 288, /* 288 DWORDs */
142 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
143 .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
144 .max_transfer_size = 65535,
145 .max_packet_count = 511,
148 .phy_utmi_width = -1,
150 .phy_ulpi_ext_vbus = -1,
153 .host_support_fs_ls_low_power = -1,
154 .host_ls_low_power_phy_clk = -1,
157 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
158 GAHBCFG_HBSTLEN_SHIFT,
160 .external_id_pin_ctl = -1,
164 static const struct dwc2_core_params params_amlogic = {
165 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
167 .dma_desc_enable = 0,
168 .dma_desc_fs_enable = 0,
169 .speed = DWC2_SPEED_PARAM_HIGH,
170 .enable_dynamic_fifo = 1,
171 .en_multiple_tx_fifo = -1,
172 .host_rx_fifo_size = 512,
173 .host_nperio_tx_fifo_size = 500,
174 .host_perio_tx_fifo_size = 500,
175 .max_transfer_size = -1,
176 .max_packet_count = -1,
178 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
179 .phy_utmi_width = -1,
181 .phy_ulpi_ext_vbus = -1,
184 .host_support_fs_ls_low_power = -1,
185 .host_ls_low_power_phy_clk = -1,
188 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
189 GAHBCFG_HBSTLEN_SHIFT,
191 .external_id_pin_ctl = -1,
195 static const struct dwc2_core_params params_default = {
200 * Disable descriptor dma mode by default as the HW can support
201 * it, but does not support it for SPLIT transactions.
202 * Disable it for FS devices as well.
204 .dma_desc_enable = 0,
205 .dma_desc_fs_enable = 0,
208 .enable_dynamic_fifo = -1,
209 .en_multiple_tx_fifo = -1,
210 .host_rx_fifo_size = -1,
211 .host_nperio_tx_fifo_size = -1,
212 .host_perio_tx_fifo_size = -1,
213 .max_transfer_size = -1,
214 .max_packet_count = -1,
217 .phy_utmi_width = -1,
219 .phy_ulpi_ext_vbus = -1,
222 .host_support_fs_ls_low_power = -1,
223 .host_ls_low_power_phy_clk = -1,
228 .external_id_pin_ctl = -1,
232 const struct of_device_id dwc2_of_match_table[] = {
233 { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
234 { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 },
235 { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
236 { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq },
237 { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq },
238 { .compatible = "snps,dwc2", .data = NULL },
239 { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
240 { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
241 { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
244 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
246 static void dwc2_get_device_property(struct dwc2_hsotg *hsotg,
247 char *property, u8 size, u64 *value)
255 *value = device_property_read_bool(hsotg->dev, property);
258 if (device_property_read_u8(hsotg->dev, property, &val8))
264 if (device_property_read_u16(hsotg->dev, property, &val16))
270 if (device_property_read_u32(hsotg->dev, property, &val32))
276 if (device_property_read_u64(hsotg->dev, property, value))
282 * The size is checked by the only function that calls
283 * this so this should never happen.
290 static void dwc2_set_core_param(void *param, u8 size, u64 value)
294 *((bool *)param) = !!value;
297 *((u8 *)param) = (u8)value;
300 *((u16 *)param) = (u16)value;
303 *((u32 *)param) = (u32)value;
306 *((u64 *)param) = (u64)value;
310 * The size is checked by the only function that calls
311 * this so this should never happen.
319 * dwc2_set_param() - Set a core parameter
321 * @hsotg: Programming view of the DWC_otg controller
322 * @param: Pointer to the parameter to set
323 * @lookup: True if the property should be looked up
324 * @property: The device property to read
325 * @legacy: The param value to set if @property is not available. This
326 * will typically be the legacy value set in the static
328 * @def: The default value
329 * @min: The minimum value
330 * @max: The maximum value
331 * @size: The size of the core parameter in bytes, or 0 for bool.
333 * This function looks up @property and sets the @param to that value.
334 * If the property doesn't exist it uses the passed-in @value. It will
335 * verify that the value falls between @min and @max. If it doesn't,
336 * it will output an error and set the parameter to either @def or,
337 * failing that, to @min.
339 * The @size is used to write to @param and to query the device
340 * properties so that this same function can be used with different
341 * types of parameters.
343 static void dwc2_set_param(struct dwc2_hsotg *hsotg, void *param,
344 bool lookup, char *property, u64 legacy,
345 u64 def, u64 min, u64 max, u8 size)
350 if (WARN_ON(!hsotg || !param || !property))
353 if (WARN((size > 8) || ((size & (size - 1)) != 0),
354 "Invalid size %d for %s\n", size, property))
357 dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n",
358 __func__, property, legacy, def, min, max, size);
360 sizemax = (1ULL << (size * 8)) - 1;
363 /* Override legacy settings. */
365 dwc2_get_device_property(hsotg, property, size, &value);
368 * While the value is not valid, try setting it to the default
369 * value, and failing that, set it to the minimum.
371 while ((value < min) || (value > max)) {
372 /* Print an error unless the value is set to auto. */
373 if (value != sizemax)
374 dev_err(hsotg->dev, "Invalid value %llu for param %s\n",
378 * If we are already the default, just set it to the
382 dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n",
388 /* Try the default value */
389 dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n",
394 dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value);
395 dwc2_set_core_param(param, size, value);
399 * dwc2_set_param_u16() - Set a u16 parameter
401 * See dwc2_set_param().
403 static void dwc2_set_param_u16(struct dwc2_hsotg *hsotg, u16 *param,
404 bool lookup, char *property, u16 legacy,
405 u16 def, u16 min, u16 max)
407 dwc2_set_param(hsotg, param, lookup, property,
408 legacy, def, min, max, 2);
412 * dwc2_set_param_bool() - Set a bool parameter
414 * See dwc2_set_param().
416 * Note: there is no 'legacy' argument here because there is no legacy
417 * source of bool params.
419 static void dwc2_set_param_bool(struct dwc2_hsotg *hsotg, bool *param,
420 bool lookup, char *property,
421 bool def, bool min, bool max)
423 dwc2_set_param(hsotg, param, lookup, property,
424 def, def, min, max, 0);
427 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
429 /* Parameter access functions */
430 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
435 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
436 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
439 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
440 switch (hsotg->hw_params.op_mode) {
441 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
442 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
443 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
444 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
451 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
462 "%d invalid for otg_cap parameter. Check HW configuration.\n",
464 switch (hsotg->hw_params.op_mode) {
465 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
466 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
468 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
469 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
470 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
471 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
474 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
477 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
480 hsotg->params.otg_cap = val;
483 static void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
487 if (val > 0 && (hsotg->params.host_dma <= 0 ||
488 !hsotg->hw_params.dma_desc_enable))
496 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
498 val = (hsotg->params.host_dma > 0 &&
499 hsotg->hw_params.dma_desc_enable);
500 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
503 hsotg->params.dma_desc_enable = val;
506 static void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
510 if (val > 0 && (hsotg->params.host_dma <= 0 ||
511 !hsotg->hw_params.dma_desc_enable))
519 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
521 val = (hsotg->params.host_dma > 0 &&
522 hsotg->hw_params.dma_desc_enable);
525 hsotg->params.dma_desc_fs_enable = val;
526 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
530 dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
533 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
536 "Wrong value for host_support_fs_low_power\n");
538 "host_support_fs_low_power must be 0 or 1\n");
542 "Setting host_support_fs_low_power to %d\n", val);
545 hsotg->params.host_support_fs_ls_low_power = val;
548 static void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
553 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
561 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
563 val = hsotg->hw_params.enable_dynamic_fifo;
564 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
567 hsotg->params.enable_dynamic_fifo = val;
570 static void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
574 if (val < 16 || val > hsotg->hw_params.rx_fifo_size)
580 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
582 val = hsotg->hw_params.rx_fifo_size;
583 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
586 hsotg->params.host_rx_fifo_size = val;
589 static void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
594 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
600 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
602 val = hsotg->hw_params.host_nperio_tx_fifo_size;
603 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
607 hsotg->params.host_nperio_tx_fifo_size = val;
610 static void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
615 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
621 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
623 val = hsotg->hw_params.host_perio_tx_fifo_size;
624 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
628 hsotg->params.host_perio_tx_fifo_size = val;
631 static void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
635 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
641 "%d invalid for max_transfer_size. Check HW configuration.\n",
643 val = hsotg->hw_params.max_transfer_size;
644 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
647 hsotg->params.max_transfer_size = val;
650 static void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
654 if (val < 15 || val > hsotg->hw_params.max_packet_count)
660 "%d invalid for max_packet_count. Check HW configuration.\n",
662 val = hsotg->hw_params.max_packet_count;
663 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
666 hsotg->params.max_packet_count = val;
669 static void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
673 if (val < 1 || val > hsotg->hw_params.host_channels)
679 "%d invalid for host_channels. Check HW configuration.\n",
681 val = hsotg->hw_params.host_channels;
682 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
685 hsotg->params.host_channels = val;
688 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
691 u32 hs_phy_type, fs_phy_type;
693 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
694 DWC2_PHY_TYPE_PARAM_ULPI)) {
696 dev_err(hsotg->dev, "Wrong value for phy_type\n");
697 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
703 hs_phy_type = hsotg->hw_params.hs_phy_type;
704 fs_phy_type = hsotg->hw_params.fs_phy_type;
705 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
706 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
707 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
709 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
710 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
711 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
713 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
714 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
720 "%d invalid for phy_type. Check HW configuration.\n",
722 val = DWC2_PHY_TYPE_PARAM_FS;
723 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
724 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
725 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
726 val = DWC2_PHY_TYPE_PARAM_UTMI;
728 val = DWC2_PHY_TYPE_PARAM_ULPI;
730 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
733 hsotg->params.phy_type = val;
736 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
738 return hsotg->params.phy_type;
741 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
745 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
747 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
748 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
753 if (val == DWC2_SPEED_PARAM_HIGH &&
754 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
760 "%d invalid for speed parameter. Check HW configuration.\n",
762 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
763 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
764 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
767 hsotg->params.speed = val;
770 static void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
775 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
776 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
779 "Wrong value for host_ls_low_power_phy_clk parameter\n");
781 "host_ls_low_power_phy_clk must be 0 or 1\n");
786 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
787 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
793 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
795 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
796 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
797 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
798 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
802 hsotg->params.host_ls_low_power_phy_clk = val;
805 static void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
807 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
809 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
810 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
813 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
816 hsotg->params.phy_ulpi_ddr = val;
819 static void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
821 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
824 "Wrong value for phy_ulpi_ext_vbus\n");
826 "phy_ulpi_ext_vbus must be 0 or 1\n");
829 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
832 hsotg->params.phy_ulpi_ext_vbus = val;
835 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
839 switch (hsotg->hw_params.utmi_phy_data_width) {
840 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
843 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
846 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
847 valid = (val == 8 || val == 16);
854 "%d invalid for phy_utmi_width. Check HW configuration.\n",
857 val = (hsotg->hw_params.utmi_phy_data_width ==
858 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
859 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
862 hsotg->params.phy_utmi_width = val;
865 static void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
867 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
869 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
870 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
873 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
876 hsotg->params.ulpi_fs_ls = val;
879 static void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
881 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
883 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
884 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
887 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
890 hsotg->params.ts_dline = val;
893 static void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
897 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
899 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
900 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
906 if (val == 1 && !(hsotg->hw_params.i2c_enable))
912 "%d invalid for i2c_enable. Check HW configuration.\n",
914 val = hsotg->hw_params.i2c_enable;
915 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
918 hsotg->params.i2c_enable = val;
921 static void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
926 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
929 "Wrong value for en_multiple_tx_fifo,\n");
931 "en_multiple_tx_fifo must be 0 or 1\n");
936 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
942 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
944 val = hsotg->hw_params.en_multiple_tx_fifo;
945 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
948 hsotg->params.en_multiple_tx_fifo = val;
951 static void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
955 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
958 "'%d' invalid for parameter reload_ctl\n", val);
959 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
964 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
970 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
972 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
973 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
976 hsotg->params.reload_ctl = val;
979 static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
982 hsotg->params.ahbcfg = val;
984 hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
985 GAHBCFG_HBSTLEN_SHIFT;
988 static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
990 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
993 "'%d' invalid for parameter otg_ver\n", val);
995 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
998 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
1001 hsotg->params.otg_ver = val;
1004 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
1006 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1009 "'%d' invalid for parameter uframe_sched\n",
1011 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
1014 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
1017 hsotg->params.uframe_sched = val;
1020 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
1023 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1026 "'%d' invalid for parameter external_id_pin_ctl\n",
1028 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
1031 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
1034 hsotg->params.external_id_pin_ctl = val;
1037 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
1040 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1043 "'%d' invalid for parameter hibernation\n",
1045 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
1048 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
1051 hsotg->params.hibernation = val;
1054 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
1058 char *property = "g-tx-fifo-size";
1059 struct dwc2_core_params *p = &hsotg->params;
1061 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
1063 /* Read tx fifo sizes */
1064 num = device_property_read_u32_array(hsotg->dev, property, NULL, 0);
1067 device_property_read_u32_array(hsotg->dev, property,
1068 &p->g_tx_fifo_size[1],
1071 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
1073 memcpy(&p->g_tx_fifo_size[1],
1077 num = ARRAY_SIZE(p_tx_fifo);
1080 for (i = 0; i < num; i++) {
1081 if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size))
1084 dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n",
1085 property, i + 1, p->g_tx_fifo_size[i + 1]);
1089 static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg)
1091 struct dwc2_hw_params *hw = &hsotg->hw_params;
1092 struct dwc2_core_params *p = &hsotg->params;
1093 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1096 dwc2_set_param_bool(hsotg, &p->g_dma,
1097 false, "gadget-dma",
1103 * dwc2_set_parameters() - Set all core parameters.
1105 * @hsotg: Programming view of the DWC_otg controller
1106 * @params: The parameters to set
1108 static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1109 const struct dwc2_core_params *params)
1111 struct dwc2_hw_params *hw = &hsotg->hw_params;
1112 struct dwc2_core_params *p = &hsotg->params;
1113 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1115 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
1116 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
1117 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
1119 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
1120 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1123 dev_dbg(hsotg->dev, "Setting HOST parameters\n");
1125 disable = device_property_read_bool(hsotg->dev,
1126 "snps,host-dma-disable");
1128 dwc2_set_param_bool(hsotg, &p->host_dma,
1134 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1135 params->host_support_fs_ls_low_power);
1136 dwc2_set_param_enable_dynamic_fifo(hsotg,
1137 params->enable_dynamic_fifo);
1138 dwc2_set_param_host_rx_fifo_size(hsotg,
1139 params->host_rx_fifo_size);
1140 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
1141 params->host_nperio_tx_fifo_size);
1142 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
1143 params->host_perio_tx_fifo_size);
1144 dwc2_set_param_max_transfer_size(hsotg,
1145 params->max_transfer_size);
1146 dwc2_set_param_max_packet_count(hsotg,
1147 params->max_packet_count);
1148 dwc2_set_param_host_channels(hsotg, params->host_channels);
1149 dwc2_set_param_phy_type(hsotg, params->phy_type);
1150 dwc2_set_param_speed(hsotg, params->speed);
1151 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1152 params->host_ls_low_power_phy_clk);
1153 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1154 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1155 params->phy_ulpi_ext_vbus);
1156 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1157 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1158 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1159 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1160 dwc2_set_param_en_multiple_tx_fifo(hsotg,
1161 params->en_multiple_tx_fifo);
1162 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1163 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1164 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
1165 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
1166 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
1167 dwc2_set_param_hibernation(hsotg, params->hibernation);
1170 * Set devicetree-only parameters. These parameters do not
1171 * take any values from @params.
1173 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
1174 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1175 dev_dbg(hsotg->dev, "Setting peripheral device properties\n");
1177 dwc2_set_gadget_dma(hsotg);
1180 * The values for g_rx_fifo_size (2048) and
1181 * g_np_tx_fifo_size (1024) come from the legacy s3c
1182 * gadget driver. These defaults have been hard-coded
1183 * for some time so many platforms depend on these
1184 * values. Leave them as defaults for now and only
1185 * auto-detect if the hardware does not support the
1188 dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size,
1189 true, "g-rx-fifo-size", 2048,
1191 16, hw->rx_fifo_size);
1193 dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size,
1194 true, "g-np-tx-fifo-size", 1024,
1195 hw->dev_nperio_tx_fifo_size,
1196 16, hw->dev_nperio_tx_fifo_size);
1198 dwc2_set_param_tx_fifo_sizes(hsotg);
1203 * Gets host hardware parameters. Forces host mode if not currently in
1204 * host mode. Should be called immediately after a core soft reset in
1205 * order to get the reset values.
1207 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1209 struct dwc2_hw_params *hw = &hsotg->hw_params;
1214 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
1217 forced = dwc2_force_mode_if_needed(hsotg, true);
1219 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1220 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1221 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1222 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1225 dwc2_clear_force_mode(hsotg);
1227 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1228 FIFOSIZE_DEPTH_SHIFT;
1229 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1230 FIFOSIZE_DEPTH_SHIFT;
1234 * Gets device hardware parameters. Forces device mode if not
1235 * currently in device mode. Should be called immediately after a core
1236 * soft reset in order to get the reset values.
1238 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1240 struct dwc2_hw_params *hw = &hsotg->hw_params;
1244 if (hsotg->dr_mode == USB_DR_MODE_HOST)
1247 forced = dwc2_force_mode_if_needed(hsotg, false);
1249 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1250 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1253 dwc2_clear_force_mode(hsotg);
1255 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1256 FIFOSIZE_DEPTH_SHIFT;
1260 * During device initialization, read various hardware configuration
1261 * registers and interpret the contents.
1263 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1265 struct dwc2_hw_params *hw = &hsotg->hw_params;
1267 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
1271 * Attempt to ensure this device is really a DWC_otg Controller.
1272 * Read and verify the GSNPSID register contents. The value should be
1273 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
1274 * as in "OTG version 2.xx" or "OTG version 3.xx".
1276 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
1277 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
1278 (hw->snpsid & 0xfffff000) != 0x4f543000) {
1279 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
1284 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
1285 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
1286 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
1288 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
1289 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1290 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
1291 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
1292 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
1294 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
1295 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
1296 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1297 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
1298 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1301 * Host specific hardware parameters. Reading these parameters
1302 * requires the controller to be in host mode. The mode will
1303 * be forced, if necessary, to read these values.
1305 dwc2_get_host_hwparams(hsotg);
1306 dwc2_get_dev_hwparams(hsotg);
1309 hw->dev_ep_dirs = hwcfg1;
1312 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1313 GHWCFG2_OP_MODE_SHIFT;
1314 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
1315 GHWCFG2_ARCHITECTURE_SHIFT;
1316 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
1317 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
1318 GHWCFG2_NUM_HOST_CHAN_SHIFT);
1319 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
1320 GHWCFG2_HS_PHY_TYPE_SHIFT;
1321 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
1322 GHWCFG2_FS_PHY_TYPE_SHIFT;
1323 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
1324 GHWCFG2_NUM_DEV_EP_SHIFT;
1325 hw->nperio_tx_q_depth =
1326 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
1327 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
1328 hw->host_perio_tx_q_depth =
1329 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
1330 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
1331 hw->dev_token_q_depth =
1332 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
1333 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
1336 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
1337 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
1338 hw->max_transfer_size = (1 << (width + 11)) - 1;
1339 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
1340 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
1341 hw->max_packet_count = (1 << (width + 4)) - 1;
1342 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
1343 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1344 GHWCFG3_DFIFO_DEPTH_SHIFT;
1347 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1348 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1349 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1350 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1351 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1352 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1353 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1356 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1357 GRXFSIZ_DEPTH_SHIFT;
1359 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1360 dev_dbg(hsotg->dev, " op_mode=%d\n",
1362 dev_dbg(hsotg->dev, " arch=%d\n",
1364 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
1365 hw->dma_desc_enable);
1366 dev_dbg(hsotg->dev, " power_optimized=%d\n",
1367 hw->power_optimized);
1368 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
1370 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
1372 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
1374 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
1375 hw->utmi_phy_data_width);
1376 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
1378 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
1379 hw->num_dev_perio_in_ep);
1380 dev_dbg(hsotg->dev, " host_channels=%d\n",
1382 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
1383 hw->max_transfer_size);
1384 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
1385 hw->max_packet_count);
1386 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
1387 hw->nperio_tx_q_depth);
1388 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
1389 hw->host_perio_tx_q_depth);
1390 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
1391 hw->dev_token_q_depth);
1392 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
1393 hw->enable_dynamic_fifo);
1394 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
1395 hw->en_multiple_tx_fifo);
1396 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
1397 hw->total_fifo_size);
1398 dev_dbg(hsotg->dev, " rx_fifo_size=%d\n",
1400 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
1401 hw->host_nperio_tx_fifo_size);
1402 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
1403 hw->host_perio_tx_fifo_size);
1404 dev_dbg(hsotg->dev, "\n");
1409 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1411 const struct of_device_id *match;
1412 struct dwc2_core_params params;
1414 match = of_match_device(dwc2_of_match_table, hsotg->dev);
1415 if (match && match->data)
1416 params = *((struct dwc2_core_params *)match->data);
1418 params = params_default;
1420 dwc2_set_parameters(hsotg, ¶ms);