1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the core HCD code, and implements the Linux hc_driver
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
71 * @hsotg: Programming view of the DWC_otg controller
73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
80 /* Clear any pending interrupts */
81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
97 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
101 * Initializes the FSLSPClkSel field of the HCFG register depending on the
104 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
110 hsotg->params.ulpi_fs_ls) ||
111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
113 val = HCFG_FSLSPCLKSEL_48_MHZ;
115 /* High speed PHY running at full speed or high speed */
116 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg->regs + HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hcfg, hsotg->regs + HCFG);
126 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
128 u32 usbcfg, ggpio, i2cctl;
132 * core_init() is now called on every switch so only call the
133 * following for the first time through
136 dev_dbg(hsotg->dev, "FS PHY selected\n");
138 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
143 /* Reset after a PHY select */
144 retval = dwc2_core_reset(hsotg, false);
148 "%s: Reset failed, aborting", __func__);
153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg->regs + GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n");
158 * STM32F4x9 uses the GGPIO register as general
159 * core configuration register.
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(ggpio, hsotg->regs + GGPIO);
168 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
169 * do this on HNP Dev/Host mode switches (done in dev_init and
172 if (dwc2_is_host_mode(hsotg))
173 dwc2_init_fs_ls_pclk_sel(hsotg);
175 if (hsotg->params.i2c_enable) {
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
179 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
183 /* Program GI2CCTL.I2CEn */
184 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
196 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
198 u32 usbcfg, usbcfg_old;
204 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
208 * HS PHY parameters. These parameters are preserved during soft reset
209 * so only program the first time. Do a soft reset immediately after
212 switch (hsotg->params.phy_type) {
213 case DWC2_PHY_TYPE_PARAM_ULPI:
215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
218 if (hsotg->params.phy_ulpi_ddr)
219 usbcfg |= GUSBCFG_DDRSEL;
221 /* Set external VBUS indicator as needed. */
222 if (hsotg->params.oc_disable)
223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
224 GUSBCFG_INDICATORPASSTHROUGH);
226 case DWC2_PHY_TYPE_PARAM_UTMI:
227 /* UTMI+ interface */
228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230 if (hsotg->params.phy_utmi_width == 16)
231 usbcfg |= GUSBCFG_PHYIF16;
234 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
241 /* Reset after setting the PHY parameters */
242 retval = dwc2_core_reset(hsotg, false);
245 "%s: Reset failed, aborting", __func__);
253 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
261 /* If FS/LS mode with FS/LS PHY */
262 retval = dwc2_fs_phy_init(hsotg, select_phy);
267 retval = dwc2_hs_phy_init(hsotg, select_phy);
272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
281 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
290 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
292 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH:
296 dev_err(hsotg->dev, "External DMA Mode not supported\n");
299 case GHWCFG2_INT_DMA_ARCH:
300 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
301 if (hsotg->params.ahbcfg != -1) {
302 ahbcfg &= GAHBCFG_CTRL_MASK;
303 ahbcfg |= hsotg->params.ahbcfg &
308 case GHWCFG2_SLAVE_ONLY_ARCH:
310 dev_dbg(hsotg->dev, "Slave Only Mode\n");
314 if (hsotg->params.host_dma)
315 ahbcfg |= GAHBCFG_DMA_EN;
317 hsotg->params.dma_desc_enable = false;
319 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
328 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
331 switch (hsotg->hw_params.op_mode) {
332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
333 if (hsotg->params.otg_cap ==
334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
335 usbcfg |= GUSBCFG_HNPCAP;
336 if (hsotg->params.otg_cap !=
337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_SRPCAP;
341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
344 if (hsotg->params.otg_cap !=
345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
346 usbcfg |= GUSBCFG_SRPCAP;
349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
359 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
361 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
362 if (IS_ERR(hsotg->vbus_supply))
365 return regulator_enable(hsotg->vbus_supply);
368 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
370 if (hsotg->vbus_supply)
371 return regulator_disable(hsotg->vbus_supply);
377 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
379 * @hsotg: Programming view of DWC_otg controller
381 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
385 dev_dbg(hsotg->dev, "%s()\n", __func__);
387 /* Disable all interrupts */
388 dwc2_writel(0, hsotg->regs + GINTMSK);
389 dwc2_writel(0, hsotg->regs + HAINTMSK);
391 /* Enable the common interrupts */
392 dwc2_enable_common_interrupts(hsotg);
394 /* Enable host mode interrupts without disturbing common interrupts */
395 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
396 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
397 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
401 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
403 * @hsotg: Programming view of DWC_otg controller
405 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
407 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
409 /* Disable host mode interrupts without disturbing common interrupts */
410 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
411 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
412 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
416 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
417 * For system that have a total fifo depth that is smaller than the default
420 * @hsotg: Programming view of DWC_otg controller
422 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
424 struct dwc2_core_params *params = &hsotg->params;
425 struct dwc2_hw_params *hw = &hsotg->hw_params;
426 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
428 total_fifo_size = hw->total_fifo_size;
429 rxfsiz = params->host_rx_fifo_size;
430 nptxfsiz = params->host_nperio_tx_fifo_size;
431 ptxfsiz = params->host_perio_tx_fifo_size;
434 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
435 * allocation with support for high bandwidth endpoints. Synopsys
436 * defines MPS(Max Packet size) for a periodic EP=1024, and for
437 * non-periodic as 512.
439 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
441 * For Buffer DMA mode/Scatter Gather DMA mode
442 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
443 * with n = number of host channel.
444 * 2 * ((1024/4) + 2) = 516
446 rxfsiz = 516 + hw->host_channels;
449 * min non-periodic tx fifo depth
450 * 2 * (largest non-periodic USB packet used / 4)
456 * min periodic tx fifo depth
457 * (largest packet size*MC)/4
462 params->host_rx_fifo_size = rxfsiz;
463 params->host_nperio_tx_fifo_size = nptxfsiz;
464 params->host_perio_tx_fifo_size = ptxfsiz;
468 * If the summation of RX, NPTX and PTX fifo sizes is still
469 * bigger than the total_fifo_size, then we have a problem.
471 * We won't be able to allocate as many endpoints. Right now,
472 * we're just printing an error message, but ideally this FIFO
473 * allocation algorithm would be improved in the future.
475 * FIXME improve this FIFO allocation algorithm.
477 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
478 dev_err(hsotg->dev, "invalid fifo sizes\n");
481 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
483 struct dwc2_core_params *params = &hsotg->params;
484 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
486 if (!params->enable_dynamic_fifo)
489 dwc2_calculate_dynamic_fifo(hsotg);
492 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
493 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
494 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
495 grxfsiz |= params->host_rx_fifo_size <<
496 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
497 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
498 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
499 dwc2_readl(hsotg->regs + GRXFSIZ));
501 /* Non-periodic Tx FIFO */
502 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
503 dwc2_readl(hsotg->regs + GNPTXFSIZ));
504 nptxfsiz = params->host_nperio_tx_fifo_size <<
505 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
506 nptxfsiz |= params->host_rx_fifo_size <<
507 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
508 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
509 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
510 dwc2_readl(hsotg->regs + GNPTXFSIZ));
512 /* Periodic Tx FIFO */
513 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
514 dwc2_readl(hsotg->regs + HPTXFSIZ));
515 hptxfsiz = params->host_perio_tx_fifo_size <<
516 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
517 hptxfsiz |= (params->host_rx_fifo_size +
518 params->host_nperio_tx_fifo_size) <<
519 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
520 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
521 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
522 dwc2_readl(hsotg->regs + HPTXFSIZ));
524 if (hsotg->params.en_multiple_tx_fifo &&
525 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
527 * This feature was implemented in 2.91a version
528 * Global DFIFOCFG calculation for Host mode -
529 * include RxFIFO, NPTXFIFO and HPTXFIFO
531 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
532 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
533 dfifocfg |= (params->host_rx_fifo_size +
534 params->host_nperio_tx_fifo_size +
535 params->host_perio_tx_fifo_size) <<
536 GDFIFOCFG_EPINFOBASE_SHIFT &
537 GDFIFOCFG_EPINFOBASE_MASK;
538 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
543 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
544 * the HFIR register according to PHY type and speed
546 * @hsotg: Programming view of DWC_otg controller
548 * NOTE: The caller can modify the value of the HFIR register only after the
549 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
552 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
556 int clock = 60; /* default value */
558 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
559 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
561 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
562 !(usbcfg & GUSBCFG_PHYIF16))
564 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
565 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
567 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
568 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
570 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
571 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
573 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
574 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
576 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
577 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
579 if ((usbcfg & GUSBCFG_PHYSEL) &&
580 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
583 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
584 /* High speed case */
585 return 125 * clock - 1;
588 return 1000 * clock - 1;
592 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
595 * @core_if: Programming view of DWC_otg controller
596 * @dest: Destination buffer for the packet
597 * @bytes: Number of bytes to copy to the destination
599 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
601 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
602 u32 *data_buf = (u32 *)dest;
603 int word_count = (bytes + 3) / 4;
607 * Todo: Account for the case where dest is not dword aligned. This
608 * requires reading data from the FIFO into a u32 temp buffer, then
609 * moving it into the data buffer.
612 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
614 for (i = 0; i < word_count; i++, data_buf++)
615 *data_buf = dwc2_readl(fifo);
619 * dwc2_dump_channel_info() - Prints the state of a host channel
621 * @hsotg: Programming view of DWC_otg controller
622 * @chan: Pointer to the channel to dump
624 * Must be called with interrupt disabled and spinlock held
626 * NOTE: This function will be removed once the peripheral controller code
627 * is integrated and the driver is stable
629 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
630 struct dwc2_host_chan *chan)
633 int num_channels = hsotg->params.host_channels;
644 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
645 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
646 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
647 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
649 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
650 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
652 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
654 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
655 chan->dev_addr, chan->ep_num, chan->ep_is_in);
656 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
657 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
658 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
659 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
660 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
661 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
662 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
663 (unsigned long)chan->xfer_dma);
664 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
665 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
666 dev_dbg(hsotg->dev, " NP inactive sched:\n");
667 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
669 dev_dbg(hsotg->dev, " %p\n", qh);
670 dev_dbg(hsotg->dev, " NP waiting sched:\n");
671 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
673 dev_dbg(hsotg->dev, " %p\n", qh);
674 dev_dbg(hsotg->dev, " NP active sched:\n");
675 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
677 dev_dbg(hsotg->dev, " %p\n", qh);
678 dev_dbg(hsotg->dev, " Channels:\n");
679 for (i = 0; i < num_channels; i++) {
680 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
682 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
684 #endif /* VERBOSE_DEBUG */
687 static int _dwc2_hcd_start(struct usb_hcd *hcd);
689 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
691 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
693 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
694 _dwc2_hcd_start(hcd);
697 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
699 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
701 hcd->self.is_b_host = 0;
704 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
705 int *hub_addr, int *hub_port)
707 struct urb *urb = context;
710 *hub_addr = urb->dev->tt->hub->devnum;
713 *hub_port = urb->dev->ttport;
717 * =========================================================================
718 * Low Level Host Channel Access Functions
719 * =========================================================================
722 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
723 struct dwc2_host_chan *chan)
725 u32 hcintmsk = HCINTMSK_CHHLTD;
727 switch (chan->ep_type) {
728 case USB_ENDPOINT_XFER_CONTROL:
729 case USB_ENDPOINT_XFER_BULK:
730 dev_vdbg(hsotg->dev, "control/bulk\n");
731 hcintmsk |= HCINTMSK_XFERCOMPL;
732 hcintmsk |= HCINTMSK_STALL;
733 hcintmsk |= HCINTMSK_XACTERR;
734 hcintmsk |= HCINTMSK_DATATGLERR;
735 if (chan->ep_is_in) {
736 hcintmsk |= HCINTMSK_BBLERR;
738 hcintmsk |= HCINTMSK_NAK;
739 hcintmsk |= HCINTMSK_NYET;
741 hcintmsk |= HCINTMSK_ACK;
744 if (chan->do_split) {
745 hcintmsk |= HCINTMSK_NAK;
746 if (chan->complete_split)
747 hcintmsk |= HCINTMSK_NYET;
749 hcintmsk |= HCINTMSK_ACK;
752 if (chan->error_state)
753 hcintmsk |= HCINTMSK_ACK;
756 case USB_ENDPOINT_XFER_INT:
758 dev_vdbg(hsotg->dev, "intr\n");
759 hcintmsk |= HCINTMSK_XFERCOMPL;
760 hcintmsk |= HCINTMSK_NAK;
761 hcintmsk |= HCINTMSK_STALL;
762 hcintmsk |= HCINTMSK_XACTERR;
763 hcintmsk |= HCINTMSK_DATATGLERR;
764 hcintmsk |= HCINTMSK_FRMOVRUN;
767 hcintmsk |= HCINTMSK_BBLERR;
768 if (chan->error_state)
769 hcintmsk |= HCINTMSK_ACK;
770 if (chan->do_split) {
771 if (chan->complete_split)
772 hcintmsk |= HCINTMSK_NYET;
774 hcintmsk |= HCINTMSK_ACK;
778 case USB_ENDPOINT_XFER_ISOC:
780 dev_vdbg(hsotg->dev, "isoc\n");
781 hcintmsk |= HCINTMSK_XFERCOMPL;
782 hcintmsk |= HCINTMSK_FRMOVRUN;
783 hcintmsk |= HCINTMSK_ACK;
785 if (chan->ep_is_in) {
786 hcintmsk |= HCINTMSK_XACTERR;
787 hcintmsk |= HCINTMSK_BBLERR;
791 dev_err(hsotg->dev, "## Unknown EP type ##\n");
795 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
797 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
800 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
801 struct dwc2_host_chan *chan)
803 u32 hcintmsk = HCINTMSK_CHHLTD;
806 * For Descriptor DMA mode core halts the channel on AHB error.
807 * Interrupt is not required.
809 if (!hsotg->params.dma_desc_enable) {
811 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
812 hcintmsk |= HCINTMSK_AHBERR;
815 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
816 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
817 hcintmsk |= HCINTMSK_XFERCOMPL;
820 if (chan->error_state && !chan->do_split &&
821 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
823 dev_vdbg(hsotg->dev, "setting ACK\n");
824 hcintmsk |= HCINTMSK_ACK;
825 if (chan->ep_is_in) {
826 hcintmsk |= HCINTMSK_DATATGLERR;
827 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
828 hcintmsk |= HCINTMSK_NAK;
832 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
834 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
837 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
838 struct dwc2_host_chan *chan)
842 if (hsotg->params.host_dma) {
844 dev_vdbg(hsotg->dev, "DMA enabled\n");
845 dwc2_hc_enable_dma_ints(hsotg, chan);
848 dev_vdbg(hsotg->dev, "DMA disabled\n");
849 dwc2_hc_enable_slave_ints(hsotg, chan);
852 /* Enable the top level host channel interrupt */
853 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
854 intmsk |= 1 << chan->hc_num;
855 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
857 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
859 /* Make sure host channel interrupts are enabled */
860 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
861 intmsk |= GINTSTS_HCHINT;
862 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
864 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
868 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
869 * a specific endpoint
871 * @hsotg: Programming view of DWC_otg controller
872 * @chan: Information needed to initialize the host channel
874 * The HCCHARn register is set up with the characteristics specified in chan.
875 * Host channel interrupts that may need to be serviced while this transfer is
876 * in progress are enabled.
878 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
880 u8 hc_num = chan->hc_num;
886 dev_vdbg(hsotg->dev, "%s()\n", __func__);
888 /* Clear old interrupt conditions for this host channel */
889 hcintmsk = 0xffffffff;
890 hcintmsk &= ~HCINTMSK_RESERVED14_31;
891 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
893 /* Enable channel interrupts required for this transfer */
894 dwc2_hc_enable_ints(hsotg, chan);
897 * Program the HCCHARn register with the endpoint characteristics for
898 * the current transfer
900 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
901 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
903 hcchar |= HCCHAR_EPDIR;
904 if (chan->speed == USB_SPEED_LOW)
905 hcchar |= HCCHAR_LSPDDEV;
906 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
907 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
908 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
910 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
913 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
915 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
917 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
919 dev_vdbg(hsotg->dev, " Is In: %d\n",
921 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
922 chan->speed == USB_SPEED_LOW);
923 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
925 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
929 /* Program the HCSPLT register for SPLITs */
930 if (chan->do_split) {
933 "Programming HC %d with split --> %s\n",
935 chan->complete_split ? "CSPLIT" : "SSPLIT");
936 if (chan->complete_split)
937 hcsplt |= HCSPLT_COMPSPLT;
938 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
940 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
942 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
945 dev_vdbg(hsotg->dev, " comp split %d\n",
946 chan->complete_split);
947 dev_vdbg(hsotg->dev, " xact pos %d\n",
949 dev_vdbg(hsotg->dev, " hub addr %d\n",
951 dev_vdbg(hsotg->dev, " hub port %d\n",
953 dev_vdbg(hsotg->dev, " is_in %d\n",
955 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
957 dev_vdbg(hsotg->dev, " xferlen %d\n",
962 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
966 * dwc2_hc_halt() - Attempts to halt a host channel
968 * @hsotg: Controller register interface
969 * @chan: Host channel to halt
970 * @halt_status: Reason for halting the channel
972 * This function should only be called in Slave mode or to abort a transfer in
973 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
974 * controller halts the channel when the transfer is complete or a condition
975 * occurs that requires application intervention.
977 * In slave mode, checks for a free request queue entry, then sets the Channel
978 * Enable and Channel Disable bits of the Host Channel Characteristics
979 * register of the specified channel to intiate the halt. If there is no free
980 * request queue entry, sets only the Channel Disable bit of the HCCHARn
981 * register to flush requests for this channel. In the latter case, sets a
982 * flag to indicate that the host channel needs to be halted when a request
983 * queue slot is open.
985 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
986 * HCCHARn register. The controller ensures there is space in the request
987 * queue before submitting the halt request.
989 * Some time may elapse before the core flushes any posted requests for this
990 * host channel and halts. The Channel Halted interrupt handler completes the
991 * deactivation of the host channel.
993 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
994 enum dwc2_halt_status halt_status)
996 u32 nptxsts, hptxsts, hcchar;
999 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1002 * In buffer DMA or external DMA mode channel can't be halted
1003 * for non-split periodic channels. At the end of the next
1004 * uframe/frame (in the worst case), the core generates a channel
1005 * halted and disables the channel automatically.
1007 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
1008 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
1009 if (!chan->do_split &&
1010 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
1011 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
1012 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1018 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1019 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1021 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1022 halt_status == DWC2_HC_XFER_AHB_ERR) {
1024 * Disable all channel interrupts except Ch Halted. The QTD
1025 * and QH state associated with this transfer has been cleared
1026 * (in the case of URB_DEQUEUE), so the channel needs to be
1027 * shut down carefully to prevent crashes.
1029 u32 hcintmsk = HCINTMSK_CHHLTD;
1031 dev_vdbg(hsotg->dev, "dequeue/error\n");
1032 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1035 * Make sure no other interrupts besides halt are currently
1036 * pending. Handling another interrupt could cause a crash due
1037 * to the QTD and QH state.
1039 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1042 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1043 * even if the channel was already halted for some other
1046 chan->halt_status = halt_status;
1048 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1049 if (!(hcchar & HCCHAR_CHENA)) {
1051 * The channel is either already halted or it hasn't
1052 * started yet. In DMA mode, the transfer may halt if
1053 * it finishes normally or a condition occurs that
1054 * requires driver intervention. Don't want to halt
1055 * the channel again. In either Slave or DMA mode,
1056 * it's possible that the transfer has been assigned
1057 * to a channel, but not started yet when an URB is
1058 * dequeued. Don't want to halt a channel that hasn't
1064 if (chan->halt_pending) {
1066 * A halt has already been issued for this channel. This might
1067 * happen when a transfer is aborted by a higher level in
1070 dev_vdbg(hsotg->dev,
1071 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1072 __func__, chan->hc_num);
1076 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1078 /* No need to set the bit in DDMA for disabling the channel */
1079 /* TODO check it everywhere channel is disabled */
1080 if (!hsotg->params.dma_desc_enable) {
1082 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1083 hcchar |= HCCHAR_CHENA;
1086 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1088 hcchar |= HCCHAR_CHDIS;
1090 if (!hsotg->params.host_dma) {
1092 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1093 hcchar |= HCCHAR_CHENA;
1095 /* Check for space in the request queue to issue the halt */
1096 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1097 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1098 dev_vdbg(hsotg->dev, "control/bulk\n");
1099 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1100 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1101 dev_vdbg(hsotg->dev, "Disabling channel\n");
1102 hcchar &= ~HCCHAR_CHENA;
1106 dev_vdbg(hsotg->dev, "isoc/intr\n");
1107 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1108 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1109 hsotg->queuing_high_bandwidth) {
1111 dev_vdbg(hsotg->dev, "Disabling channel\n");
1112 hcchar &= ~HCCHAR_CHENA;
1117 dev_vdbg(hsotg->dev, "DMA enabled\n");
1120 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1121 chan->halt_status = halt_status;
1123 if (hcchar & HCCHAR_CHENA) {
1125 dev_vdbg(hsotg->dev, "Channel enabled\n");
1126 chan->halt_pending = 1;
1127 chan->halt_on_queue = 0;
1130 dev_vdbg(hsotg->dev, "Channel disabled\n");
1131 chan->halt_on_queue = 1;
1135 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1137 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1139 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1140 chan->halt_pending);
1141 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1142 chan->halt_on_queue);
1143 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1149 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1151 * @hsotg: Programming view of DWC_otg controller
1152 * @chan: Identifies the host channel to clean up
1154 * This function is normally called after a transfer is done and the host
1155 * channel is being released
1157 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1161 chan->xfer_started = 0;
1163 list_del_init(&chan->split_order_list_entry);
1166 * Clear channel interrupt enables and any unhandled channel interrupt
1169 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1170 hcintmsk = 0xffffffff;
1171 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1172 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1176 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1177 * which frame a periodic transfer should occur
1179 * @hsotg: Programming view of DWC_otg controller
1180 * @chan: Identifies the host channel to set up and its properties
1181 * @hcchar: Current value of the HCCHAR register for the specified host channel
1183 * This function has no effect on non-periodic transfers
1185 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1186 struct dwc2_host_chan *chan, u32 *hcchar)
1188 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1189 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1199 * Try to figure out if we're an even or odd frame. If we set
1200 * even and the current frame number is even the the transfer
1201 * will happen immediately. Similar if both are odd. If one is
1202 * even and the other is odd then the transfer will happen when
1203 * the frame number ticks.
1205 * There's a bit of a balancing act to get this right.
1206 * Sometimes we may want to send data in the current frame (AK
1207 * right away). We might want to do this if the frame number
1208 * _just_ ticked, but we might also want to do this in order
1209 * to continue a split transaction that happened late in a
1210 * microframe (so we didn't know to queue the next transfer
1211 * until the frame number had ticked). The problem is that we
1212 * need a lot of knowledge to know if there's actually still
1213 * time to send things or if it would be better to wait until
1216 * We can look at how much time is left in the current frame
1217 * and make a guess about whether we'll have time to transfer.
1221 /* Get speed host is running at */
1222 host_speed = (chan->speed != USB_SPEED_HIGH &&
1223 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1225 /* See how many bytes are in the periodic FIFO right now */
1226 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1227 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1228 bytes_in_fifo = sizeof(u32) *
1229 (hsotg->params.host_perio_tx_fifo_size -
1233 * Roughly estimate bus time for everything in the periodic
1234 * queue + our new transfer. This is "rough" because we're
1235 * using a function that makes takes into account IN/OUT
1236 * and INT/ISO and we're just slamming in one value for all
1237 * transfers. This should be an over-estimate and that should
1238 * be OK, but we can probably tighten it.
1240 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1241 chan->xfer_len + bytes_in_fifo);
1242 xfer_us = NS_TO_US(xfer_ns);
1244 /* See what frame number we'll be at by the time we finish */
1245 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1247 /* This is when we were scheduled to be on the wire */
1248 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1251 * If we'd finish _after_ the frame we're scheduled in then
1252 * it's hopeless. Just schedule right away and hope for the
1253 * best. Note that it _might_ be wise to call back into the
1254 * scheduler to pick a better frame, but this is better than
1257 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1258 dwc2_sch_vdbg(hsotg,
1259 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1260 chan->qh, wire_frame, frame_number,
1261 dwc2_frame_num_dec(frame_number,
1263 wire_frame = frame_number;
1266 * We picked a different frame number; communicate this
1267 * back to the scheduler so it doesn't try to schedule
1268 * another in the same frame.
1270 * Remember that next_active_frame is 1 before the wire
1273 chan->qh->next_active_frame =
1274 dwc2_frame_num_dec(frame_number, 1);
1278 *hcchar |= HCCHAR_ODDFRM;
1280 *hcchar &= ~HCCHAR_ODDFRM;
1284 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1286 /* Set up the initial PID for the transfer */
1287 if (chan->speed == USB_SPEED_HIGH) {
1288 if (chan->ep_is_in) {
1289 if (chan->multi_count == 1)
1290 chan->data_pid_start = DWC2_HC_PID_DATA0;
1291 else if (chan->multi_count == 2)
1292 chan->data_pid_start = DWC2_HC_PID_DATA1;
1294 chan->data_pid_start = DWC2_HC_PID_DATA2;
1296 if (chan->multi_count == 1)
1297 chan->data_pid_start = DWC2_HC_PID_DATA0;
1299 chan->data_pid_start = DWC2_HC_PID_MDATA;
1302 chan->data_pid_start = DWC2_HC_PID_DATA0;
1307 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1310 * @hsotg: Programming view of DWC_otg controller
1311 * @chan: Information needed to initialize the host channel
1313 * This function should only be called in Slave mode. For a channel associated
1314 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1315 * associated with a periodic EP, the periodic Tx FIFO is written.
1317 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1318 * the number of bytes written to the Tx FIFO.
1320 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1321 struct dwc2_host_chan *chan)
1324 u32 remaining_count;
1327 u32 __iomem *data_fifo;
1328 u32 *data_buf = (u32 *)chan->xfer_buf;
1331 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1333 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1335 remaining_count = chan->xfer_len - chan->xfer_count;
1336 if (remaining_count > chan->max_packet)
1337 byte_count = chan->max_packet;
1339 byte_count = remaining_count;
1341 dword_count = (byte_count + 3) / 4;
1343 if (((unsigned long)data_buf & 0x3) == 0) {
1344 /* xfer_buf is DWORD aligned */
1345 for (i = 0; i < dword_count; i++, data_buf++)
1346 dwc2_writel(*data_buf, data_fifo);
1348 /* xfer_buf is not DWORD aligned */
1349 for (i = 0; i < dword_count; i++, data_buf++) {
1350 u32 data = data_buf[0] | data_buf[1] << 8 |
1351 data_buf[2] << 16 | data_buf[3] << 24;
1352 dwc2_writel(data, data_fifo);
1356 chan->xfer_count += byte_count;
1357 chan->xfer_buf += byte_count;
1361 * dwc2_hc_do_ping() - Starts a PING transfer
1363 * @hsotg: Programming view of DWC_otg controller
1364 * @chan: Information needed to initialize the host channel
1366 * This function should only be called in Slave mode. The Do Ping bit is set in
1367 * the HCTSIZ register, then the channel is enabled.
1369 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1370 struct dwc2_host_chan *chan)
1376 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1379 hctsiz = TSIZ_DOPNG;
1380 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1381 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1383 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1384 hcchar |= HCCHAR_CHENA;
1385 hcchar &= ~HCCHAR_CHDIS;
1386 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1390 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1391 * channel and starts the transfer
1393 * @hsotg: Programming view of DWC_otg controller
1394 * @chan: Information needed to initialize the host channel. The xfer_len value
1395 * may be reduced to accommodate the max widths of the XferSize and
1396 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1397 * changed to reflect the final xfer_len value.
1399 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1400 * the caller must ensure that there is sufficient space in the request queue
1403 * For an OUT transfer in Slave mode, it loads a data packet into the
1404 * appropriate FIFO. If necessary, additional data packets are loaded in the
1407 * For an IN transfer in Slave mode, a data packet is requested. The data
1408 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1409 * additional data packets are requested in the Host ISR.
1411 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1412 * register along with a packet count of 1 and the channel is enabled. This
1413 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1414 * simply set to 0 since no data transfer occurs in this case.
1416 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1417 * all the information required to perform the subsequent data transfer. In
1418 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1419 * controller performs the entire PING protocol, then starts the data
1422 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1423 struct dwc2_host_chan *chan)
1425 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1426 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1433 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1435 if (chan->do_ping) {
1436 if (!hsotg->params.host_dma) {
1438 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1439 dwc2_hc_do_ping(hsotg, chan);
1440 chan->xfer_started = 1;
1445 dev_vdbg(hsotg->dev, "ping, DMA\n");
1447 hctsiz |= TSIZ_DOPNG;
1450 if (chan->do_split) {
1452 dev_vdbg(hsotg->dev, "split\n");
1455 if (chan->complete_split && !chan->ep_is_in)
1457 * For CSPLIT OUT Transfer, set the size to 0 so the
1458 * core doesn't expect any data written to the FIFO
1461 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1462 chan->xfer_len = chan->max_packet;
1463 else if (!chan->ep_is_in && chan->xfer_len > 188)
1464 chan->xfer_len = 188;
1466 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1469 /* For split set ec_mc for immediate retries */
1470 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1471 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1477 dev_vdbg(hsotg->dev, "no split\n");
1479 * Ensure that the transfer length and packet count will fit
1480 * in the widths allocated for them in the HCTSIZn register
1482 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1483 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1485 * Make sure the transfer size is no larger than one
1486 * (micro)frame's worth of data. (A check was done
1487 * when the periodic transfer was accepted to ensure
1488 * that a (micro)frame's worth of data can be
1489 * programmed into a channel.)
1491 u32 max_periodic_len =
1492 chan->multi_count * chan->max_packet;
1494 if (chan->xfer_len > max_periodic_len)
1495 chan->xfer_len = max_periodic_len;
1496 } else if (chan->xfer_len > max_hc_xfer_size) {
1498 * Make sure that xfer_len is a multiple of max packet
1502 max_hc_xfer_size - chan->max_packet + 1;
1505 if (chan->xfer_len > 0) {
1506 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1508 if (num_packets > max_hc_pkt_count) {
1509 num_packets = max_hc_pkt_count;
1510 chan->xfer_len = num_packets * chan->max_packet;
1513 /* Need 1 packet for transfer length of 0 */
1519 * Always program an integral # of max packets for IN
1522 chan->xfer_len = num_packets * chan->max_packet;
1524 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1525 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1527 * Make sure that the multi_count field matches the
1528 * actual transfer length
1530 chan->multi_count = num_packets;
1532 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1533 dwc2_set_pid_isoc(chan);
1535 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1538 /* The ec_mc gets the multi_count for non-split */
1539 ec_mc = chan->multi_count;
1542 chan->start_pkt_count = num_packets;
1543 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1544 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1545 TSIZ_SC_MC_PID_MASK;
1546 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1548 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1549 hctsiz, chan->hc_num);
1551 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1553 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1554 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1555 TSIZ_XFERSIZE_SHIFT);
1556 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1557 (hctsiz & TSIZ_PKTCNT_MASK) >>
1559 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1560 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1561 TSIZ_SC_MC_PID_SHIFT);
1564 if (hsotg->params.host_dma) {
1565 dwc2_writel((u32)chan->xfer_dma,
1566 hsotg->regs + HCDMA(chan->hc_num));
1568 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1569 (unsigned long)chan->xfer_dma, chan->hc_num);
1572 /* Start the split */
1573 if (chan->do_split) {
1574 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1576 hcsplt |= HCSPLT_SPLTENA;
1577 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1580 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1581 hcchar &= ~HCCHAR_MULTICNT_MASK;
1582 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1583 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1585 if (hcchar & HCCHAR_CHDIS)
1586 dev_warn(hsotg->dev,
1587 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1588 __func__, chan->hc_num, hcchar);
1590 /* Set host channel enable after all other setup is complete */
1591 hcchar |= HCCHAR_CHENA;
1592 hcchar &= ~HCCHAR_CHDIS;
1595 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1596 (hcchar & HCCHAR_MULTICNT_MASK) >>
1597 HCCHAR_MULTICNT_SHIFT);
1599 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1601 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1604 chan->xfer_started = 1;
1607 if (!hsotg->params.host_dma &&
1608 !chan->ep_is_in && chan->xfer_len > 0)
1609 /* Load OUT packet into the appropriate Tx FIFO */
1610 dwc2_hc_write_packet(hsotg, chan);
1614 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1615 * host channel and starts the transfer in Descriptor DMA mode
1617 * @hsotg: Programming view of DWC_otg controller
1618 * @chan: Information needed to initialize the host channel
1620 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1621 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1622 * with micro-frame bitmap.
1624 * Initializes HCDMA register with descriptor list address and CTD value then
1625 * starts the transfer via enabling the channel.
1627 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1628 struct dwc2_host_chan *chan)
1634 hctsiz |= TSIZ_DOPNG;
1636 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1637 dwc2_set_pid_isoc(chan);
1639 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1640 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1641 TSIZ_SC_MC_PID_MASK;
1643 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1644 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1646 /* Non-zero only for high-speed interrupt endpoints */
1647 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1650 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1652 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1653 chan->data_pid_start);
1654 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1657 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1659 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1660 chan->desc_list_sz, DMA_TO_DEVICE);
1662 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1665 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1666 &chan->desc_list_addr, chan->hc_num);
1668 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1669 hcchar &= ~HCCHAR_MULTICNT_MASK;
1670 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1671 HCCHAR_MULTICNT_MASK;
1673 if (hcchar & HCCHAR_CHDIS)
1674 dev_warn(hsotg->dev,
1675 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1676 __func__, chan->hc_num, hcchar);
1678 /* Set host channel enable after all other setup is complete */
1679 hcchar |= HCCHAR_CHENA;
1680 hcchar &= ~HCCHAR_CHDIS;
1683 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1684 (hcchar & HCCHAR_MULTICNT_MASK) >>
1685 HCCHAR_MULTICNT_SHIFT);
1687 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1689 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1692 chan->xfer_started = 1;
1697 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1698 * a previous call to dwc2_hc_start_transfer()
1700 * @hsotg: Programming view of DWC_otg controller
1701 * @chan: Information needed to initialize the host channel
1703 * The caller must ensure there is sufficient space in the request queue and Tx
1704 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1705 * the controller acts autonomously to complete transfers programmed to a host
1708 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1709 * if there is any data remaining to be queued. For an IN transfer, another
1710 * data packet is always requested. For the SETUP phase of a control transfer,
1711 * this function does nothing.
1713 * Return: 1 if a new request is queued, 0 if no more requests are required
1716 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1717 struct dwc2_host_chan *chan)
1720 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1724 /* SPLITs always queue just once per channel */
1727 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1728 /* SETUPs are queued only once since they can't be NAK'd */
1731 if (chan->ep_is_in) {
1733 * Always queue another request for other IN transfers. If
1734 * back-to-back INs are issued and NAKs are received for both,
1735 * the driver may still be processing the first NAK when the
1736 * second NAK is received. When the interrupt handler clears
1737 * the NAK interrupt for the first NAK, the second NAK will
1738 * not be seen. So we can't depend on the NAK interrupt
1739 * handler to requeue a NAK'd request. Instead, IN requests
1740 * are issued each time this function is called. When the
1741 * transfer completes, the extra requests for the channel will
1744 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1746 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1747 hcchar |= HCCHAR_CHENA;
1748 hcchar &= ~HCCHAR_CHDIS;
1750 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1752 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1759 if (chan->xfer_count < chan->xfer_len) {
1760 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1761 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1762 u32 hcchar = dwc2_readl(hsotg->regs +
1763 HCCHAR(chan->hc_num));
1765 dwc2_hc_set_even_odd_frame(hsotg, chan,
1769 /* Load OUT packet into the appropriate Tx FIFO */
1770 dwc2_hc_write_packet(hsotg, chan);
1779 * =========================================================================
1781 * =========================================================================
1785 * Processes all the URBs in a single list of QHs. Completes them with
1786 * -ETIMEDOUT and frees the QTD.
1788 * Must be called with interrupt disabled and spinlock held
1790 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1791 struct list_head *qh_list)
1793 struct dwc2_qh *qh, *qh_tmp;
1794 struct dwc2_qtd *qtd, *qtd_tmp;
1796 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1797 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1799 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1800 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1805 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1806 struct list_head *qh_list)
1808 struct dwc2_qtd *qtd, *qtd_tmp;
1809 struct dwc2_qh *qh, *qh_tmp;
1810 unsigned long flags;
1813 /* The list hasn't been initialized yet */
1816 spin_lock_irqsave(&hsotg->lock, flags);
1818 /* Ensure there are no QTDs or URBs left */
1819 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1821 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1822 dwc2_hcd_qh_unlink(hsotg, qh);
1824 /* Free each QTD in the QH's QTD list */
1825 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1827 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1829 if (qh->channel && qh->channel->qh == qh)
1830 qh->channel->qh = NULL;
1832 spin_unlock_irqrestore(&hsotg->lock, flags);
1833 dwc2_hcd_qh_free(hsotg, qh);
1834 spin_lock_irqsave(&hsotg->lock, flags);
1837 spin_unlock_irqrestore(&hsotg->lock, flags);
1841 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1842 * and periodic schedules. The QTD associated with each URB is removed from
1843 * the schedule and freed. This function may be called when a disconnect is
1844 * detected or when the HCD is being stopped.
1846 * Must be called with interrupt disabled and spinlock held
1848 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1850 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1851 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1852 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1853 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1854 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1855 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1856 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1860 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1862 * @hsotg: Pointer to struct dwc2_hsotg
1864 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1868 if (hsotg->op_state == OTG_STATE_B_HOST) {
1870 * Reset the port. During a HNP mode switch the reset
1871 * needs to occur within 1ms and have a duration of at
1874 hprt0 = dwc2_read_hprt0(hsotg);
1876 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1879 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1880 msecs_to_jiffies(50));
1883 /* Must be called with interrupt disabled and spinlock held */
1884 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1886 int num_channels = hsotg->params.host_channels;
1887 struct dwc2_host_chan *channel;
1891 if (!hsotg->params.host_dma) {
1892 /* Flush out any channel requests in slave mode */
1893 for (i = 0; i < num_channels; i++) {
1894 channel = hsotg->hc_ptr_array[i];
1895 if (!list_empty(&channel->hc_list_entry))
1897 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1898 if (hcchar & HCCHAR_CHENA) {
1899 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1900 hcchar |= HCCHAR_CHDIS;
1901 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1906 for (i = 0; i < num_channels; i++) {
1907 channel = hsotg->hc_ptr_array[i];
1908 if (!list_empty(&channel->hc_list_entry))
1910 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1911 if (hcchar & HCCHAR_CHENA) {
1912 /* Halt the channel */
1913 hcchar |= HCCHAR_CHDIS;
1914 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1917 dwc2_hc_cleanup(hsotg, channel);
1918 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1920 * Added for Descriptor DMA to prevent channel double cleanup in
1921 * release_channel_ddma(), which is called from ep_disable when
1922 * device disconnects
1926 /* All channels have been freed, mark them available */
1927 if (hsotg->params.uframe_sched) {
1928 hsotg->available_host_channels =
1929 hsotg->params.host_channels;
1931 hsotg->non_periodic_channels = 0;
1932 hsotg->periodic_channels = 0;
1937 * dwc2_hcd_connect() - Handles connect of the HCD
1939 * @hsotg: Pointer to struct dwc2_hsotg
1941 * Must be called with interrupt disabled and spinlock held
1943 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1945 if (hsotg->lx_state != DWC2_L0)
1946 usb_hcd_resume_root_hub(hsotg->priv);
1948 hsotg->flags.b.port_connect_status_change = 1;
1949 hsotg->flags.b.port_connect_status = 1;
1953 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1955 * @hsotg: Pointer to struct dwc2_hsotg
1956 * @force: If true, we won't try to reconnect even if we see device connected.
1958 * Must be called with interrupt disabled and spinlock held
1960 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1965 /* Set status flags for the hub driver */
1966 hsotg->flags.b.port_connect_status_change = 1;
1967 hsotg->flags.b.port_connect_status = 0;
1970 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1971 * interrupt mask and status bits and disabling subsequent host
1972 * channel interrupts.
1974 intr = dwc2_readl(hsotg->regs + GINTMSK);
1975 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1976 dwc2_writel(intr, hsotg->regs + GINTMSK);
1977 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1978 dwc2_writel(intr, hsotg->regs + GINTSTS);
1981 * Turn off the vbus power only if the core has transitioned to device
1982 * mode. If still in host mode, need to keep power on to detect a
1985 if (dwc2_is_device_mode(hsotg)) {
1986 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1987 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1988 dwc2_writel(0, hsotg->regs + HPRT0);
1991 dwc2_disable_host_interrupts(hsotg);
1994 /* Respond with an error status to all URBs in the schedule */
1995 dwc2_kill_all_urbs(hsotg);
1997 if (dwc2_is_host_mode(hsotg))
1998 /* Clean up any host channels that were in use */
1999 dwc2_hcd_cleanup_channels(hsotg);
2001 dwc2_host_disconnect(hsotg);
2004 * Add an extra check here to see if we're actually connected but
2005 * we don't have a detection interrupt pending. This can happen if:
2006 * 1. hardware sees connect
2007 * 2. hardware sees disconnect
2008 * 3. hardware sees connect
2009 * 4. dwc2_port_intr() - clears connect interrupt
2010 * 5. dwc2_handle_common_intr() - calls here
2012 * Without the extra check here we will end calling disconnect
2013 * and won't get any future interrupts to handle the connect.
2016 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2017 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2018 dwc2_hcd_connect(hsotg);
2023 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2025 * @hsotg: Pointer to struct dwc2_hsotg
2027 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2029 if (hsotg->bus_suspended) {
2030 hsotg->flags.b.port_suspend_change = 1;
2031 usb_hcd_resume_root_hub(hsotg->priv);
2034 if (hsotg->lx_state == DWC2_L1)
2035 hsotg->flags.b.port_l1_change = 1;
2039 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2041 * @hsotg: Pointer to struct dwc2_hsotg
2043 * Must be called with interrupt disabled and spinlock held
2045 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2047 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2050 * The root hub should be disconnected before this function is called.
2051 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2052 * and the QH lists (via ..._hcd_endpoint_disable).
2055 /* Turn off all host-specific interrupts */
2056 dwc2_disable_host_interrupts(hsotg);
2058 /* Turn off the vbus power */
2059 dev_dbg(hsotg->dev, "PortPower off\n");
2060 dwc2_writel(0, hsotg->regs + HPRT0);
2063 /* Caller must hold driver lock */
2064 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2065 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2066 struct dwc2_qtd *qtd)
2072 if (!hsotg->flags.b.port_connect_status) {
2073 /* No longer connected */
2074 dev_err(hsotg->dev, "Not connected\n");
2078 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2080 /* Some configurations cannot support LS traffic on a FS root port */
2081 if ((dev_speed == USB_SPEED_LOW) &&
2082 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2083 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2084 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2085 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2087 if (prtspd == HPRT0_SPD_FULL_SPEED)
2094 dwc2_hcd_qtd_init(qtd, urb);
2095 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2098 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2103 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2104 if (!(intr_mask & GINTSTS_SOF)) {
2105 enum dwc2_transaction_type tr_type;
2107 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2108 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2110 * Do not schedule SG transactions until qtd has
2111 * URB_GIVEBACK_ASAP set
2115 tr_type = dwc2_hcd_select_transactions(hsotg);
2116 if (tr_type != DWC2_TRANSACTION_NONE)
2117 dwc2_hcd_queue_transactions(hsotg, tr_type);
2123 /* Must be called with interrupt disabled and spinlock held */
2124 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2125 struct dwc2_hcd_urb *urb)
2128 struct dwc2_qtd *urb_qtd;
2132 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2138 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2144 if (urb_qtd->in_process && qh->channel) {
2145 dwc2_dump_channel_info(hsotg, qh->channel);
2147 /* The QTD is in process (it has been assigned to a channel) */
2148 if (hsotg->flags.b.port_connect_status)
2150 * If still connected (i.e. in host mode), halt the
2151 * channel so it can be used for other transfers. If
2152 * no longer connected, the host registers can't be
2153 * written to halt the channel since the core is in
2156 dwc2_hc_halt(hsotg, qh->channel,
2157 DWC2_HC_XFER_URB_DEQUEUE);
2161 * Free the QTD and clean up the associated QH. Leave the QH in the
2162 * schedule if it has any remaining QTDs.
2164 if (!hsotg->params.dma_desc_enable) {
2165 u8 in_process = urb_qtd->in_process;
2167 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2169 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2171 } else if (list_empty(&qh->qtd_list)) {
2172 dwc2_hcd_qh_unlink(hsotg, qh);
2175 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2181 /* Must NOT be called with interrupt disabled or spinlock held */
2182 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2183 struct usb_host_endpoint *ep, int retry)
2185 struct dwc2_qtd *qtd, *qtd_tmp;
2187 unsigned long flags;
2190 spin_lock_irqsave(&hsotg->lock, flags);
2198 while (!list_empty(&qh->qtd_list) && retry--) {
2201 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2206 spin_unlock_irqrestore(&hsotg->lock, flags);
2208 spin_lock_irqsave(&hsotg->lock, flags);
2216 dwc2_hcd_qh_unlink(hsotg, qh);
2218 /* Free each QTD in the QH's QTD list */
2219 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2220 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2224 if (qh->channel && qh->channel->qh == qh)
2225 qh->channel->qh = NULL;
2227 spin_unlock_irqrestore(&hsotg->lock, flags);
2229 dwc2_hcd_qh_free(hsotg, qh);
2235 spin_unlock_irqrestore(&hsotg->lock, flags);
2240 /* Must be called with interrupt disabled and spinlock held */
2241 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2242 struct usb_host_endpoint *ep)
2244 struct dwc2_qh *qh = ep->hcpriv;
2249 qh->data_toggle = DWC2_HC_PID_DATA0;
2255 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2256 * prepares the core for device mode or host mode operation
2258 * @hsotg: Programming view of the DWC_otg controller
2259 * @initial_setup: If true then this is the first init for this instance.
2261 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2266 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2268 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2270 /* Set ULPI External VBUS bit if needed */
2271 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2272 if (hsotg->params.phy_ulpi_ext_vbus)
2273 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2275 /* Set external TS Dline pulsing bit if needed */
2276 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2277 if (hsotg->params.ts_dline)
2278 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2280 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2283 * Reset the Controller
2285 * We only need to reset the controller if this is a re-init.
2286 * For the first init we know for sure that earlier code reset us (it
2287 * needed to in order to properly detect various parameters).
2289 if (!initial_setup) {
2290 retval = dwc2_core_reset(hsotg, false);
2292 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2299 * This needs to happen in FS mode before any other programming occurs
2301 retval = dwc2_phy_init(hsotg, initial_setup);
2305 /* Program the GAHBCFG Register */
2306 retval = dwc2_gahbcfg_init(hsotg);
2310 /* Program the GUSBCFG register */
2311 dwc2_gusbcfg_init(hsotg);
2313 /* Program the GOTGCTL register */
2314 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2315 otgctl &= ~GOTGCTL_OTGVER;
2316 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2318 /* Clear the SRP success bit for FS-I2c */
2319 hsotg->srp_success = 0;
2321 /* Enable common interrupts */
2322 dwc2_enable_common_interrupts(hsotg);
2325 * Do device or host initialization based on mode during PCD and
2326 * HCD initialization
2328 if (dwc2_is_host_mode(hsotg)) {
2329 dev_dbg(hsotg->dev, "Host Mode\n");
2330 hsotg->op_state = OTG_STATE_A_HOST;
2332 dev_dbg(hsotg->dev, "Device Mode\n");
2333 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2340 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2343 * @hsotg: Programming view of DWC_otg controller
2345 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2346 * request queues. Host channels are reset to ensure that they are ready for
2347 * performing transfers.
2349 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2351 u32 hcfg, hfir, otgctl, usbcfg;
2353 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2355 /* Set HS/FS Timeout Calibration to 7 (max available value).
2356 * The number of PHY clocks that the application programs in
2357 * this field is added to the high/full speed interpacket timeout
2358 * duration in the core to account for any additional delays
2359 * introduced by the PHY. This can be required, because the delay
2360 * introduced by the PHY in generating the linestate condition
2361 * can vary from one PHY to another.
2363 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2364 usbcfg |= GUSBCFG_TOUTCAL(7);
2365 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2367 /* Restart the Phy Clock */
2368 dwc2_writel(0, hsotg->regs + PCGCTL);
2370 /* Initialize Host Configuration Register */
2371 dwc2_init_fs_ls_pclk_sel(hsotg);
2372 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2373 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2374 hcfg = dwc2_readl(hsotg->regs + HCFG);
2375 hcfg |= HCFG_FSLSSUPP;
2376 dwc2_writel(hcfg, hsotg->regs + HCFG);
2380 * This bit allows dynamic reloading of the HFIR register during
2381 * runtime. This bit needs to be programmed during initial configuration
2382 * and its value must not be changed during runtime.
2384 if (hsotg->params.reload_ctl) {
2385 hfir = dwc2_readl(hsotg->regs + HFIR);
2386 hfir |= HFIR_RLDCTRL;
2387 dwc2_writel(hfir, hsotg->regs + HFIR);
2390 if (hsotg->params.dma_desc_enable) {
2391 u32 op_mode = hsotg->hw_params.op_mode;
2393 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2394 !hsotg->hw_params.dma_desc_enable ||
2395 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2396 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2397 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2399 "Hardware does not support descriptor DMA mode -\n");
2401 "falling back to buffer DMA mode.\n");
2402 hsotg->params.dma_desc_enable = false;
2404 hcfg = dwc2_readl(hsotg->regs + HCFG);
2405 hcfg |= HCFG_DESCDMA;
2406 dwc2_writel(hcfg, hsotg->regs + HCFG);
2410 /* Configure data FIFO sizes */
2411 dwc2_config_fifos(hsotg);
2413 /* TODO - check this */
2414 /* Clear Host Set HNP Enable in the OTG Control Register */
2415 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2416 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2417 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2419 /* Make sure the FIFOs are flushed */
2420 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2421 dwc2_flush_rx_fifo(hsotg);
2423 /* Clear Host Set HNP Enable in the OTG Control Register */
2424 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2425 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2426 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2428 if (!hsotg->params.dma_desc_enable) {
2429 int num_channels, i;
2432 /* Flush out any leftover queued requests */
2433 num_channels = hsotg->params.host_channels;
2434 for (i = 0; i < num_channels; i++) {
2435 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2436 hcchar &= ~HCCHAR_CHENA;
2437 hcchar |= HCCHAR_CHDIS;
2438 hcchar &= ~HCCHAR_EPDIR;
2439 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2442 /* Halt all channels to put them into a known state */
2443 for (i = 0; i < num_channels; i++) {
2444 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2445 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2446 hcchar &= ~HCCHAR_EPDIR;
2447 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2448 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2451 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2452 HCCHAR_CHENA, 1000)) {
2453 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2459 /* Enable ACG feature in host mode, if supported */
2460 dwc2_enable_acg(hsotg);
2462 /* Turn on the vbus power */
2463 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2464 if (hsotg->op_state == OTG_STATE_A_HOST) {
2465 u32 hprt0 = dwc2_read_hprt0(hsotg);
2467 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2468 !!(hprt0 & HPRT0_PWR));
2469 if (!(hprt0 & HPRT0_PWR)) {
2471 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2475 dwc2_enable_host_interrupts(hsotg);
2479 * Initializes dynamic portions of the DWC_otg HCD state
2481 * Must be called with interrupt disabled and spinlock held
2483 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2485 struct dwc2_host_chan *chan, *chan_tmp;
2489 hsotg->flags.d32 = 0;
2490 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2492 if (hsotg->params.uframe_sched) {
2493 hsotg->available_host_channels =
2494 hsotg->params.host_channels;
2496 hsotg->non_periodic_channels = 0;
2497 hsotg->periodic_channels = 0;
2501 * Put all channels in the free channel list and clean up channel
2504 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2506 list_del_init(&chan->hc_list_entry);
2508 num_channels = hsotg->params.host_channels;
2509 for (i = 0; i < num_channels; i++) {
2510 chan = hsotg->hc_ptr_array[i];
2511 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2512 dwc2_hc_cleanup(hsotg, chan);
2515 /* Initialize the DWC core for host mode operation */
2516 dwc2_core_host_init(hsotg);
2519 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2520 struct dwc2_host_chan *chan,
2521 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2523 int hub_addr, hub_port;
2526 chan->xact_pos = qtd->isoc_split_pos;
2527 chan->complete_split = qtd->complete_split;
2528 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2529 chan->hub_addr = (u8)hub_addr;
2530 chan->hub_port = (u8)hub_port;
2533 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2534 struct dwc2_host_chan *chan,
2535 struct dwc2_qtd *qtd)
2537 struct dwc2_hcd_urb *urb = qtd->urb;
2538 struct dwc2_hcd_iso_packet_desc *frame_desc;
2540 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2541 case USB_ENDPOINT_XFER_CONTROL:
2542 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2544 switch (qtd->control_phase) {
2545 case DWC2_CONTROL_SETUP:
2546 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2549 chan->data_pid_start = DWC2_HC_PID_SETUP;
2550 if (hsotg->params.host_dma)
2551 chan->xfer_dma = urb->setup_dma;
2553 chan->xfer_buf = urb->setup_packet;
2557 case DWC2_CONTROL_DATA:
2558 dev_vdbg(hsotg->dev, " Control data transaction\n");
2559 chan->data_pid_start = qtd->data_toggle;
2562 case DWC2_CONTROL_STATUS:
2564 * Direction is opposite of data direction or IN if no
2567 dev_vdbg(hsotg->dev, " Control status transaction\n");
2568 if (urb->length == 0)
2572 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2575 chan->data_pid_start = DWC2_HC_PID_DATA1;
2577 if (hsotg->params.host_dma)
2578 chan->xfer_dma = hsotg->status_buf_dma;
2580 chan->xfer_buf = hsotg->status_buf;
2585 case USB_ENDPOINT_XFER_BULK:
2586 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2589 case USB_ENDPOINT_XFER_INT:
2590 chan->ep_type = USB_ENDPOINT_XFER_INT;
2593 case USB_ENDPOINT_XFER_ISOC:
2594 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2595 if (hsotg->params.dma_desc_enable)
2598 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2599 frame_desc->status = 0;
2601 if (hsotg->params.host_dma) {
2602 chan->xfer_dma = urb->dma;
2603 chan->xfer_dma += frame_desc->offset +
2604 qtd->isoc_split_offset;
2606 chan->xfer_buf = urb->buf;
2607 chan->xfer_buf += frame_desc->offset +
2608 qtd->isoc_split_offset;
2611 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2613 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2614 if (chan->xfer_len <= 188)
2615 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2617 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2623 #define DWC2_USB_DMA_ALIGN 4
2625 struct dma_aligned_buffer {
2627 void *old_xfer_buffer;
2631 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2633 struct dma_aligned_buffer *temp;
2635 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2638 temp = container_of(urb->transfer_buffer,
2639 struct dma_aligned_buffer, data);
2641 if (usb_urb_dir_in(urb))
2642 memcpy(temp->old_xfer_buffer, temp->data,
2643 urb->transfer_buffer_length);
2644 urb->transfer_buffer = temp->old_xfer_buffer;
2645 kfree(temp->kmalloc_ptr);
2647 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2650 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2652 struct dma_aligned_buffer *temp, *kmalloc_ptr;
2653 size_t kmalloc_size;
2655 if (urb->num_sgs || urb->sg ||
2656 urb->transfer_buffer_length == 0 ||
2657 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2660 /* Allocate a buffer with enough padding for alignment */
2661 kmalloc_size = urb->transfer_buffer_length +
2662 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
2664 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2668 /* Position our struct dma_aligned_buffer such that data is aligned */
2669 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
2670 temp->kmalloc_ptr = kmalloc_ptr;
2671 temp->old_xfer_buffer = urb->transfer_buffer;
2672 if (usb_urb_dir_out(urb))
2673 memcpy(temp->data, urb->transfer_buffer,
2674 urb->transfer_buffer_length);
2675 urb->transfer_buffer = temp->data;
2677 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2682 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2687 /* We assume setup_dma is always aligned; warn if not */
2688 WARN_ON_ONCE(urb->setup_dma &&
2689 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2691 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2695 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2697 dwc2_free_dma_aligned_buffer(urb);
2702 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2704 usb_hcd_unmap_urb_for_dma(hcd, urb);
2705 dwc2_free_dma_aligned_buffer(urb);
2709 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2710 * channel and initializes the host channel to perform the transactions. The
2711 * host channel is removed from the free list.
2713 * @hsotg: The HCD state structure
2714 * @qh: Transactions from the first QTD for this QH are selected and assigned
2715 * to a free host channel
2717 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2719 struct dwc2_host_chan *chan;
2720 struct dwc2_hcd_urb *urb;
2721 struct dwc2_qtd *qtd;
2724 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2726 if (list_empty(&qh->qtd_list)) {
2727 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2731 if (list_empty(&hsotg->free_hc_list)) {
2732 dev_dbg(hsotg->dev, "No free channel to assign\n");
2736 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2739 /* Remove host channel from free list */
2740 list_del_init(&chan->hc_list_entry);
2742 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2745 qtd->in_process = 1;
2748 * Use usb_pipedevice to determine device address. This address is
2749 * 0 before the SET_ADDRESS command and the correct address afterward.
2751 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2752 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2753 chan->speed = qh->dev_speed;
2754 chan->max_packet = dwc2_max_packet(qh->maxp);
2756 chan->xfer_started = 0;
2757 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2758 chan->error_state = (qtd->error_count > 0);
2759 chan->halt_on_queue = 0;
2760 chan->halt_pending = 0;
2764 * The following values may be modified in the transfer type section
2765 * below. The xfer_len value may be reduced when the transfer is
2766 * started to accommodate the max widths of the XferSize and PktCnt
2767 * fields in the HCTSIZn register.
2770 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2774 chan->do_ping = qh->ping_state;
2776 chan->data_pid_start = qh->data_toggle;
2777 chan->multi_count = 1;
2779 if (urb->actual_length > urb->length &&
2780 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2781 urb->actual_length = urb->length;
2783 if (hsotg->params.host_dma)
2784 chan->xfer_dma = urb->dma + urb->actual_length;
2786 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2788 chan->xfer_len = urb->length - urb->actual_length;
2789 chan->xfer_count = 0;
2791 /* Set the split attributes if required */
2793 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2797 /* Set the transfer attributes */
2798 dwc2_hc_init_xfer(hsotg, chan, qtd);
2800 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2801 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2803 * This value may be modified when the transfer is started
2804 * to reflect the actual transfer length
2806 chan->multi_count = dwc2_hb_mult(qh->maxp);
2808 if (hsotg->params.dma_desc_enable) {
2809 chan->desc_list_addr = qh->desc_list_dma;
2810 chan->desc_list_sz = qh->desc_list_sz;
2813 dwc2_hc_init(hsotg, chan);
2820 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2821 * schedule and assigns them to available host channels. Called from the HCD
2822 * interrupt handler functions.
2824 * @hsotg: The HCD state structure
2826 * Return: The types of new transactions that were assigned to host channels
2828 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2829 struct dwc2_hsotg *hsotg)
2831 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2832 struct list_head *qh_ptr;
2836 #ifdef DWC2_DEBUG_SOF
2837 dev_vdbg(hsotg->dev, " Select Transactions\n");
2840 /* Process entries in the periodic ready list */
2841 qh_ptr = hsotg->periodic_sched_ready.next;
2842 while (qh_ptr != &hsotg->periodic_sched_ready) {
2843 if (list_empty(&hsotg->free_hc_list))
2845 if (hsotg->params.uframe_sched) {
2846 if (hsotg->available_host_channels <= 1)
2848 hsotg->available_host_channels--;
2850 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2851 if (dwc2_assign_and_init_hc(hsotg, qh))
2855 * Move the QH from the periodic ready schedule to the
2856 * periodic assigned schedule
2858 qh_ptr = qh_ptr->next;
2859 list_move_tail(&qh->qh_list_entry,
2860 &hsotg->periodic_sched_assigned);
2861 ret_val = DWC2_TRANSACTION_PERIODIC;
2865 * Process entries in the inactive portion of the non-periodic
2866 * schedule. Some free host channels may not be used if they are
2867 * reserved for periodic transfers.
2869 num_channels = hsotg->params.host_channels;
2870 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2871 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2872 if (!hsotg->params.uframe_sched &&
2873 hsotg->non_periodic_channels >= num_channels -
2874 hsotg->periodic_channels)
2876 if (list_empty(&hsotg->free_hc_list))
2878 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2879 if (hsotg->params.uframe_sched) {
2880 if (hsotg->available_host_channels < 1)
2882 hsotg->available_host_channels--;
2885 if (dwc2_assign_and_init_hc(hsotg, qh))
2889 * Move the QH from the non-periodic inactive schedule to the
2890 * non-periodic active schedule
2892 qh_ptr = qh_ptr->next;
2893 list_move_tail(&qh->qh_list_entry,
2894 &hsotg->non_periodic_sched_active);
2896 if (ret_val == DWC2_TRANSACTION_NONE)
2897 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2899 ret_val = DWC2_TRANSACTION_ALL;
2901 if (!hsotg->params.uframe_sched)
2902 hsotg->non_periodic_channels++;
2909 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2910 * a host channel associated with either a periodic or non-periodic transfer
2912 * @hsotg: The HCD state structure
2913 * @chan: Host channel descriptor associated with either a periodic or
2914 * non-periodic transfer
2915 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2916 * for periodic transfers or the non-periodic Tx FIFO
2917 * for non-periodic transfers
2919 * Return: 1 if a request is queued and more requests may be needed to
2920 * complete the transfer, 0 if no more requests are required for this
2921 * transfer, -1 if there is insufficient space in the Tx FIFO
2923 * This function assumes that there is space available in the appropriate
2924 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2925 * it checks whether space is available in the appropriate Tx FIFO.
2927 * Must be called with interrupt disabled and spinlock held
2929 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2930 struct dwc2_host_chan *chan,
2931 u16 fifo_dwords_avail)
2936 /* Put ourselves on the list to keep order straight */
2937 list_move_tail(&chan->split_order_list_entry,
2938 &hsotg->split_order);
2940 if (hsotg->params.host_dma) {
2941 if (hsotg->params.dma_desc_enable) {
2942 if (!chan->xfer_started ||
2943 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2944 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2945 chan->qh->ping_state = 0;
2947 } else if (!chan->xfer_started) {
2948 dwc2_hc_start_transfer(hsotg, chan);
2949 chan->qh->ping_state = 0;
2951 } else if (chan->halt_pending) {
2952 /* Don't queue a request if the channel has been halted */
2953 } else if (chan->halt_on_queue) {
2954 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2955 } else if (chan->do_ping) {
2956 if (!chan->xfer_started)
2957 dwc2_hc_start_transfer(hsotg, chan);
2958 } else if (!chan->ep_is_in ||
2959 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2960 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2961 if (!chan->xfer_started) {
2962 dwc2_hc_start_transfer(hsotg, chan);
2965 retval = dwc2_hc_continue_transfer(hsotg, chan);
2971 if (!chan->xfer_started) {
2972 dwc2_hc_start_transfer(hsotg, chan);
2975 retval = dwc2_hc_continue_transfer(hsotg, chan);
2983 * Processes periodic channels for the next frame and queues transactions for
2984 * these channels to the DWC_otg controller. After queueing transactions, the
2985 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2986 * to queue as Periodic Tx FIFO or request queue space becomes available.
2987 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2989 * Must be called with interrupt disabled and spinlock held
2991 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2993 struct list_head *qh_ptr;
2999 bool no_queue_space = false;
3000 bool no_fifo_space = false;
3003 /* If empty list then just adjust interrupt enables */
3004 if (list_empty(&hsotg->periodic_sched_assigned))
3008 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3010 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3011 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3012 TXSTS_QSPCAVAIL_SHIFT;
3013 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3014 TXSTS_FSPCAVAIL_SHIFT;
3017 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3019 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3023 qh_ptr = hsotg->periodic_sched_assigned.next;
3024 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3025 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3026 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3027 TXSTS_QSPCAVAIL_SHIFT;
3028 if (qspcavail == 0) {
3029 no_queue_space = true;
3033 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3035 qh_ptr = qh_ptr->next;
3039 /* Make sure EP's TT buffer is clean before queueing qtds */
3040 if (qh->tt_buffer_dirty) {
3041 qh_ptr = qh_ptr->next;
3046 * Set a flag if we're queuing high-bandwidth in slave mode.
3047 * The flag prevents any halts to get into the request queue in
3048 * the middle of multiple high-bandwidth packets getting queued.
3050 if (!hsotg->params.host_dma &&
3051 qh->channel->multi_count > 1)
3052 hsotg->queuing_high_bandwidth = 1;
3054 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3055 TXSTS_FSPCAVAIL_SHIFT;
3056 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3058 no_fifo_space = true;
3063 * In Slave mode, stay on the current transfer until there is
3064 * nothing more to do or the high-bandwidth request count is
3065 * reached. In DMA mode, only need to queue one request. The
3066 * controller automatically handles multiple packets for
3067 * high-bandwidth transfers.
3069 if (hsotg->params.host_dma || status == 0 ||
3070 qh->channel->requests == qh->channel->multi_count) {
3071 qh_ptr = qh_ptr->next;
3073 * Move the QH from the periodic assigned schedule to
3074 * the periodic queued schedule
3076 list_move_tail(&qh->qh_list_entry,
3077 &hsotg->periodic_sched_queued);
3079 /* done queuing high bandwidth */
3080 hsotg->queuing_high_bandwidth = 0;
3085 if (no_queue_space || no_fifo_space ||
3086 (!hsotg->params.host_dma &&
3087 !list_empty(&hsotg->periodic_sched_assigned))) {
3089 * May need to queue more transactions as the request
3090 * queue or Tx FIFO empties. Enable the periodic Tx
3091 * FIFO empty interrupt. (Always use the half-empty
3092 * level to ensure that new requests are loaded as
3093 * soon as possible.)
3095 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3096 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3097 gintmsk |= GINTSTS_PTXFEMP;
3098 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3102 * Disable the Tx FIFO empty interrupt since there are
3103 * no more transactions that need to be queued right
3104 * now. This function is called from interrupt
3105 * handlers to queue more transactions as transfer
3108 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3109 if (gintmsk & GINTSTS_PTXFEMP) {
3110 gintmsk &= ~GINTSTS_PTXFEMP;
3111 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3117 * Processes active non-periodic channels and queues transactions for these
3118 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3119 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3120 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3121 * FIFO Empty interrupt is disabled.
3123 * Must be called with interrupt disabled and spinlock held
3125 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3127 struct list_head *orig_qh_ptr;
3134 int no_queue_space = 0;
3135 int no_fifo_space = 0;
3138 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3140 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3141 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3142 TXSTS_QSPCAVAIL_SHIFT;
3143 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3144 TXSTS_FSPCAVAIL_SHIFT;
3145 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3147 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3151 * Keep track of the starting point. Skip over the start-of-list
3154 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3155 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3156 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3159 * Process once through the active list or until no more space is
3160 * available in the request queue or the Tx FIFO
3163 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3164 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3165 TXSTS_QSPCAVAIL_SHIFT;
3166 if (!hsotg->params.host_dma && qspcavail == 0) {
3171 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3176 /* Make sure EP's TT buffer is clean before queueing qtds */
3177 if (qh->tt_buffer_dirty)
3180 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3181 TXSTS_FSPCAVAIL_SHIFT;
3182 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3186 } else if (status < 0) {
3191 /* Advance to next QH, skipping start-of-list entry */
3192 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3193 if (hsotg->non_periodic_qh_ptr ==
3194 &hsotg->non_periodic_sched_active)
3195 hsotg->non_periodic_qh_ptr =
3196 hsotg->non_periodic_qh_ptr->next;
3197 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3199 if (!hsotg->params.host_dma) {
3200 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3201 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3202 TXSTS_QSPCAVAIL_SHIFT;
3203 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3204 TXSTS_FSPCAVAIL_SHIFT;
3205 dev_vdbg(hsotg->dev,
3206 " NP Tx Req Queue Space Avail (after queue): %d\n",
3208 dev_vdbg(hsotg->dev,
3209 " NP Tx FIFO Space Avail (after queue): %d\n",
3212 if (more_to_do || no_queue_space || no_fifo_space) {
3214 * May need to queue more transactions as the request
3215 * queue or Tx FIFO empties. Enable the non-periodic
3216 * Tx FIFO empty interrupt. (Always use the half-empty
3217 * level to ensure that new requests are loaded as
3218 * soon as possible.)
3220 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3221 gintmsk |= GINTSTS_NPTXFEMP;
3222 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3225 * Disable the Tx FIFO empty interrupt since there are
3226 * no more transactions that need to be queued right
3227 * now. This function is called from interrupt
3228 * handlers to queue more transactions as transfer
3231 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3232 gintmsk &= ~GINTSTS_NPTXFEMP;
3233 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3239 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3240 * and queues transactions for these channels to the DWC_otg controller. Called
3241 * from the HCD interrupt handler functions.
3243 * @hsotg: The HCD state structure
3244 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3247 * Must be called with interrupt disabled and spinlock held
3249 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3250 enum dwc2_transaction_type tr_type)
3252 #ifdef DWC2_DEBUG_SOF
3253 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3255 /* Process host channels associated with periodic transfers */
3256 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3257 tr_type == DWC2_TRANSACTION_ALL)
3258 dwc2_process_periodic_channels(hsotg);
3260 /* Process host channels associated with non-periodic transfers */
3261 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3262 tr_type == DWC2_TRANSACTION_ALL) {
3263 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3264 dwc2_process_non_periodic_channels(hsotg);
3267 * Ensure NP Tx FIFO empty interrupt is disabled when
3268 * there are no non-periodic transfers to process
3270 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3272 gintmsk &= ~GINTSTS_NPTXFEMP;
3273 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3278 static void dwc2_conn_id_status_change(struct work_struct *work)
3280 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3284 unsigned long flags;
3286 dev_dbg(hsotg->dev, "%s()\n", __func__);
3288 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3289 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3290 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3291 !!(gotgctl & GOTGCTL_CONID_B));
3293 /* B-Device connector (Device Mode) */
3294 if (gotgctl & GOTGCTL_CONID_B) {
3295 dwc2_vbus_supply_exit(hsotg);
3296 /* Wait for switch to device mode */
3297 dev_dbg(hsotg->dev, "connId B\n");
3298 if (hsotg->bus_suspended) {
3299 dev_info(hsotg->dev,
3300 "Do port resume before switching to device mode\n");
3301 dwc2_port_resume(hsotg);
3303 while (!dwc2_is_device_mode(hsotg)) {
3304 dev_info(hsotg->dev,
3305 "Waiting for Peripheral Mode, Mode=%s\n",
3306 dwc2_is_host_mode(hsotg) ? "Host" :
3310 * Sometimes the initial GOTGCTRL read is wrong, so
3311 * check it again and jump to host mode if that was
3314 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3315 if (!(gotgctl & GOTGCTL_CONID_B))
3322 "Connection id status change timed out\n");
3323 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3324 dwc2_core_init(hsotg, false);
3325 dwc2_enable_global_interrupts(hsotg);
3326 spin_lock_irqsave(&hsotg->lock, flags);
3327 dwc2_hsotg_core_init_disconnected(hsotg, false);
3328 spin_unlock_irqrestore(&hsotg->lock, flags);
3329 /* Enable ACG feature in device mode,if supported */
3330 dwc2_enable_acg(hsotg);
3331 dwc2_hsotg_core_connect(hsotg);
3334 /* A-Device connector (Host Mode) */
3335 dev_dbg(hsotg->dev, "connId A\n");
3336 while (!dwc2_is_host_mode(hsotg)) {
3337 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3338 dwc2_is_host_mode(hsotg) ?
3339 "Host" : "Peripheral");
3346 "Connection id status change timed out\n");
3348 spin_lock_irqsave(&hsotg->lock, flags);
3349 dwc2_hsotg_disconnect(hsotg);
3350 spin_unlock_irqrestore(&hsotg->lock, flags);
3352 hsotg->op_state = OTG_STATE_A_HOST;
3353 /* Initialize the Core for Host mode */
3354 dwc2_core_init(hsotg, false);
3355 dwc2_enable_global_interrupts(hsotg);
3356 dwc2_hcd_start(hsotg);
3360 static void dwc2_wakeup_detected(struct timer_list *t)
3362 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3365 dev_dbg(hsotg->dev, "%s()\n", __func__);
3368 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3369 * so that OPT tests pass with all PHYs.)
3371 hprt0 = dwc2_read_hprt0(hsotg);
3372 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3373 hprt0 &= ~HPRT0_RES;
3374 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3375 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3376 dwc2_readl(hsotg->regs + HPRT0));
3378 dwc2_hcd_rem_wakeup(hsotg);
3379 hsotg->bus_suspended = false;
3381 /* Change to L0 state */
3382 hsotg->lx_state = DWC2_L0;
3385 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3387 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3389 return hcd->self.b_hnp_enable;
3392 /* Must NOT be called with interrupt disabled or spinlock held */
3393 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3395 unsigned long flags;
3400 dev_dbg(hsotg->dev, "%s()\n", __func__);
3402 spin_lock_irqsave(&hsotg->lock, flags);
3404 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3405 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3406 gotgctl |= GOTGCTL_HSTSETHNPEN;
3407 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3408 hsotg->op_state = OTG_STATE_A_SUSPEND;
3411 hprt0 = dwc2_read_hprt0(hsotg);
3412 hprt0 |= HPRT0_SUSP;
3413 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3415 hsotg->bus_suspended = true;
3418 * If power_down is supported, Phy clock will be suspended
3419 * after registers are backuped.
3421 if (!hsotg->params.power_down) {
3422 /* Suspend the Phy Clock */
3423 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3424 pcgctl |= PCGCTL_STOPPCLK;
3425 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3429 /* For HNP the bus must be suspended for at least 200ms */
3430 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3431 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3432 pcgctl &= ~PCGCTL_STOPPCLK;
3433 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3435 spin_unlock_irqrestore(&hsotg->lock, flags);
3439 spin_unlock_irqrestore(&hsotg->lock, flags);
3443 /* Must NOT be called with interrupt disabled or spinlock held */
3444 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3446 unsigned long flags;
3450 spin_lock_irqsave(&hsotg->lock, flags);
3453 * If power_down is supported, Phy clock is already resumed
3454 * after registers restore.
3456 if (!hsotg->params.power_down) {
3457 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3458 pcgctl &= ~PCGCTL_STOPPCLK;
3459 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3460 spin_unlock_irqrestore(&hsotg->lock, flags);
3462 spin_lock_irqsave(&hsotg->lock, flags);
3465 hprt0 = dwc2_read_hprt0(hsotg);
3467 hprt0 &= ~HPRT0_SUSP;
3468 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3469 spin_unlock_irqrestore(&hsotg->lock, flags);
3471 msleep(USB_RESUME_TIMEOUT);
3473 spin_lock_irqsave(&hsotg->lock, flags);
3474 hprt0 = dwc2_read_hprt0(hsotg);
3475 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3476 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3477 hsotg->bus_suspended = false;
3478 spin_unlock_irqrestore(&hsotg->lock, flags);
3481 /* Handles hub class-specific requests */
3482 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3483 u16 wvalue, u16 windex, char *buf, u16 wlength)
3485 struct usb_hub_descriptor *hub_desc;
3493 case ClearHubFeature:
3494 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3497 case C_HUB_LOCAL_POWER:
3498 case C_HUB_OVER_CURRENT:
3499 /* Nothing required here */
3505 "ClearHubFeature request %1xh unknown\n",
3510 case ClearPortFeature:
3511 if (wvalue != USB_PORT_FEAT_L1)
3512 if (!windex || windex > 1)
3515 case USB_PORT_FEAT_ENABLE:
3517 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3518 hprt0 = dwc2_read_hprt0(hsotg);
3520 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3523 case USB_PORT_FEAT_SUSPEND:
3525 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3527 if (hsotg->bus_suspended) {
3528 if (hsotg->hibernated)
3529 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3531 dwc2_port_resume(hsotg);
3535 case USB_PORT_FEAT_POWER:
3537 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3538 hprt0 = dwc2_read_hprt0(hsotg);
3539 hprt0 &= ~HPRT0_PWR;
3540 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3543 case USB_PORT_FEAT_INDICATOR:
3545 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3546 /* Port indicator not supported */
3549 case USB_PORT_FEAT_C_CONNECTION:
3551 * Clears driver's internal Connect Status Change flag
3554 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3555 hsotg->flags.b.port_connect_status_change = 0;
3558 case USB_PORT_FEAT_C_RESET:
3559 /* Clears driver's internal Port Reset Change flag */
3561 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3562 hsotg->flags.b.port_reset_change = 0;
3565 case USB_PORT_FEAT_C_ENABLE:
3567 * Clears the driver's internal Port Enable/Disable
3571 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3572 hsotg->flags.b.port_enable_change = 0;
3575 case USB_PORT_FEAT_C_SUSPEND:
3577 * Clears the driver's internal Port Suspend Change
3578 * flag, which is set when resume signaling on the host
3582 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3583 hsotg->flags.b.port_suspend_change = 0;
3586 case USB_PORT_FEAT_C_PORT_L1:
3588 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3589 hsotg->flags.b.port_l1_change = 0;
3592 case USB_PORT_FEAT_C_OVER_CURRENT:
3594 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3595 hsotg->flags.b.port_over_current_change = 0;
3601 "ClearPortFeature request %1xh unknown or unsupported\n",
3606 case GetHubDescriptor:
3607 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3608 hub_desc = (struct usb_hub_descriptor *)buf;
3609 hub_desc->bDescLength = 9;
3610 hub_desc->bDescriptorType = USB_DT_HUB;
3611 hub_desc->bNbrPorts = 1;
3612 hub_desc->wHubCharacteristics =
3613 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3614 HUB_CHAR_INDV_PORT_OCPM);
3615 hub_desc->bPwrOn2PwrGood = 1;
3616 hub_desc->bHubContrCurrent = 0;
3617 hub_desc->u.hs.DeviceRemovable[0] = 0;
3618 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3622 dev_dbg(hsotg->dev, "GetHubStatus\n");
3627 dev_vdbg(hsotg->dev,
3628 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3630 if (!windex || windex > 1)
3634 if (hsotg->flags.b.port_connect_status_change)
3635 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3636 if (hsotg->flags.b.port_enable_change)
3637 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3638 if (hsotg->flags.b.port_suspend_change)
3639 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3640 if (hsotg->flags.b.port_l1_change)
3641 port_status |= USB_PORT_STAT_C_L1 << 16;
3642 if (hsotg->flags.b.port_reset_change)
3643 port_status |= USB_PORT_STAT_C_RESET << 16;
3644 if (hsotg->flags.b.port_over_current_change) {
3645 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3646 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3649 if (!hsotg->flags.b.port_connect_status) {
3651 * The port is disconnected, which means the core is
3652 * either in device mode or it soon will be. Just
3653 * return 0's for the remainder of the port status
3654 * since the port register can't be read if the core
3655 * is in device mode.
3657 *(__le32 *)buf = cpu_to_le32(port_status);
3661 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3662 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3664 if (hprt0 & HPRT0_CONNSTS)
3665 port_status |= USB_PORT_STAT_CONNECTION;
3666 if (hprt0 & HPRT0_ENA)
3667 port_status |= USB_PORT_STAT_ENABLE;
3668 if (hprt0 & HPRT0_SUSP)
3669 port_status |= USB_PORT_STAT_SUSPEND;
3670 if (hprt0 & HPRT0_OVRCURRACT)
3671 port_status |= USB_PORT_STAT_OVERCURRENT;
3672 if (hprt0 & HPRT0_RST)
3673 port_status |= USB_PORT_STAT_RESET;
3674 if (hprt0 & HPRT0_PWR)
3675 port_status |= USB_PORT_STAT_POWER;
3677 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3678 if (speed == HPRT0_SPD_HIGH_SPEED)
3679 port_status |= USB_PORT_STAT_HIGH_SPEED;
3680 else if (speed == HPRT0_SPD_LOW_SPEED)
3681 port_status |= USB_PORT_STAT_LOW_SPEED;
3683 if (hprt0 & HPRT0_TSTCTL_MASK)
3684 port_status |= USB_PORT_STAT_TEST;
3685 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3687 if (hsotg->params.dma_desc_fs_enable) {
3689 * Enable descriptor DMA only if a full speed
3690 * device is connected.
3692 if (hsotg->new_connection &&
3694 (USB_PORT_STAT_CONNECTION |
3695 USB_PORT_STAT_HIGH_SPEED |
3696 USB_PORT_STAT_LOW_SPEED)) ==
3697 USB_PORT_STAT_CONNECTION)) {
3700 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3701 hsotg->params.dma_desc_enable = true;
3702 hcfg = dwc2_readl(hsotg->regs + HCFG);
3703 hcfg |= HCFG_DESCDMA;
3704 dwc2_writel(hcfg, hsotg->regs + HCFG);
3705 hsotg->new_connection = false;
3709 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3710 *(__le32 *)buf = cpu_to_le32(port_status);
3714 dev_dbg(hsotg->dev, "SetHubFeature\n");
3715 /* No HUB features supported */
3718 case SetPortFeature:
3719 dev_dbg(hsotg->dev, "SetPortFeature\n");
3720 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3723 if (!hsotg->flags.b.port_connect_status) {
3725 * The port is disconnected, which means the core is
3726 * either in device mode or it soon will be. Just
3727 * return without doing anything since the port
3728 * register can't be written if the core is in device
3735 case USB_PORT_FEAT_SUSPEND:
3737 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3738 if (windex != hsotg->otg_port)
3740 if (hsotg->params.power_down == 2)
3741 dwc2_enter_hibernation(hsotg, 1);
3743 dwc2_port_suspend(hsotg, windex);
3746 case USB_PORT_FEAT_POWER:
3748 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3749 hprt0 = dwc2_read_hprt0(hsotg);
3751 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3754 case USB_PORT_FEAT_RESET:
3755 if (hsotg->params.power_down == 2 &&
3757 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3758 hprt0 = dwc2_read_hprt0(hsotg);
3760 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3761 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3762 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3763 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3764 /* ??? Original driver does this */
3765 dwc2_writel(0, hsotg->regs + PCGCTL);
3767 hprt0 = dwc2_read_hprt0(hsotg);
3768 /* Clear suspend bit if resetting from suspend state */
3769 hprt0 &= ~HPRT0_SUSP;
3772 * When B-Host the Port reset bit is set in the Start
3773 * HCD Callback function, so that the reset is started
3774 * within 1ms of the HNP success interrupt
3776 if (!dwc2_hcd_is_b_host(hsotg)) {
3777 hprt0 |= HPRT0_PWR | HPRT0_RST;
3779 "In host mode, hprt0=%08x\n", hprt0);
3780 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3783 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3785 hprt0 &= ~HPRT0_RST;
3786 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3787 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3790 case USB_PORT_FEAT_INDICATOR:
3792 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3796 case USB_PORT_FEAT_TEST:
3797 hprt0 = dwc2_read_hprt0(hsotg);
3799 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3800 hprt0 &= ~HPRT0_TSTCTL_MASK;
3801 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3802 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3808 "SetPortFeature %1xh unknown or unsupported\n",
3818 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3819 typereq, windex, wvalue);
3826 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3833 retval = (hsotg->flags.b.port_connect_status_change ||
3834 hsotg->flags.b.port_reset_change ||
3835 hsotg->flags.b.port_enable_change ||
3836 hsotg->flags.b.port_suspend_change ||
3837 hsotg->flags.b.port_over_current_change);
3841 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3842 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3843 hsotg->flags.b.port_connect_status_change);
3844 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3845 hsotg->flags.b.port_reset_change);
3846 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3847 hsotg->flags.b.port_enable_change);
3848 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3849 hsotg->flags.b.port_suspend_change);
3850 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3851 hsotg->flags.b.port_over_current_change);
3857 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3859 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3861 #ifdef DWC2_DEBUG_SOF
3862 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3863 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3865 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3868 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3870 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3871 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3872 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3873 unsigned int us_per_frame;
3874 unsigned int frame_number;
3875 unsigned int remaining;
3876 unsigned int interval;
3877 unsigned int phy_clks;
3879 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3880 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3882 /* Extract fields */
3883 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3884 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3885 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3888 * Number of phy clocks since the last tick of the frame number after
3891 phy_clks = (interval - remaining) +
3892 DIV_ROUND_UP(interval * us, us_per_frame);
3894 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3897 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3899 return hsotg->op_state == OTG_STATE_B_HOST;
3902 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3906 struct dwc2_hcd_urb *urb;
3907 u32 size = sizeof(*urb) + iso_desc_count *
3908 sizeof(struct dwc2_hcd_iso_packet_desc);
3910 urb = kzalloc(size, mem_flags);
3912 urb->packet_count = iso_desc_count;
3916 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3917 struct dwc2_hcd_urb *urb, u8 dev_addr,
3918 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3921 ep_type == USB_ENDPOINT_XFER_BULK ||
3922 ep_type == USB_ENDPOINT_XFER_CONTROL)
3923 dev_vdbg(hsotg->dev,
3924 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3925 dev_addr, ep_num, ep_dir, ep_type, mps);
3926 urb->pipe_info.dev_addr = dev_addr;
3927 urb->pipe_info.ep_num = ep_num;
3928 urb->pipe_info.pipe_type = ep_type;
3929 urb->pipe_info.pipe_dir = ep_dir;
3930 urb->pipe_info.mps = mps;
3934 * NOTE: This function will be removed once the peripheral controller code
3935 * is integrated and the driver is stable
3937 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3940 struct dwc2_host_chan *chan;
3941 struct dwc2_hcd_urb *urb;
3942 struct dwc2_qtd *qtd;
3948 num_channels = hsotg->params.host_channels;
3949 dev_dbg(hsotg->dev, "\n");
3951 "************************************************************\n");
3952 dev_dbg(hsotg->dev, "HCD State:\n");
3953 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3955 for (i = 0; i < num_channels; i++) {
3956 chan = hsotg->hc_ptr_array[i];
3957 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3959 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3960 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3961 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3962 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3963 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3964 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3965 chan->data_pid_start);
3966 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3967 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3968 chan->xfer_started);
3969 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3970 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3971 (unsigned long)chan->xfer_dma);
3972 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3973 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3974 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3975 chan->halt_on_queue);
3976 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3977 chan->halt_pending);
3978 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3979 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3980 dev_dbg(hsotg->dev, " complete_split: %d\n",
3981 chan->complete_split);
3982 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3983 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3984 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3985 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3986 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3988 if (chan->xfer_started) {
3989 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3991 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3992 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3993 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3994 hcint = dwc2_readl(hsotg->regs + HCINT(i));
3995 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
3996 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3997 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3998 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3999 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4000 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4003 if (!(chan->xfer_started && chan->qh))
4006 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4007 if (!qtd->in_process)
4010 dev_dbg(hsotg->dev, " URB Info:\n");
4011 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4015 " Dev: %d, EP: %d %s\n",
4016 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4017 dwc2_hcd_get_ep_num(&urb->pipe_info),
4018 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4021 " Max packet size: %d\n",
4022 dwc2_hcd_get_mps(&urb->pipe_info));
4024 " transfer_buffer: %p\n",
4027 " transfer_dma: %08lx\n",
4028 (unsigned long)urb->dma);
4030 " transfer_buffer_length: %d\n",
4032 dev_dbg(hsotg->dev, " actual_length: %d\n",
4033 urb->actual_length);
4038 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4039 hsotg->non_periodic_channels);
4040 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4041 hsotg->periodic_channels);
4042 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4043 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
4044 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4045 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4046 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4047 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4048 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
4049 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4050 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4051 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4052 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4053 dwc2_dump_global_registers(hsotg);
4054 dwc2_dump_host_registers(hsotg);
4056 "************************************************************\n");
4057 dev_dbg(hsotg->dev, "\n");
4061 struct wrapper_priv_data {
4062 struct dwc2_hsotg *hsotg;
4065 /* Gets the dwc2_hsotg from a usb_hcd */
4066 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4068 struct wrapper_priv_data *p;
4070 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4075 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4077 * This will get the dwc2_tt structure (and ttport) associated with the given
4078 * context (which is really just a struct urb pointer).
4080 * The first time this is called for a given TT we allocate memory for our
4081 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4082 * then the refcount for the structure will go to 0 and we'll free it.
4084 * @hsotg: The HCD state structure for the DWC OTG controller.
4085 * @qh: The QH structure.
4086 * @context: The priv pointer from a struct dwc2_hcd_urb.
4087 * @mem_flags: Flags for allocating memory.
4088 * @ttport: We'll return this device's port number here. That's used to
4089 * reference into the bitmap if we're on a multi_tt hub.
4091 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4092 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4095 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4096 gfp_t mem_flags, int *ttport)
4098 struct urb *urb = context;
4099 struct dwc2_tt *dwc_tt = NULL;
4102 *ttport = urb->dev->ttport;
4104 dwc_tt = urb->dev->tt->hcpriv;
4109 * For single_tt we need one schedule. For multi_tt
4110 * we need one per port.
4112 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4113 sizeof(dwc_tt->periodic_bitmaps[0]);
4114 if (urb->dev->tt->multi)
4115 bitmap_size *= urb->dev->tt->hub->maxchild;
4117 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4122 dwc_tt->usb_tt = urb->dev->tt;
4123 dwc_tt->usb_tt->hcpriv = dwc_tt;
4133 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4135 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4136 * of the structure are done.
4138 * It's OK to call this with NULL.
4140 * @hsotg: The HCD state structure for the DWC OTG controller.
4141 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4143 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4145 /* Model kfree and make put of NULL a no-op */
4149 WARN_ON(dwc_tt->refcount < 1);
4152 if (!dwc_tt->refcount) {
4153 dwc_tt->usb_tt->hcpriv = NULL;
4158 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4160 struct urb *urb = context;
4162 return urb->dev->speed;
4165 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4168 struct usb_bus *bus = hcd_to_bus(hcd);
4171 bus->bandwidth_allocated += bw / urb->interval;
4172 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4173 bus->bandwidth_isoc_reqs++;
4175 bus->bandwidth_int_reqs++;
4178 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4181 struct usb_bus *bus = hcd_to_bus(hcd);
4184 bus->bandwidth_allocated -= bw / urb->interval;
4185 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4186 bus->bandwidth_isoc_reqs--;
4188 bus->bandwidth_int_reqs--;
4192 * Sets the final status of an URB and returns it to the upper layer. Any
4193 * required cleanup of the URB is performed.
4195 * Must be called with interrupt disabled and spinlock held
4197 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4204 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4209 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4213 urb = qtd->urb->priv;
4215 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4219 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4222 dev_vdbg(hsotg->dev,
4223 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4224 __func__, urb, usb_pipedevice(urb->pipe),
4225 usb_pipeendpoint(urb->pipe),
4226 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4227 urb->actual_length);
4229 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4230 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4231 for (i = 0; i < urb->number_of_packets; ++i) {
4232 urb->iso_frame_desc[i].actual_length =
4233 dwc2_hcd_urb_get_iso_desc_actual_length(
4235 urb->iso_frame_desc[i].status =
4236 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4240 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4241 for (i = 0; i < urb->number_of_packets; i++)
4242 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4243 i, urb->iso_frame_desc[i].status);
4246 urb->status = status;
4248 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4249 urb->actual_length < urb->transfer_buffer_length)
4250 urb->status = -EREMOTEIO;
4253 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4254 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4255 struct usb_host_endpoint *ep = urb->ep;
4258 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4259 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4263 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4268 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4272 * Work queue function for starting the HCD when A-Cable is connected
4274 static void dwc2_hcd_start_func(struct work_struct *work)
4276 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4279 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4280 dwc2_host_start(hsotg);
4284 * Reset work queue function
4286 static void dwc2_hcd_reset_func(struct work_struct *work)
4288 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4290 unsigned long flags;
4293 dev_dbg(hsotg->dev, "USB RESET function called\n");
4295 spin_lock_irqsave(&hsotg->lock, flags);
4297 hprt0 = dwc2_read_hprt0(hsotg);
4298 hprt0 &= ~HPRT0_RST;
4299 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4300 hsotg->flags.b.port_reset_change = 1;
4302 spin_unlock_irqrestore(&hsotg->lock, flags);
4306 * =========================================================================
4307 * Linux HC Driver Functions
4308 * =========================================================================
4312 * Initializes the DWC_otg controller and its root hub and prepares it for host
4313 * mode operation. Activates the root port. Returns 0 on success and a negative
4314 * error code on failure.
4316 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4318 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4319 struct usb_bus *bus = hcd_to_bus(hcd);
4320 unsigned long flags;
4322 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4324 spin_lock_irqsave(&hsotg->lock, flags);
4325 hsotg->lx_state = DWC2_L0;
4326 hcd->state = HC_STATE_RUNNING;
4327 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4329 if (dwc2_is_device_mode(hsotg)) {
4330 spin_unlock_irqrestore(&hsotg->lock, flags);
4331 return 0; /* why 0 ?? */
4334 dwc2_hcd_reinit(hsotg);
4336 /* Initialize and connect root hub if one is not already attached */
4337 if (bus->root_hub) {
4338 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4339 /* Inform the HUB driver to resume */
4340 usb_hcd_resume_root_hub(hcd);
4343 spin_unlock_irqrestore(&hsotg->lock, flags);
4345 dwc2_vbus_supply_init(hsotg);
4351 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4354 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4356 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4357 unsigned long flags;
4359 /* Turn off all host-specific interrupts */
4360 dwc2_disable_host_interrupts(hsotg);
4362 /* Wait for interrupt processing to finish */
4363 synchronize_irq(hcd->irq);
4365 spin_lock_irqsave(&hsotg->lock, flags);
4366 /* Ensure hcd is disconnected */
4367 dwc2_hcd_disconnect(hsotg, true);
4368 dwc2_hcd_stop(hsotg);
4369 hsotg->lx_state = DWC2_L3;
4370 hcd->state = HC_STATE_HALT;
4371 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4372 spin_unlock_irqrestore(&hsotg->lock, flags);
4374 dwc2_vbus_supply_exit(hsotg);
4376 usleep_range(1000, 3000);
4379 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4381 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4382 unsigned long flags;
4386 spin_lock_irqsave(&hsotg->lock, flags);
4388 if (dwc2_is_device_mode(hsotg))
4391 if (hsotg->lx_state != DWC2_L0)
4394 if (!HCD_HW_ACCESSIBLE(hcd))
4397 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4400 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
4401 goto skip_power_saving;
4404 * Drive USB suspend and disable port Power
4405 * if usb bus is not suspended.
4407 if (!hsotg->bus_suspended) {
4408 hprt0 = dwc2_read_hprt0(hsotg);
4409 hprt0 |= HPRT0_SUSP;
4410 hprt0 &= ~HPRT0_PWR;
4411 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4412 dwc2_vbus_supply_exit(hsotg);
4415 /* Enter partial_power_down */
4416 ret = dwc2_enter_partial_power_down(hsotg);
4418 if (ret != -ENOTSUPP)
4420 "enter partial_power_down failed\n");
4421 goto skip_power_saving;
4424 /* Ask phy to be suspended */
4425 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4426 spin_unlock_irqrestore(&hsotg->lock, flags);
4427 usb_phy_set_suspend(hsotg->uphy, true);
4428 spin_lock_irqsave(&hsotg->lock, flags);
4431 /* After entering partial_power_down, hardware is no more accessible */
4432 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4435 hsotg->lx_state = DWC2_L2;
4437 spin_unlock_irqrestore(&hsotg->lock, flags);
4442 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4444 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4445 unsigned long flags;
4448 spin_lock_irqsave(&hsotg->lock, flags);
4450 if (dwc2_is_device_mode(hsotg))
4453 if (hsotg->lx_state != DWC2_L2)
4456 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
4457 hsotg->lx_state = DWC2_L0;
4462 * Set HW accessible bit before powering on the controller
4463 * since an interrupt may rise.
4465 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4468 * Enable power if not already done.
4469 * This must not be spinlocked since duration
4470 * of this call is unknown.
4472 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4473 spin_unlock_irqrestore(&hsotg->lock, flags);
4474 usb_phy_set_suspend(hsotg->uphy, false);
4475 spin_lock_irqsave(&hsotg->lock, flags);
4478 /* Exit partial_power_down */
4479 ret = dwc2_exit_partial_power_down(hsotg, true);
4480 if (ret && (ret != -ENOTSUPP))
4481 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4483 hsotg->lx_state = DWC2_L0;
4485 spin_unlock_irqrestore(&hsotg->lock, flags);
4487 if (hsotg->bus_suspended) {
4488 spin_lock_irqsave(&hsotg->lock, flags);
4489 hsotg->flags.b.port_suspend_change = 1;
4490 spin_unlock_irqrestore(&hsotg->lock, flags);
4491 dwc2_port_resume(hsotg);
4493 dwc2_vbus_supply_init(hsotg);
4495 /* Wait for controller to correctly update D+/D- level */
4496 usleep_range(3000, 5000);
4499 * Clear Port Enable and Port Status changes.
4500 * Enable Port Power.
4502 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4503 HPRT0_ENACHG, hsotg->regs + HPRT0);
4504 /* Wait for controller to detect Port Connect */
4505 usleep_range(5000, 7000);
4510 spin_unlock_irqrestore(&hsotg->lock, flags);
4515 /* Returns the current frame number */
4516 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4518 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4520 return dwc2_hcd_get_frame_number(hsotg);
4523 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4526 #ifdef VERBOSE_DEBUG
4527 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4528 char *pipetype = NULL;
4531 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4532 dev_vdbg(hsotg->dev, " Device address: %d\n",
4533 usb_pipedevice(urb->pipe));
4534 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4535 usb_pipeendpoint(urb->pipe),
4536 usb_pipein(urb->pipe) ? "IN" : "OUT");
4538 switch (usb_pipetype(urb->pipe)) {
4540 pipetype = "CONTROL";
4545 case PIPE_INTERRUPT:
4546 pipetype = "INTERRUPT";
4548 case PIPE_ISOCHRONOUS:
4549 pipetype = "ISOCHRONOUS";
4553 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4554 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4557 switch (urb->dev->speed) {
4558 case USB_SPEED_HIGH:
4561 case USB_SPEED_FULL:
4572 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4573 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4574 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4575 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4576 urb->transfer_buffer_length);
4577 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4578 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4579 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4580 urb->setup_packet, (unsigned long)urb->setup_dma);
4581 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4583 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4586 for (i = 0; i < urb->number_of_packets; i++) {
4587 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4588 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4589 urb->iso_frame_desc[i].offset,
4590 urb->iso_frame_desc[i].length);
4597 * Starts processing a USB transfer request specified by a USB Request Block
4598 * (URB). mem_flags indicates the type of memory allocation to use while
4599 * processing this URB.
4601 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4604 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4605 struct usb_host_endpoint *ep = urb->ep;
4606 struct dwc2_hcd_urb *dwc2_urb;
4609 int alloc_bandwidth = 0;
4613 unsigned long flags;
4615 bool qh_allocated = false;
4616 struct dwc2_qtd *qtd;
4619 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4620 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4626 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4627 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4628 spin_lock_irqsave(&hsotg->lock, flags);
4629 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4630 alloc_bandwidth = 1;
4631 spin_unlock_irqrestore(&hsotg->lock, flags);
4634 switch (usb_pipetype(urb->pipe)) {
4636 ep_type = USB_ENDPOINT_XFER_CONTROL;
4638 case PIPE_ISOCHRONOUS:
4639 ep_type = USB_ENDPOINT_XFER_ISOC;
4642 ep_type = USB_ENDPOINT_XFER_BULK;
4644 case PIPE_INTERRUPT:
4645 ep_type = USB_ENDPOINT_XFER_INT;
4649 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4654 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4655 usb_pipeendpoint(urb->pipe), ep_type,
4656 usb_pipein(urb->pipe),
4657 usb_maxpacket(urb->dev, urb->pipe,
4658 !(usb_pipein(urb->pipe))));
4660 buf = urb->transfer_buffer;
4662 if (hcd->self.uses_dma) {
4663 if (!buf && (urb->transfer_dma & 3)) {
4665 "%s: unaligned transfer with no transfer_buffer",
4672 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4673 tflags |= URB_GIVEBACK_ASAP;
4674 if (urb->transfer_flags & URB_ZERO_PACKET)
4675 tflags |= URB_SEND_ZERO_PACKET;
4677 dwc2_urb->priv = urb;
4678 dwc2_urb->buf = buf;
4679 dwc2_urb->dma = urb->transfer_dma;
4680 dwc2_urb->length = urb->transfer_buffer_length;
4681 dwc2_urb->setup_packet = urb->setup_packet;
4682 dwc2_urb->setup_dma = urb->setup_dma;
4683 dwc2_urb->flags = tflags;
4684 dwc2_urb->interval = urb->interval;
4685 dwc2_urb->status = -EINPROGRESS;
4687 for (i = 0; i < urb->number_of_packets; ++i)
4688 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4689 urb->iso_frame_desc[i].offset,
4690 urb->iso_frame_desc[i].length);
4692 urb->hcpriv = dwc2_urb;
4693 qh = (struct dwc2_qh *)ep->hcpriv;
4694 /* Create QH for the endpoint if it doesn't exist */
4696 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4702 qh_allocated = true;
4705 qtd = kzalloc(sizeof(*qtd), mem_flags);
4711 spin_lock_irqsave(&hsotg->lock, flags);
4712 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4716 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4720 if (alloc_bandwidth) {
4721 dwc2_allocate_bus_bandwidth(hcd,
4722 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4726 spin_unlock_irqrestore(&hsotg->lock, flags);
4731 dwc2_urb->priv = NULL;
4732 usb_hcd_unlink_urb_from_ep(hcd, urb);
4733 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4734 qh->channel->qh = NULL;
4736 spin_unlock_irqrestore(&hsotg->lock, flags);
4742 struct dwc2_qtd *qtd2, *qtd2_tmp;
4745 dwc2_hcd_qh_unlink(hsotg, qh);
4746 /* Free each QTD in the QH's QTD list */
4747 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4749 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4750 dwc2_hcd_qh_free(hsotg, qh);
4759 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4761 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4764 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4766 unsigned long flags;
4768 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4769 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4771 spin_lock_irqsave(&hsotg->lock, flags);
4773 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4778 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4782 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4784 usb_hcd_unlink_urb_from_ep(hcd, urb);
4789 /* Higher layer software sets URB status */
4790 spin_unlock(&hsotg->lock);
4791 usb_hcd_giveback_urb(hcd, urb, status);
4792 spin_lock(&hsotg->lock);
4794 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4795 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4797 spin_unlock_irqrestore(&hsotg->lock, flags);
4803 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4804 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4805 * must already be dequeued.
4807 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4808 struct usb_host_endpoint *ep)
4810 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4813 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4814 ep->desc.bEndpointAddress, ep->hcpriv);
4815 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4819 * Resets endpoint specific parameter values, in current version used to reset
4820 * the data toggle (as a WA). This function can be called from usb_clear_halt
4823 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4824 struct usb_host_endpoint *ep)
4826 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4827 unsigned long flags;
4830 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4831 ep->desc.bEndpointAddress);
4833 spin_lock_irqsave(&hsotg->lock, flags);
4834 dwc2_hcd_endpoint_reset(hsotg, ep);
4835 spin_unlock_irqrestore(&hsotg->lock, flags);
4839 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4840 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4843 * This function is called by the USB core when an interrupt occurs
4845 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4847 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4849 return dwc2_handle_hcd_intr(hsotg);
4853 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4854 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4855 * is the status change indicator for the single root port. Returns 1 if either
4856 * change indicator is 1, otherwise returns 0.
4858 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4860 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4862 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4866 /* Handles hub class-specific requests */
4867 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4868 u16 windex, char *buf, u16 wlength)
4870 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4871 wvalue, windex, buf, wlength);
4875 /* Handles hub TT buffer clear completions */
4876 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4877 struct usb_host_endpoint *ep)
4879 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4881 unsigned long flags;
4887 spin_lock_irqsave(&hsotg->lock, flags);
4888 qh->tt_buffer_dirty = 0;
4890 if (hsotg->flags.b.port_connect_status)
4891 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4893 spin_unlock_irqrestore(&hsotg->lock, flags);
4897 * HPRT0_SPD_HIGH_SPEED: high speed
4898 * HPRT0_SPD_FULL_SPEED: full speed
4900 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4902 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4904 if (hsotg->params.speed == speed)
4907 hsotg->params.speed = speed;
4908 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4911 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4913 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4915 if (!hsotg->params.change_speed_quirk)
4919 * On removal, set speed to default high-speed.
4921 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4922 udev->parent->speed < USB_SPEED_HIGH) {
4923 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4924 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4928 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4930 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4932 if (!hsotg->params.change_speed_quirk)
4935 if (udev->speed == USB_SPEED_HIGH) {
4936 dev_info(hsotg->dev, "Set speed to high-speed\n");
4937 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4938 } else if ((udev->speed == USB_SPEED_FULL ||
4939 udev->speed == USB_SPEED_LOW)) {
4941 * Change speed setting to full-speed if there's
4942 * a full-speed or low-speed device plugged in.
4944 dev_info(hsotg->dev, "Set speed to full-speed\n");
4945 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4951 static struct hc_driver dwc2_hc_driver = {
4952 .description = "dwc2_hsotg",
4953 .product_desc = "DWC OTG Controller",
4954 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4956 .irq = _dwc2_hcd_irq,
4957 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4959 .start = _dwc2_hcd_start,
4960 .stop = _dwc2_hcd_stop,
4961 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4962 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4963 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4964 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4965 .get_frame_number = _dwc2_hcd_get_frame_number,
4967 .hub_status_data = _dwc2_hcd_hub_status_data,
4968 .hub_control = _dwc2_hcd_hub_control,
4969 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4971 .bus_suspend = _dwc2_hcd_suspend,
4972 .bus_resume = _dwc2_hcd_resume,
4974 .map_urb_for_dma = dwc2_map_urb_for_dma,
4975 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
4979 * Frees secondary storage associated with the dwc2_hsotg structure contained
4980 * in the struct usb_hcd field
4982 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4988 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4990 /* Free memory for QH/QTD lists */
4991 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4992 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
4993 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4994 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4995 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4996 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4997 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4999 /* Free memory for the host channels */
5000 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5001 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5004 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5006 hsotg->hc_ptr_array[i] = NULL;
5011 if (hsotg->params.host_dma) {
5012 if (hsotg->status_buf) {
5013 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5015 hsotg->status_buf_dma);
5016 hsotg->status_buf = NULL;
5019 kfree(hsotg->status_buf);
5020 hsotg->status_buf = NULL;
5023 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5025 /* Disable all interrupts */
5026 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5027 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5028 dwc2_writel(0, hsotg->regs + GINTMSK);
5030 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5031 dctl = dwc2_readl(hsotg->regs + DCTL);
5032 dctl |= DCTL_SFTDISCON;
5033 dwc2_writel(dctl, hsotg->regs + DCTL);
5036 if (hsotg->wq_otg) {
5037 if (!cancel_work_sync(&hsotg->wf_otg))
5038 flush_workqueue(hsotg->wq_otg);
5039 destroy_workqueue(hsotg->wq_otg);
5042 del_timer(&hsotg->wkp_timer);
5045 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5047 /* Turn off all host-specific interrupts */
5048 dwc2_disable_host_interrupts(hsotg);
5050 dwc2_hcd_free(hsotg);
5054 * Initializes the HCD. This function allocates memory for and initializes the
5055 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5056 * USB bus with the core and calls the hc_driver->start() function. It returns
5057 * a negative error on failure.
5059 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5061 struct platform_device *pdev = to_platform_device(hsotg->dev);
5062 struct resource *res;
5063 struct usb_hcd *hcd;
5064 struct dwc2_host_chan *channel;
5066 int i, num_channels;
5072 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5076 hcfg = dwc2_readl(hsotg->regs + HCFG);
5077 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5079 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5080 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5081 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5082 if (!hsotg->frame_num_array)
5084 hsotg->last_frame_num_array = kzalloc(
5085 sizeof(*hsotg->last_frame_num_array) *
5086 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5087 if (!hsotg->last_frame_num_array)
5090 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5092 /* Check if the bus driver or platform code has setup a dma_mask */
5093 if (hsotg->params.host_dma &&
5094 !hsotg->dev->dma_mask) {
5095 dev_warn(hsotg->dev,
5096 "dma_mask not set, disabling DMA\n");
5097 hsotg->params.host_dma = false;
5098 hsotg->params.dma_desc_enable = false;
5101 /* Set device flags indicating whether the HCD supports DMA */
5102 if (hsotg->params.host_dma) {
5103 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5104 dev_warn(hsotg->dev, "can't set DMA mask\n");
5105 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5106 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5109 if (hsotg->params.change_speed_quirk) {
5110 dwc2_hc_driver.free_dev = dwc2_free_dev;
5111 dwc2_hc_driver.reset_device = dwc2_reset_device;
5114 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5118 if (!hsotg->params.host_dma)
5119 hcd->self.uses_dma = 0;
5123 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5124 hcd->rsrc_start = res->start;
5125 hcd->rsrc_len = resource_size(res);
5127 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5131 * Disable the global interrupt until all the interrupt handlers are
5134 dwc2_disable_global_interrupts(hsotg);
5136 /* Initialize the DWC_otg core, and select the Phy type */
5137 retval = dwc2_core_init(hsotg, true);
5141 /* Create new workqueue and init work */
5143 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5144 if (!hsotg->wq_otg) {
5145 dev_err(hsotg->dev, "Failed to create workqueue\n");
5148 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5150 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5152 /* Initialize the non-periodic schedule */
5153 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5154 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5155 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5157 /* Initialize the periodic schedule */
5158 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5159 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5160 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5161 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5163 INIT_LIST_HEAD(&hsotg->split_order);
5166 * Create a host channel descriptor for each host channel implemented
5167 * in the controller. Initialize the channel descriptor array.
5169 INIT_LIST_HEAD(&hsotg->free_hc_list);
5170 num_channels = hsotg->params.host_channels;
5171 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5173 for (i = 0; i < num_channels; i++) {
5174 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5177 channel->hc_num = i;
5178 INIT_LIST_HEAD(&channel->split_order_list_entry);
5179 hsotg->hc_ptr_array[i] = channel;
5182 /* Initialize hsotg start work */
5183 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5185 /* Initialize port reset work */
5186 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5189 * Allocate space for storing data on status transactions. Normally no
5190 * data is sent, but this space acts as a bit bucket. This must be
5191 * done after usb_add_hcd since that function allocates the DMA buffer
5194 if (hsotg->params.host_dma)
5195 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5196 DWC2_HCD_STATUS_BUF_SIZE,
5197 &hsotg->status_buf_dma, GFP_KERNEL);
5199 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5202 if (!hsotg->status_buf)
5206 * Create kmem caches to handle descriptor buffers in descriptor
5208 * Alignment must be set to 512 bytes.
5210 if (hsotg->params.dma_desc_enable ||
5211 hsotg->params.dma_desc_fs_enable) {
5212 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5213 sizeof(struct dwc2_dma_desc) *
5214 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5216 if (!hsotg->desc_gen_cache) {
5218 "unable to create dwc2 generic desc cache\n");
5221 * Disable descriptor dma mode since it will not be
5224 hsotg->params.dma_desc_enable = false;
5225 hsotg->params.dma_desc_fs_enable = false;
5228 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5229 sizeof(struct dwc2_dma_desc) *
5230 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5231 if (!hsotg->desc_hsisoc_cache) {
5233 "unable to create dwc2 hs isoc desc cache\n");
5235 kmem_cache_destroy(hsotg->desc_gen_cache);
5238 * Disable descriptor dma mode since it will not be
5241 hsotg->params.dma_desc_enable = false;
5242 hsotg->params.dma_desc_fs_enable = false;
5246 hsotg->otg_port = 1;
5247 hsotg->frame_list = NULL;
5248 hsotg->frame_list_dma = 0;
5249 hsotg->periodic_qh_count = 0;
5251 /* Initiate lx_state to L3 disconnected state */
5252 hsotg->lx_state = DWC2_L3;
5254 hcd->self.otg_port = hsotg->otg_port;
5256 /* Don't support SG list at this point */
5257 hcd->self.sg_tablesize = 0;
5259 if (!IS_ERR_OR_NULL(hsotg->uphy))
5260 otg_set_host(hsotg->uphy->otg, &hcd->self);
5263 * Finish generic HCD initialization and start the HCD. This function
5264 * allocates the DMA buffer pool, registers the USB bus, requests the
5265 * IRQ line, and calls hcd_start method.
5267 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5271 device_wakeup_enable(hcd->self.controller);
5273 dwc2_hcd_dump_state(hsotg);
5275 dwc2_enable_global_interrupts(hsotg);
5280 kmem_cache_destroy(hsotg->desc_gen_cache);
5281 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5283 dwc2_hcd_release(hsotg);
5288 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5289 kfree(hsotg->last_frame_num_array);
5290 kfree(hsotg->frame_num_array);
5293 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5299 * Frees memory and resources associated with the HCD and deregisters the bus.
5301 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5303 struct usb_hcd *hcd;
5305 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5307 hcd = dwc2_hsotg_to_hcd(hsotg);
5308 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5311 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5316 if (!IS_ERR_OR_NULL(hsotg->uphy))
5317 otg_set_host(hsotg->uphy->otg, NULL);
5319 usb_remove_hcd(hcd);
5322 kmem_cache_destroy(hsotg->desc_gen_cache);
5323 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5325 dwc2_hcd_release(hsotg);
5328 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5329 kfree(hsotg->last_frame_num_array);
5330 kfree(hsotg->frame_num_array);
5335 * dwc2_backup_host_registers() - Backup controller host registers.
5336 * When suspending usb bus, registers needs to be backuped
5337 * if controller power is disabled once suspended.
5339 * @hsotg: Programming view of the DWC_otg controller
5341 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5343 struct dwc2_hregs_backup *hr;
5346 dev_dbg(hsotg->dev, "%s\n", __func__);
5348 /* Backup Host regs */
5349 hr = &hsotg->hr_backup;
5350 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5351 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5352 for (i = 0; i < hsotg->params.host_channels; ++i)
5353 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5355 hr->hprt0 = dwc2_read_hprt0(hsotg);
5356 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5357 hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
5364 * dwc2_restore_host_registers() - Restore controller host registers.
5365 * When resuming usb bus, device registers needs to be restored
5366 * if controller power were disabled.
5368 * @hsotg: Programming view of the DWC_otg controller
5370 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5372 struct dwc2_hregs_backup *hr;
5375 dev_dbg(hsotg->dev, "%s\n", __func__);
5377 /* Restore host regs */
5378 hr = &hsotg->hr_backup;
5380 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5386 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5387 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5389 for (i = 0; i < hsotg->params.host_channels; ++i)
5390 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5392 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5393 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5394 dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ);
5395 hsotg->frame_number = 0;
5401 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5403 * @hsotg: Programming view of the DWC_otg controller
5405 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5407 unsigned long flags;
5414 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5415 ret = dwc2_backup_global_registers(hsotg);
5417 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5421 ret = dwc2_backup_host_registers(hsotg);
5423 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5428 /* Enter USB Suspend Mode */
5429 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5430 hprt0 |= HPRT0_SUSP;
5431 hprt0 &= ~HPRT0_ENA;
5432 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5434 /* Wait for the HPRT0.PrtSusp register field to be set */
5435 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 300))
5436 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5439 * We need to disable interrupts to prevent servicing of any IRQ
5440 * during going to hibernation
5442 spin_lock_irqsave(&hsotg->lock, flags);
5443 hsotg->lx_state = DWC2_L2;
5445 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
5446 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5447 /* ULPI interface */
5448 /* Suspend the Phy Clock */
5449 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5450 pcgcctl |= PCGCTL_STOPPCLK;
5451 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5454 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5455 gpwrdn |= GPWRDN_PMUACTV;
5456 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5459 /* UTMI+ Interface */
5460 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5461 gpwrdn |= GPWRDN_PMUACTV;
5462 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5465 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5466 pcgcctl |= PCGCTL_STOPPCLK;
5467 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5471 /* Enable interrupts from wake up logic */
5472 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5473 gpwrdn |= GPWRDN_PMUINTSEL;
5474 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5477 /* Unmask host mode interrupts in GPWRDN */
5478 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5479 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5480 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5481 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5482 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5485 /* Enable Power Down Clamp */
5486 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5487 gpwrdn |= GPWRDN_PWRDNCLMP;
5488 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5491 /* Switch off VDD */
5492 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5493 gpwrdn |= GPWRDN_PWRDNSWTCH;
5494 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5496 hsotg->hibernated = 1;
5497 hsotg->bus_suspended = 1;
5498 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5499 spin_unlock_irqrestore(&hsotg->lock, flags);
5504 * dwc2_host_exit_hibernation()
5506 * @hsotg: Programming view of the DWC_otg controller
5507 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5508 * @param reset: indicates whether resume is initiated by Reset.
5510 * Return: non-zero if failed to enter to hibernation.
5512 * This function is for exiting from Host mode hibernation by
5513 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5515 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5521 struct dwc2_gregs_backup *gr;
5522 struct dwc2_hregs_backup *hr;
5524 gr = &hsotg->gr_backup;
5525 hr = &hsotg->hr_backup;
5528 "%s: called with rem_wakeup = %d reset = %d\n",
5529 __func__, rem_wakeup, reset);
5531 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5532 hsotg->hibernated = 0;
5535 * This step is not described in functional spec but if not wait for
5536 * this delay, mismatch interrupts occurred because just after restore
5537 * core is in Device mode(gintsts.curmode == 0)
5541 /* Clear all pending interupts */
5542 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5544 /* De-assert Restore */
5545 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5546 gpwrdn &= ~GPWRDN_RESTORE;
5547 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5550 /* Restore GUSBCFG, HCFG */
5551 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5552 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5554 /* De-assert Wakeup Logic */
5555 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5556 gpwrdn &= ~GPWRDN_PMUACTV;
5557 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5562 hprt0 &= ~HPRT0_ENA;
5563 hprt0 &= ~HPRT0_SUSP;
5564 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5568 hprt0 &= ~HPRT0_ENA;
5569 hprt0 &= ~HPRT0_SUSP;
5573 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5575 /* Wait for Resume time and then program HPRT again */
5577 hprt0 &= ~HPRT0_RST;
5578 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5581 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5583 /* Wait for Resume time and then program HPRT again */
5585 hprt0 &= ~HPRT0_RES;
5586 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5588 /* Clear all interrupt status */
5589 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5590 hprt0 |= HPRT0_CONNDET;
5591 hprt0 |= HPRT0_ENACHG;
5592 hprt0 &= ~HPRT0_ENA;
5593 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5595 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5597 /* Clear all pending interupts */
5598 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5600 /* Restore global registers */
5601 ret = dwc2_restore_global_registers(hsotg);
5603 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5608 /* Restore host registers */
5609 ret = dwc2_restore_host_registers(hsotg);
5611 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5616 hsotg->hibernated = 0;
5617 hsotg->bus_suspended = 0;
5618 hsotg->lx_state = DWC2_L0;
5619 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");