1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
34 /* conversion functions */
35 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
37 return container_of(req, struct dwc2_hsotg_req, req);
40 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
42 return container_of(ep, struct dwc2_hsotg_ep, ep);
45 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
47 return container_of(gadget, struct dwc2_hsotg, gadget);
50 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
52 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
55 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
57 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
60 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
61 u32 ep_index, u32 dir_in)
64 return hsotg->eps_in[ep_index];
66 return hsotg->eps_out[ep_index];
69 /* forward declaration of functions */
70 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
76 * Return true if we're using DMA.
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
89 * g_using_dma is set depending on dts flag.
91 static inline bool using_dma(struct dwc2_hsotg *hsotg)
93 return hsotg->params.g_dma;
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
100 * Return true if we're using descriptor DMA.
102 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
104 return hsotg->params.g_dma_desc;
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
111 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
112 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
114 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116 hs_ep->target_frame += hs_ep->interval;
117 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
118 hs_ep->frame_overrun = true;
119 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
121 hs_ep->frame_overrun = false;
126 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
127 * @hsotg: The device state
128 * @ints: A bitmask of the interrupts to enable
130 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
132 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
135 new_gsintmsk = gsintmsk | ints;
137 if (new_gsintmsk != gsintmsk) {
138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
139 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
144 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
145 * @hsotg: The device state
146 * @ints: A bitmask of the interrupts to enable
148 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
150 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
153 new_gsintmsk = gsintmsk & ~ints;
155 if (new_gsintmsk != gsintmsk)
156 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
160 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
161 * @hsotg: The device state
162 * @ep: The endpoint index
163 * @dir_in: True if direction is in.
164 * @en: The enable value, true to enable
166 * Set or clear the mask for an individual endpoint's interrupt
169 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
170 unsigned int ep, unsigned int dir_in,
180 local_irq_save(flags);
181 daint = dwc2_readl(hsotg, DAINTMSK);
186 dwc2_writel(hsotg, daint, DAINTMSK);
187 local_irq_restore(flags);
191 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
193 * @hsotg: Programming view of the DWC_otg controller
195 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
197 if (hsotg->hw_params.en_multiple_tx_fifo)
198 /* In dedicated FIFO mode we need count of IN EPs */
199 return hsotg->hw_params.num_dev_in_eps;
201 /* In shared FIFO mode we need count of Periodic IN EPs */
202 return hsotg->hw_params.num_dev_perio_in_ep;
206 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
207 * device mode TX FIFOs
209 * @hsotg: Programming view of the DWC_otg controller
211 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
217 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
218 hsotg->params.g_np_tx_fifo_size);
220 /* Get Endpoint Info Control block size in DWORDs. */
221 tx_addr_max = hsotg->hw_params.total_fifo_size;
223 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
224 if (tx_addr_max <= addr)
227 return tx_addr_max - addr;
231 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
234 * @hsotg: Programming view of the DWC_otg controller
236 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
241 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
243 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
246 return tx_fifo_depth;
248 return tx_fifo_depth / tx_fifo_count;
252 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
253 * @hsotg: The device instance.
255 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
262 u32 *txfsz = hsotg->params.g_tx_fifo_size;
264 /* Reset fifo map if not correctly cleared during previous session */
265 WARN_ON(hsotg->fifo_map);
268 /* set RX/NPTX FIFO sizes */
269 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
270 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
271 FIFOSIZE_STARTADDR_SHIFT) |
272 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
276 * arange all the rest of the TX FIFOs, as some versions of this
277 * block have overlapping default addresses. This also ensures
278 * that if the settings have been changed, then they are set to
282 /* start at the end of the GNPTXFSIZ, rounded up */
283 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
286 * Configure fifos sizes from provided configuration and assign
287 * them to endpoints dynamically according to maxpacket size value of
290 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
294 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
295 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
296 "insufficient fifo memory");
299 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
300 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
303 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
304 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
307 * according to p428 of the design guide, we need to ensure that
308 * all fifos are flushed before continuing
311 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
312 GRSTCTL_RXFFLSH, GRSTCTL);
314 /* wait until the fifos are both flushed */
317 val = dwc2_readl(hsotg, GRSTCTL);
319 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
322 if (--timeout == 0) {
324 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
332 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
336 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
337 * @ep: USB endpoint to allocate request for.
338 * @flags: Allocation flags
340 * Allocate a new USB request structure appropriate for the specified endpoint
342 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
345 struct dwc2_hsotg_req *req;
347 req = kzalloc(sizeof(*req), flags);
351 INIT_LIST_HEAD(&req->queue);
357 * is_ep_periodic - return true if the endpoint is in periodic mode.
358 * @hs_ep: The endpoint to query.
360 * Returns true if the endpoint is in periodic mode, meaning it is being
361 * used for an Interrupt or ISO transfer.
363 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
365 return hs_ep->periodic;
369 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
370 * @hsotg: The device state.
371 * @hs_ep: The endpoint for the request
372 * @hs_req: The request being processed.
374 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
375 * of a request to ensure the buffer is ready for access by the caller.
377 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
378 struct dwc2_hsotg_ep *hs_ep,
379 struct dwc2_hsotg_req *hs_req)
381 struct usb_request *req = &hs_req->req;
383 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
387 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
388 * for Control endpoint
389 * @hsotg: The device state.
391 * This function will allocate 4 descriptor chains for EP 0: 2 for
392 * Setup stage, per one for IN and OUT data/status transactions.
394 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
396 hsotg->setup_desc[0] =
397 dmam_alloc_coherent(hsotg->dev,
398 sizeof(struct dwc2_dma_desc),
399 &hsotg->setup_desc_dma[0],
401 if (!hsotg->setup_desc[0])
404 hsotg->setup_desc[1] =
405 dmam_alloc_coherent(hsotg->dev,
406 sizeof(struct dwc2_dma_desc),
407 &hsotg->setup_desc_dma[1],
409 if (!hsotg->setup_desc[1])
412 hsotg->ctrl_in_desc =
413 dmam_alloc_coherent(hsotg->dev,
414 sizeof(struct dwc2_dma_desc),
415 &hsotg->ctrl_in_desc_dma,
417 if (!hsotg->ctrl_in_desc)
420 hsotg->ctrl_out_desc =
421 dmam_alloc_coherent(hsotg->dev,
422 sizeof(struct dwc2_dma_desc),
423 &hsotg->ctrl_out_desc_dma,
425 if (!hsotg->ctrl_out_desc)
435 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
436 * @hsotg: The controller state.
437 * @hs_ep: The endpoint we're going to write for.
438 * @hs_req: The request to write data for.
440 * This is called when the TxFIFO has some space in it to hold a new
441 * transmission and we have something to give it. The actual setup of
442 * the data size is done elsewhere, so all we have to do is to actually
445 * The return value is zero if there is more space (or nothing was done)
446 * otherwise -ENOSPC is returned if the FIFO space was used up.
448 * This routine is only needed for PIO
450 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
451 struct dwc2_hsotg_ep *hs_ep,
452 struct dwc2_hsotg_req *hs_req)
454 bool periodic = is_ep_periodic(hs_ep);
455 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
456 int buf_pos = hs_req->req.actual;
457 int to_write = hs_ep->size_loaded;
463 to_write -= (buf_pos - hs_ep->last_load);
465 /* if there's nothing to write, get out early */
469 if (periodic && !hsotg->dedicated_fifos) {
470 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
475 * work out how much data was loaded so we can calculate
476 * how much data is left in the fifo.
479 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
482 * if shared fifo, we cannot write anything until the
483 * previous data has been completely sent.
485 if (hs_ep->fifo_load != 0) {
486 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
490 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
492 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
494 /* how much of the data has moved */
495 size_done = hs_ep->size_loaded - size_left;
497 /* how much data is left in the fifo */
498 can_write = hs_ep->fifo_load - size_done;
499 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
500 __func__, can_write);
502 can_write = hs_ep->fifo_size - can_write;
503 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
504 __func__, can_write);
506 if (can_write <= 0) {
507 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
510 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
511 can_write = dwc2_readl(hsotg,
512 DTXFSTS(hs_ep->fifo_index));
517 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
519 "%s: no queue slots available (0x%08x)\n",
522 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
526 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
527 can_write *= 4; /* fifo size is in 32bit quantities. */
530 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
532 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
533 __func__, gnptxsts, can_write, to_write, max_transfer);
536 * limit to 512 bytes of data, it seems at least on the non-periodic
537 * FIFO, requests of >512 cause the endpoint to get stuck with a
538 * fragment of the end of the transfer in it.
540 if (can_write > 512 && !periodic)
544 * limit the write to one max-packet size worth of data, but allow
545 * the transfer to return that it did not run out of fifo space
548 if (to_write > max_transfer) {
549 to_write = max_transfer;
551 /* it's needed only when we do not use dedicated fifos */
552 if (!hsotg->dedicated_fifos)
553 dwc2_hsotg_en_gsint(hsotg,
554 periodic ? GINTSTS_PTXFEMP :
558 /* see if we can write data */
560 if (to_write > can_write) {
561 to_write = can_write;
562 pkt_round = to_write % max_transfer;
565 * Round the write down to an
566 * exact number of packets.
568 * Note, we do not currently check to see if we can ever
569 * write a full packet or not to the FIFO.
573 to_write -= pkt_round;
576 * enable correct FIFO interrupt to alert us when there
580 /* it's needed only when we do not use dedicated fifos */
581 if (!hsotg->dedicated_fifos)
582 dwc2_hsotg_en_gsint(hsotg,
583 periodic ? GINTSTS_PTXFEMP :
587 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
588 to_write, hs_req->req.length, can_write, buf_pos);
593 hs_req->req.actual = buf_pos + to_write;
594 hs_ep->total_data += to_write;
597 hs_ep->fifo_load += to_write;
599 to_write = DIV_ROUND_UP(to_write, 4);
600 data = hs_req->req.buf + buf_pos;
602 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
604 return (to_write >= can_write) ? -ENOSPC : 0;
608 * get_ep_limit - get the maximum data legnth for this endpoint
609 * @hs_ep: The endpoint
611 * Return the maximum data that can be queued in one go on a given endpoint
612 * so that transfers that are too long can be split.
614 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
616 int index = hs_ep->index;
617 unsigned int maxsize;
621 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
622 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
626 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
631 /* we made the constant loading easier above by using +1 */
636 * constrain by packet count if maxpkts*pktsize is greater
637 * than the length register size.
640 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
641 maxsize = maxpkt * hs_ep->ep.maxpacket;
647 * dwc2_hsotg_read_frameno - read current frame number
648 * @hsotg: The device instance
650 * Return the current frame number
652 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
656 dsts = dwc2_readl(hsotg, DSTS);
657 dsts &= DSTS_SOFFN_MASK;
658 dsts >>= DSTS_SOFFN_SHIFT;
664 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
665 * DMA descriptor chain prepared for specific endpoint
666 * @hs_ep: The endpoint
668 * Return the maximum data that can be queued in one go on a given endpoint
669 * depending on its descriptor chain capacity so that transfers that
670 * are too long can be split.
672 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
674 int is_isoc = hs_ep->isochronous;
675 unsigned int maxsize;
678 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
679 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
681 maxsize = DEV_DMA_NBYTES_LIMIT;
683 /* Above size of one descriptor was chosen, multiple it */
684 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
690 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
691 * @hs_ep: The endpoint
692 * @mask: RX/TX bytes mask to be defined
694 * Returns maximum data payload for one descriptor after analyzing endpoint
696 * DMA descriptor transfer bytes limit depends on EP type:
698 * Isochronous - descriptor rx/tx bytes bitfield limit,
699 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
700 * have concatenations from various descriptors within one packet.
702 * Selects corresponding mask for RX/TX bytes as well.
704 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
706 u32 mps = hs_ep->ep.maxpacket;
707 int dir_in = hs_ep->dir_in;
710 if (!hs_ep->index && !dir_in) {
712 *mask = DEV_DMA_NBYTES_MASK;
713 } else if (hs_ep->isochronous) {
715 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
716 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
718 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
719 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
722 desc_size = DEV_DMA_NBYTES_LIMIT;
723 *mask = DEV_DMA_NBYTES_MASK;
725 /* Round down desc_size to be mps multiple */
726 desc_size -= desc_size % mps;
733 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
734 * @hs_ep: The endpoint
735 * @dma_buff: DMA address to use
736 * @len: Length of the transfer
738 * This function will iterate over descriptor chain and fill its entries
739 * with corresponding information based on transfer data.
741 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
745 struct dwc2_hsotg *hsotg = hs_ep->parent;
746 int dir_in = hs_ep->dir_in;
747 struct dwc2_dma_desc *desc = hs_ep->desc_list;
748 u32 mps = hs_ep->ep.maxpacket;
754 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
756 hs_ep->desc_count = (len / maxsize) +
757 ((len % maxsize) ? 1 : 0);
759 hs_ep->desc_count = 1;
761 for (i = 0; i < hs_ep->desc_count; ++i) {
763 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
764 << DEV_DMA_BUFF_STS_SHIFT);
767 if (!hs_ep->index && !dir_in)
768 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
770 desc->status |= (maxsize <<
771 DEV_DMA_NBYTES_SHIFT & mask);
772 desc->buf = dma_buff + offset;
777 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
780 desc->status |= (len % mps) ? DEV_DMA_SHORT :
781 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
783 dev_err(hsotg->dev, "wrong len %d\n", len);
786 len << DEV_DMA_NBYTES_SHIFT & mask;
787 desc->buf = dma_buff + offset;
790 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
791 desc->status |= (DEV_DMA_BUFF_STS_HREADY
792 << DEV_DMA_BUFF_STS_SHIFT);
798 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
799 * @hs_ep: The isochronous endpoint.
800 * @dma_buff: usb requests dma buffer.
801 * @len: usb request transfer length.
803 * Fills next free descriptor with the data of the arrived usb request,
804 * frame info, sets Last and IOC bits increments next_desc. If filled
805 * descriptor is not the first one, removes L bit from the previous descriptor
808 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
809 dma_addr_t dma_buff, unsigned int len)
811 struct dwc2_dma_desc *desc;
812 struct dwc2_hsotg *hsotg = hs_ep->parent;
818 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
820 index = hs_ep->next_desc;
821 desc = &hs_ep->desc_list[index];
823 /* Check if descriptor chain full */
824 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
825 DEV_DMA_BUFF_STS_HREADY) {
826 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
830 /* Clear L bit of previous desc if more than one entries in the chain */
831 if (hs_ep->next_desc)
832 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
834 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
835 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
838 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
840 desc->buf = dma_buff;
841 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
842 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
846 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
849 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
850 DEV_DMA_ISOC_PID_MASK) |
851 ((len % hs_ep->ep.maxpacket) ?
853 ((hs_ep->target_frame <<
854 DEV_DMA_ISOC_FRNUM_SHIFT) &
855 DEV_DMA_ISOC_FRNUM_MASK);
858 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
859 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
861 /* Increment frame number by interval for IN */
863 dwc2_gadget_incr_frame_num(hs_ep);
865 /* Update index of last configured entry in the chain */
867 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC)
868 hs_ep->next_desc = 0;
874 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
875 * @hs_ep: The isochronous endpoint.
877 * Prepare descriptor chain for isochronous endpoints. Afterwards
878 * write DMA address to HW and enable the endpoint.
880 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
882 struct dwc2_hsotg *hsotg = hs_ep->parent;
883 struct dwc2_hsotg_req *hs_req, *treq;
884 int index = hs_ep->index;
890 struct dwc2_dma_desc *desc;
892 if (list_empty(&hs_ep->queue)) {
893 hs_ep->target_frame = TARGET_FRAME_INITIAL;
894 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
898 /* Initialize descriptor chain by Host Busy status */
899 for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) {
900 desc = &hs_ep->desc_list[i];
902 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
903 << DEV_DMA_BUFF_STS_SHIFT);
906 hs_ep->next_desc = 0;
907 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
908 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
914 hs_ep->compl_desc = 0;
915 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
916 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
918 /* write descriptor chain address to control register */
919 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
921 ctrl = dwc2_readl(hsotg, depctl);
922 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
923 dwc2_writel(hsotg, ctrl, depctl);
927 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
928 * @hsotg: The controller state.
929 * @hs_ep: The endpoint to process a request for
930 * @hs_req: The request to start.
931 * @continuing: True if we are doing more for the current request.
933 * Start the given request running by setting the endpoint registers
934 * appropriately, and writing any data to the FIFOs.
936 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
937 struct dwc2_hsotg_ep *hs_ep,
938 struct dwc2_hsotg_req *hs_req,
941 struct usb_request *ureq = &hs_req->req;
942 int index = hs_ep->index;
943 int dir_in = hs_ep->dir_in;
949 unsigned int packets;
951 unsigned int dma_reg;
954 if (hs_ep->req && !continuing) {
955 dev_err(hsotg->dev, "%s: active request\n", __func__);
958 } else if (hs_ep->req != hs_req && continuing) {
960 "%s: continue different req\n", __func__);
966 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
967 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
968 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
970 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
971 __func__, dwc2_readl(hsotg, epctrl_reg), index,
972 hs_ep->dir_in ? "in" : "out");
974 /* If endpoint is stalled, we will restart request later */
975 ctrl = dwc2_readl(hsotg, epctrl_reg);
977 if (index && ctrl & DXEPCTL_STALL) {
978 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
982 length = ureq->length - ureq->actual;
983 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
984 ureq->length, ureq->actual);
986 if (!using_desc_dma(hsotg))
987 maxreq = get_ep_limit(hs_ep);
989 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
991 if (length > maxreq) {
992 int round = maxreq % hs_ep->ep.maxpacket;
994 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
995 __func__, length, maxreq, round);
997 /* round down to multiple of packets */
1005 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1007 packets = 1; /* send one packet if length is zero. */
1009 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1010 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1014 if (dir_in && index != 0)
1015 if (hs_ep->isochronous)
1016 epsize = DXEPTSIZ_MC(packets);
1018 epsize = DXEPTSIZ_MC(1);
1023 * zero length packet should be programmed on its own and should not
1024 * be counted in DIEPTSIZ.PktCnt with other packets.
1026 if (dir_in && ureq->zero && !continuing) {
1027 /* Test if zlp is actually required. */
1028 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1029 !(ureq->length % hs_ep->ep.maxpacket))
1030 hs_ep->send_zlp = 1;
1033 epsize |= DXEPTSIZ_PKTCNT(packets);
1034 epsize |= DXEPTSIZ_XFERSIZE(length);
1036 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1037 __func__, packets, length, ureq->length, epsize, epsize_reg);
1039 /* store the request as the current one we're doing */
1040 hs_ep->req = hs_req;
1042 if (using_desc_dma(hsotg)) {
1044 u32 mps = hs_ep->ep.maxpacket;
1046 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1050 else if (length % mps)
1051 length += (mps - (length % mps));
1055 * If more data to send, adjust DMA for EP0 out data stage.
1056 * ureq->dma stays unchanged, hence increment it by already
1057 * passed passed data count before starting new transaction.
1059 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1061 offset = ureq->actual;
1063 /* Fill DDMA chain entries */
1064 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1067 /* write descriptor chain address to control register */
1068 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1070 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1071 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1073 /* write size / packets */
1074 dwc2_writel(hsotg, epsize, epsize_reg);
1076 if (using_dma(hsotg) && !continuing && (length != 0)) {
1078 * write DMA address to control register, buffer
1079 * already synced by dwc2_hsotg_ep_queue().
1082 dwc2_writel(hsotg, ureq->dma, dma_reg);
1084 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1085 __func__, &ureq->dma, dma_reg);
1089 if (hs_ep->isochronous && hs_ep->interval == 1) {
1090 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1091 dwc2_gadget_incr_frame_num(hs_ep);
1093 if (hs_ep->target_frame & 0x1)
1094 ctrl |= DXEPCTL_SETODDFR;
1096 ctrl |= DXEPCTL_SETEVENFR;
1099 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1101 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1103 /* For Setup request do not clear NAK */
1104 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1105 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1107 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1108 dwc2_writel(hsotg, ctrl, epctrl_reg);
1111 * set these, it seems that DMA support increments past the end
1112 * of the packet buffer so we need to calculate the length from
1115 hs_ep->size_loaded = length;
1116 hs_ep->last_load = ureq->actual;
1118 if (dir_in && !using_dma(hsotg)) {
1119 /* set these anyway, we may need them for non-periodic in */
1120 hs_ep->fifo_load = 0;
1122 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1126 * Note, trying to clear the NAK here causes problems with transmit
1127 * on the S3C6400 ending up with the TXFIFO becoming full.
1130 /* check ep is enabled */
1131 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1133 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1134 index, dwc2_readl(hsotg, epctrl_reg));
1136 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1137 __func__, dwc2_readl(hsotg, epctrl_reg));
1139 /* enable ep interrupts */
1140 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1144 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1145 * @hsotg: The device state.
1146 * @hs_ep: The endpoint the request is on.
1147 * @req: The request being processed.
1149 * We've been asked to queue a request, so ensure that the memory buffer
1150 * is correctly setup for DMA. If we've been passed an extant DMA address
1151 * then ensure the buffer has been synced to memory. If our buffer has no
1152 * DMA memory, then we map the memory and mark our request to allow us to
1153 * cleanup on completion.
1155 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1156 struct dwc2_hsotg_ep *hs_ep,
1157 struct usb_request *req)
1161 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1168 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1169 __func__, req->buf, req->length);
1174 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1175 struct dwc2_hsotg_ep *hs_ep,
1176 struct dwc2_hsotg_req *hs_req)
1178 void *req_buf = hs_req->req.buf;
1180 /* If dma is not being used or buffer is aligned */
1181 if (!using_dma(hsotg) || !((long)req_buf & 3))
1184 WARN_ON(hs_req->saved_req_buf);
1186 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1187 hs_ep->ep.name, req_buf, hs_req->req.length);
1189 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1190 if (!hs_req->req.buf) {
1191 hs_req->req.buf = req_buf;
1193 "%s: unable to allocate memory for bounce buffer\n",
1198 /* Save actual buffer */
1199 hs_req->saved_req_buf = req_buf;
1202 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1207 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1208 struct dwc2_hsotg_ep *hs_ep,
1209 struct dwc2_hsotg_req *hs_req)
1211 /* If dma is not being used or buffer was aligned */
1212 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1215 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1216 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1218 /* Copy data from bounce buffer on successful out transfer */
1219 if (!hs_ep->dir_in && !hs_req->req.status)
1220 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1221 hs_req->req.actual);
1223 /* Free bounce buffer */
1224 kfree(hs_req->req.buf);
1226 hs_req->req.buf = hs_req->saved_req_buf;
1227 hs_req->saved_req_buf = NULL;
1231 * dwc2_gadget_target_frame_elapsed - Checks target frame
1232 * @hs_ep: The driver endpoint to check
1234 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1235 * corresponding transfer.
1237 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1239 struct dwc2_hsotg *hsotg = hs_ep->parent;
1240 u32 target_frame = hs_ep->target_frame;
1241 u32 current_frame = hsotg->frame_number;
1242 bool frame_overrun = hs_ep->frame_overrun;
1244 if (!frame_overrun && current_frame >= target_frame)
1247 if (frame_overrun && current_frame >= target_frame &&
1248 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1255 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1256 * @hsotg: The driver state
1257 * @hs_ep: the ep descriptor chain is for
1259 * Called to update EP0 structure's pointers depend on stage of
1262 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1263 struct dwc2_hsotg_ep *hs_ep)
1265 switch (hsotg->ep0_state) {
1266 case DWC2_EP0_SETUP:
1267 case DWC2_EP0_STATUS_OUT:
1268 hs_ep->desc_list = hsotg->setup_desc[0];
1269 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1271 case DWC2_EP0_DATA_IN:
1272 case DWC2_EP0_STATUS_IN:
1273 hs_ep->desc_list = hsotg->ctrl_in_desc;
1274 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1276 case DWC2_EP0_DATA_OUT:
1277 hs_ep->desc_list = hsotg->ctrl_out_desc;
1278 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1281 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1289 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1292 struct dwc2_hsotg_req *hs_req = our_req(req);
1293 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1294 struct dwc2_hsotg *hs = hs_ep->parent;
1301 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1302 ep->name, req, req->length, req->buf, req->no_interrupt,
1303 req->zero, req->short_not_ok);
1305 /* Prevent new request submission when controller is suspended */
1306 if (hs->lx_state != DWC2_L0) {
1307 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1312 /* initialise status of the request */
1313 INIT_LIST_HEAD(&hs_req->queue);
1315 req->status = -EINPROGRESS;
1317 /* In DDMA mode for ISOC's don't queue request if length greater
1318 * than descriptor limits.
1320 if (using_desc_dma(hs) && hs_ep->isochronous) {
1321 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1322 if (hs_ep->dir_in && req->length > maxsize) {
1323 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1324 req->length, maxsize);
1328 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1329 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1330 req->length, hs_ep->ep.maxpacket);
1335 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1339 /* if we're using DMA, sync the buffers as necessary */
1340 if (using_dma(hs)) {
1341 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1345 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1346 if (using_desc_dma(hs) && !hs_ep->index) {
1347 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1352 first = list_empty(&hs_ep->queue);
1353 list_add_tail(&hs_req->queue, &hs_ep->queue);
1356 * Handle DDMA isochronous transfers separately - just add new entry
1357 * to the descriptor chain.
1358 * Transfer will be started once SW gets either one of NAK or
1359 * OutTknEpDis interrupts.
1361 if (using_desc_dma(hs) && hs_ep->isochronous) {
1362 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1363 dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1364 hs_req->req.length);
1370 if (!hs_ep->isochronous) {
1371 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1375 /* Update current frame number value. */
1376 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1377 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1378 dwc2_gadget_incr_frame_num(hs_ep);
1379 /* Update current frame number value once more as it
1382 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1385 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1386 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1391 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1394 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1395 struct dwc2_hsotg *hs = hs_ep->parent;
1396 unsigned long flags = 0;
1399 spin_lock_irqsave(&hs->lock, flags);
1400 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1401 spin_unlock_irqrestore(&hs->lock, flags);
1406 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1407 struct usb_request *req)
1409 struct dwc2_hsotg_req *hs_req = our_req(req);
1415 * dwc2_hsotg_complete_oursetup - setup completion callback
1416 * @ep: The endpoint the request was on.
1417 * @req: The request completed.
1419 * Called on completion of any requests the driver itself
1420 * submitted that need cleaning up.
1422 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1423 struct usb_request *req)
1425 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1426 struct dwc2_hsotg *hsotg = hs_ep->parent;
1428 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1430 dwc2_hsotg_ep_free_request(ep, req);
1434 * ep_from_windex - convert control wIndex value to endpoint
1435 * @hsotg: The driver state.
1436 * @windex: The control request wIndex field (in host order).
1438 * Convert the given wIndex into a pointer to an driver endpoint
1439 * structure, or return NULL if it is not a valid endpoint.
1441 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1444 struct dwc2_hsotg_ep *ep;
1445 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1446 int idx = windex & 0x7F;
1448 if (windex >= 0x100)
1451 if (idx > hsotg->num_of_eps)
1454 ep = index_to_ep(hsotg, idx, dir);
1456 if (idx && ep->dir_in != dir)
1463 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1464 * @hsotg: The driver state.
1465 * @testmode: requested usb test mode
1466 * Enable usb Test Mode requested by the Host.
1468 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1470 int dctl = dwc2_readl(hsotg, DCTL);
1472 dctl &= ~DCTL_TSTCTL_MASK;
1479 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1484 dwc2_writel(hsotg, dctl, DCTL);
1489 * dwc2_hsotg_send_reply - send reply to control request
1490 * @hsotg: The device state
1492 * @buff: Buffer for request
1493 * @length: Length of reply.
1495 * Create a request and queue it on the given endpoint. This is useful as
1496 * an internal method of sending replies to certain control requests, etc.
1498 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1499 struct dwc2_hsotg_ep *ep,
1503 struct usb_request *req;
1506 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1508 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1509 hsotg->ep0_reply = req;
1511 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1515 req->buf = hsotg->ep0_buff;
1516 req->length = length;
1518 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1522 req->complete = dwc2_hsotg_complete_oursetup;
1525 memcpy(req->buf, buff, length);
1527 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1529 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1537 * dwc2_hsotg_process_req_status - process request GET_STATUS
1538 * @hsotg: The device state
1539 * @ctrl: USB control request
1541 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1542 struct usb_ctrlrequest *ctrl)
1544 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1545 struct dwc2_hsotg_ep *ep;
1549 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1552 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1556 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1557 case USB_RECIP_DEVICE:
1559 * bit 0 => self powered
1560 * bit 1 => remote wakeup
1562 reply = cpu_to_le16(0);
1565 case USB_RECIP_INTERFACE:
1566 /* currently, the data result should be zero */
1567 reply = cpu_to_le16(0);
1570 case USB_RECIP_ENDPOINT:
1571 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1575 reply = cpu_to_le16(ep->halted ? 1 : 0);
1582 if (le16_to_cpu(ctrl->wLength) != 2)
1585 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1587 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1594 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1597 * get_ep_head - return the first request on the endpoint
1598 * @hs_ep: The controller endpoint to get
1600 * Get the first request on the endpoint.
1602 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1604 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1609 * dwc2_gadget_start_next_request - Starts next request from ep queue
1610 * @hs_ep: Endpoint structure
1612 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1613 * in its handler. Hence we need to unmask it here to be able to do
1614 * resynchronization.
1616 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1619 struct dwc2_hsotg *hsotg = hs_ep->parent;
1620 int dir_in = hs_ep->dir_in;
1621 struct dwc2_hsotg_req *hs_req;
1622 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1624 if (!list_empty(&hs_ep->queue)) {
1625 hs_req = get_ep_head(hs_ep);
1626 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1629 if (!hs_ep->isochronous)
1633 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1636 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1638 mask = dwc2_readl(hsotg, epmsk_reg);
1639 mask |= DOEPMSK_OUTTKNEPDISMSK;
1640 dwc2_writel(hsotg, mask, epmsk_reg);
1645 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1646 * @hsotg: The device state
1647 * @ctrl: USB control request
1649 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1650 struct usb_ctrlrequest *ctrl)
1652 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1653 struct dwc2_hsotg_req *hs_req;
1654 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1655 struct dwc2_hsotg_ep *ep;
1662 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1663 __func__, set ? "SET" : "CLEAR");
1665 wValue = le16_to_cpu(ctrl->wValue);
1666 wIndex = le16_to_cpu(ctrl->wIndex);
1667 recip = ctrl->bRequestType & USB_RECIP_MASK;
1670 case USB_RECIP_DEVICE:
1672 case USB_DEVICE_REMOTE_WAKEUP:
1673 hsotg->remote_wakeup_allowed = 1;
1676 case USB_DEVICE_TEST_MODE:
1677 if ((wIndex & 0xff) != 0)
1682 hsotg->test_mode = wIndex >> 8;
1683 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1686 "%s: failed to send reply\n", __func__);
1695 case USB_RECIP_ENDPOINT:
1696 ep = ep_from_windex(hsotg, wIndex);
1698 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1704 case USB_ENDPOINT_HALT:
1705 halted = ep->halted;
1707 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1709 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1712 "%s: failed to send reply\n", __func__);
1717 * we have to complete all requests for ep if it was
1718 * halted, and the halt was cleared by CLEAR_FEATURE
1721 if (!set && halted) {
1723 * If we have request in progress,
1729 list_del_init(&hs_req->queue);
1730 if (hs_req->req.complete) {
1731 spin_unlock(&hsotg->lock);
1732 usb_gadget_giveback_request(
1733 &ep->ep, &hs_req->req);
1734 spin_lock(&hsotg->lock);
1738 /* If we have pending request, then start it */
1740 dwc2_gadget_start_next_request(ep);
1755 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1758 * dwc2_hsotg_stall_ep0 - stall ep0
1759 * @hsotg: The device state
1761 * Set stall for ep0 as response for setup request.
1763 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1765 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1769 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1770 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1773 * DxEPCTL_Stall will be cleared by EP once it has
1774 * taken effect, so no need to clear later.
1777 ctrl = dwc2_readl(hsotg, reg);
1778 ctrl |= DXEPCTL_STALL;
1779 ctrl |= DXEPCTL_CNAK;
1780 dwc2_writel(hsotg, ctrl, reg);
1783 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1784 ctrl, reg, dwc2_readl(hsotg, reg));
1787 * complete won't be called, so we enqueue
1788 * setup request here
1790 dwc2_hsotg_enqueue_setup(hsotg);
1794 * dwc2_hsotg_process_control - process a control request
1795 * @hsotg: The device state
1796 * @ctrl: The control request received
1798 * The controller has received the SETUP phase of a control request, and
1799 * needs to work out what to do next (and whether to pass it on to the
1802 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1803 struct usb_ctrlrequest *ctrl)
1805 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1810 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1811 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1812 ctrl->wIndex, ctrl->wLength);
1814 if (ctrl->wLength == 0) {
1816 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1817 } else if (ctrl->bRequestType & USB_DIR_IN) {
1819 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1822 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1825 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1826 switch (ctrl->bRequest) {
1827 case USB_REQ_SET_ADDRESS:
1828 hsotg->connected = 1;
1829 dcfg = dwc2_readl(hsotg, DCFG);
1830 dcfg &= ~DCFG_DEVADDR_MASK;
1831 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1832 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1833 dwc2_writel(hsotg, dcfg, DCFG);
1835 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1837 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1840 case USB_REQ_GET_STATUS:
1841 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1844 case USB_REQ_CLEAR_FEATURE:
1845 case USB_REQ_SET_FEATURE:
1846 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1851 /* as a fallback, try delivering it to the driver to deal with */
1853 if (ret == 0 && hsotg->driver) {
1854 spin_unlock(&hsotg->lock);
1855 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1856 spin_lock(&hsotg->lock);
1858 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1862 * the request is either unhandlable, or is not formatted correctly
1863 * so respond with a STALL for the status stage to indicate failure.
1867 dwc2_hsotg_stall_ep0(hsotg);
1871 * dwc2_hsotg_complete_setup - completion of a setup transfer
1872 * @ep: The endpoint the request was on.
1873 * @req: The request completed.
1875 * Called on completion of any requests the driver itself submitted for
1878 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1879 struct usb_request *req)
1881 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1882 struct dwc2_hsotg *hsotg = hs_ep->parent;
1884 if (req->status < 0) {
1885 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1889 spin_lock(&hsotg->lock);
1890 if (req->actual == 0)
1891 dwc2_hsotg_enqueue_setup(hsotg);
1893 dwc2_hsotg_process_control(hsotg, req->buf);
1894 spin_unlock(&hsotg->lock);
1898 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1899 * @hsotg: The device state.
1901 * Enqueue a request on EP0 if necessary to received any SETUP packets
1902 * received from the host.
1904 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1906 struct usb_request *req = hsotg->ctrl_req;
1907 struct dwc2_hsotg_req *hs_req = our_req(req);
1910 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1914 req->buf = hsotg->ctrl_buff;
1915 req->complete = dwc2_hsotg_complete_setup;
1917 if (!list_empty(&hs_req->queue)) {
1918 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1922 hsotg->eps_out[0]->dir_in = 0;
1923 hsotg->eps_out[0]->send_zlp = 0;
1924 hsotg->ep0_state = DWC2_EP0_SETUP;
1926 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1928 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1930 * Don't think there's much we can do other than watch the
1936 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1937 struct dwc2_hsotg_ep *hs_ep)
1940 u8 index = hs_ep->index;
1941 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1942 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1945 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1948 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1950 if (using_desc_dma(hsotg)) {
1951 /* Not specific buffer needed for ep0 ZLP */
1952 dma_addr_t dma = hs_ep->desc_list_dma;
1955 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1957 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1959 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1960 DXEPTSIZ_XFERSIZE(0),
1964 ctrl = dwc2_readl(hsotg, epctl_reg);
1965 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1966 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1967 ctrl |= DXEPCTL_USBACTEP;
1968 dwc2_writel(hsotg, ctrl, epctl_reg);
1972 * dwc2_hsotg_complete_request - complete a request given to us
1973 * @hsotg: The device state.
1974 * @hs_ep: The endpoint the request was on.
1975 * @hs_req: The request to complete.
1976 * @result: The result code (0 => Ok, otherwise errno)
1978 * The given request has finished, so call the necessary completion
1979 * if it has one and then look to see if we can start a new request
1982 * Note, expects the ep to already be locked as appropriate.
1984 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1985 struct dwc2_hsotg_ep *hs_ep,
1986 struct dwc2_hsotg_req *hs_req,
1990 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1994 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1995 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1998 * only replace the status if we've not already set an error
1999 * from a previous transaction
2002 if (hs_req->req.status == -EINPROGRESS)
2003 hs_req->req.status = result;
2005 if (using_dma(hsotg))
2006 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2008 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2011 list_del_init(&hs_req->queue);
2014 * call the complete request with the locks off, just in case the
2015 * request tries to queue more work for this endpoint.
2018 if (hs_req->req.complete) {
2019 spin_unlock(&hsotg->lock);
2020 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2021 spin_lock(&hsotg->lock);
2024 /* In DDMA don't need to proceed to starting of next ISOC request */
2025 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2029 * Look to see if there is anything else to do. Note, the completion
2030 * of the previous request may have caused a new request to be started
2031 * so be careful when doing this.
2034 if (!hs_ep->req && result >= 0)
2035 dwc2_gadget_start_next_request(hs_ep);
2039 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2040 * @hs_ep: The endpoint the request was on.
2042 * Get first request from the ep queue, determine descriptor on which complete
2043 * happened. SW discovers which descriptor currently in use by HW, adjusts
2044 * dma_address and calculates index of completed descriptor based on the value
2045 * of DEPDMA register. Update actual length of request, giveback to gadget.
2047 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2049 struct dwc2_hsotg *hsotg = hs_ep->parent;
2050 struct dwc2_hsotg_req *hs_req;
2051 struct usb_request *ureq;
2055 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2057 /* Process only descriptors with buffer status set to DMA done */
2058 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2059 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2061 hs_req = get_ep_head(hs_ep);
2063 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2066 ureq = &hs_req->req;
2068 /* Check completion status */
2069 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2071 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2072 DEV_DMA_ISOC_RX_NBYTES_MASK;
2073 ureq->actual = ureq->length - ((desc_sts & mask) >>
2074 DEV_DMA_ISOC_NBYTES_SHIFT);
2076 /* Adjust actual len for ISOC Out if len is
2079 if (!hs_ep->dir_in && ureq->length & 0x3)
2080 ureq->actual += 4 - (ureq->length & 0x3);
2083 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2085 hs_ep->compl_desc++;
2086 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1))
2087 hs_ep->compl_desc = 0;
2088 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2093 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2094 * @hs_ep: The isochronous endpoint.
2096 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2097 * interrupt. Reset target frame and next_desc to allow to start
2098 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2099 * interrupt for OUT direction.
2101 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2103 struct dwc2_hsotg *hsotg = hs_ep->parent;
2106 dwc2_flush_rx_fifo(hsotg);
2107 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2109 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2110 hs_ep->next_desc = 0;
2111 hs_ep->compl_desc = 0;
2115 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2116 * @hsotg: The device state.
2117 * @ep_idx: The endpoint index for the data
2118 * @size: The size of data in the fifo, in bytes
2120 * The FIFO status shows there is data to read from the FIFO for a given
2121 * endpoint, so sort out whether we need to read the data into a request
2122 * that has been made for that endpoint.
2124 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2126 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2127 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2133 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2137 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2138 __func__, size, ep_idx, epctl);
2140 /* dump the data from the FIFO, we've nothing we can do */
2141 for (ptr = 0; ptr < size; ptr += 4)
2142 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2148 read_ptr = hs_req->req.actual;
2149 max_req = hs_req->req.length - read_ptr;
2151 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2152 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2154 if (to_read > max_req) {
2156 * more data appeared than we where willing
2157 * to deal with in this request.
2160 /* currently we don't deal this */
2164 hs_ep->total_data += to_read;
2165 hs_req->req.actual += to_read;
2166 to_read = DIV_ROUND_UP(to_read, 4);
2169 * note, we might over-write the buffer end by 3 bytes depending on
2170 * alignment of the data.
2172 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2173 hs_req->req.buf + read_ptr, to_read);
2177 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2178 * @hsotg: The device instance
2179 * @dir_in: If IN zlp
2181 * Generate a zero-length IN packet request for terminating a SETUP
2184 * Note, since we don't write any data to the TxFIFO, then it is
2185 * currently believed that we do not need to wait for any space in
2188 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2190 /* eps_out[0] is used in both directions */
2191 hsotg->eps_out[0]->dir_in = dir_in;
2192 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2194 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2197 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2202 ctrl = dwc2_readl(hsotg, epctl_reg);
2203 if (ctrl & DXEPCTL_EOFRNUM)
2204 ctrl |= DXEPCTL_SETEVENFR;
2206 ctrl |= DXEPCTL_SETODDFR;
2207 dwc2_writel(hsotg, ctrl, epctl_reg);
2211 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2212 * @hs_ep - The endpoint on which transfer went
2214 * Iterate over endpoints descriptor chain and get info on bytes remained
2215 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2217 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2219 struct dwc2_hsotg *hsotg = hs_ep->parent;
2220 unsigned int bytes_rem = 0;
2221 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2228 for (i = 0; i < hs_ep->desc_count; ++i) {
2229 status = desc->status;
2230 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2232 if (status & DEV_DMA_STS_MASK)
2233 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2234 i, status & DEV_DMA_STS_MASK);
2241 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2242 * @hsotg: The device instance
2243 * @epnum: The endpoint received from
2245 * The RXFIFO has delivered an OutDone event, which means that the data
2246 * transfer for an OUT endpoint has been completed, either by a short
2247 * packet or by the finish of a transfer.
2249 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2251 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2252 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2253 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2254 struct usb_request *req = &hs_req->req;
2255 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2259 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2263 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2264 dev_dbg(hsotg->dev, "zlp packet received\n");
2265 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2266 dwc2_hsotg_enqueue_setup(hsotg);
2270 if (using_desc_dma(hsotg))
2271 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2273 if (using_dma(hsotg)) {
2274 unsigned int size_done;
2277 * Calculate the size of the transfer by checking how much
2278 * is left in the endpoint size register and then working it
2279 * out from the amount we loaded for the transfer.
2281 * We need to do this as DMA pointers are always 32bit aligned
2282 * so may overshoot/undershoot the transfer.
2285 size_done = hs_ep->size_loaded - size_left;
2286 size_done += hs_ep->last_load;
2288 req->actual = size_done;
2291 /* if there is more request to do, schedule new transfer */
2292 if (req->actual < req->length && size_left == 0) {
2293 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2297 if (req->actual < req->length && req->short_not_ok) {
2298 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2299 __func__, req->actual, req->length);
2302 * todo - what should we return here? there's no one else
2303 * even bothering to check the status.
2307 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2308 if (!using_desc_dma(hsotg) && epnum == 0 &&
2309 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2310 /* Move to STATUS IN */
2311 dwc2_hsotg_ep0_zlp(hsotg, true);
2316 * Slave mode OUT transfers do not go through XferComplete so
2317 * adjust the ISOC parity here.
2319 if (!using_dma(hsotg)) {
2320 if (hs_ep->isochronous && hs_ep->interval == 1)
2321 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2322 else if (hs_ep->isochronous && hs_ep->interval > 1)
2323 dwc2_gadget_incr_frame_num(hs_ep);
2326 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2330 * dwc2_hsotg_handle_rx - RX FIFO has data
2331 * @hsotg: The device instance
2333 * The IRQ handler has detected that the RX FIFO has some data in it
2334 * that requires processing, so find out what is in there and do the
2337 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2338 * chunks, so if you have x packets received on an endpoint you'll get x
2339 * FIFO events delivered, each with a packet's worth of data in it.
2341 * When using DMA, we should not be processing events from the RXFIFO
2342 * as the actual data should be sent to the memory directly and we turn
2343 * on the completion interrupts to get notifications of transfer completion.
2345 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2347 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2348 u32 epnum, status, size;
2350 WARN_ON(using_dma(hsotg));
2352 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2353 status = grxstsr & GRXSTS_PKTSTS_MASK;
2355 size = grxstsr & GRXSTS_BYTECNT_MASK;
2356 size >>= GRXSTS_BYTECNT_SHIFT;
2358 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2359 __func__, grxstsr, size, epnum);
2361 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2362 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2363 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2366 case GRXSTS_PKTSTS_OUTDONE:
2367 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2368 dwc2_hsotg_read_frameno(hsotg));
2370 if (!using_dma(hsotg))
2371 dwc2_hsotg_handle_outdone(hsotg, epnum);
2374 case GRXSTS_PKTSTS_SETUPDONE:
2376 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2377 dwc2_hsotg_read_frameno(hsotg),
2378 dwc2_readl(hsotg, DOEPCTL(0)));
2380 * Call dwc2_hsotg_handle_outdone here if it was not called from
2381 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2382 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2384 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2385 dwc2_hsotg_handle_outdone(hsotg, epnum);
2388 case GRXSTS_PKTSTS_OUTRX:
2389 dwc2_hsotg_rx_data(hsotg, epnum, size);
2392 case GRXSTS_PKTSTS_SETUPRX:
2394 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2395 dwc2_hsotg_read_frameno(hsotg),
2396 dwc2_readl(hsotg, DOEPCTL(0)));
2398 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2400 dwc2_hsotg_rx_data(hsotg, epnum, size);
2404 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2407 dwc2_hsotg_dump(hsotg);
2413 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2414 * @mps: The maximum packet size in bytes.
2416 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2420 return D0EPCTL_MPS_64;
2422 return D0EPCTL_MPS_32;
2424 return D0EPCTL_MPS_16;
2426 return D0EPCTL_MPS_8;
2429 /* bad max packet size, warn and return invalid result */
2435 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2436 * @hsotg: The driver state.
2437 * @ep: The index number of the endpoint
2438 * @mps: The maximum packet size in bytes
2439 * @mc: The multicount value
2440 * @dir_in: True if direction is in.
2442 * Configure the maximum packet size for the given endpoint, updating
2443 * the hardware control registers to reflect this.
2445 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2446 unsigned int ep, unsigned int mps,
2447 unsigned int mc, unsigned int dir_in)
2449 struct dwc2_hsotg_ep *hs_ep;
2452 hs_ep = index_to_ep(hsotg, ep, dir_in);
2457 u32 mps_bytes = mps;
2459 /* EP0 is a special case */
2460 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2463 hs_ep->ep.maxpacket = mps_bytes;
2471 hs_ep->ep.maxpacket = mps;
2475 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2476 reg &= ~DXEPCTL_MPS_MASK;
2478 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2480 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2481 reg &= ~DXEPCTL_MPS_MASK;
2483 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2489 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2493 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2494 * @hsotg: The driver state
2495 * @idx: The index for the endpoint (0..15)
2497 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2499 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2502 /* wait until the fifo is flushed */
2503 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2504 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2509 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2510 * @hsotg: The driver state
2511 * @hs_ep: The driver endpoint to check.
2513 * Check to see if there is a request that has data to send, and if so
2514 * make an attempt to write data into the FIFO.
2516 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2517 struct dwc2_hsotg_ep *hs_ep)
2519 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2521 if (!hs_ep->dir_in || !hs_req) {
2523 * if request is not enqueued, we disable interrupts
2524 * for endpoints, excepting ep0
2526 if (hs_ep->index != 0)
2527 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2532 if (hs_req->req.actual < hs_req->req.length) {
2533 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2535 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2542 * dwc2_hsotg_complete_in - complete IN transfer
2543 * @hsotg: The device state.
2544 * @hs_ep: The endpoint that has just completed.
2546 * An IN transfer has been completed, update the transfer's state and then
2547 * call the relevant completion routines.
2549 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2550 struct dwc2_hsotg_ep *hs_ep)
2552 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2553 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2554 int size_left, size_done;
2557 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2561 /* Finish ZLP handling for IN EP0 transactions */
2562 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2563 dev_dbg(hsotg->dev, "zlp packet sent\n");
2566 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2567 * changed to IN. Change back to complete OUT transfer request
2571 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2572 if (hsotg->test_mode) {
2575 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2577 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2579 dwc2_hsotg_stall_ep0(hsotg);
2583 dwc2_hsotg_enqueue_setup(hsotg);
2588 * Calculate the size of the transfer by checking how much is left
2589 * in the endpoint size register and then working it out from
2590 * the amount we loaded for the transfer.
2592 * We do this even for DMA, as the transfer may have incremented
2593 * past the end of the buffer (DMA transfers are always 32bit
2596 if (using_desc_dma(hsotg)) {
2597 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2599 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2602 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2605 size_done = hs_ep->size_loaded - size_left;
2606 size_done += hs_ep->last_load;
2608 if (hs_req->req.actual != size_done)
2609 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2610 __func__, hs_req->req.actual, size_done);
2612 hs_req->req.actual = size_done;
2613 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2614 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2616 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2617 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2618 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2622 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2623 if (hs_ep->send_zlp) {
2624 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2625 hs_ep->send_zlp = 0;
2626 /* transfer will be completed on next complete interrupt */
2630 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2631 /* Move to STATUS OUT */
2632 dwc2_hsotg_ep0_zlp(hsotg, false);
2636 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2640 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2641 * @hsotg: The device state.
2642 * @idx: Index of ep.
2643 * @dir_in: Endpoint direction 1-in 0-out.
2645 * Reads for endpoint with given index and direction, by masking
2646 * epint_reg with coresponding mask.
2648 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2649 unsigned int idx, int dir_in)
2651 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2652 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2657 mask = dwc2_readl(hsotg, epmsk_reg);
2658 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2659 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2660 mask |= DXEPINT_SETUP_RCVD;
2662 ints = dwc2_readl(hsotg, epint_reg);
2668 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2669 * @hs_ep: The endpoint on which interrupt is asserted.
2671 * This interrupt indicates that the endpoint has been disabled per the
2672 * application's request.
2674 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2675 * in case of ISOC completes current request.
2677 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2678 * request starts it.
2680 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2682 struct dwc2_hsotg *hsotg = hs_ep->parent;
2683 struct dwc2_hsotg_req *hs_req;
2684 unsigned char idx = hs_ep->index;
2685 int dir_in = hs_ep->dir_in;
2686 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2687 int dctl = dwc2_readl(hsotg, DCTL);
2689 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2692 int epctl = dwc2_readl(hsotg, epctl_reg);
2694 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2696 if (hs_ep->isochronous) {
2697 dwc2_hsotg_complete_in(hsotg, hs_ep);
2701 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2702 int dctl = dwc2_readl(hsotg, DCTL);
2704 dctl |= DCTL_CGNPINNAK;
2705 dwc2_writel(hsotg, dctl, DCTL);
2710 if (dctl & DCTL_GOUTNAKSTS) {
2711 dctl |= DCTL_CGOUTNAK;
2712 dwc2_writel(hsotg, dctl, DCTL);
2715 if (!hs_ep->isochronous)
2718 if (list_empty(&hs_ep->queue)) {
2719 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2725 hs_req = get_ep_head(hs_ep);
2727 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2729 dwc2_gadget_incr_frame_num(hs_ep);
2730 /* Update current frame number value. */
2731 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2732 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2734 dwc2_gadget_start_next_request(hs_ep);
2738 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2739 * @ep: The endpoint on which interrupt is asserted.
2741 * This is starting point for ISOC-OUT transfer, synchronization done with
2742 * first out token received from host while corresponding EP is disabled.
2744 * Device does not know initial frame in which out token will come. For this
2745 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2746 * getting this interrupt SW starts calculation for next transfer frame.
2748 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2750 struct dwc2_hsotg *hsotg = ep->parent;
2751 int dir_in = ep->dir_in;
2754 if (dir_in || !ep->isochronous)
2757 if (using_desc_dma(hsotg)) {
2758 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2759 /* Start first ISO Out */
2760 ep->target_frame = hsotg->frame_number;
2761 dwc2_gadget_start_isoc_ddma(ep);
2766 if (ep->interval > 1 &&
2767 ep->target_frame == TARGET_FRAME_INITIAL) {
2770 ep->target_frame = hsotg->frame_number;
2771 dwc2_gadget_incr_frame_num(ep);
2773 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2774 if (ep->target_frame & 0x1)
2775 ctrl |= DXEPCTL_SETODDFR;
2777 ctrl |= DXEPCTL_SETEVENFR;
2779 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2782 dwc2_gadget_start_next_request(ep);
2783 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2784 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2785 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2789 * dwc2_gadget_handle_nak - handle NAK interrupt
2790 * @hs_ep: The endpoint on which interrupt is asserted.
2792 * This is starting point for ISOC-IN transfer, synchronization done with
2793 * first IN token received from host while corresponding EP is disabled.
2795 * Device does not know when first one token will arrive from host. On first
2796 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2797 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2798 * sent in response to that as there was no data in FIFO. SW is basing on this
2799 * interrupt to obtain frame in which token has come and then based on the
2800 * interval calculates next frame for transfer.
2802 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2804 struct dwc2_hsotg *hsotg = hs_ep->parent;
2805 int dir_in = hs_ep->dir_in;
2807 if (!dir_in || !hs_ep->isochronous)
2810 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2812 if (using_desc_dma(hsotg)) {
2813 hs_ep->target_frame = hsotg->frame_number;
2814 dwc2_gadget_incr_frame_num(hs_ep);
2815 dwc2_gadget_start_isoc_ddma(hs_ep);
2819 hs_ep->target_frame = hsotg->frame_number;
2820 if (hs_ep->interval > 1) {
2821 u32 ctrl = dwc2_readl(hsotg,
2822 DIEPCTL(hs_ep->index));
2823 if (hs_ep->target_frame & 0x1)
2824 ctrl |= DXEPCTL_SETODDFR;
2826 ctrl |= DXEPCTL_SETEVENFR;
2828 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2831 dwc2_hsotg_complete_request(hsotg, hs_ep,
2832 get_ep_head(hs_ep), 0);
2835 if (!using_desc_dma(hsotg))
2836 dwc2_gadget_incr_frame_num(hs_ep);
2840 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2841 * @hsotg: The driver state
2842 * @idx: The index for the endpoint (0..15)
2843 * @dir_in: Set if this is an IN endpoint
2845 * Process and clear any interrupt pending for an individual endpoint
2847 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2850 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2851 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2852 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2853 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2857 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2858 ctrl = dwc2_readl(hsotg, epctl_reg);
2860 /* Clear endpoint interrupts */
2861 dwc2_writel(hsotg, ints, epint_reg);
2864 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2865 __func__, idx, dir_in ? "in" : "out");
2869 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2870 __func__, idx, dir_in ? "in" : "out", ints);
2872 /* Don't process XferCompl interrupt if it is a setup packet */
2873 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2874 ints &= ~DXEPINT_XFERCOMPL;
2877 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2878 * stage and xfercomplete was generated without SETUP phase done
2879 * interrupt. SW should parse received setup packet only after host's
2880 * exit from setup phase of control transfer.
2882 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2883 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2884 ints &= ~DXEPINT_XFERCOMPL;
2886 if (ints & DXEPINT_XFERCOMPL) {
2888 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2889 __func__, dwc2_readl(hsotg, epctl_reg),
2890 dwc2_readl(hsotg, epsiz_reg));
2892 /* In DDMA handle isochronous requests separately */
2893 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2894 /* XferCompl set along with BNA */
2895 if (!(ints & DXEPINT_BNAINTR))
2896 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2897 } else if (dir_in) {
2899 * We get OutDone from the FIFO, so we only
2900 * need to look at completing IN requests here
2901 * if operating slave mode
2903 if (hs_ep->isochronous && hs_ep->interval > 1)
2904 dwc2_gadget_incr_frame_num(hs_ep);
2906 dwc2_hsotg_complete_in(hsotg, hs_ep);
2907 if (ints & DXEPINT_NAKINTRPT)
2908 ints &= ~DXEPINT_NAKINTRPT;
2910 if (idx == 0 && !hs_ep->req)
2911 dwc2_hsotg_enqueue_setup(hsotg);
2912 } else if (using_dma(hsotg)) {
2914 * We're using DMA, we need to fire an OutDone here
2915 * as we ignore the RXFIFO.
2917 if (hs_ep->isochronous && hs_ep->interval > 1)
2918 dwc2_gadget_incr_frame_num(hs_ep);
2920 dwc2_hsotg_handle_outdone(hsotg, idx);
2924 if (ints & DXEPINT_EPDISBLD)
2925 dwc2_gadget_handle_ep_disabled(hs_ep);
2927 if (ints & DXEPINT_OUTTKNEPDIS)
2928 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2930 if (ints & DXEPINT_NAKINTRPT)
2931 dwc2_gadget_handle_nak(hs_ep);
2933 if (ints & DXEPINT_AHBERR)
2934 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2936 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2937 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2939 if (using_dma(hsotg) && idx == 0) {
2941 * this is the notification we've received a
2942 * setup packet. In non-DMA mode we'd get this
2943 * from the RXFIFO, instead we need to process
2950 dwc2_hsotg_handle_outdone(hsotg, 0);
2954 if (ints & DXEPINT_STSPHSERCVD) {
2955 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2957 /* Safety check EP0 state when STSPHSERCVD asserted */
2958 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2959 /* Move to STATUS IN for DDMA */
2960 if (using_desc_dma(hsotg))
2961 dwc2_hsotg_ep0_zlp(hsotg, true);
2966 if (ints & DXEPINT_BACK2BACKSETUP)
2967 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2969 if (ints & DXEPINT_BNAINTR) {
2970 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2971 if (hs_ep->isochronous)
2972 dwc2_gadget_handle_isoc_bna(hs_ep);
2975 if (dir_in && !hs_ep->isochronous) {
2976 /* not sure if this is important, but we'll clear it anyway */
2977 if (ints & DXEPINT_INTKNTXFEMP) {
2978 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2982 /* this probably means something bad is happening */
2983 if (ints & DXEPINT_INTKNEPMIS) {
2984 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2988 /* FIFO has space or is empty (see GAHBCFG) */
2989 if (hsotg->dedicated_fifos &&
2990 ints & DXEPINT_TXFEMP) {
2991 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2993 if (!using_dma(hsotg))
2994 dwc2_hsotg_trytx(hsotg, hs_ep);
3000 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3001 * @hsotg: The device state.
3003 * Handle updating the device settings after the enumeration phase has
3006 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3008 u32 dsts = dwc2_readl(hsotg, DSTS);
3009 int ep0_mps = 0, ep_mps = 8;
3012 * This should signal the finish of the enumeration phase
3013 * of the USB handshaking, so we should now know what rate
3017 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3020 * note, since we're limited by the size of transfer on EP0, and
3021 * it seems IN transfers must be a even number of packets we do
3022 * not advertise a 64byte MPS on EP0.
3025 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3026 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3027 case DSTS_ENUMSPD_FS:
3028 case DSTS_ENUMSPD_FS48:
3029 hsotg->gadget.speed = USB_SPEED_FULL;
3030 ep0_mps = EP0_MPS_LIMIT;
3034 case DSTS_ENUMSPD_HS:
3035 hsotg->gadget.speed = USB_SPEED_HIGH;
3036 ep0_mps = EP0_MPS_LIMIT;
3040 case DSTS_ENUMSPD_LS:
3041 hsotg->gadget.speed = USB_SPEED_LOW;
3045 * note, we don't actually support LS in this driver at the
3046 * moment, and the documentation seems to imply that it isn't
3047 * supported by the PHYs on some of the devices.
3051 dev_info(hsotg->dev, "new device is %s\n",
3052 usb_speed_string(hsotg->gadget.speed));
3055 * we should now know the maximum packet size for an
3056 * endpoint, so set the endpoints to a default value.
3061 /* Initialize ep0 for both in and out directions */
3062 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3063 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3064 for (i = 1; i < hsotg->num_of_eps; i++) {
3065 if (hsotg->eps_in[i])
3066 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3068 if (hsotg->eps_out[i])
3069 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3074 /* ensure after enumeration our EP0 is active */
3076 dwc2_hsotg_enqueue_setup(hsotg);
3078 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3079 dwc2_readl(hsotg, DIEPCTL0),
3080 dwc2_readl(hsotg, DOEPCTL0));
3084 * kill_all_requests - remove all requests from the endpoint's queue
3085 * @hsotg: The device state.
3086 * @ep: The endpoint the requests may be on.
3087 * @result: The result code to use.
3089 * Go through the requests on the given endpoint and mark them
3090 * completed with the given result code.
3092 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3093 struct dwc2_hsotg_ep *ep,
3096 struct dwc2_hsotg_req *req, *treq;
3101 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3102 dwc2_hsotg_complete_request(hsotg, ep, req,
3105 if (!hsotg->dedicated_fifos)
3107 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3108 if (size < ep->fifo_size)
3109 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3112 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3115 * dwc2_hsotg_disconnect - disconnect service
3116 * @hsotg: The device state.
3118 * The device has been disconnected. Remove all current
3119 * transactions and signal the gadget driver that this
3122 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3126 if (!hsotg->connected)
3129 hsotg->connected = 0;
3130 hsotg->test_mode = 0;
3132 /* all endpoints should be shutdown */
3133 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3134 if (hsotg->eps_in[ep])
3135 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3136 if (hsotg->eps_out[ep])
3137 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3140 call_gadget(hsotg, disconnect);
3141 hsotg->lx_state = DWC2_L3;
3143 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3147 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3148 * @hsotg: The device state:
3149 * @periodic: True if this is a periodic FIFO interrupt
3151 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3153 struct dwc2_hsotg_ep *ep;
3156 /* look through for any more data to transmit */
3157 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3158 ep = index_to_ep(hsotg, epno, 1);
3166 if ((periodic && !ep->periodic) ||
3167 (!periodic && ep->periodic))
3170 ret = dwc2_hsotg_trytx(hsotg, ep);
3176 /* IRQ flags which will trigger a retry around the IRQ loop */
3177 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3182 * dwc2_hsotg_core_init - issue softreset to the core
3183 * @hsotg: The device state
3184 * @is_usb_reset: Usb resetting flag
3186 * Issue a soft reset to the core, and await the core finishing it.
3188 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3197 /* Kill any ep0 requests as controller will be reinitialized */
3198 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3200 if (!is_usb_reset) {
3201 if (dwc2_core_reset(hsotg, true))
3204 /* all endpoints should be shutdown */
3205 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3206 if (hsotg->eps_in[ep])
3207 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3208 if (hsotg->eps_out[ep])
3209 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3214 * we must now enable ep0 ready for host detection and then
3215 * set configuration.
3218 /* keep other bits untouched (so e.g. forced modes are not lost) */
3219 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3220 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3221 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3223 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3224 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3225 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3226 /* FS/LS Dedicated Transceiver Interface */
3227 usbcfg |= GUSBCFG_PHYSEL;
3229 /* set the PLL on, remove the HNP/SRP and set the PHY */
3230 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3231 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3232 (val << GUSBCFG_USBTRDTIM_SHIFT);
3234 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3236 dwc2_hsotg_init_fifo(hsotg);
3239 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3241 dcfg |= DCFG_EPMISCNT(1);
3243 switch (hsotg->params.speed) {
3244 case DWC2_SPEED_PARAM_LOW:
3245 dcfg |= DCFG_DEVSPD_LS;
3247 case DWC2_SPEED_PARAM_FULL:
3248 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3249 dcfg |= DCFG_DEVSPD_FS48;
3251 dcfg |= DCFG_DEVSPD_FS;
3254 dcfg |= DCFG_DEVSPD_HS;
3257 if (hsotg->params.ipg_isoc_en)
3258 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3260 dwc2_writel(hsotg, dcfg, DCFG);
3262 /* Clear any pending OTG interrupts */
3263 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3265 /* Clear any pending interrupts */
3266 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3267 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3268 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3269 GINTSTS_USBRST | GINTSTS_RESETDET |
3270 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3271 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3272 GINTSTS_LPMTRANRCVD;
3274 if (!using_desc_dma(hsotg))
3275 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3277 if (!hsotg->params.external_id_pin_ctl)
3278 intmsk |= GINTSTS_CONIDSTSCHNG;
3280 dwc2_writel(hsotg, intmsk, GINTMSK);
3282 if (using_dma(hsotg)) {
3283 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3284 hsotg->params.ahbcfg,
3287 /* Set DDMA mode support in the core if needed */
3288 if (using_desc_dma(hsotg))
3289 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3292 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3293 (GAHBCFG_NP_TXF_EMP_LVL |
3294 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3295 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3299 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3300 * when we have no data to transfer. Otherwise we get being flooded by
3304 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3305 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3306 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3307 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3311 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3312 * DMA mode we may need this and StsPhseRcvd.
3314 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3315 DOEPMSK_STSPHSERCVDMSK) : 0) |
3316 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3320 /* Enable BNA interrupt for DDMA */
3321 if (using_desc_dma(hsotg)) {
3322 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3323 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3326 dwc2_writel(hsotg, 0, DAINTMSK);
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3329 dwc2_readl(hsotg, DIEPCTL0),
3330 dwc2_readl(hsotg, DOEPCTL0));
3332 /* enable in and out endpoint interrupts */
3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3336 * Enable the RXFIFO when in slave mode, as this is how we collect
3337 * the data. In DMA mode, we get events from the FIFO but also
3338 * things we cannot process, so do not use it.
3340 if (!using_dma(hsotg))
3341 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3343 /* Enable interrupts for EP0 in and out */
3344 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3347 if (!is_usb_reset) {
3348 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3349 udelay(10); /* see openiboot */
3350 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3357 * writing to the EPCTL register..
3360 /* set to read 1 8byte packet */
3361 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3362 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3364 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3365 DXEPCTL_CNAK | DXEPCTL_EPENA |
3369 /* enable, but don't activate EP0in */
3370 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3371 DXEPCTL_USBACTEP, DIEPCTL0);
3373 /* clear global NAKs */
3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3376 val |= DCTL_SFTDISCON;
3377 dwc2_set_bit(hsotg, DCTL, val);
3379 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg);
3382 /* must be at-least 3ms to allow bus to see disconnect */
3385 hsotg->lx_state = DWC2_L0;
3387 dwc2_hsotg_enqueue_setup(hsotg);
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg, DIEPCTL0),
3391 dwc2_readl(hsotg, DOEPCTL0));
3394 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3396 /* set the soft-disconnect bit */
3397 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3400 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3402 /* remove the soft-disconnect and let's go */
3403 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3407 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3408 * @hsotg: The device state:
3410 * This interrupt indicates one of the following conditions occurred while
3411 * transmitting an ISOC transaction.
3412 * - Corrupted IN Token for ISOC EP.
3413 * - Packet not complete in FIFO.
3415 * The following actions will be taken:
3416 * - Determine the EP
3417 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3419 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3421 struct dwc2_hsotg_ep *hs_ep;
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3428 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3430 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx];
3432 /* Proceed only unmasked ISOC EPs */
3433 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3436 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3437 if ((epctrl & DXEPCTL_EPENA) &&
3438 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3445 /* Clear interrupt */
3446 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3450 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3451 * @hsotg: The device state:
3453 * This interrupt indicates one of the following conditions occurred while
3454 * transmitting an ISOC transaction.
3455 * - Corrupted OUT Token for ISOC EP.
3456 * - Packet not complete in FIFO.
3458 * The following actions will be taken:
3459 * - Determine the EP
3460 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3462 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3468 struct dwc2_hsotg_ep *hs_ep;
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3473 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT;
3476 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3477 hs_ep = hsotg->eps_out[idx];
3478 /* Proceed only unmasked ISOC EPs */
3479 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3482 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3483 if ((epctrl & DXEPCTL_EPENA) &&
3484 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg, GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(hsotg, gintmsk, GINTMSK);
3490 gintsts = dwc2_readl(hsotg, GINTSTS);
3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3492 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3498 /* Clear interrupt */
3499 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3503 * dwc2_hsotg_irq - handle device interrupt
3504 * @irq: The IRQ number triggered
3505 * @pw: The pw value when registered the handler.
3507 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3509 struct dwc2_hsotg *hsotg = pw;
3510 int retry_count = 8;
3514 if (!dwc2_is_device_mode(hsotg))
3517 spin_lock(&hsotg->lock);
3519 gintsts = dwc2_readl(hsotg, GINTSTS);
3520 gintmsk = dwc2_readl(hsotg, GINTMSK);
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3527 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3530 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3532 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) {
3534 dwc2_exit_partial_power_down(hsotg, true);
3535 hsotg->lx_state = DWC2_L0;
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3540 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3541 u32 connected = hsotg->connected;
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg, GNPTXSTS));
3547 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3549 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg);
3552 /* Reset device address to zero */
3553 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3555 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true);
3559 if (gintsts & GINTSTS_ENUMDONE) {
3560 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3562 dwc2_hsotg_irq_enumdone(hsotg);
3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3566 u32 daint = dwc2_readl(hsotg, DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3568 u32 daint_out, daint_in;
3572 daint_out = daint >> DAINT_OUTEP_SHIFT;
3573 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3575 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3577 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3578 ep++, daint_out >>= 1) {
3580 dwc2_hsotg_epint(hsotg, ep, 0);
3583 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3584 ep++, daint_in >>= 1) {
3586 dwc2_hsotg_epint(hsotg, ep, 1);
3590 /* check both FIFOs */
3592 if (gintsts & GINTSTS_NPTXFEMP) {
3593 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3596 * Disable the interrupt to stop it happening again
3597 * unless one of these endpoint routines decides that
3598 * it needs re-enabling
3601 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3602 dwc2_hsotg_irq_fifoempty(hsotg, false);
3605 if (gintsts & GINTSTS_PTXFEMP) {
3606 dev_dbg(hsotg->dev, "PTxFEmp\n");
3608 /* See note in GINTSTS_NPTxFEmp */
3610 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3611 dwc2_hsotg_irq_fifoempty(hsotg, true);
3614 if (gintsts & GINTSTS_RXFLVL) {
3616 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3617 * we need to retry dwc2_hsotg_handle_rx if this is still
3621 dwc2_hsotg_handle_rx(hsotg);
3624 if (gintsts & GINTSTS_ERLYSUSP) {
3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3626 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3630 * these next two seem to crop-up occasionally causing the core
3631 * to shutdown the USB transfer, so try clearing them and logging
3635 if (gintsts & GINTSTS_GOUTNAKEFF) {
3640 struct dwc2_hsotg_ep *hs_ep;
3642 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT;
3644 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg, GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(hsotg, gintmsk, GINTMSK);
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3651 hs_ep = hsotg->eps_out[idx];
3652 /* Proceed only unmasked ISOC EPs */
3653 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3656 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3658 if (epctrl & DXEPCTL_EPENA) {
3659 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3665 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3668 if (gintsts & GINTSTS_GINNAKEFF) {
3669 dev_info(hsotg->dev, "GINNakEff triggered\n");
3671 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3673 dwc2_hsotg_dump(hsotg);
3676 if (gintsts & GINTSTS_INCOMPL_SOIN)
3677 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3679 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3680 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3683 * if we've had fifo events, we should try and go around the
3684 * loop again to see if there's any point in returning yet.
3687 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3690 spin_unlock(&hsotg->lock);
3695 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3696 struct dwc2_hsotg_ep *hs_ep)
3701 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3702 DOEPCTL(hs_ep->index);
3703 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3704 DOEPINT(hs_ep->index);
3706 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3709 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3711 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100))
3715 dev_warn(hsotg->dev,
3716 "%s: timeout DIEPINT.NAKEFF\n",
3719 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3720 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100))
3723 dev_warn(hsotg->dev,
3724 "%s: timeout GINTSTS.GINNAKEFF\n",
3728 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3729 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3731 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3733 GINTSTS_GOUTNAKEFF, 100))
3734 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3739 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3741 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3743 dev_warn(hsotg->dev,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3746 /* Clear EPDISBLD interrupt */
3747 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3749 if (hs_ep->dir_in) {
3750 unsigned short fifo_index;
3752 if (hsotg->dedicated_fifos || hs_ep->periodic)
3753 fifo_index = hs_ep->fifo_index;
3758 dwc2_flush_tx_fifo(hsotg, fifo_index);
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3762 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3765 /* Remove global NAKs */
3766 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3771 * dwc2_hsotg_ep_enable - enable the given endpoint
3772 * @ep: The USB endpint to configure
3773 * @desc: The USB endpoint descriptor to configure with.
3775 * This is called from the USB gadget code's usb_ep_enable().
3777 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3778 const struct usb_endpoint_descriptor *desc)
3780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3781 struct dwc2_hsotg *hsotg = hs_ep->parent;
3782 unsigned long flags;
3783 unsigned int index = hs_ep->index;
3789 unsigned int dir_in;
3790 unsigned int i, val, size;
3792 unsigned char ep_type;
3795 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3796 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3797 desc->wMaxPacketSize, desc->bInterval);
3799 /* not to be called for EP0 */
3801 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3805 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3806 if (dir_in != hs_ep->dir_in) {
3807 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3811 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3812 mps = usb_endpoint_maxp(desc);
3813 mc = usb_endpoint_maxp_mult(desc);
3815 /* ISOC IN in DDMA supported bInterval up to 10 */
3816 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3817 dir_in && desc->bInterval > 10) {
3819 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3823 /* High bandwidth ISOC OUT in DDMA not supported */
3824 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3825 !dir_in && mc > 1) {
3827 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
3831 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3833 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3834 epctrl = dwc2_readl(hsotg, epctrl_reg);
3836 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3837 __func__, epctrl, epctrl_reg);
3839 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3840 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3841 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3842 MAX_DMA_DESC_NUM_GENERIC *
3843 sizeof(struct dwc2_dma_desc),
3844 &hs_ep->desc_list_dma, GFP_ATOMIC);
3845 if (!hs_ep->desc_list) {
3851 spin_lock_irqsave(&hsotg->lock, flags);
3853 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3854 epctrl |= DXEPCTL_MPS(mps);
3857 * mark the endpoint as active, otherwise the core may ignore
3858 * transactions entirely for this endpoint
3860 epctrl |= DXEPCTL_USBACTEP;
3862 /* update the endpoint state */
3863 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3865 /* default, set to non-periodic */
3866 hs_ep->isochronous = 0;
3867 hs_ep->periodic = 0;
3869 hs_ep->interval = desc->bInterval;
3872 case USB_ENDPOINT_XFER_ISOC:
3873 epctrl |= DXEPCTL_EPTYPE_ISO;
3874 epctrl |= DXEPCTL_SETEVENFR;
3875 hs_ep->isochronous = 1;
3876 hs_ep->interval = 1 << (desc->bInterval - 1);
3877 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3878 hs_ep->next_desc = 0;
3879 hs_ep->compl_desc = 0;
3881 hs_ep->periodic = 1;
3882 mask = dwc2_readl(hsotg, DIEPMSK);
3883 mask |= DIEPMSK_NAKMSK;
3884 dwc2_writel(hsotg, mask, DIEPMSK);
3886 mask = dwc2_readl(hsotg, DOEPMSK);
3887 mask |= DOEPMSK_OUTTKNEPDISMSK;
3888 dwc2_writel(hsotg, mask, DOEPMSK);
3892 case USB_ENDPOINT_XFER_BULK:
3893 epctrl |= DXEPCTL_EPTYPE_BULK;
3896 case USB_ENDPOINT_XFER_INT:
3898 hs_ep->periodic = 1;
3900 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3901 hs_ep->interval = 1 << (desc->bInterval - 1);
3903 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3906 case USB_ENDPOINT_XFER_CONTROL:
3907 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3912 * if the hardware has dedicated fifos, we must give each IN EP
3913 * a unique tx-fifo even if it is non-periodic.
3915 if (dir_in && hsotg->dedicated_fifos) {
3917 u32 fifo_size = UINT_MAX;
3919 size = hs_ep->ep.maxpacket * hs_ep->mc;
3920 for (i = 1; i < hsotg->num_of_eps; ++i) {
3921 if (hsotg->fifo_map & (1 << i))
3923 val = dwc2_readl(hsotg, DPTXFSIZN(i));
3924 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3927 /* Search for smallest acceptable fifo */
3928 if (val < fifo_size) {
3935 "%s: No suitable fifo found\n", __func__);
3939 hsotg->fifo_map |= 1 << fifo_index;
3940 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3941 hs_ep->fifo_index = fifo_index;
3942 hs_ep->fifo_size = fifo_size;
3945 /* for non control endpoints, set PID to D0 */
3946 if (index && !hs_ep->isochronous)
3947 epctrl |= DXEPCTL_SETD0PID;
3949 /* WA for Full speed ISOC IN in DDMA mode.
3950 * By Clear NAK status of EP, core will send ZLP
3951 * to IN token and assert NAK interrupt relying
3952 * on TxFIFO status only
3955 if (hsotg->gadget.speed == USB_SPEED_FULL &&
3956 hs_ep->isochronous && dir_in) {
3957 /* The WA applies only to core versions from 2.72a
3958 * to 4.00a (including both). Also for FS_IOT_1.00a
3961 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
3963 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
3964 gsnpsid <= DWC2_CORE_REV_4_00a) ||
3965 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
3966 gsnpsid == DWC2_HS_IOT_REV_1_00a)
3967 epctrl |= DXEPCTL_CNAK;
3970 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3973 dwc2_writel(hsotg, epctrl, epctrl_reg);
3974 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3975 __func__, dwc2_readl(hsotg, epctrl_reg));
3977 /* enable the endpoint interrupt */
3978 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3981 spin_unlock_irqrestore(&hsotg->lock, flags);
3984 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3985 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3986 sizeof(struct dwc2_dma_desc),
3987 hs_ep->desc_list, hs_ep->desc_list_dma);
3988 hs_ep->desc_list = NULL;
3995 * dwc2_hsotg_ep_disable - disable given endpoint
3996 * @ep: The endpoint to disable.
3998 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4000 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4001 struct dwc2_hsotg *hsotg = hs_ep->parent;
4002 int dir_in = hs_ep->dir_in;
4003 int index = hs_ep->index;
4004 unsigned long flags;
4009 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4011 if (ep == &hsotg->eps_out[0]->ep) {
4012 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4016 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4017 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4021 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4023 locked = spin_is_locked(&hsotg->lock);
4025 spin_lock_irqsave(&hsotg->lock, flags);
4027 ctrl = dwc2_readl(hsotg, epctrl_reg);
4029 if (ctrl & DXEPCTL_EPENA)
4030 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4032 ctrl &= ~DXEPCTL_EPENA;
4033 ctrl &= ~DXEPCTL_USBACTEP;
4034 ctrl |= DXEPCTL_SNAK;
4036 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4037 dwc2_writel(hsotg, ctrl, epctrl_reg);
4039 /* disable endpoint interrupts */
4040 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4042 /* terminate all requests with shutdown */
4043 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4045 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4046 hs_ep->fifo_index = 0;
4047 hs_ep->fifo_size = 0;
4050 spin_unlock_irqrestore(&hsotg->lock, flags);
4056 * on_list - check request is on the given endpoint
4057 * @ep: The endpoint to check.
4058 * @test: The request to test if it is on the endpoint.
4060 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4062 struct dwc2_hsotg_req *req, *treq;
4064 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4073 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4074 * @ep: The endpoint to dequeue.
4075 * @req: The request to be removed from a queue.
4077 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4079 struct dwc2_hsotg_req *hs_req = our_req(req);
4080 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4081 struct dwc2_hsotg *hs = hs_ep->parent;
4082 unsigned long flags;
4084 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4086 spin_lock_irqsave(&hs->lock, flags);
4088 if (!on_list(hs_ep, hs_req)) {
4089 spin_unlock_irqrestore(&hs->lock, flags);
4093 /* Dequeue already started request */
4094 if (req == &hs_ep->req->req)
4095 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4097 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4098 spin_unlock_irqrestore(&hs->lock, flags);
4104 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4105 * @ep: The endpoint to set halt.
4106 * @value: Set or unset the halt.
4107 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4108 * the endpoint is busy processing requests.
4110 * We need to stall the endpoint immediately if request comes from set_feature
4111 * protocol command handler.
4113 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4115 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4116 struct dwc2_hsotg *hs = hs_ep->parent;
4117 int index = hs_ep->index;
4122 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4126 dwc2_hsotg_stall_ep0(hs);
4129 "%s: can't clear halt on ep0\n", __func__);
4133 if (hs_ep->isochronous) {
4134 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4138 if (!now && value && !list_empty(&hs_ep->queue)) {
4139 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4144 if (hs_ep->dir_in) {
4145 epreg = DIEPCTL(index);
4146 epctl = dwc2_readl(hs, epreg);
4149 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4150 if (epctl & DXEPCTL_EPENA)
4151 epctl |= DXEPCTL_EPDIS;
4153 epctl &= ~DXEPCTL_STALL;
4154 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4155 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4156 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4157 epctl |= DXEPCTL_SETD0PID;
4159 dwc2_writel(hs, epctl, epreg);
4161 epreg = DOEPCTL(index);
4162 epctl = dwc2_readl(hs, epreg);
4165 epctl |= DXEPCTL_STALL;
4167 epctl &= ~DXEPCTL_STALL;
4168 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4169 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4170 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4171 epctl |= DXEPCTL_SETD0PID;
4173 dwc2_writel(hs, epctl, epreg);
4176 hs_ep->halted = value;
4182 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4183 * @ep: The endpoint to set halt.
4184 * @value: Set or unset the halt.
4186 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4188 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4189 struct dwc2_hsotg *hs = hs_ep->parent;
4190 unsigned long flags = 0;
4193 spin_lock_irqsave(&hs->lock, flags);
4194 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4195 spin_unlock_irqrestore(&hs->lock, flags);
4200 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4201 .enable = dwc2_hsotg_ep_enable,
4202 .disable = dwc2_hsotg_ep_disable,
4203 .alloc_request = dwc2_hsotg_ep_alloc_request,
4204 .free_request = dwc2_hsotg_ep_free_request,
4205 .queue = dwc2_hsotg_ep_queue_lock,
4206 .dequeue = dwc2_hsotg_ep_dequeue,
4207 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4208 /* note, don't believe we have any call for the fifo routines */
4212 * dwc2_hsotg_init - initialize the usb core
4213 * @hsotg: The driver state
4215 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4219 /* unmask subset of endpoint interrupts */
4221 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4222 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4225 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4226 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4229 dwc2_writel(hsotg, 0, DAINTMSK);
4231 /* Be in disconnected state until gadget is registered */
4232 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4236 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4237 dwc2_readl(hsotg, GRXFSIZ),
4238 dwc2_readl(hsotg, GNPTXFSIZ));
4240 dwc2_hsotg_init_fifo(hsotg);
4242 /* keep other bits untouched (so e.g. forced modes are not lost) */
4243 usbcfg = dwc2_readl(hsotg, GUSBCFG);
4244 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4245 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4247 /* set the PLL on, remove the HNP/SRP and set the PHY */
4248 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4249 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4250 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4251 dwc2_writel(hsotg, usbcfg, GUSBCFG);
4253 if (using_dma(hsotg))
4254 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4258 * dwc2_hsotg_udc_start - prepare the udc for work
4259 * @gadget: The usb gadget state
4260 * @driver: The usb gadget driver
4262 * Perform initialization to prepare udc device and driver
4265 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4266 struct usb_gadget_driver *driver)
4268 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4269 unsigned long flags;
4273 pr_err("%s: called with no device\n", __func__);
4278 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4282 if (driver->max_speed < USB_SPEED_FULL)
4283 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4285 if (!driver->setup) {
4286 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4290 WARN_ON(hsotg->driver);
4292 driver->driver.bus = NULL;
4293 hsotg->driver = driver;
4294 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4295 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4297 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4298 ret = dwc2_lowlevel_hw_enable(hsotg);
4303 if (!IS_ERR_OR_NULL(hsotg->uphy))
4304 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4306 spin_lock_irqsave(&hsotg->lock, flags);
4307 if (dwc2_hw_is_device(hsotg)) {
4308 dwc2_hsotg_init(hsotg);
4309 dwc2_hsotg_core_init_disconnected(hsotg, false);
4313 spin_unlock_irqrestore(&hsotg->lock, flags);
4315 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4320 hsotg->driver = NULL;
4325 * dwc2_hsotg_udc_stop - stop the udc
4326 * @gadget: The usb gadget state
4328 * Stop udc hw block and stay tunned for future transmissions
4330 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4332 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4333 unsigned long flags = 0;
4339 /* all endpoints should be shutdown */
4340 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4341 if (hsotg->eps_in[ep])
4342 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4343 if (hsotg->eps_out[ep])
4344 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4347 spin_lock_irqsave(&hsotg->lock, flags);
4349 hsotg->driver = NULL;
4350 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4353 spin_unlock_irqrestore(&hsotg->lock, flags);
4355 if (!IS_ERR_OR_NULL(hsotg->uphy))
4356 otg_set_peripheral(hsotg->uphy->otg, NULL);
4358 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4359 dwc2_lowlevel_hw_disable(hsotg);
4365 * dwc2_hsotg_gadget_getframe - read the frame number
4366 * @gadget: The usb gadget state
4368 * Read the {micro} frame number
4370 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4372 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4376 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4377 * @gadget: The usb gadget state
4378 * @is_on: Current state of the USB PHY
4380 * Connect/Disconnect the USB PHY pullup
4382 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4384 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4385 unsigned long flags = 0;
4387 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4390 /* Don't modify pullup state while in host mode */
4391 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4392 hsotg->enabled = is_on;
4396 spin_lock_irqsave(&hsotg->lock, flags);
4399 dwc2_hsotg_core_init_disconnected(hsotg, false);
4400 /* Enable ACG feature in device mode,if supported */
4401 dwc2_enable_acg(hsotg);
4402 dwc2_hsotg_core_connect(hsotg);
4404 dwc2_hsotg_core_disconnect(hsotg);
4405 dwc2_hsotg_disconnect(hsotg);
4409 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4410 spin_unlock_irqrestore(&hsotg->lock, flags);
4415 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4417 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4418 unsigned long flags;
4420 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4421 spin_lock_irqsave(&hsotg->lock, flags);
4424 * If controller is hibernated, it must exit from power_down
4425 * before being initialized / de-initialized
4427 if (hsotg->lx_state == DWC2_L2)
4428 dwc2_exit_partial_power_down(hsotg, false);
4431 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4433 dwc2_hsotg_core_init_disconnected(hsotg, false);
4434 if (hsotg->enabled) {
4435 /* Enable ACG feature in device mode,if supported */
4436 dwc2_enable_acg(hsotg);
4437 dwc2_hsotg_core_connect(hsotg);
4440 dwc2_hsotg_core_disconnect(hsotg);
4441 dwc2_hsotg_disconnect(hsotg);
4444 spin_unlock_irqrestore(&hsotg->lock, flags);
4449 * dwc2_hsotg_vbus_draw - report bMaxPower field
4450 * @gadget: The usb gadget state
4451 * @mA: Amount of current
4453 * Report how much power the device may consume to the phy.
4455 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4457 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4459 if (IS_ERR_OR_NULL(hsotg->uphy))
4461 return usb_phy_set_power(hsotg->uphy, mA);
4464 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4465 .get_frame = dwc2_hsotg_gadget_getframe,
4466 .udc_start = dwc2_hsotg_udc_start,
4467 .udc_stop = dwc2_hsotg_udc_stop,
4468 .pullup = dwc2_hsotg_pullup,
4469 .vbus_session = dwc2_hsotg_vbus_session,
4470 .vbus_draw = dwc2_hsotg_vbus_draw,
4474 * dwc2_hsotg_initep - initialise a single endpoint
4475 * @hsotg: The device state.
4476 * @hs_ep: The endpoint to be initialised.
4477 * @epnum: The endpoint number
4478 * @dir_in: True if direction is in.
4480 * Initialise the given endpoint (as part of the probe and device state
4481 * creation) to give to the gadget driver. Setup the endpoint name, any
4482 * direction information and other state that may be required.
4484 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4485 struct dwc2_hsotg_ep *hs_ep,
4498 hs_ep->dir_in = dir_in;
4499 hs_ep->index = epnum;
4501 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4503 INIT_LIST_HEAD(&hs_ep->queue);
4504 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4506 /* add to the list of endpoints known by the gadget driver */
4508 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4510 hs_ep->parent = hsotg;
4511 hs_ep->ep.name = hs_ep->name;
4513 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4514 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4516 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4517 epnum ? 1024 : EP0_MPS_LIMIT);
4518 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4521 hs_ep->ep.caps.type_control = true;
4523 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4524 hs_ep->ep.caps.type_iso = true;
4525 hs_ep->ep.caps.type_bulk = true;
4527 hs_ep->ep.caps.type_int = true;
4531 hs_ep->ep.caps.dir_in = true;
4533 hs_ep->ep.caps.dir_out = true;
4536 * if we're using dma, we need to set the next-endpoint pointer
4537 * to be something valid.
4540 if (using_dma(hsotg)) {
4541 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4544 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4546 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4551 * dwc2_hsotg_hw_cfg - read HW configuration registers
4552 * @hsotg: Programming view of the DWC_otg controller
4554 * Read the USB core HW configuration registers
4556 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4562 /* check hardware configuration */
4564 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4567 hsotg->num_of_eps++;
4569 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4570 sizeof(struct dwc2_hsotg_ep),
4572 if (!hsotg->eps_in[0])
4574 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4575 hsotg->eps_out[0] = hsotg->eps_in[0];
4577 cfg = hsotg->hw_params.dev_ep_dirs;
4578 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4580 /* Direction in or both */
4581 if (!(ep_type & 2)) {
4582 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4583 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4584 if (!hsotg->eps_in[i])
4587 /* Direction out or both */
4588 if (!(ep_type & 1)) {
4589 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4590 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4591 if (!hsotg->eps_out[i])
4596 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4597 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4599 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4601 hsotg->dedicated_fifos ? "dedicated" : "shared",
4607 * dwc2_hsotg_dump - dump state of the udc
4608 * @hsotg: Programming view of the DWC_otg controller
4611 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4614 struct device *dev = hsotg->dev;
4618 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4619 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4620 dwc2_readl(hsotg, DIEPMSK));
4622 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4623 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4625 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4626 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4628 /* show periodic fifo settings */
4630 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4631 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4632 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4633 val >> FIFOSIZE_DEPTH_SHIFT,
4634 val & FIFOSIZE_STARTADDR_MASK);
4637 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4639 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4640 dwc2_readl(hsotg, DIEPCTL(idx)),
4641 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4642 dwc2_readl(hsotg, DIEPDMA(idx)));
4644 val = dwc2_readl(hsotg, DOEPCTL(idx));
4646 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4647 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4648 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4649 dwc2_readl(hsotg, DOEPDMA(idx)));
4652 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4653 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4658 * dwc2_gadget_init - init function for gadget
4659 * @hsotg: Programming view of the DWC_otg controller
4662 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4664 struct device *dev = hsotg->dev;
4668 /* Dump fifo information */
4669 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4670 hsotg->params.g_np_tx_fifo_size);
4671 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4673 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4674 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4675 hsotg->gadget.name = dev_name(dev);
4676 hsotg->remote_wakeup_allowed = 0;
4678 if (hsotg->params.lpm)
4679 hsotg->gadget.lpm_capable = true;
4681 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4682 hsotg->gadget.is_otg = 1;
4683 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4684 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4686 ret = dwc2_hsotg_hw_cfg(hsotg);
4688 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4692 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4693 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4694 if (!hsotg->ctrl_buff)
4697 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4698 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4699 if (!hsotg->ep0_buff)
4702 if (using_desc_dma(hsotg)) {
4703 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4708 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4709 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4711 dev_err(dev, "cannot claim IRQ for gadget\n");
4715 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4717 if (hsotg->num_of_eps == 0) {
4718 dev_err(dev, "wrong number of EPs (zero)\n");
4722 /* setup endpoint information */
4724 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4725 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4727 /* allocate EP0 request */
4729 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4731 if (!hsotg->ctrl_req) {
4732 dev_err(dev, "failed to allocate ctrl req\n");
4736 /* initialise the endpoints now the core has been initialised */
4737 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4738 if (hsotg->eps_in[epnum])
4739 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4741 if (hsotg->eps_out[epnum])
4742 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4746 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4748 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep,
4752 dwc2_hsotg_dump(hsotg);
4758 * dwc2_hsotg_remove - remove function for hsotg driver
4759 * @hsotg: Programming view of the DWC_otg controller
4762 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4764 usb_del_gadget_udc(&hsotg->gadget);
4765 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4770 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4772 unsigned long flags;
4774 if (hsotg->lx_state != DWC2_L0)
4777 if (hsotg->driver) {
4780 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4781 hsotg->driver->driver.name);
4783 spin_lock_irqsave(&hsotg->lock, flags);
4785 dwc2_hsotg_core_disconnect(hsotg);
4786 dwc2_hsotg_disconnect(hsotg);
4787 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4788 spin_unlock_irqrestore(&hsotg->lock, flags);
4790 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4791 if (hsotg->eps_in[ep])
4792 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4793 if (hsotg->eps_out[ep])
4794 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4801 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4803 unsigned long flags;
4805 if (hsotg->lx_state == DWC2_L2)
4808 if (hsotg->driver) {
4809 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4810 hsotg->driver->driver.name);
4812 spin_lock_irqsave(&hsotg->lock, flags);
4813 dwc2_hsotg_core_init_disconnected(hsotg, false);
4814 if (hsotg->enabled) {
4815 /* Enable ACG feature in device mode,if supported */
4816 dwc2_enable_acg(hsotg);
4817 dwc2_hsotg_core_connect(hsotg);
4819 spin_unlock_irqrestore(&hsotg->lock, flags);
4826 * dwc2_backup_device_registers() - Backup controller device registers.
4827 * When suspending usb bus, registers needs to be backuped
4828 * if controller power is disabled once suspended.
4830 * @hsotg: Programming view of the DWC_otg controller
4832 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4834 struct dwc2_dregs_backup *dr;
4837 dev_dbg(hsotg->dev, "%s\n", __func__);
4839 /* Backup dev regs */
4840 dr = &hsotg->dr_backup;
4842 dr->dcfg = dwc2_readl(hsotg, DCFG);
4843 dr->dctl = dwc2_readl(hsotg, DCTL);
4844 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
4845 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
4846 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
4848 for (i = 0; i < hsotg->num_of_eps; i++) {
4850 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
4852 /* Ensure DATA PID is correctly configured */
4853 if (dr->diepctl[i] & DXEPCTL_DPID)
4854 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4856 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4858 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
4859 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
4861 /* Backup OUT EPs */
4862 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
4864 /* Ensure DATA PID is correctly configured */
4865 if (dr->doepctl[i] & DXEPCTL_DPID)
4866 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4868 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4870 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
4871 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
4872 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
4879 * dwc2_restore_device_registers() - Restore controller device registers.
4880 * When resuming usb bus, device registers needs to be restored
4881 * if controller power were disabled.
4883 * @hsotg: Programming view of the DWC_otg controller
4884 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
4886 * Return: 0 if successful, negative error code otherwise
4888 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4890 struct dwc2_dregs_backup *dr;
4893 dev_dbg(hsotg->dev, "%s\n", __func__);
4895 /* Restore dev regs */
4896 dr = &hsotg->dr_backup;
4898 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4905 dwc2_writel(hsotg, dr->dctl, DCTL);
4907 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
4908 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
4909 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
4911 for (i = 0; i < hsotg->num_of_eps; i++) {
4912 /* Restore IN EPs */
4913 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
4914 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
4915 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
4916 /** WA for enabled EPx's IN in DDMA mode. On entering to
4917 * hibernation wrong value read and saved from DIEPDMAx,
4918 * as result BNA interrupt asserted on hibernation exit
4919 * by restoring from saved area.
4921 if (hsotg->params.g_dma_desc &&
4922 (dr->diepctl[i] & DXEPCTL_EPENA))
4923 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
4924 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
4925 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
4926 /* Restore OUT EPs */
4927 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
4928 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4929 * hibernation wrong value read and saved from DOEPDMAx,
4930 * as result BNA interrupt asserted on hibernation exit
4931 * by restoring from saved area.
4933 if (hsotg->params.g_dma_desc &&
4934 (dr->doepctl[i] & DXEPCTL_EPENA))
4935 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
4936 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
4937 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
4944 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
4946 * @hsotg: Programming view of DWC_otg controller
4949 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4953 if (!hsotg->params.lpm)
4956 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
4957 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
4958 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4959 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4960 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4961 dwc2_writel(hsotg, val, GLPMCFG);
4962 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
4966 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
4968 * @hsotg: Programming view of the DWC_otg controller
4970 * Return non-zero if failed to enter to hibernation.
4972 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4977 /* Change to L2(suspend) state */
4978 hsotg->lx_state = DWC2_L2;
4979 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
4980 ret = dwc2_backup_global_registers(hsotg);
4982 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
4986 ret = dwc2_backup_device_registers(hsotg);
4988 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
4993 gpwrdn = GPWRDN_PWRDNRSTN;
4994 gpwrdn |= GPWRDN_PMUACTV;
4995 dwc2_writel(hsotg, gpwrdn, GPWRDN);
4998 /* Set flag to indicate that we are in hibernation */
4999 hsotg->hibernated = 1;
5001 /* Enable interrupts from wake up logic */
5002 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5003 gpwrdn |= GPWRDN_PMUINTSEL;
5004 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5007 /* Unmask device mode interrupts in GPWRDN */
5008 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5009 gpwrdn |= GPWRDN_RST_DET_MSK;
5010 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5011 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5012 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5015 /* Enable Power Down Clamp */
5016 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5017 gpwrdn |= GPWRDN_PWRDNCLMP;
5018 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5021 /* Switch off VDD */
5022 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5023 gpwrdn |= GPWRDN_PWRDNSWTCH;
5024 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5027 /* Save gpwrdn register for further usage if stschng interrupt */
5028 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5029 dev_dbg(hsotg->dev, "Hibernation completed\n");
5035 * dwc2_gadget_exit_hibernation()
5036 * This function is for exiting from Device mode hibernation by host initiated
5037 * resume/reset and device initiated remote-wakeup.
5039 * @hsotg: Programming view of the DWC_otg controller
5040 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5041 * @reset: indicates whether resume is initiated by Reset.
5043 * Return non-zero if failed to exit from hibernation.
5045 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5046 int rem_wakeup, int reset)
5052 struct dwc2_gregs_backup *gr;
5053 struct dwc2_dregs_backup *dr;
5055 gr = &hsotg->gr_backup;
5056 dr = &hsotg->dr_backup;
5058 if (!hsotg->hibernated) {
5059 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5063 "%s: called with rem_wakeup = %d reset = %d\n",
5064 __func__, rem_wakeup, reset);
5066 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5069 /* Clear all pending interupts */
5070 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5073 /* De-assert Restore */
5074 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5075 gpwrdn &= ~GPWRDN_RESTORE;
5076 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5080 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5081 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5082 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5085 /* Restore GUSBCFG, DCFG and DCTL */
5086 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5087 dwc2_writel(hsotg, dr->dcfg, DCFG);
5088 dwc2_writel(hsotg, dr->dctl, DCTL);
5090 /* De-assert Wakeup Logic */
5091 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5092 gpwrdn &= ~GPWRDN_PMUACTV;
5093 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5097 /* Start Remote Wakeup Signaling */
5098 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5101 /* Set Device programming done bit */
5102 dctl = dwc2_readl(hsotg, DCTL);
5103 dctl |= DCTL_PWRONPRGDONE;
5104 dwc2_writel(hsotg, dctl, DCTL);
5106 /* Wait for interrupts which must be cleared */
5108 /* Clear all pending interupts */
5109 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5111 /* Restore global registers */
5112 ret = dwc2_restore_global_registers(hsotg);
5114 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5119 /* Restore device registers */
5120 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5122 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5129 dctl = dwc2_readl(hsotg, DCTL);
5130 dctl &= ~DCTL_RMTWKUPSIG;
5131 dwc2_writel(hsotg, dctl, DCTL);
5134 hsotg->hibernated = 0;
5135 hsotg->lx_state = DWC2_L0;
5136 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");